Semiconductor device and manufacturing method and working method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method and a working method thereof. The semiconductor device comprises a substrate; a plurality of deep trench capacitor cells, each deep trench capacitor cell comprising at least one deep trench formed in the substrate, a layer of conductive material, and a layer of dielectric material, the conductive material layers and the dielectric material layers are sequentially, alternately and conformally formed in the at least one deep trench and extend to the substrate on the periphery of the at least one deep trench, and the adjacent conductive material layers are electrically isolated through the dielectric material layers; and the MOS tubes are formed in the substrate between the adjacent deep groove capacitor units, the MOS tubes are electrically connected with the odd-numbered layers or even-numbered layers of conductive material layers in the deep groove capacitor units on the two sides of the MOS tubes respectively, and the adjacent deep groove capacitor units are controlled to be connected or disconnected by controlling connection or disconnection of the MOS tubes. According to the technical scheme of the invention, the reduction of the yield of the chip can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method and working method thereof. BACKGROUND

[0002] Deep trench capacitor (DTC) has the functions of noise reduction, filtering and stabilizing current, and is commonly used in 2.5D adapter board and other products. A large number of deep trench capacitors are generally provided on a single chip, and each deep trench capacitor is connected in parallel to achieve power supply function together. However, if one of the deep trench capacitors is short-circuited, the function of the whole chip will be affected, thereby reducing the yield of the chip.

[0003] Therefore, how to avoid reducing the yield of the chip is a problem to be solved. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method and working method thereof, so as to avoid reducing the yield of the chip.

[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:

[0006] a substrate;

[0007] a plurality of deep trench capacitor units, each of which comprises at least one deep trench, a conductive material layer and a dielectric material layer, the at least one deep trench is formed in the substrate, the conductive material layer and the dielectric material layer are formed in the at least one deep trench in turn and extend to the substrate outside the at least one deep trench, and the adjacent conductive material layers are electrically isolated by the dielectric material layer;

[0008] a MOS tube formed in the substrate between adjacent deep trench capacitor units, the MOS tube is electrically connected to the odd or even conductive material layer of the deep trench capacitor unit on both sides thereof, and the communication or disconnection of adjacent deep trench capacitor units is controlled by controlling the conduction or shutdown of the MOS tube.

[0009] Optionally, the MOS tube comprises a gate structure, a source region and a drain region, the gate structure is formed on the surface of the substrate and / or in the substrate, the source region and the drain region are formed in the substrate on both sides of the gate structure, and the source region and the drain region are electrically connected to the odd or even conductive material layer of the deep trench capacitor unit on both sides of the MOS tube.

[0010] Optionally, the gate structure comprises a gate dielectric layer and a gate layer, and the material of the gate layer is metal or polysilicon.

[0011] Optionally, the semiconductor device further comprises:

[0012] a conductive interconnection structure, the source region and the drain region are electrically connected to the odd or even number of the conductive material layers of the deep trench capacitor cells on both sides of the MOS transistor through the conductive interconnection structure, respectively.

[0013] Optionally, the semiconductor device further comprises:

[0014] an isolation layer formed between the substrate and the bottommost conductive material layer.

[0015] Optionally, the material of the conductive material layer comprises at least one of metal, metal nitride and polysilicon.

[0016] The present application also provides a method for manufacturing a semiconductor device, comprising:

[0017] providing a substrate;

[0018] forming a plurality of deep trench capacitor cells, each of the deep trench capacitor cells comprising at least one deep trench formed in the substrate, and conductive material layers and dielectric material layers formed in the deep trench in turn and conformally, and extending to the substrate outside the deep trench, the adjacent conductive material layers being electrically isolated by the dielectric material layers; and

[0019] forming a MOS transistor in the substrate between the adjacent deep trench capacitor cells, the MOS transistor being electrically connected to the odd or even number of the conductive material layers of the deep trench capacitor cells on both sides of the MOS transistor, and the communication or disconnection of the adjacent deep trench capacitor cells being controlled by controlling the on or off of the MOS transistor.

[0020] Optionally, the MOS transistor comprises a gate structure formed on the surface of the substrate and / or in the substrate, and a source region and a drain region formed in the substrate on both sides of the gate structure, the source region and the drain region being electrically connected to the odd or even number of the conductive material layers of the deep trench capacitor cells on both sides of the MOS transistor, respectively.

[0021] The application further provides a working method of a semiconductor device, the semiconductor device comprising a plurality of deep trench capacitor units and MOS tubes, each of the deep trench capacitor units comprising at least one deep trench formed in a substrate, a layer of conductive material and a layer of dielectric material, the layer of conductive material and the layer of dielectric material being alternately and conformally formed in the at least one deep trench and extending to the substrate outside the at least one deep trench, the layer of conductive material being electrically isolated from the layer of dielectric material between adjacent layers of the conductive material, and the MOS tubes being formed in the substrate between adjacent deep trench capacitor units, the MOS tubes being electrically connected to odd-numbered or even-numbered layers of the conductive material in the deep trench capacitor units on both sides of the MOS tubes, respectively.

[0022] The working method of the semiconductor device comprises controlling the MOS tubes to be turned on or turned off, thereby controlling adjacent deep trench capacitor units to be connected or disconnected.

[0023] Optionally, the MOS tubes comprise a gate structure formed on a surface of the substrate and / or in the substrate, a source region and a drain region formed in the substrate on both sides of the gate structure, and the source region and the drain region being electrically connected to odd-numbered or even-numbered layers of the conductive material in the deep trench capacitor units on both sides of the MOS tubes, respectively.

[0024] Optionally, when the MOS tubes are NMOS, the working method of the semiconductor device comprises:

[0025] applying a positive voltage to the gate structure so that a voltage difference between the gate structure and the source region is higher than a threshold voltage to control the NMOS to be turned on, or applying a negative voltage to the gate structure so that the voltage difference between the gate structure and the source region is lower than the threshold voltage, or not applying a voltage to the gate structure to control the NMOS to be turned off.

[0026] When the MOS tubes are PMOS, the working method of the semiconductor device comprises:

[0027] applying a negative voltage to the gate structure so that a voltage difference between the gate structure and the source region is lower than a threshold voltage to control the PMOS to be turned on, or applying a positive voltage to the gate structure so that the voltage difference between the gate structure and the source region is higher than the threshold voltage, or not applying a voltage to the gate structure to control the PMOS to be turned off.

[0028] Compared with the prior art, the technical scheme of the application has the following beneficial effects:

[0029] 1. The semiconductor device of the present application, comprising: a plurality of deep trench capacitor units, each of the deep trench capacitor units comprising at least one deep trench formed in the substrate, a layer of conductive material and a layer of dielectric material, the layer of conductive material and the layer of dielectric material being conformally formed in the at least one deep trench and extending onto the substrate outside the at least one deep trench, the layer of conductive material and the layer of dielectric material being alternately formed in sequence, the layer of dielectric material electrically isolating the adjacent layers of conductive material; and a MOS tube formed in the substrate between the adjacent deep trench capacitor units, the MOS tube being electrically connected to the odd layers or even layers of the layer of conductive material of the deep trench capacitor units on both sides of the MOS tube, the MOS tube being controlled to be turned on or turned off to control the adjacent deep trench capacitor units to be connected or disconnected, so that the yield of the chip can be improved.

[0030] 2. The manufacturing method of the semiconductor device of the present application, comprising: forming a plurality of deep trench capacitor units, each of the deep trench capacitor units comprising at least one deep trench formed in the substrate, a layer of conductive material and a layer of dielectric material, the layer of conductive material and the layer of dielectric material being conformally formed in the at least one deep trench and extending onto the substrate outside the at least one deep trench, the layer of conductive material and the layer of dielectric material being alternately formed in sequence, the layer of dielectric material electrically isolating the adjacent layers of conductive material; and forming a MOS tube in the substrate between the adjacent deep trench capacitor units, the MOS tube being electrically connected to the odd layers or even layers of the layer of conductive material of the deep trench capacitor units on both sides of the MOS tube, the MOS tube being controlled to be turned on or turned off to control the adjacent deep trench capacitor units to be connected or disconnected, so that the yield of the chip can be improved.

[0031] 3. The working method of the semiconductor device of the present application, comprising: controlling the MOS tube to be turned on or turned off to control the adjacent deep trench capacitor units to be connected or disconnected, so that the yield of the chip can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a top view of the semiconductor device of an embodiment of the present application;

[0033] Figure 2 is Figure 1 is a sectional view of the semiconductor device shown in FIG. 1 along the direction of AA';

[0034] Figure 3 is a flow chart of the manufacturing method of the semiconductor device of an embodiment of the present application.

[0035] wherein the accompanying drawings Figures 1-3 The reference signs in the drawings are explained as follows:

[0036] 10 - substrate; 11 - deep trench capacitor cell; 111 - deep trench; 112 - electrically conductive material layer; 113 - dielectric material layer; 12 - MOS transistor; 121 - gate layer; 122 - source region; 123 - drain region; 13 - insulating dielectric layer; 14 - interlayer dielectric layer; 151 - first electrically conductive plug; 152 - first interconnect layer; 153 - second electrically conductive plug; 154 - second interconnect layer; 161 - fourth interconnect layer. DETAILED DESCRIPTION

[0037] To make the objects, advantages and features of the present application more clear, the following further describes the semiconductor device and the manufacturing method and working method thereof. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0038] An embodiment of the present application provides a semiconductor device, comprising: a substrate; a plurality of deep trench capacitor cells, each of the deep trench capacitor cells comprising at least one deep trench, an electrically conductive material layer and a dielectric material layer, the at least one deep trench being formed in the substrate, the electrically conductive material layer and the dielectric material layer being formed in the at least one deep trench in turn and alternately conformally and extending to the substrate outside the at least one deep trench, the electrically conductive material layers being electrically isolated by the dielectric material layers; and a MOS transistor formed in the substrate between the adjacent deep trench capacitor cells, the MOS transistor being electrically connected with the odd or even electrically conductive material layers of the deep trench capacitor cells on both sides of the MOS transistor, and the communication or disconnection of the adjacent deep trench capacitor cells being controlled by controlling the on or off of the MOS transistor.

[0039] The following refers to Figures 1-2 The semiconductor device provided by the embodiment is described in detail.

[0040] The substrate 10 can be made of any suitable material known to those skilled in the art, for example, at least one of the following materials: silicon, germanium, germanium silicon, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator).

[0041] A plurality of deep trench capacitor cells 11, each of the deep trench capacitor cells 11 comprising at least one deep trench 111, an electrically conductive material layer 112 and a dielectric material layer 113, the at least one deep trench 111 being formed in the substrate 10, the electrically conductive material layer 112 and the dielectric material layer 113 being formed in the at least one deep trench 111 in turn and alternately conformally and extending to the substrate 10 outside the at least one deep trench 111, the electrically conductive material layers 112 being electrically isolated by the dielectric material layers 113.

[0042] In one embodiment, a plurality of deep trench capacitor units 11 are arranged in an array in the substrate 10.

[0043] The number of layers of the conductive material layer 112 is at least two, and the number of layers of the dielectric material layer 113 is at least one; in the deep trench capacitor unit 11, the bottommost layer is the conductive material layer 112, and the topmost layer is the conductive material layer 112 or the dielectric material layer 113.

[0044] In one embodiment, the topmost conductive material layer 112 or the dielectric material layer 113 fills the deep trench 111; or in another embodiment, the topmost conductive material layer 112 or the dielectric material layer 113 does not fill the deep trench 111.

[0045] In one embodiment, as shown in Figure 2 In one embodiment, as shown in

[0046] In one embodiment, the dielectric material layer 113 is only located between adjacent two layers of the conductive material layer 112; in another embodiment, the dielectric material layer 113 between adjacent two layers of the conductive material layer 112 also extends to the next layer of the conductive material layer 112 outside the peripheral of the previous layer of the conductive material layer 112.

[0047] The semiconductor device further comprises an isolation layer formed between the substrate 10 and the bottommost conductive material layer 112, for isolating the substrate 10 and the bottommost conductive material layer 112.

[0048] The conductive material layer 112 is various materials known to those skilled in the art that can conduct electricity, preferably at least one of metal, metal nitride and polysilicon.

[0049] The dielectric material layer 113 is various materials known to those skilled in the art that can insulate, preferably the material of the dielectric material layer 113 has a dielectric constant greater than 7.9 (7.9 is the dielectric constant of silicon nitride), for example, metal oxide material, so that the deep trench capacitor has a higher capacitance density. It should be noted that the material of the dielectric material layer 113 can also be silicon oxide or silicon oxynitride and other materials.

[0050] The material of the isolation layer can be at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0051] The MOS transistor 12 is formed in the substrate 10 between adjacent deep trench capacitor units 11, and is electrically connected to the odd or even conductive material layer 112 of the deep trench capacitor units 11 on both sides of the MOS transistor 12. The MOS transistor 12 is turned on or off to control the connection or disconnection of adjacent deep trench capacitor units 11.

[0052] The MOS transistor 12 can be an NMOS or a PMOS.

[0053] The MOS transistor 12 includes a gate structure, a source region 122, and a drain region 123. The gate structure is formed on the surface of the substrate 10 and / or in the substrate 10. The source region 122 and the drain region 123 are formed in the substrate 10 on both sides of the gate structure. The source region 122 and the drain region 123 are electrically connected to the odd or even conductive material layer 112 of the deep trench capacitor units 11 on both sides of the MOS transistor 12.

[0054] The gate structure includes a gate dielectric layer and a gate layer 121.

[0055] The material of the gate dielectric layer can be at least one of silicon oxide, silicon oxynitride, and silicon nitride. The material of the gate layer 121 is metal or polysilicon.

[0056] Preferably, the isolation layer and the gate dielectric layer are the same material formed by the same process to simplify the process steps. When the gate structure is formed on the surface of the substrate 10, an insulating dielectric layer 13 can be formed on the inner wall of the deep trench 111 and the substrate 10 around the deep trench 111. The insulating dielectric layer 13 between the bottommost conductive material layer 112 and the substrate 10 can serve as the isolation layer. The insulating dielectric layer 13 between the substrate 10 and the gate layer 121 between adjacent deep trench capacitor units 11 can serve as the gate dielectric layer. When the gate structure is formed in the substrate 10, a via (not shown) is formed in the substrate 10 between adjacent deep trench capacitor units 11. An insulating dielectric layer 13 can be formed on the inner wall of the deep trench 111, the inner wall of the via, and the substrate 10 around the deep trench 111 and the via. The insulating dielectric layer 13 between the bottommost conductive material layer 112 and the substrate 10 can serve as the isolation layer. The insulating dielectric layer 13 on the inner wall of the via can serve as the gate dielectric layer, and the gate layer 121 fills the via.

[0057] When the gate structure is formed on the surface of the substrate 10, the region of the substrate 10 between the source region 122 and the drain region 123 under the gate structure is a channel; when the gate structure is formed in the substrate 10, the region of the substrate 10 between the source region 122 and the drain region 123 is a channel.

[0058] In an embodiment, the depth of the via is greater than the depth of the deep trench 111.

[0059] The semiconductor device further comprises: a first conductive interconnection structure connecting the source region 122 and the conductive material layer 112 of odd-numbered layers or even-numbered layers of the deep trench capacitor unit 11 near the side of the source region 122; and a second conductive interconnection structure connecting the drain region 123 and the conductive material layer 112 of odd-numbered layers or even-numbered layers of the deep trench capacitor unit 11 near the side of the drain region 123.

[0060] In an embodiment, when the MOS transistor 12 is turned on, the conductive material layer 112 of odd-numbered layers of the deep trench capacitor unit 11 near the side of the source region 122 is in communication with the conductive material layer 112 of odd-numbered layers of the deep trench capacitor unit 11 near the side of the drain region 123; or, the conductive material layer 112 of odd-numbered layers of the deep trench capacitor unit 11 near the side of the source region 122 is in communication with the conductive material layer 112 of even-numbered layers of the deep trench capacitor unit 11 near the side of the drain region 123.

[0061] The semiconductor device further comprises: a third conductive interconnection structure connecting the conductive material layer 112 of all the deep trench capacitor units 11 that are not connected by the first conductive interconnection structure and the second conductive interconnection structure; and a voltage can be applied to the conductive material layer 112 of the deep trench capacitor unit 11 through the first conductive interconnection structure, the second conductive interconnection structure, and the third conductive interconnection structure, thereby enabling the deep trench capacitor unit 11 to work. For example, in an embodiment, the first conductive interconnection structure connects the conductive material layer 112 of even-numbered layers of the deep trench capacitor unit 11 near the side of the source region 122, and the second conductive interconnection structure connects the conductive material layer 112 of even-numbered layers of the deep trench capacitor unit 11 near the side of the drain region 123; then the third conductive interconnection structure connects the conductive material layer 112 of odd-numbered layers of the deep trench capacitor unit 11 near the side of the source region 122 and the conductive material layer 112 of odd-numbered layers of the deep trench capacitor unit 11 near the side of the drain region 123.

[0062] The first conductive interconnection structure can include at least one layer of first conductive plugs 151 and at least one layer of first interconnection layers 152, the source region 122 is connected to the bottommost first interconnection layer 152 through the first conductive plug 151 from the odd or even layer of the conductive material layer 112 in the deep trench capacitor cell 11 near the side of the source region 122, and the first conductive plug 151 is connected between the adjacent two layers of the first interconnection layers 152; the second conductive interconnection structure can include at least one layer of second conductive plugs 153 and at least one layer of second interconnection layers 154, the drain region 123 is connected to the bottommost second interconnection layer 154 through the second conductive plug 153 from the odd or even layer of the conductive material layer 112 in the deep trench capacitor cell 11 near the side of the drain region 123, and the second conductive plug 153 is connected between the adjacent two layers of the second interconnection layers 154; the third conductive interconnection structure can include at least one layer of third conductive plugs (not shown) and at least one layer of third interconnection layers (not shown), the conductive material layer 112 not connected to the first conductive interconnection structure and the second conductive interconnection structure is connected to the bottommost third interconnection layer through the third conductive plug, and the third conductive plug is connected between the adjacent two layers of the third interconnection layers.

[0063] The semiconductor device further comprises a fourth conductive interconnection structure electrically connected to the gate layer 121 in the gate structure, so as to enable the application of voltage to the gate layer 121 in the gate structure through the fourth conductive interconnection structure.

[0064] The fourth conductive interconnection structure can include at least one layer of fourth conductive plugs and at least one layer of fourth interconnection layers 161, and the gate layer 121 can be electrically connected to the bottommost fourth interconnection layer 161 through the fourth conductive plug; when the fourth conductive interconnection structure includes at least two layers of fourth conductive plugs and at least two layers of fourth interconnection layers 161, the fourth conductive plug is also electrically connected between the adjacent two layers of the fourth interconnection layers 161. Among them, Figure 2 In the embodiment shown, the fourth conductive plug connected between the gate layer 121 and the bottommost fourth interconnection layer 161 is the same material as the gate layer 121 formed by the same process, so as to simplify the process steps.

[0065] The semiconductor device further comprises an interlayer dielectric layer 14 formed on the substrate 10, the deep trench capacitor unit 11 and the MOS transistor 12, the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure are formed in the interlayer dielectric layer 14, and the interlayer dielectric layer 14 can expose the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure.

[0066] When the topmost layer of the conductive material layer 112 or the dielectric material layer 113 does not seal the deep trench 111, the interlayer dielectric layer 14 seals the deep trench 111. The interlayer dielectric layer 14 can fill or not fill the deep trench 111.

[0067] The interlayer dielectric layer 14 can include one or a combination of at least two of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride and NDC (Nitrogen doped Silicon Carbide), borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG) and the like.

[0068] When the MOS transistor 12 is an NMOS, a positive voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, so that the channel between the source region 122 and the drain region 123 is turned on, i.e. the NMOS is turned on; or a negative voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, or no voltage is applied to the gate structure, so that the channel between the source region 122 and the drain region 123 is turned off, i.e. the NMOS is turned off.

[0069] When the MOS transistor 12 is a PMOS, a negative voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, so that the channel between the source region 122 and the drain region 123 is turned on, i.e. the PMOS is turned on; or a positive voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, or no voltage is applied to the gate structure, so that the channel between the source region 122 and the drain region 123 is turned off, i.e. the PMOS is turned off.

[0070] From the above, the semiconductor device provided by the application, because the MOS tube 12 is formed in the substrate 10 between adjacent deep trench capacitor units 11, and the MOS tube 12 is electrically connected with the odd or even layer conductive material layer 112 of the deep trench capacitor unit 11 on both sides, so that the communication or disconnection between adjacent deep trench capacitor units 11 can be controlled by controlling the on or off of the MOS tube 12, and when an abnormality occurs in a certain deep trench capacitor unit 11 of the plurality of deep trench capacitor units 11, for example, a short circuit occurs in a certain deep trench capacitor unit 11, the MOS tube 12 around the abnormal deep trench capacitor unit 11 can be turned off to disconnect the abnormal deep trench capacitor unit 11 from the normal deep trench capacitor unit 11, and the voltage applied to the odd or even layer conductive material layer 112 of the normal deep trench capacitor unit 11 cannot be applied to the odd or even layer conductive material layer 112 of the abnormal deep trench capacitor unit 11, that is, the abnormal deep trench capacitor unit 11 is isolated from other normal deep trench capacitor units 11 by the off MOS tube 12; and the MOS tube 12 between adjacent normal deep trench capacitor units 11 is turned on, so that the adjacent normal deep trench capacitor units 11 are connected. Therefore, when the semiconductor device is working, by controlling the off of the MOS tube 12 around the abnormal deep trench capacitor unit 11 and the on of the MOS tube 12 between adjacent normal deep trench capacitor units 11, the abnormal deep trench capacitor unit 11 is isolated, that is, only the abnormal deep trench capacitor unit 11 cannot work, while the normal deep trench capacitor unit 11 can continue to work, avoiding the influence of the abnormal deep trench capacitor unit 11 on the normal deep trench capacitor unit 11, and avoiding the whole chip being regarded as a defective product because only one or part of the deep trench capacitor units 11 in the chip are abnormal, that is, when there is one or part of the abnormal deep trench capacitor units 11 in the chip, the chip can still be used as a good product, thereby avoiding reducing the yield of the chip.

[0071] When the semiconductor device is operating, because the MOS transistor 12 surrounding the abnormal deep trench capacitor cell 11 is turned off, the voltage applied to the first and second conductive interconnect structures electrically connected to the normal deep trench capacitor cell 11 cannot be applied to the odd or even layers of conductive material 112 in the abnormal deep trench capacitor cell 11. Since the MOS transistors 12 between adjacent normal deep trench capacitor cells 11 are turned on, applying a voltage to any one of the first or second conductive interconnect structures electrically connected to the normal deep trench capacitor cell 11 allows voltage to be applied to the odd or even layers of conductive material 112 in all normal deep trench capacitor cells 11. Therefore, applying a voltage to the third conductive interconnect structure and any one of the first or second conductive interconnect structures electrically connected to the normal deep trench capacitor cell 11 allows all normal deep trench capacitor cells 11 to operate normally, while the isolated abnormal deep trench capacitor cell 11 cannot operate.

[0072] For example, in Figure 1 In the illustrated embodiment, among the nine deep trench capacitor cells 11, the middle deep trench capacitor cell 11 (i.e., A2) malfunctions, while the surrounding eight deep trench capacitor cells 11 (i.e., A1) are normal. When the semiconductor device is operating, the four MOS transistors 12 surrounding the malfunctioning deep trench capacitor cell 11 are turned off, and the MOS transistors 12 between adjacent normal deep trench capacitor cells 11 are turned on. A voltage is applied to the third conductive interconnect structure and the first conductive interconnect structure or the second conductive interconnect structure electrically connected to any one of the normal deep trench capacitor cells 11, so that the malfunctioning deep trench capacitor cell 11 cannot work, while the eight normal deep trench capacitor cells 11 can work normally.

[0073] In a single chip, the more deep trenches 111 in each deep trench capacitor cell 11, the fewer MOS transistors 12 are required, and the smaller the area occupied by the MOS transistors 12. However, the capacitance loss when a deep trench capacitor cell 11 malfunctions is also greater. Conversely, the fewer deep trenches 111 in each deep trench capacitor cell 11, the more MOS transistors 12 are required, and the larger the area occupied by the MOS transistors 12. However, the capacitance loss when a deep trench capacitor cell 11 malfunctions is also smaller. Therefore, an appropriate number of deep trenches 111 can be set in each deep trench capacitor cell 11 according to the performance requirements of the semiconductor device.

[0074] Based on the same inventive concept, one embodiment of the present application provides a method for manufacturing a semiconductor device, referring to Figure 3 From Figure 3 it can be seen that the method for manufacturing a semiconductor device comprises:

[0075] Step S1, providing a substrate;

[0076] Step S2, forming a plurality of deep trench capacitor units, each of which comprises at least one deep trench formed in the substrate, a conductive material layer and a dielectric material layer, the conductive material layer and the dielectric material layer are alternately conformally formed in the at least one deep trench and extend to the substrate outside the at least one deep trench, and the adjacent conductive material layers are electrically isolated by the dielectric material layer; and forming MOS tubes in the substrate between adjacent deep trench capacitor units, the MOS tubes are electrically connected to the odd or even layers of the conductive material layers in the deep trench capacitor units on both sides of the MOS tubes, and the communication or disconnection of adjacent deep trench capacitor units is controlled by controlling the conduction or shutdown of the MOS tubes.

[0077] Referring to Figure 1 , Figure 2 the method for manufacturing a semiconductor device provided by the embodiment will be described in detail.

[0078] According to step S1, a substrate 10 is provided.

[0079] The material of the substrate 10 can be any suitable substrate known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, germanium silicon, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator).

[0080] According to step S2, a plurality of deep trench capacitor units 11 are formed, each of which comprises at least one deep trench 111 formed in the substrate 10, a layer of conductive material 112 and a layer of dielectric material 113 formed in the at least one deep trench 111 and extending to the substrate 10 outside the at least one deep trench 111, the layer of conductive material 112 and the layer of dielectric material 113 being formed alternately and conformally, and adjacent layers of the layer of conductive material 112 are electrically isolated by the layer of dielectric material 113; and a MOS transistor 12 is formed in the substrate 10 between adjacent deep trench capacitor units 11, the MOS transistor 12 being electrically connected to odd-numbered or even-numbered layers of the layer of conductive material 112 in the deep trench capacitor units 11 on both sides of the MOS transistor 12, and the MOS transistor 12 is controlled to be turned on or turned off to control the connection or disconnection of adjacent deep trench capacitor units 11.

[0081] In the method, the deep trench 111 is formed by etching the substrate 10, and the layer of conductive material 112 and the layer of dielectric material 113 are formed by performing a deposition and etching process.

[0082] In an embodiment, the plurality of deep trench capacitor units 11 are arranged in an array in the substrate 10.

[0083] The structure of the deep trench capacitor unit 11 is described in the semiconductor device and will not be repeated here.

[0084] After the deep trench 111 is formed and before the bottommost layer of the layer of conductive material 112 is formed, the method further comprises forming an isolation layer conformally formed in the at least one deep trench 111 and extending to the substrate 10 outside the at least one deep trench 111, the isolation layer being located between the substrate 10 and the bottommost layer of the layer of conductive material 112, and used to isolate the substrate 10 and the bottommost layer of the layer of conductive material 112.

[0085] The order of forming the plurality of deep trench capacitor units 11 and the MOS transistor 12 is not limited. The plurality of deep trench capacitor units 11 can be formed first, and then the MOS transistor 12 is formed; or the MOS transistor 12 can be formed first, and then the plurality of deep trench capacitor units 11 are formed.

[0086] The structure of the MOS transistor 12 is described in the semiconductor device and will not be repeated here.

[0087] The method for manufacturing the semiconductor device further comprises forming a first conductive interconnection structure and a second conductive interconnection structure, the first conductive interconnection structure connecting the source region 122 and the conductive material layer 112 of the odd-numbered layer or the even-numbered layer of the deep trench capacitor unit 11 near the side of the source region 122, and the second conductive interconnection structure connecting the drain region 123 and the conductive material layer 112 of the odd-numbered layer or the even-numbered layer of the deep trench capacitor unit 11 near the side of the drain region 123.

[0088] In an embodiment, when the MOS transistor 12 is turned on, the conductive material layer 112 of the odd-numbered layer of the deep trench capacitor unit 11 near the side of the source region 122 is connected to the conductive material layer 112 of the odd-numbered layer of the deep trench capacitor unit 11 near the side of the drain region 123, or the conductive material layer 112 of the odd-numbered layer of the deep trench capacitor unit 11 near the side of the source region 122 is connected to the conductive material layer 112 of the even-numbered layer of the deep trench capacitor unit 11 near the side of the drain region 123.

[0089] The method for manufacturing the semiconductor device further comprises forming a third conductive interconnection structure, the conductive material layer 112 of all the deep trench capacitor units 11 not connected to the first conductive interconnection structure and the second conductive interconnection structure being connected to the third conductive interconnection structure, so that the conductive material layer 112 of the deep trench capacitor unit 11 can be applied with a voltage through the first conductive interconnection structure, the second conductive interconnection structure and the third conductive interconnection structure, and the deep trench capacitor unit 11 is thus enabled to work.

[0090] The method for manufacturing the semiconductor device further comprises forming a fourth conductive interconnection structure, the fourth conductive interconnection structure being electrically connected to the gate layer 121 in the gate structure, so that the gate layer 121 in the gate structure can be applied with a voltage through the fourth conductive interconnection structure.

[0091] In an embodiment, the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure are formed simultaneously, so as to simplify the process steps.

[0092] The structures of the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure are described in the semiconductor device, and thus will not be described here again.

[0093] The method for manufacturing the semiconductor device further comprises: forming an interlayer dielectric layer 14 on the substrate 10, the deep trench capacitor unit 11 and the MOS transistor 12, the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure are formed in the interlayer dielectric layer 14, and the interlayer dielectric layer 14 can expose the first conductive interconnection structure, the second conductive interconnection structure, the third conductive interconnection structure and the fourth conductive interconnection structure.

[0094] When the MOS transistor 12 is an NMOS, a positive voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, to make the channel between the source region 122 and the drain region 123 conductive, i.e. the NMOS is turned on; or a negative voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, or no voltage is applied to the gate structure, to make the channel between the source region 122 and the drain region 123 non-conductive, i.e. the NMOS is turned off.

[0095] When the MOS transistor 12 is a PMOS, a negative voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, to make the channel between the source region 122 and the drain region 123 conductive, i.e. the PMOS is turned on; or a positive voltage can be applied to the gate structure through the fourth conductive interconnection structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, or no voltage is applied to the gate structure, to make the channel between the source region 122 and the drain region 123 non-conductive, i.e. the PMOS is turned off.

[0096] According to the above, the semiconductor device manufacturing method provided by the application can realize the following effects: by forming the MOS tube 12 in the substrate 10 between adjacent deep trench capacitor units 11, and electrically connecting the MOS tube 12 with the odd or even conductive material layer 112 of the deep trench capacitor unit 11 on both sides of the MOS tube 12, the communication or disconnection between adjacent deep trench capacitor units 11 can be controlled by controlling the on or off of the MOS tube 12, so that when an abnormality occurs in a certain deep trench capacitor unit 11, for example, when a certain deep trench capacitor unit 11 is short-circuited, the MOS tube 12 around the abnormal deep trench capacitor unit 11 can be turned off to disconnect the abnormal deep trench capacitor unit 11 from the normal deep trench capacitor unit 11, so that the voltage applied to the odd or even conductive material layer 112 of the normal deep trench capacitor unit 11 cannot be applied to the odd or even conductive material layer 112 of the abnormal deep trench capacitor unit 11, that is, the abnormal deep trench capacitor unit 11 is isolated from other normal deep trench capacitor units 11 by the turned-off MOS tube 12; and the MOS tube 12 between adjacent normal deep trench capacitor units 11 is turned on, so that the adjacent normal deep trench capacitor units 11 are connected. Therefore, during the operation of the semiconductor device, by turning off the MOS tube 12 around the abnormal deep trench capacitor unit 11 and turning on the MOS tube 12 between adjacent normal deep trench capacitor units 11, the abnormal deep trench capacitor unit 11 is isolated, that is, only the abnormal deep trench capacitor unit 11 cannot work, while the normal deep trench capacitor unit 11 can continue to work, avoiding the influence of the abnormal deep trench capacitor unit 11 on the normal deep trench capacitor unit 11, thereby avoiding the situation that only one or part of the deep trench capacitor units 11 in the entire chip are abnormal, resulting in the entire chip being regarded as a defective product, that is, when there is one or part of the abnormal deep trench capacitor units 11 in the chip, the chip can still be used as a good product, thereby avoiding reducing the yield of the chip.

[0097] Wherein, during the operation of the semiconductor device, the MOS transistor 12 outside the abnormal deep trench capacitor unit 11 is turned off, so that the voltage applied to the first and second conductive interconnection structures electrically connected to the normal deep trench capacitor unit 11 cannot be applied to the odd or even conductive material layer 112 in the abnormal deep trench capacitor unit 11; the MOS transistor 12 between adjacent normal deep trench capacitor units 11 is turned on, so that the voltage applied to the first or second conductive interconnection structure electrically connected to any one normal deep trench capacitor unit 11 can be applied to the odd or even conductive material layer 112 in all normal deep trench capacitor units 11. Therefore, by applying voltage to the third conductive interconnection structure and the first or second conductive interconnection structure electrically connected to any one normal deep trench capacitor unit 11, all normal deep trench capacitor units 11 can work normally, and the isolated abnormal deep trench capacitor unit 11 cannot work.

[0098] Based on the same inventive concept, an embodiment of the present application provides a working method of a semiconductor device, the semiconductor device comprising a plurality of deep trench capacitor units and MOS transistors, each deep trench capacitor unit comprising at least one deep trench formed in a substrate, conductive material layers and dielectric material layers, the conductive material layers and the dielectric material layers being alternately and conformally formed in the at least one deep trench and extending to the substrate outside the at least one deep trench, the adjacent conductive material layers being electrically isolated by the dielectric material layers; the MOS transistors being formed in the substrate between adjacent deep trench capacitor units, the MOS transistors being electrically connected to the odd or even conductive material layers of the deep trench capacitor units on both sides of the MOS transistors; the working method of the semiconductor device comprising: controlling the MOS transistors to be turned on or turned off, thereby controlling the adjacent deep trench capacitor units to be connected or disconnected.

[0099] The specific structure of the semiconductor device is described above and will not be repeated here.

[0100] Referring to Figure 1 and Figure 2 Figure 2 , the working method of the semiconductor device comprises:

[0101] Applying voltage or no voltage to the MOS transistor 12 to control the MOS transistor 12 to be turned on or turned off, thereby controlling the adjacent deep trench capacitor units 11 to be connected or disconnected.

[0102] When the MOS transistor 12 is an NMOS, the working method of the semiconductor device comprises: applying a positive voltage to the gate structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, to make the channel between the source region 122 and the drain region 123 conductive, i.e. the NMOS is turned on, and then the adjacent deep trench capacitor units 11 are connected through the first conductive interconnection structure, the second conductive interconnection structure and the NMOS; or, a negative voltage can be applied to the gate structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, or no voltage is applied to the gate structure, to make the channel between the source region 122 and the drain region 123 off, i.e. the NMOS is turned off, and then the adjacent deep trench capacitor units 11 are disconnected.

[0103] When the MOS transistor 12 is a PMOS, the working method of the semiconductor device comprises: applying a negative voltage to the gate structure, so that the voltage difference between the gate structure and the source region 122 is lower than the threshold voltage, to make the channel between the source region 122 and the drain region 123 conductive, i.e. the PMOS is turned on, and then the adjacent deep trench capacitor units 11 are connected through the first conductive interconnection structure, the second conductive interconnection structure and the PMOS; or, a positive voltage is applied to the gate structure, so that the voltage difference between the gate structure and the source region 122 is higher than the threshold voltage, or no voltage is applied to the gate structure, to make the channel between the source region 122 and the drain region 123 off, i.e. the PMOS is turned off, and then the adjacent deep trench capacitor units 11 are disconnected.

[0104] As can be seen from the above, in the semiconductor device, the MOS tube 12 is formed in the substrate 10 between adjacent deep trench capacitor units 11, and the MOS tube 12 is electrically connected to the odd or even layer of the conductive material layer 112 in the deep trench capacitor unit 11 on both sides of the MOS tube 12, so that the adjacent deep trench capacitor units 11 can be connected or disconnected by controlling the on or off of the MOS tube 12. When an abnormality occurs in a certain deep trench capacitor unit 11 in the plurality of deep trench capacitor units 11, for example, when a certain deep trench capacitor unit 11 short-circuits, the MOS tube 12 around the abnormal deep trench capacitor unit 11 can be turned off to disconnect the abnormal deep trench capacitor unit 11 from the normal deep trench capacitor unit 11, so that the voltage applied to the odd or even layer of the conductive material layer 112 in the normal deep trench capacitor unit 11 cannot be applied to the odd or even layer of the conductive material layer 112 in the abnormal deep trench capacitor unit 11, that is, the abnormal deep trench capacitor unit 11 is isolated from other normal deep trench capacitor units 11 by the turned-off MOS tube 12; and the MOS tube 12 between adjacent normal deep trench capacitor units 11 is turned on, so that the adjacent normal deep trench capacitor units 11 are connected. Therefore, during the operation of the semiconductor device, by turning off the MOS tube 12 around the abnormal deep trench capacitor unit 11 and turning on the MOS tube 12 between adjacent normal deep trench capacitor units 11, the abnormal deep trench capacitor unit 11 is isolated, that is, only the abnormal deep trench capacitor unit 11 cannot work, while the normal deep trench capacitor units 11 can continue to work, avoiding the influence of the abnormal deep trench capacitor unit 11 on the normal deep trench capacitor units 11, thereby avoiding the entire chip being discarded as a defective product due to the abnormality of only one or part of the deep trench capacitor units 11 in the chip, that is, when there is one or part of the abnormal deep trench capacitor units 11 in the chip, the chip can still be used as a good product, thereby avoiding reducing the yield of the chip.

[0105] When the semiconductor device is working, the MOS transistor 12 outside the abnormal deep trench capacitor unit 11 is turned off, so that the voltage applied to the first conductive interconnection structure and the second conductive interconnection structure electrically connected to the normal deep trench capacitor unit 11 cannot be applied to the odd or even conductive material layer 112 in the abnormal deep trench capacitor unit 11; the MOS transistor 12 between the adjacent normal deep trench capacitor units 11 is turned on, so that the voltage applied to the first conductive interconnection structure or the second conductive interconnection structure electrically connected to any one normal deep trench capacitor unit 11 can be applied to the odd or even conductive material layer 112 in all the deep trench capacitor units 11. Therefore, the voltage applied to the third conductive interconnection structure and the first conductive interconnection structure or the second conductive interconnection structure electrically connected to any one normal deep trench capacitor unit 11 can make all the normal deep trench capacitor units 11 work normally, and the isolated abnormal deep trench capacitor unit 11 cannot work.

[0106] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification or change made by those skilled in the art according to the above disclosure is within the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A plurality of deep trench capacitor cells, each of the deep trench capacitor cells comprising at least one deep trench, a conductive material layer and a dielectric material layer, wherein the at least one deep trench is formed in the substrate, and the conductive material layer and the dielectric material layer are sequentially and conformally formed in the at least one deep trench and extend to the periphery of the at least one deep trench on the substrate, and adjacent conductive material layers are electrically isolated from each other by the dielectric material layer; A MOS transistor is formed in the substrate between adjacent deep trench capacitor cells. The MOS transistor is electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of it. The connection or disconnection of adjacent deep trench capacitor cells is controlled by controlling the conduction or disconnection of the MOS transistor.

2. The semiconductor device as claimed in claim 1, characterized in that, The MOS transistor includes a gate structure, a source region, and a drain region. The gate structure is formed on the surface of the substrate and / or within the substrate. The source region and the drain region are formed in the substrate on both sides of the gate structure. The source region and the drain region are electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of the MOS transistor.

3. The semiconductor device as described in claim 2, characterized in that, The gate structure includes a gate dielectric layer and a gate layer, wherein the gate layer is made of metal or polysilicon.

4. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes: A conductive interconnect structure is provided, wherein the source region and the drain region are electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of the MOS transistor through the conductive interconnect structure.

5. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: An isolation layer is formed between the substrate and the bottommost conductive material layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The conductive material layer is made of at least one of metal, metal nitride, and polycrystalline silicon.

7. A method for manufacturing a semiconductor device, characterized in that, include: Provide a substrate; Multiple deep trench capacitor units are formed, each deep trench capacitor unit comprising at least one deep trench, a conductive material layer and a dielectric material layer, wherein the at least one deep trench is formed in the substrate, and the conductive material layer and the dielectric material layer are sequentially and conformally formed in the at least one deep trench and extend to the periphery of the at least one deep trench on the substrate, and adjacent conductive material layers are electrically isolated from each other by the dielectric material layer; as well as, A MOS transistor is formed in the substrate between adjacent deep trench capacitor cells. The MOS transistor is electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides. The connection or disconnection of adjacent deep trench capacitor cells is controlled by controlling the conduction or disconnection of the MOS transistor.

8. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The MOS transistor includes a gate structure, a source region, and a drain region. The gate structure is formed on the surface of the substrate and / or within the substrate. The source region and the drain region are formed in the substrate on both sides of the gate structure. The source region and the drain region are electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of the MOS transistor.

9. A method for operating a semiconductor device, characterized in that, The semiconductor device includes a plurality of deep trench capacitor cells and a MOSFET. Each deep trench capacitor cell includes at least one deep trench, a conductive material layer, and a dielectric material layer. The at least one deep trench is formed in the substrate. The conductive material layer and the dielectric material layer are formed conformally and alternately within the at least one deep trench and extend onto the substrate surrounding the at least one deep trench. Adjacent conductive material layers are electrically isolated from each other by the dielectric material layers. The MOSFET is formed in the substrate between adjacent deep trench capacitor cells and is electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of the MOSFET. The operation method of the semiconductor device includes: controlling the MOS transistor to be turned on or off, thereby controlling the adjacent deep trench capacitor cells to be connected or disconnected.

10. The method of operating the semiconductor device as described in claim 9, characterized in that, The MOS transistor includes a gate structure, a source region, and a drain region. The gate structure is formed on the surface of the substrate and / or within the substrate. The source region and the drain region are formed in the substrate on both sides of the gate structure. The source region and the drain region are electrically connected to the odd-numbered or even-numbered conductive material layers in the deep trench capacitor cells on both sides of the MOS transistor.

11. The method of operating the semiconductor device as described in claim 10, characterized in that, When the MOS transistor is an NMOS, the operation method of the semiconductor device includes: A positive voltage is applied to the gate structure such that the voltage difference between the gate structure and the source region is higher than a threshold voltage to control the NMOS to turn on; or, a negative voltage is applied to the gate structure such that the voltage difference between the gate structure and the source region is lower than a threshold voltage, or no voltage is applied to the gate structure to control the NMOS to turn off. When the MOS transistor is a PMOS, the operation method of the semiconductor device includes: A negative voltage is applied to the gate structure such that the voltage difference between the gate structure and the source region is lower than a threshold voltage to control the PMOS to turn on; or, a positive voltage is applied to the gate structure such that the voltage difference between the gate structure and the source region is higher than a threshold voltage, or no voltage is applied to the gate structure to control the PMOS to turn off.

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