Semiconductor device including field effect transistor and method of manufacturing same

Abstract

A semiconductor device includes: a substrate including an active pattern; a device isolation layer disposed between the active patterns; a stack pattern disposed on the substrate; a power transmission network layer disposed on the first surface of the substrate; a first through hole penetrating the stack pattern; and a second via disposed between the power transfer network layer and the first via, in which the second via penetrates the active pattern and the device isolation layer.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0063245, filed on May 14, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. BACKGROUND

[0003] Generally, a semiconductor device can include an integrated circuit having, for example, a metal oxide semiconductor field effect transistor (MOSFET). As the size and design of semiconductor devices are continuously reduced, the size of MOSFETs is also increasingly reduced. The miniaturization of MOSFETs can cause the characteristics of certain semiconductor devices to degrade. Accordingly, research has been conducted to overcome the limitations brought about by the increased integration of semiconductor devices and to manufacture semiconductor devices having improved performance. SUMMARY

[0004] According to an embodiment of the present inventive concept, a semiconductor device includes a substrate including active patterns; a device isolation layer disposed between the active patterns; a stack pattern disposed on the substrate; a power delivery network layer disposed on a first surface of the substrate; a first via penetrating the stack pattern; and a second via disposed between the power delivery network layer and the first via, wherein the second via penetrates the active patterns and the device isolation layer.

[0005] According to an embodiment of the present inventive concept, a semiconductor device includes a substrate including logic cells and tap cells adjacent to the logic cells; metal lines disposed on the substrate and spaced apart from each other in a first direction, wherein each of the metal lines extends in a second direction that crosses the first direction; and a power delivery network layer disposed on a lower surface of the substrate, wherein the tap cells include vias that connect some of the metal lines and the power delivery network layer to each other, wherein the vias include a first via and a second via that are in contact with each other, wherein the second via penetrates at least a portion of the substrate, and wherein an interface between the first via and the second via is closer to an upper surface of the substrate than to the lower surface of the substrate.

[0006] According to embodiments of the inventive concept, a semiconductor device includes logic cells and tap cells arranged on a substrate, metal lines and power lines provided on the substrate, and a power delivery network layer provided on a lower surface of the substrate, wherein each of the logic cells includes a channel pattern provided on an active pattern, a device isolation layer provided between the active patterns, a source / drain pattern provided between the channel patterns, and a gate electrode provided on the channel patterns, wherein each of the tap cells includes a via connecting the metal lines and the power delivery network layer to each other, and wherein a lower surface of the device isolation layer is coplanar with a lower surface of the active pattern. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

[0008] FIG. 1 , FIG. 2 and FIG. 3 are diagrams illustrating a semiconductor device according to embodiments of the inventive concept.

[0009] FIG. 4 is a plan view illustrating a semiconductor device according to embodiments of the inventive concept.

[0010] FIG. 5A , FIG. 5B , FIG. 5C and FIG. 5D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of FIG. 4 , respectively.

[0011] FIG. 6 is a plan view illustrating a semiconductor device according to embodiments of the inventive concept.

[0012] FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A and FIG. 9B are cross-sectional views illustrating a semiconductor device according to embodiments of the inventive concept, wherein FIG. 7A , FIG. 8A and FIG. 9A are cross-sectional views taken along line E-E' of FIG. 6 , and FIG. 7B , FIG. 8B and FIG. 9B are cross-sectional views taken along line F-F' of FIG. 6 .

[0013] FIG. 10 and FIG. 11This is a plan view showing the arrangement of tap units of a semiconductor device according to an embodiment of the present invention.

[0014] FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A , FIG. 15B , FIG. 16A and FIG. 16B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein, FIG. 12A , FIG. 13A , FIG. 14A , FIG. 15A and FIG. 16A It is along FIG. 6 The cross-sectional view taken by line E-E', and FIG. 12B , FIG. 13B , FIG. 14B , FIG. 15B and FIG. 16B It is along FIG. 6 The cross-sectional view taken by line F-F'. Detailed Implementation

[0015] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings. Throughout this specification and the drawings, the same reference numerals may refer to the same elements, and therefore, their redundant descriptions may be omitted.

[0016] FIGS. 1-3 This is a diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0017] Reference FIG. 1 A single-height cell (SHC) can be configured. A first electric field line M1_R1 and a second electric field line M1_R2 can be disposed on the substrate 100. The first electric field line M1_R1 can be a conductive path providing it with a source voltage VSS or ground voltage. The second electric field line M1_R2 can be a conductive path providing it with a drain voltage VDD or a power supply voltage.

[0018] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. The single-height cell SHC may include a first active region AR1 and a second active region AR2. For example, one of the first active region AR1 and the second active region AR2 may be a PMOSFET region. The other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. For example, the single-height cell SHC may have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0019] Each of the first active regions AR1 and the second active regions AR2 can have a first width W1 in the first direction D1. A length of the single-height cell SHC in the first direction D1 can be defined as a first height HE1. The first height HGT1 can be substantially equal to a distance (e.g., pitch) between the first power line M1_R1 and the second power line M1_R2.

[0020] The single-height cell SHC can constitute one logic cell. In the present specification, a logic cell can refer to a logical element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, the logic cell can include transistors for configuring the logical element and wires connecting the transistors to each other.

[0021] Referring to FIG. 2 A double-height cell DHC can be provided. The first power line M1_R1, the second power line M1_R2, and the third power line M1_R3 can be provided on the substrate 100. The second power line M1_R2 can be provided between the first power line M1_R1 and the third power line M1_R3. For example, the third power line M1_R3 can be a path that provides a source voltage VSS.

[0022] The double-height cell DHC can be defined between the first power line M1_R1 and the third power line M1_R3. The double-height cell DHC can include two first active regions AR1 and two second active regions AR2.

[0023] The first active regions AR1 can be adjacent to the first power line M1_R1. One of the second active regions AR2 can be adjacent to the second power line M1_R2. The other of the second active regions AR2 can be adjacent to the third power line M1_R3. When viewed in a plan view, the first power line M1_R1 can be provided between the two first active regions AR1.

[0024] A length of the double-height cell DHC in the first direction D1 can be defined as a second height HE2. The second height HE2 can be about twice the first height HE1 of the single-height cell SHC. For example, the first active regions AR1 of the double-height cell DHC can be bundled to function as one PMOSFET region. Accordingly, a channel size of a PMOS transistor of the double-height cell DHC can be greater than a channel size of a PMOS transistor of the single-height cell SHC. FIG. 1 FIG. 1

[0025] For example, the channel size of the PMOS transistor of the double-height cell DHC can be about twice the channel size of the PMOS transistor of the single-height cell SHC. Accordingly, the double-height cell DHC can operate at a higher speed than the single-height cell SHC.

[0026] ​​In this specification, FIG. 2 The double-height cell DHC illustrated can be defined as a multi-height cell. The multi-height cell can include a triple-height cell whose cell height is about three times the height of the single-height cell SHC.

[0027] Referring to FIG. 3 The substrate 100 can include a first logic cell LC1, a second logic cell LC2, and a tap cell TC arranged two-dimensionally. A first power line M1_R1 and a second power line M1_R2 can be disposed on the substrate 100. The first logic cell LC1, the second logic cell LC2, and the tap cell TC can be disposed between the first power line M1_R1 and the second power line M1_R2. The first logic cell LC1 and the second logic cell LC2 can be spaced apart from each other in a second direction D2. The tap cell TC can be disposed between the first logic cell LC1 and the second logic cell LC2. For example, each of the first logic cell LC1 and the second logic cell LC2 can be a single-height cell SHC described later with reference to FIG. 2. FIG. 1 The tap cell TC can include a via TVI. The via TVI can be connected to a power transmission network layer described later. For example, the tap cell TC can be a cell for applying a voltage from the power transmission network layer to the adjacent first logic cell LC1 and second logic cell LC2, which will be described later. In addition, the tap cell TC can be a cell for transmitting a signal to the first logic cell LC1 and the second logic cell LC2. That is, unlike the first logic cell LC1 and the second logic cell LC2, the tap cell TC can not include a logic element. For example, the tap cell TC can be a type of dummy cell that can apply a voltage or transmit a signal to the first logic cell LC1 and the second logic cell LC2, but can not perform a circuit function. Accordingly, the voltage or the signal can be quickly provided to the first logic cell LC1 and the second logic cell LC2 adjacent to the tap cell TC. Accordingly, the electrical performance of the semiconductor device can be improved.

[0028] Each of the separation structures DB can be respectively disposed between the first logic cell LC1 and the tap cell TC, and between the second logic cell LC2 and the tap cell TC. The separation structures DB can be spaced apart from each other in the second direction D2, and each of the separation structures DB can extend in the first direction D1. Each of the first active region AR1 and the second active region AR2 of the first logic cell LC1, the second logic cell LC2, and the tap cell TC can be electrically separated by the separation structures DB, respectively.

[0029] The tap cell TC can include a via TVI. The via TVI can be connected to a power transmission network layer described later. For example, the tap cell TC can be a cell for applying a voltage from the power transmission network layer to the adjacent first logic cell LC1 and second logic cell LC2, which will be described later. In addition, the tap cell TC can be a cell for transmitting a signal to the first logic cell LC1 and the second logic cell LC2. That is, unlike the first logic cell LC1 and the second logic cell LC2, the tap cell TC can not include a logic element. For example, the tap cell TC can be a type of dummy cell that can apply a voltage or transmit a signal to the first logic cell LC1 and the second logic cell LC2, but can not perform a circuit function. Accordingly, the voltage or the signal can be quickly provided to the first logic cell LC1 and the second logic cell LC2 adjacent to the tap cell TC. Accordingly, the electrical performance of the semiconductor device can be improved.

[0030] FIG. 3The arrangement of the first logic cell LC1, the second logic cell LC2, and the tap cell TC shown is an example, and the arrangement between the first logic cell LC1, the second logic cell LC2, and the tap cell TC can be provided in various ways. For example, at least one of the first logic cell LC1 and / or the second logic cell LC2 can be the logic cell LC described with reference to FIG. 2 The multi-height cell described. Furthermore, a plurality of tap cells TC can be provided.

[0031] FIG. 4 is a plan view for illustrating a semiconductor device according to an embodiment of the present inventive concept. FIGS. 5A-5D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of FIG. 4

[0032] Referring to FIG. 4 and FIGS. 5A-5D A substrate 100 including a logic cell LC can be provided. The logic cell LC can be the first logic cell LC1 or the second logic cell LC2 described with reference to FIG. 3 The logic cell LC can be the single-height cell SHC described with reference to FIG. 1 The substrate 100 can be a semiconductor substrate including, for example, silicon, germanium, silicon-germanium, or the like, or a compound semiconductor substrate. For example, the substrate 100 can be a silicon substrate.

[0033] The substrate 100 can include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 can extend in the second direction D2. For example, the first active region AR1 can be an NMOSFET region, and the second active region AR2 can be a PMOSFET region.

[0034] The substrate 100 can include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be provided on the first active region AR1, and the second active pattern AP2 can be provided on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 can be defined by a trench TR formed in the substrate 100. The first active pattern AP1 and the second active pattern AP2 can extend in the second direction D2.

[0035] ​According to embodiments of the inventive concept, the rest of the substrate 100 except for the first active pattern AP1 and the second active pattern AP2 can be removed by a planarization process. Accordingly, the first active pattern AP1 and the second active pattern AP2 of the substrate 100 can be left. That is, the thickness of the first active pattern AP1 and the second active pattern AP2 can be substantially the same as the thickness of the substrate 100. For example, the upper surface 100U of the substrate 100 can correspond to the upper surfaces of the first active pattern AP1 and the second active pattern AP2. The lower surface 100L of the substrate 100 can correspond to the lower surfaces of the first active pattern AP1 and the second active pattern AP2. For example, when the rest of the substrate 100 is removed leaving the first active pattern AP1 and the second active pattern AP2, the thickness of the substrate 100 can be reduced. Accordingly, the semiconductor device can be miniaturized.

[0036] A device isolation layer ST can be disposed between the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can fill the trench TR. A lower surface STL of the device isolation layer ST can be substantially coplanar with the lower surfaces of the first active pattern AP1 and the second active pattern AP2. For example, the lower surface STL of the device isolation layer ST can be located at substantially the same height as the lower surface 100L of the substrate 100. For example, the device isolation layer ST can include a silicon oxide layer. The device isolation layer ST can not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described later.

[0037] The first channel pattern CH1 can be disposed on the first active pattern AP1. The second channel pattern CH2 can be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 can include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3, which are sequentially stacked on the first active pattern AP1 and the second active pattern AP2. The first to third semiconductor patterns SP1, SP2, and SP3 can be spaced apart from each other in a vertical direction (e.g., the third direction D3).

[0038] Each of the first to third semiconductor patterns SP1, SP2, and SP3 can include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 can include crystalline silicon, and more particularly, single crystalline silicon. Further, the first to third semiconductor patterns SP1, SP2, and SP3 can be stacked nanosheets.

[0039] A plurality of first source / drain patterns SD1 can be disposed on the first active pattern AP1. A plurality of first recesses RS1 can be formed on an upper portion of the first active pattern AP1. Each of the first source / drain patterns SD1 can be disposed in the first recess RS1, respectively. The first source / drain pattern SD1 can be an impurity region having a first conductivity type (e.g., n-type). A first channel pattern CH1 can be disposed between the first source / drain patterns SD1 adjacent to each other in the second direction D2. For example, the stacked first to third semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1 can connect the first source / drain patterns SD1 adjacent to each other in the second direction D2.

[0040] A plurality of second source / drain patterns SD2 can be disposed on the second active pattern AP2. A plurality of second recesses RS2 can be formed on an upper portion of the second active pattern AP2. Each of the second source / drain patterns SD2 can be disposed in the second recess RS2, respectively. The second source / drain pattern SD2 can be an impurity region having a second conductivity type (e.g., p-type). A second channel pattern CH2 can be disposed between the second source / drain patterns SD2 adjacent to each other in the second direction D2. For example, the stacked first to third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 can connect the second source / drain patterns SD2 adjacent to each other in the second direction D2.

[0041] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be an epitaxial pattern formed through a selective epitaxial growth (SEG) process. For example, an upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than an upper surface of the third semiconductor pattern SP3. Also, an upper surface of at least one of the first source / drain pattern SD1 and / or the second source / drain pattern SD2 can be located at substantially the same height as the upper surface of the third semiconductor pattern SP3.

[0042] For example, the first source / drain pattern SD1 can include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 can include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Accordingly, the second source / drain patterns SD2 adjacent to each other in the second direction D2 can provide a compressive stress to the second channel pattern CH2 located between the second source / drain patterns SD2.

[0043] For example, the sidewall of the second source / drain pattern SD2 can have a non-uniform relief shape. For example, the sidewall of the second source / drain pattern SD2 can have a wavy profile. The sidewall of the second source / drain pattern SD2 can protrude toward the first to third inner electrodes PO1, PO2 and PO3 of the gate electrode GE, which will be described later.

[0044] The gate electrodes GE can be disposed on the first and second channel patterns CH1 and CH2. Each of the gate electrodes GE can extend across the first and second channel patterns CH1 and CH2 in the first direction D1. Each of the gate electrodes GE can vertically overlap the first and second channel patterns CH1 and CH2. The gate electrodes GE can be spaced apart from each other in the second direction D2.

[0045] Each of the gate electrodes GE can include a first inner electrode PO1, a second inner electrode PO2, a third inner electrode PO3, and an outer electrode PO4. The first inner electrode PO1 can be disposed between the first active pattern AP1 and the first semiconductor pattern SP1, and between the second active pattern AP2 and the first semiconductor pattern SP1. The second inner electrode PO2 can be disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third inner electrode PO3 can be disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and the outer electrode PO4 can be disposed on the third semiconductor pattern SP3.

[0046] Each of the gate electrodes GE can be disposed on the upper surface, the lower surface, and the two sidewalls of each of the first to third semiconductor patterns SP1, SP2 and SP3. For example, the transistor according to an embodiment of the inventive concept can be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0047] On the first active region AR1, an inner spacer ISP can be disposed between the first to third inner electrodes PO1, PO2 and PO3 of the gate electrode GE and the first source / drain pattern SD1. Each of the first to third inner electrodes PO1, PO2 and PO3 of the gate electrode GE can be spaced apart from the first source / drain pattern SD1 by the inner spacer ISP therebetween. The inner spacer ISP can prevent a leakage current from the gate electrode GE.

[0048] A pair of gate spacers GS can be disposed on both sidewalls of the outer electrode PO4 of each of the gate electrodes GE. The gate spacers GS can extend along the gate electrodes GE in the first direction D1. For example, the gate spacers GS can include at least one of SiCN, SiCON, and / or SiN. Also, the gate spacers GS can include a multi-layer made of at least two of SiCN, SiCON, and SiN. For example, the gate spacers GS can include a Si-containing insulating material. The gate spacers GS can act as an etch stop layer when forming the active contact AC, which will be described later. The active contact AC can be formed in a self-aligned manner by the gate spacers GS.

[0049] A gate capping pattern GP can be disposed on each of the gate electrodes GE, respectively. Each of the gate capping patterns GP can extend along the gate electrodes GE in the first direction D1. The gate capping pattern GP can include a material having etch selectivity with respect to the first and second upper insulating layers 110 and 120, which will be described later. For example, the gate capping pattern GP can include at least one of SiON, SiCN, SiCON, and SiN.

[0050] A gate insulating layer GI can be disposed between the gate electrodes GE and the first and second channel patterns CH1 and CH2. The gate insulating layer GI can cover the upper surface, the lower surface, and both sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI can cover the upper surface of the device isolation layer ST located under the gate electrodes GE. For example, the gate insulating layer GI can include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. Also, the gate insulating layer GI can have a structure in which the silicon oxide layer and the high-k dielectric layer are stacked with each other. The high-k dielectric layer can include a high dielectric constant material having a higher dielectric constant than that of the silicon oxide layer. As an example, the high dielectric constant material includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0051] According to an embodiment of the inventive concept, a semiconductor device can include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI can include a ferroelectric material layer having a ferroelectric property and a paraelectric material layer having a paraelectric property.

[0052] The ferroelectric layer can have a negative capacitance, and the paraelectric layer can have a positive capacitance. When two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance can decrease to a value smaller than the capacitance of each capacitor. Also, when at least one of the series capacitors has a negative capacitance, the total capacitance of the series capacitors can have a positive value and can be greater than the absolute value of each capacitance.

[0053] When a ferroelectric layer having a negative capacitance and a paraelectric layer having a positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric layer and paraelectric layer can increase. Due to this increase in the total capacitance, a transistor including the ferroelectric layer can have a sub-threshold swing (SS) of less than about 60 mV / decade at room temperature.

[0054] The ferroelectric layer can have ferroelectric characteristics. The ferroelectric layer can be formed of or include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, the hafnium zirconium oxide can be hafnium oxide doped with zirconium (Zr). Also, the hafnium zirconium oxide can be a compound including hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0055] The ferroelectric layer can further include a dopant. For example, the dopant can include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The kind of the dopant in the ferroelectric layer can be variously changed depending on a ferroelectric material included in the ferroelectric layer.

[0056] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer can include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0057] When the dopant is aluminum (Al), the content of aluminum in the ferroelectric layer can be in a range of about 3 at% (atomic percent) to about 8 at%. Here, the content of aluminum as the dopant can be a ratio of the number of aluminum atoms to the number of hafnium and aluminum atoms.

[0058] When the dopant is silicon (Si), the content of silicon in the ferroelectric layer can be in a range of about 2 at% to about 10 at%. When the dopant is yttrium (Y), the content of yttrium in the ferroelectric layer can be in a range of about 2 at% to about 10 at%. When the dopant is gadolinium (Gd), the content of gadolinium in the ferroelectric layer can be in a range of about 1 at% to about 7 at%. When the dopant is zirconium (Zr), the content of zirconium in the ferroelectric layer can be in a range of about 50 at% to about 80 at%.

[0059] The paraelectric layer can have a paraelectric characteristic. The paraelectric layer can be formed of or include at least one of, for example, silicon oxide and / or a high-k metal oxide. The metal oxide, which can be used as the paraelectric layer, can include at least one of, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited thereto.

[0060] The ferroelectric layer and the paraelectric layer can be formed of or include the same material as each other. The ferroelectric layer can have a ferroelectric characteristic, but the paraelectric layer can not have a ferroelectric characteristic. For example, when the ferroelectric layer and the paraelectric layer each include hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer can be different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0061] The ferroelectric layer can have a predetermined thickness that exhibits a ferroelectric characteristic. In an embodiment of the inventive concept, the thickness of the ferroelectric layer can be in the range of about 0.5 nm to about 10 nm, but the inventive concept is not limited thereto. Since the thickness associated with the occurrence of a ferroelectric characteristic varies depending on the kind of ferroelectric material, the thickness of the ferroelectric layer can vary depending on the kind of ferroelectric material.

[0062] As an example, the gate insulating layer GI can include a single ferroelectric layer. As another example, the gate insulating layer GI can include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI can have a multi-layer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked with each other.

[0063] The first upper insulating layer 110 can be disposed on the substrate 100. The first upper insulating layer 110 can cover the gate spacers GS as well as the first and second source / drain patterns SD1 and SD2. For example, the first upper insulating layer 110 can cover the upper surfaces of the source / drain patterns SD1 and SD2 and the side surfaces of the gate spacers GS. The upper surface of the first upper insulating layer 110 can be substantially coplanar with the upper surface of the gate capping pattern GP and the upper surface of the gate spacers GS, but the inventive concept is not limited thereto.

[0064] The second, third, and fourth upper insulating layers 120, 130, and 140 can be sequentially disposed on the first upper insulating layer 110. For example, the first to fourth upper insulating layers 110, 120, 130, and 140 can include silicon oxide layers.

[0065] A pair of separation structures DB facing each other in the second direction D2 can be disposed at both sides (e.g., opposite sides) of the logic cell LC. Each of the separation structures DB can extend in parallel with the gate electrode GE in the first direction D1. Each of the separation structures DB can penetrate the first upper insulating layer 110 and the second upper insulating layer 120, and can extend into the first active pattern API and the second active pattern AP2. The separation structures DB can penetrate a portion of each of the first active pattern API and the second active pattern AP2. The separation structures DB can electrically separate the logic cell LC from other adjacent cells (e.g., logic cells and tap cells).

[0066] An active contact AC can be disposed that penetrates the first upper insulating layer 110 and the second upper insulating layer 120, and is electrically connected to some of the first source / drain patterns SD1 and the second source / drain patterns SD2. Each of the active contacts AC can have a strip shape, or a cuboid shape extending in the first direction D1 when viewed in a plan view. For example, each of the active contacts AC can include a conductive pattern and a barrier pattern surrounding the conductive pattern. The barrier pattern can cover sidewalls and a bottom surface of the conductive pattern.

[0067] A metal-semiconductor compound layer SC can be disposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. Each of the active contacts AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC can include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0068] A gate contact GC can be disposed that penetrates the second upper insulating layer 120 and the gate capping pattern GP, and is electrically connected to the gate electrode GE. Each of the gate contacts GC can include a conductive pattern and a barrier pattern at least partially surrounding the conductive pattern. For example, the gate contacts GC can have substantially the same structure as the active contacts AC. Each of the gate contacts GC can be disposed to overlap the first active region AR1 and the second active region AR2, respectively, when viewed in a plan view.

[0069] The first metal layer M1 can be disposed in the third upper insulating layer 130. For example, the first metal layer M1 can include a first power line M1_R1, a second power line M1_R2, and a first line M1_I. Each of the metal lines M1_R1, M1_R2, and M1_I of the first metal layer M1 can extend in parallel to each other in the second direction D2. The metal lines M1_R1, M1_R2, and M1_I of the first metal layer M1 can be spaced apart from each other in the first direction D1.

[0070] The first line M1_I of the first metal layer M1 can be disposed between the first power line M1_R1 and the second power line M1_R2. The first line M1_I of the first metal layer M1 can be spaced apart from each other in the first direction D1. A line width of each of the first lines M1_I can be smaller than a line width of each of the first power line M1_R1 and the second power line M1_R2. For example, a length of each of the first lines M1_I in the second direction D2 can be smaller than a length of each of the first power line M1_R1 and the second power line M1_R2 in the second direction D2.

[0071] The first metal layer M1 can further include a first via VI1. The first via VI1 can be disposed under the metal lines M1_R1, M1_R2, and M1_I of the first metal layer M1. The active contact AC, the gate contact GC, and the metal lines M1_R1, M1_R2, and M1_I of the first metal layer M1 can be electrically connected to each other through the first via VI1.

[0072] The second metal layer M2 can be disposed in the fourth upper insulating layer 140. The second metal layer M2 can include a plurality of second lines M2_I. Each of the second lines M2_I of the second metal layer M2 can have a line shape, a bar shape, or a cuboid shape extending in the first direction D1. For example, each of the second lines M2_I can extend in parallel to each other in the first direction D1. The second lines M2_I can be spaced apart from each other in the second direction D2.

[0073] The second metal layer M2 can include a second via VI2 disposed under each of the second lines M2_I. The metal lines M1_R1, M1_R2, and M1_I of the first metal layer M1 and the second lines M2_I of the second metal layer M2 can be electrically connected to each other through the second via VI2. For example, the second line M2_I of the second metal layer M2 and the second via VI2 located under the second line M2_I can be formed together through a dual damascene process.

[0074] A power delivery network layer PDN can be disposed on the lower surface 100L of the substrate 100. The power delivery network layer PDN can include a first lower insulating layer 160 and a second lower insulating layer 170, a first lower via LVI1 and a second lower via LVI2, and a first lower interconnect LM1 and a second lower interconnect LM2. The first lower via LV1 and the second lower via LV2 can be electrically connected to the first lower interconnect LM1 and the second lower interconnect LM2. The first lower via LV1 and the first lower interconnect LM1 can be disposed in the first lower insulating layer 160. The second lower via LV2 and the second lower interconnect LM2 can be disposed in the second lower insulating layer 170. For example, the first lower via LV1 can be disposed on the first lower interconnect LM1 and the second lower via LV2 can be disposed on the second lower interconnect LM2.

[0075] An interlayer insulating layer 150 can be disposed between the substrate 100 and the power delivery network layer PDN. For example, the interlayer insulating layer 150 can be in contact with the lower surface 100L of the substrate 100 and the device isolation layer ST. For example, the interlayer insulating layer 150, as well as the first lower insulating layer 160 and the second lower insulating layer 170, can include a silicon oxide layer.

[0076] A back contact BAC can be disposed that penetrates the interlayer insulating layer 150 and the substrate 100 and can extend to the first source / drain pattern SD1 and the second source / drain pattern SD2. The back contact BAC can be connected to some of the first source / drain pattern SD1 and the second source / drain pattern SD2. The back contact BAC can be connected to the first lower via LV1 of the power delivery network layer PDN. The back contact BAC can be electrically connected to the first lower interconnect LM1 and the second lower interconnect LM2 through the first lower via LV1 and the second lower via LV2.

[0077] FIG. 6 FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment of the present inventive concept. FIGS. 7A-9B FIG. 2 is a cross-sectional view for illustrating the semiconductor device according to the embodiment of the present inventive concept. FIG. 7A 、 FIG. 8A and FIG. 9A are cross-sectional views taken along lines E-E' of FIG. 6 , FIG. 7B 、 FIG. 8B and FIG. 9B are cross-sectional views taken along lines F-F' of FIG. 6 .

[0078] Hereinafter, descriptions of technical features overlapping or briefly discussed with reference to technical features described with reference to FIG. 4 and FIGS. 5A-5D will be omitted or briefly discussed, and differences will be mainly described in detail.

[0079] Referring toFIG. 6 、 FIG. 7A and FIG. 7B The substrate 100 including the tapping unit TC can be provided. The tapping unit TC can be substantially the same as the tapping unit TC described with reference to FIG. 3 The logic transistors constituting a logic circuit can not be provided on the tapping unit TC.

[0080] The substrate 100 can include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 can extend in a second direction D2. For example, the first active region AR1 can be an NMOSFET region, and the second active region AR2 can be a PMOSFET region. Further, the substrate 100 can include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be provided on the first active region AR1, and the second active pattern AP2 can be provided on the second active region AR2.

[0081] A device isolation layer ST can be provided adjacent to the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be provided on side surfaces of the first active pattern AP1 and the second active pattern AP2. Further, the device isolation layer ST can be provided between the first active pattern AP1 and the second active pattern AP2, as shown in FIG. 5D A lower surface STL of the device isolation layer ST can be substantially coplanar with lower surfaces of the first active pattern AP1 and the second active pattern AP2. For example, the lower surface STL of the device isolation layer ST can be located at substantially the same height as a lower surface 100L of the substrate 100. For example, the device isolation layer ST can include a silicon oxide layer.

[0082] A stack pattern STP can be provided on each of the first active pattern AP1 and the second active pattern AP2. Each of the stack patterns STP can include an active layer ACL and a sacrificial layer SAL. The active layers ACL and the sacrificial layers SAL can be stacked alternately with each other. For example, the active layers ACL can be spaced apart from each other in a vertical direction, and the sacrificial layers SAL can be spaced apart from each other in the vertical direction. The active layers ACL can include substantially the same material as the materials of the first to third semiconductor patterns SP1, SP2, and SP3 described with reference to FIGS. 5A-5D

[0083] A sacrificial pattern PP can be provided on the stack pattern STP. The sacrificial pattern PP can cover upper and side surfaces of the stack pattern STP and the device isolation layer ST. For example, the sacrificial pattern PP can cover the upper surface of the device isolation layer ST. For example, the sacrificial pattern PP can include polysilicon. A second upper insulating layer 120 can be provided on the sacrificial pattern PP.

[0084] ​According to an embodiment of the inventive concept, the reference FIGS. 5A-5D The gate electrode GE can not be provided, for example, since the sacrificial layer SAL and the sacrificial pattern PP are retained in the tap cell TC.

[0085] The separation structures DB can be provided in the tap cell TC. Each of the separation structures DB can extend in the first direction D1. The separation structures DB can be spaced apart from each other in the second direction D2. Each of the separation structures DB can extend through the second upper insulating layer 120, the sacrificial pattern PP, and the stack pattern STP into the first and second active patterns AP1 and AP2. According to an embodiment of the inventive concept, the separation structures DB can not be provided at the center of the tap cell TC. According to an embodiment of the inventive concept, only one pair of the separation structures DB can be provided at both sides of the tap cell TC. The separation structures DB can be provided in the tap cell TC in various ways, for example.

[0086] A via TVI can be provided, which extends from the second upper insulating layer 120 to an interlayer insulating layer 150 provided on a lower surface 100L of the substrate 100. The via TVI can be located at the center of the tap cell TC when viewed in a plan view. The via TVI can be provided between the separation structures DB. The separation structures DB can be provided at both sides (e.g., opposite sides) of the via TVI, for example, but the inventive concept is not limited thereto. The via TVI can include a first via TVI1 and a second via TVI2 provided below the first via TVI1. The first and second vias TVI1 and TVI2 can be in contact with each other to form an interface TVIF.

[0087] The first via TVI1 can extend through the second upper insulating layer 120, the sacrificial pattern PP, and the stack pattern STP toward the upper surface 100U of the substrate 100. The first via TVI1 can penetrate a portion of the first and second active patterns AP1 and AP2. In addition, the first via TVI1 can penetrate a portion of the device isolation layer ST between the first and second active patterns AP1 and AP2. For example, a bottom surface of the first via TVI1 can be provided below upper surfaces of the first and second active patterns AP1 and AP2. That is, the bottom surface of the first via TVI1 can be lower than the upper surface 100U of the substrate 100. The first via TVI1 can have a width that decreases from a top portion to a bottom portion thereof. For example, the first via TVI1 can have an inverse taper shape. The width of the first via TVI1 can decrease as the first via TVI1 approaches the upper surface 100U of the substrate 100, for example.

[0088] The first via TVI1 can include a first metal pattern MP1 and a first barrier pattern BP1 in contact with the first metal pattern MP1. The first barrier pattern BP1 can cover a lower surface and a side surface of the first metal pattern MP1. That is, the first barrier pattern BP1 can extend along the side surface of the first metal pattern MP1 to the lower surface of the first metal pattern MP1. The first barrier pattern BP1 can prevent or reduce diffusion of elements constituting the first metal pattern MP1. For example, the first metal pattern MP1 can include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and / or cobalt (Co). The first barrier pattern BP1 can be a metal layer including at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and / or platinum (Pt) or a metal nitride layer including at least one of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), and / or a platinum nitride layer (PtN).

[0089] The second via TVI2 can extend through the interlayer insulation layer 150 toward the upper surface 100U of the substrate 100. The second via TVI2 can penetrate a portion of the first active pattern AP1 and the second active pattern AP2. In addition, the second via TVI2 can penetrate a portion of the device isolation layer ST between the first active pattern AP1 and the second active pattern AP2. For example, an upper surface of the second via TVI2 can be located below the upper surface 100U of the substrate 100 (or an upper surface of the first active pattern AP1 and the second active pattern AP2). Unlike the first via TVI1, the second via TVI2 can have a width that increases from a top portion to a bottom portion thereof. For example, the second via TVI2 can have a taper shape. For example, the width of the second via TVI2 can decrease as the second via TVI2 approaches the upper surface 100U of the substrate 100.

[0090] The second via TVI2 and the first via TVI1 can contact each other in the substrate 100. Accordingly, an interface TVIF between the first via TVI1 and the second via TVI2 can be disposed in the substrate 100. For example, the interface TVIF between the first via TVI1 and the second via TVI2 can be adjacent to the upper surface 100U of the substrate 100 among the upper surface 100U and the lower surface 100L of the substrate 100.

[0091] The second via hole TVI2 can include a second metal pattern MP2 and a second barrier pattern BP2 in contact with the second metal pattern MP2. The second barrier pattern BP2 can cover the upper surface and the side surface of the second metal pattern MP2. For example, the second barrier pattern BP2 can extend along the side surface of the second metal pattern MP2 to the upper surface of the second metal pattern MP2. Accordingly, the second barrier pattern BP2 can be in contact with the first barrier pattern BP1. For example, since the first barrier pattern BP1 and the second barrier pattern BP2 are disposed between the first metal pattern MP1 and the second metal pattern MP2, the first metal pattern MP1 and the second metal pattern MP2 can be spaced apart from each other. Each of the second metal pattern MP2 and the second barrier pattern BP2 can include substantially the same material as the first metal pattern MP1 and the first barrier pattern BP1, but the inventive concept is not limited thereto. For example, the first metal pattern MP1 and the second metal pattern MP2 can include different metal materials from each other.

[0092] The first metal layer M1 can be disposed in the third upper insulating layer 130. The second metal layer M2 can be disposed in the fourth upper insulating layer 140. The first metal layer M1 can include a giant via hole GVI between the first line M1_I and the via hole TVI. The giant via hole GVI can connect the first line M1_I and the first via hole TVI1 to each other. In this case, a signal can be transmitted to the logic unit adjacent to the tapping unit TC through the via hole TVI.

[0093] According to one embodiment of the inventive concept, the giant via hole GVI can be connected to at least one of the first power line M1_R1 and / or the second power line M1_R2 of the first metal layer M1. The giant via hole GVI can connect at least one of the first power line M1_R1 and / or the second power line M1_R2 to the first via hole TVI1. In this case, a voltage can be applied to the logic unit adjacent to the tapping unit TC through the via hole TVI.

[0094] For example, the via hole TVI can be electrically connected to the first metal layer M1 and the second metal layer M2 through the giant via hole GVI. Accordingly, a signal or a voltage can be transmitted or applied to the logic unit adjacent to the tapping unit TC through the via hole TVI.

[0095] The power delivery network layer PDN can be disposed on the lower surface 100L of the substrate 100. A first lower via hole LV1 of the power delivery network layer PDN can be disposed between one of the via holes TVI and the first lower interconnect LM1. The first lower via hole LV1 can connect one of the first lower interconnects LM1 to the second via hole TVI2. In other words, the via hole TVI can be electrically connected to the power delivery network layer PDN through the first lower via hole LV1. For example, the via hole TVI can electrically connect the power delivery network layer PDN with the first metal layer M1 and the second metal layer M2 to each other.

[0096] Referring to FIG. 6 , FIG. 8A and FIG. 8B , the first via TVI1 of the via TVI can include a first metal pattern MP1 and a first barrier pattern BP1. The second via TVI2 of the via TVI can include a second metal pattern MP2 and a second barrier pattern BP2.

[0097] The first via TVI1 can extend through the second upper insulating layer 120, the sacrificial pattern PP, and the stack pattern STP toward the upper surface 100U of the substrate 100. The first via TVI1 can not penetrate the first and second active patterns AP1 and AP2, and the device isolation layer ST disposed between the first and second active patterns AP1 and AP2. For example, a bottom surface of the first via TVI1 can be located at substantially the same height as an upper surface of the first and second active patterns AP1 and AP2. For example, the bottom surface of the first via TVI1 can be substantially co-planar with the upper surface 100U of the substrate 100.

[0098] The first barrier pattern BP1 of the first via TVI1 can not extend onto a lower surface of the first metal pattern MP1. For example, the lower surface of the first metal pattern MP1 can not be covered by the first barrier pattern BP1. For example, the first barrier pattern BP1 can be disposed only on side surfaces of the first metal pattern MP1. The first barrier pattern BP1 can not be disposed between the first and second metal patterns MP1 and MP2.

[0099] The second via TVI2 can extend through the interlayer insulating layer 150 toward the upper surface 100U of the substrate 100. The second via TVI2 can penetrate the first and second active patterns AP1 and AP2. In addition, the second via TVI2 can penetrate the device isolation layer ST disposed between the first and second active patterns AP1 and AP2. For example, an upper surface of the second via TVI2 can be disposed on substantially the same plane as the upper surface 100U of the substrate 100 (or the upper surfaces of the first and second active patterns AP1 and AP2).

[0100] Unlike the first barrier pattern BP1, the second barrier pattern BP2 of the second via TVI2 can extend onto an upper surface of the second metal pattern MP2. For example, the second barrier pattern BP2 can be disposed on side surfaces and the upper surface of the second metal pattern MP2. The second barrier pattern BP2 can be disposed between the first and second metal patterns MP1 and MP2. The second barrier pattern BP2 can be in contact with a portion of the first metal pattern MP1. The first and second metal patterns MP1 and MP2 can be spaced apart from each other by the second barrier pattern BP2.

[0101] The first via TVI1 and the second via TVI2 can contact each other at substantially the same height as the upper surface 100U of the substrate 100. Thus, an interface TVIF between the first via TVI1 and the second via TVI2 can be substantially coplanar with the upper surface 100U of the substrate 100.

[0102] Referring to FIG. 6 , FIG. 9A and FIG. 9B , the first via TVI1 can include the first metal pattern MP1 and a first barrier pattern BP1 on a side surface of the first metal pattern MP1. The second via TVI2 can include the second metal pattern MP2 and a second barrier pattern BP2 on a side surface of the second metal pattern MP2.

[0103] The first via TVI1 can extend toward the upper surface 100U of the substrate 100 through the second upper insulating layer 120, the sacrificial pattern PP, and a portion of the stack pattern STP. For example, a bottom surface of the first via TVI1 can be disposed in the stack pattern STP. For example, the bottom surface of the first via TVI1 can be higher than the upper surface 100U of the substrate 100.

[0104] The second via TVI2 can extend toward the upper surface 100U of the substrate 100 through the interlayer insulating layer 150. The second via TVI2 can penetrate the first active pattern AP1 and the second active pattern AP2, and the device isolation layer ST disposed between the first active pattern AP1 and the second active pattern AP2. Further, the second via TVI2 can penetrate the remaining portion of the stack pattern STP. For example, an upper surface of the second via TVI2 can be higher than the upper surface 100U of the substrate 100 (or the upper surfaces of the first active pattern AP1 and the second active pattern AP2).

[0105] The first barrier pattern BP1 of the first via TVI1 can not extend onto a lower surface of the first metal pattern MP1. Further, the second barrier pattern BP2 of the second via TVI2 can not extend onto an upper surface of the second metal pattern MP2. For example, the first barrier pattern BP1 can be disposed only on a side surface of the first metal pattern MP1, and the second barrier pattern BP2 can be disposed only on a side surface of the second metal pattern MP2. For example, the first barrier pattern BP1 and / or the second barrier pattern BP2 can not be disposed between the first metal pattern MP1 and the second metal pattern MP2. Thus, the first metal pattern MP1 and the second metal pattern MP2 can contact each other.

[0106] The first via TVI1 and the second via TVI2 can contact each other at a height higher than the upper surface 100U of the substrate 100. Thus, the interface TVIF between the first via TVI1 and the second via TVI2 can be higher than the upper surface 100U of the substrate 100. For example, the interface TVIF between the first via TVI1 and the second via TVI2 can be provided in the stack pattern STP.

[0107] Referring again to FIG. 6 and FIGS. 7A-9B , the first via TVI1 and the mega-via GVI can be formed on the upper surface 100U of the substrate 100, and the second via TVI2 and the first lower via LV1 can be formed on the lower surface 100L of the substrate 100. For example, after the first via TVI1 is formed, the second via TVI2 can be formed to contact the first via TVI1. That is, the first via TVI1 and the second via TVI2 of the via TVI can be formed separately by different processes. Thus, misalignment of the via TVI with the mega-via GVI and / or the first lower via LV1 can be prevented.

[0108] Further, a difference between a height of the first via TVI1 in the third direction D3 and a height of the second via TVI2 in the third direction D3 can be relatively small. For example, the height of the first via TVI1 can be about 0.5 to about 2.0 times the height of the second via TVI2. The interface TVIF between the first via TVI1 and the second via TVI2 can be provided closer to the upper surface 100U of the substrate 100 than to the lower surface 100L of the substrate 100. Since the first via TVI1 and the second via TVI2 are formed at similar heights, a metal material can be easily formed in the via TVI having a large aspect ratio without voids. Thus, the electrical characteristics and reliability of the semiconductor device can be improved.

[0109] FIG. 10 and FIG. 11 is a plan view showing an arrangement of a tapping unit of a semiconductor device according to an embodiment of the inventive concept.

[0110] Referring again to FIG. 10 , a semiconductor device according to an embodiment of the inventive concept can be manufactured based on a designed layout. For example, a layout of the semiconductor device can be created using a layout design tool.

[0111] The first power line M1_R1 and the second power line M1_R2 can be arranged on the layout. For example, the first power line M1_R1 can define a path of a drain voltage VDD, and the second power line M1_R2 can define a path of a source voltage VSS. The first power line M1_R1 and the second power line M1_R2 can be alternately arranged at a substantially constant pitch in the first direction D1. Each of the first power line M1_R1 and the second power line M1_R2 can extend in the second direction D2.

[0112] The logic cells LC, the tap cells TC, and the fill cells FC can be arranged between the first power line M1_R1 and the second power line M1_R2. The logic cells LC can include at least one single-height cell SHC, at least one double-height cell DHC, and at least one triple-height cell THC. The single-height cells SHC can be substantially the same as described with reference to FIG. 1 The double-height cells DHC and the triple-height cells THC can be substantially the same as described with reference to FIG. 2 The double-height cells DHC and the triple-height cells THC can be substantially the same as described with reference to

[0113] The tap cells TC can be arranged to be spaced apart from the logic cells LC. Each of the tap cells TC can be substantially the same as described with reference to FIG. 6 and FIGS. 7A-9B The tap cells TC can be arranged to be spaced apart from the logic cells LC. Each of the tap cells TC can be substantially the same as described with reference to

[0114] Each of the fill cells FC can be arranged between adjacent logic cells LC. The fill cells FC can fill a blank space between the logic cells LC. For example, the fill cells FC can be dummy cells.

[0115] The double-height cells DHC and the triple-height cells THC can be substantially the same as described with reference to FIG. 11 The first power line M1_R1 and the second power line M1_R2 can be arranged on the layout. The first power line M1_R1 and the second power line M1_R2 can be arranged at a substantially constant pitch in the first direction D1. Each of the first power line M1_R1 and the second power line M1_R2 can extend in the second direction D2.

[0116] Passive units and tap units TC can be disposed between the first electric field line M1_R1 and the second electric field line M1_R2. The passive units may include a first passive unit PC1 and a second passive unit PC2. The first passive unit PC1 and the second passive unit PC2 may be spaced apart from each other in the second direction D2. A separation structure DB may be disposed on both sides of each of the first passive unit PC1 and the second passive unit PC2. Each of the first passive unit PC1 and the second passive unit PC2 may include a gate electrode GE, an active region AR, and an active contact AC. Each of the first passive unit PC1 and the second passive unit PC2 may include a three-dimensional field-effect transistor, which has a reference... FIGS. 5A-5D The length of the channel is the length of the long channel.

[0117] Tap unit TC can be located between the first passive unit PC1 and the second passive unit PC2. Tap unit TC can be connected to a reference. FIG. 6 and FIGS. 7A-9B The tap units TC are essentially the same. For example, the tap unit TC can send signals or apply voltages to adjacent first passive unit PC1 and second passive unit PC2.

[0118] FIGS. 12A-16B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention. FIG. 12A , FIG. 13A , FIG. 14A , FIG. 15A and FIG. 16A It is along FIG. 6 The cross-sectional view taken by line E-E', and FIG. 12B , FIG. 13B , FIG. 14B , FIG. 15B and FIG. 16B It is along FIG. 6 The cross-sectional view taken by line F-F'.

[0119] Reference FIG. 12A and FIG. 12B A substrate 100 may be provided, comprising a first active region AR1 and a second active region AR2. An active layer ACL and a sacrificial layer SAL may be alternately stacked on the upper surface 100U of the substrate 100. The active layer ACL may, for example, comprise one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the sacrificial layer SAL may comprise another of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0120] The sacrificial layers SAL can include a material having etch selectivity with respect to the active layers ACL. For example, the active layers ACL can include silicon (Si), and the sacrificial layers SAL can include silicon-germanium (SiGe). The concentration of germanium (Ge) in each of the sacrificial layers SAL can be about 10 at% to about 30 at%.

[0121] Each of the mask patterns can be formed on the first active region AR1 and the second active region AR2 of the substrate 100, respectively. Each of the mask patterns can have a linear, bar, or cuboid shape extending in the second direction D2. An etching process using the mask patterns can be performed to form trenches TR defining the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 can be formed on the first active region AR1. The second active pattern AP2 can be formed on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 can have a linear shape extending in parallel to each other in the second direction D2 when viewed in a plan view.

[0122] The stack pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. Each of the stack patterns STP can include the active layers ACL and the sacrificial layers SAL alternately stacked on the active patterns AP1 and AP2. For example, the stack pattern STP can be formed by an etching process to form the first active pattern AP1 and the second active pattern AP2.

[0123] Thereafter, a device isolation layer ST can be formed to fill the trenches TR. For example, an insulating layer covering the first active pattern AP1 and the second active pattern AP2 and the stack pattern STP can be formed on the upper surface 100U of the substrate 100, and the insulating layer can be recessed to form the device isolation layer. The stack pattern STP can be exposed on the device isolation layer ST. In other words, the stack pattern STP can vertically protrude above the device isolation layer ST and can not be covered by the stack pattern STP. The device isolation layer ST can include an insulating material such as a silicon oxide layer.

[0124] Referring to FIG. 13A and FIG. 13B , a sacrificial pattern PP can be formed on the substrate 100 to cover the stack pattern STP. The sacrificial pattern PP can cover the upper surface and the side surface of the stack pattern STP. For example, the sacrificial pattern PP can be in contact with the device isolation layer ST. A second upper insulating layer 120 can be formed on the sacrificial pattern PP. For example, the second upper insulating layer 120 can include a silicon oxide layer.

[0125] Thereafter, a separation structure DB can be formed to penetrate the second upper insulating layer 120, the sacrificial pattern PP, and the stack pattern STP. The separation structure DB can extend from the second upper insulating layer 120 to the first active pattern AP1 by penetrating the stack pattern STP. The separation structure DB can include an insulating material such as a silicon oxide layer or a silicon nitride layer.

[0126] In the case of the logic cell LC described with reference to FIG. 4 and FIGS. 5A-5D The sacrificial pattern PP can be formed in a linear, bar, or cuboid shape extending in the first direction D1. FIG. 5A and FIG. 5B The first and second recesses RS1 and RS2 can be formed by using the sacrificial pattern PP, and the first and second source / drain patterns SD1 and SD2 can be formed in the first and second recesses RS1 and RS2, respectively. Thereafter, the sacrificial pattern PP and the sacrificial layer SAL can be selectively removed, and the gate insulating layer GI and the gate electrode GE can be formed in spaces where the sacrificial pattern PP and the sacrificial layer SAL have been removed.

[0127] With reference to FIG. 14A and FIG. 14B A first via TVH1 penetrating the second upper insulating layer 120, the sacrificial pattern PP, and a portion of the stack pattern STP can be formed to expose the first and second active patterns AP1 and AP2. With reference to FIG. 4 and FIGS. 5A-5D The first via TVH1 can not be formed in the logic cell LC described with reference to

[0128] The first barrier pattern BP1 can be formed on an inner wall of the first via TVH1. The first metal pattern MP1 can be formed on the first barrier pattern BP1 in the first via TVH1. Forming the first barrier pattern BP1 and the first metal pattern MP1 can include forming a first barrier layer covering the inner wall of the first via TVH1 with a substantially uniform thickness, forming a first metal layer on the first barrier layer in the first via TVH1, and planarizing the first metal layer to expose the second upper insulating layer 120. Accordingly, the first barrier pattern BP1 can be formed of the first barrier layer, and the first metal pattern MP1 can be formed of the first metal layer. Accordingly, the first via TVH1 including the first metal pattern MP1 and the first barrier pattern BP1 can be formed in the first via TVH1.

[0129] Referring to FIG. 15A and FIG. 15B , a first metal layer M1 and a second metal layer M2 can be sequentially formed on the second upper insulating layer 120. The first metal layer M1 can include a first power line M1_R1 and a second power line M1_R2, a first line M1_I, and a giant via GVI in a third upper insulating layer 130. The second metal layer M2 can include a second line M2_I and a second via VI2 in a fourth upper insulating layer 140.

[0130] After the second metal layer M2 is formed, the carrier substrate can be bonded to the fourth upper insulating layer 140. The semiconductor device can be flipped by using the carrier substrate. Accordingly, the lower surface 100L of the substrate 100 can be located at a higher height than the upper surface 100U of the substrate 100. In addition, the lower surface 100L of the substrate 100 can be exposed to the outside.

[0131] Thereafter, a planarization process CMP can be performed on the substrate 100. By the planarization process CMP, the thickness of the substrate 100 can be reduced. The planarization process CMP can be performed until the lower surface STL of the device isolation layer ST is exposed. For example, the planarization process CMP can remove the remaining portion of the substrate 100 except for the first active pattern AP1 and the second active pattern AP2. The lower surface STL of the device isolation layer ST, the lower surfaces of the first active pattern AP1 and the second active pattern AP2, and the lower surface 100L of the substrate 100 can be substantially coplanar. Accordingly, the thickness of the substrate 100 can be substantially the same as the thickness of each of the first active pattern AP1 and the second active pattern AP2. Accordingly, the semiconductor device can be miniaturized.

[0132] Referring to FIG. 16A and FIG. 16B , an interlayer insulating layer 150 can be formed on the lower surface 100L of the substrate 100. A mask pattern can be formed on the interlayer insulating layer 150, and a second via TVH2 that penetrates the interlayer insulating layer 150 and the device isolation layer ST can be formed by an etching process using the mask pattern. Referring to FIG. 4 and FIGS. 5A-5D , the second via TVH2 can not be formed in the logic cell LC. The second via TVI2 can be disposed between the first active pattern AP1 and the second active pattern AP2, and between the separation structures DB adjacent to each other. The second via TVH2 can expose the first barrier pattern BP1 of the first via TVI1. The width of the second via TVH2 can decrease as the second via TVH2 approaches the upper surface 100U of the substrate 100.

[0133] The second barrier pattern BP2 can be formed on the inner wall of the second via TVH2. The second metal pattern MP2 can be formed on the second barrier pattern BP2 in the second via TVH2. Forming the second barrier pattern BP2 and the second metal pattern MP2 can be substantially the same as forming the first barrier pattern BP1 and the first metal pattern MP1. Accordingly, the second via TVI2 can be formed to contact the first via TVI1. For example, the height of the second via TVI2 can be about 0.5 to about 2.0 times the height of the first via TVI1.

[0134] Referring again to FIG. 7A and FIG. 7B , the power delivery network layer PDN can be formed on the interlayer insulating layer 150. Forming the power delivery network layer PDN can include forming the first lower insulating layer 160, and forming the first lower via LV1 and the first lower interconnect LM1 in the first lower insulating layer 160. Forming the power delivery network layer PDN can further include forming the second lower insulating layer 170 on the first lower insulating layer 160, and forming the second lower via LV2 and the second lower interconnect LM2 in the second lower insulating layer 170.

[0135] After forming the power delivery network layer PDN, the semiconductor device can be flipped again, and the carrier substrate located on the fourth upper insulating layer 140 can be removed.

[0136] According to embodiments of the inventive concept, the rest of the substrate 100 except for the first active pattern AP1 and the second active pattern AP2 can be removed through a planarization process. Accordingly, the thickness of the first active pattern AP1 and the second active pattern AP2 can be substantially the same as the thickness of the substrate 100. Accordingly, the thickness of the substrate 100 can become thinner.

[0137] Further, the first via TVI1 and the giant via GVI can be formed on the upper surface 100U of the substrate 100, and the second via TVI2 and the first lower via LV1 can be formed on the lower surface 100L of the substrate 100. The first via TVI1 and the second via TVI2 of the via TVI can be separately formed through different processes from each other, and can be formed to have similar heights to each other. Accordingly, the metal material can be easily formed in the via TVI having a higher aspect ratio without voids while preventing misalignment of the via TVI with the giant via GVI and / or the first lower via LV1. Accordingly, the electrical characteristics and reliability of the semiconductor device can be improved.

[0138] The remaining portion of the substrate of the semiconductor device according to the embodiment of the present inventive concept except for the active pattern can be removed by a planarization process. Accordingly, the thickness of the substrate can be reduced. Further, the first via hole and the second via hole can be separately formed by processes different from each other, and can be formed to have similar heights to each other. Accordingly, misalignment of the via hole with the adjacent via hole can be prevented, and a metal material can be easily formed in the via hole having a large aspect ratio without voids. Accordingly, the semiconductor device can be miniaturized, and the electrical characteristics and reliability of the semiconductor device can be improved.

[0139] While the present application has been described with reference to the embodiments thereof, it is to be understood that the application is not limited to the embodiments and constructions. To this end, many modifications, variations and changes in detail can be made to the embodiments of the present application without departing from the spirit and scope of the application.

Claims

1. A semiconductor device, comprising: Substrate, including active patterning; Device isolation layers are located between the active patterns; Stacked patterns on the substrate; A power transmission network layer is located on the lower surface of the substrate. The first through-hole penetrates the stacked pattern; as well as The second via is located between the power transmission network layer and the first via. The second via penetrates the active pattern and the device isolation layer.

2. The semiconductor device according to claim 1, wherein, The lower surface of the substrate is coplanar with the lower surface of the device isolation layer.

3. The semiconductor device according to claim 1, wherein, The stacking pattern comprises active layers and sacrificial layers that are alternately stacked on the substrate.

4. The semiconductor device according to claim 1, further comprising a separation structure located on the side of the first through-hole. in, Each of the separation structures intersects with the active pattern.

5. The semiconductor device according to claim 1, wherein, The first through hole and the second through hole are in contact with each other to form an interface between the first through hole and the second through hole, and The interface is disposed between the upper surface and the lower surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The first through-hole includes a first metal pattern and a first blocking pattern, the first blocking pattern being on the side surface of the first metal pattern. The second through hole includes a second metal pattern and a second blocking pattern, with the second blocking pattern on the side surface of the second metal pattern.

7. The semiconductor device according to claim 6, wherein, The first blocking pattern extends to the lower surface of the first metal pattern. Wherein, the second blocking pattern extends to the upper surface of the second metal pattern, and The first blocking pattern and the second blocking pattern are in contact with each other.

8. The semiconductor device according to claim 6, wherein, The first metal pattern and the second metal pattern comprise different metal materials.

9. The semiconductor device according to claim 6, wherein, The second blocking pattern extends to the upper surface of the second metal pattern, and The second blocking pattern is in contact with the first metal pattern.

10. A semiconductor device, comprising: The substrate includes logic cells and tap cells adjacent to the logic cells; Metal lines, on the substrate, and spaced apart from each other in a first direction, wherein each of the metal lines extends in a second direction intersecting the first direction; and A power transmission network layer is located on the lower surface of the substrate. The tap unit includes through-holes that connect some of the metal wires to the power transmission network layer. The through holes include a first through hole and a second through hole that are in contact with each other. Wherein, the second through-hole penetrates at least a portion of the substrate, and The interface between the first through-hole and the second through-hole is closer to the upper surface of the substrate than to the lower surface of the substrate.

11. The semiconductor device according to claim 10, wherein, The substrate includes an active pattern, and The thickness of the substrate is the same as the thickness of each active pattern in the active pattern.

12. The semiconductor device of claim 11, further comprising a device isolation layer located between the active patterns. in, The lower surface of the device isolation layer is coplanar with the lower surface of the substrate. The second through-hole penetrates at least a portion of the device's isolation layer.

13. The semiconductor device according to claim 11, wherein, The logic unit includes: Source / drain pattern, on the active pattern; Multiple semiconductor patterns are spaced apart from and between the source / drain patterns; and The gate electrode at least partially surrounds each of the plurality of semiconductor patterns.

14. The semiconductor device according to claim 13, wherein, The logic unit further includes a rear contact portion that connects some of the source / drain patterns in the source / drain pattern to the power transmission network layer.

15. The semiconductor device according to claim 13, wherein, Some of the source / drain patterns in the source / drain pattern are electrically connected to the via through some of the metal wires in the metal wires.

16. The semiconductor device according to claim 10, wherein, The width of the first via decreases as the first via approaches the upper surface of the substrate, and The width of the second via decreases as the second via approaches the upper surface of the substrate.

17. The semiconductor device of claim 10, further comprising an interlayer insulating layer located between the lower surface of the substrate and the power transmission network layer. in, The interlayer insulation layer at least partially surrounds a portion of the second via.

18. A semiconductor device, comprising: Logic units and tap units are arranged on the substrate; Metal wires and electric lines are on the substrate; as well as A power transmission network layer is located on the lower surface of the substrate. Each of the logic units includes: Channel pattern, on the active pattern; Device isolation layers are located between the active patterns; Source / drain patterns, between the channel patterns; and Gate electrode, on the channel pattern, Each of the tap units includes a through-hole that connects the metal wire and the power transmission network layer to each other. The lower surface of the device isolation layer is coplanar with the lower surface of the active pattern.

19. The semiconductor device according to claim 18, wherein, The logic unit includes a first logic unit and a second logic unit that are adjacent to each other. One of the tapping units is located between the first logic unit and the second logic unit.

20. The semiconductor device according to claim 18, wherein, The tap unit is arranged to be spaced apart from the logic unit.

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