Three-dimensional semiconductor device including gate cutting pattern

Abstract

A three-dimensional semiconductor device is provided. The three-dimensional semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode on the lower channel pattern and the upper channel pattern; and a gate cutting pattern penetrating the gate electrode, and the gate cutting pattern may have an intermediate width between an upper surface and a lower surface thereof, the intermediate width being smaller than an upper width of an upper portion of the gate cutting pattern and a lower width of a lower portion of the gate cutting pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0064086, filed on May 16, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically, to a three-dimensional semiconductor device including a gate dicing pattern and a method of manufacturing the three-dimensional semiconductor device. Background Technology

[0004] Semiconductor devices can include integrated circuits having, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size of semiconductor devices decreases and design rules become more precise, MOSFETs can be scaled down. However, as MOSFETs are scaled down, the operating characteristics of the semiconductor device may deteriorate. Summary of the Invention

[0005] One aspect of the present invention is to provide a three-dimensional semiconductor device with improved integration and electrical characteristics.

[0006] One aspect of the present invention provides a method for manufacturing a three-dimensional semiconductor device with improved integration and electrical properties.

[0007] The inventive concept is not limited to the given description, and other aspects not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] A three-dimensional semiconductor device according to some embodiments of the present invention may include: a first active region located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region located on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode located on the lower channel pattern and the upper channel pattern; and a gate dicing pattern penetrating the gate electrode, wherein the gate dicing pattern has an intermediate width located between its upper surface and lower surface, the intermediate width being smaller than the upper width of the upper portion of the gate dicing pattern and the lower width of the lower portion of the gate dicing pattern.

[0009] A three-dimensional semiconductor device according to some embodiments of the present invention may include: a first active region located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region located on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; and a gate dicing pattern penetrating the gate electrode, wherein the gate dicing pattern includes a first portion and a second portion, the first portion being adjacent to the second active region, the second portion being disposed on the first portion and adjacent to the first active region, and each of the first portion and the second portion having a width that decreases toward the middle width of the gate dicing pattern.

[0010] A three-dimensional semiconductor device according to some embodiments of the present invention may include: a first active region located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region located on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a lower active contact connected to the lower source / drain pattern; an upper active contact connected to the upper source / drain pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; a gate contact connected to the gate electrode; and a gate dicing pattern extending in a second direction intersecting the first direction and penetrating the gate electrode, wherein the gate dicing pattern includes a first portion and a second portion below the first portion, and the gate dicing pattern has an intermediate width located at the interface where the first portion and the second portion contact each other, the intermediate width being smaller than the upper width of the second portion of the gate dicing pattern and the lower width of the first portion of the gate dicing pattern. Attached Figure Description

[0011] The exemplary embodiments will become clearer from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0012] Figure 1 This is a conceptual diagram of the logic unit of a semiconductor device used to explain a comparative example of the concept according to the present invention.

[0013] Figure 2 This is a conceptual diagram used to explain the logic unit of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 3 This is a plan view used to explain embodiments of a three-dimensional semiconductor device according to the present invention.

[0015] Figures 4A to 4DThis is a diagram used to explain an embodiment of a three-dimensional semiconductor device according to the present invention, and is along... Figure 3 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D' in the diagram.

[0016] Figures 5A to 5C This is a diagram illustrating the gate dicing pattern of a three-dimensional semiconductor device according to an embodiment of the present invention, and is... Figure 4C A magnified view of region 'M'.

[0017] Figure 6A and Figure 6B , Figures 7A to 7C , Figures 8A to 8D , Figures 9A to 9D , Figures 10A to 10D ,as well as Figures 11A to 11D These are illustrations used to explain a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 3 A cross-sectional view taken from line B-B'. Figure 7B , Figure 8C , Figure 9C and Figure 10C as well as Figure 11C It is along Figure 3 The cross-sectional view taken by line C-C', and Figure 6B , Figure 7C , Figure 8D , Figure 9D , Figure 10D and Figure 11D It is along Figure 3 The cross-sectional view taken by line D-D'. Detailed Implementation

[0018] In the following description, embodiments of the inventive concept will be illustrated with reference to the accompanying drawings. The inventive concept can be implemented in various modifications and has various forms, and specific embodiments are shown in the drawings and described in detail in the context of the drawings. However, it is to be understood that the inventive concept is not intended to be limited to the specific forms disclosed, but rather, the inventive concept is intended to cover all modifications, equivalents, and substitutions falling within the spirit and scope of the inventive concept.

[0019] The same reference numerals may refer to the same elements throughout the specification. In the drawings, the thickness, proportions, and dimensions of elements may be exaggerated in order to effectively describe the technical content.

[0020] Figure 1 This is a conceptual diagram of the logic unit of a semiconductor device used to explain a comparative example of the concept according to the present invention.

[0021] Reference Figure 1 A single-height cell (SHC) can be provided. Specifically, a first electric field line (POR1) and a second electric field line (POR2) ​​can be disposed on the substrate 100. A drain voltage (or electric field voltage) can be applied to one of the first electric field line (POR1) and the second electric field line (POR2). A source voltage (or ground voltage) can be applied to the other of the first electric field line (POR1) and the second electric field line (POR2). For example, the source voltage can be applied to the first electric field line (POR1), and the drain voltage can be applied to the second electric field line (POR2).

[0022] A single-height cell (SHC) can be defined between a first power line POR1 and a second power line POR2. The single-height cell SHC can include a lower active region (LAR) and an upper active region (UAR). One of the lower active region (LAR) and the upper active region (UAR) can be a PMOSFET region. The other of the lower active region (LAR) and the upper active region (UAR) can be an NMOSFET region. For example, the lower active region (LAR) can be an NMOSFET region, and the upper active region (UAR) can be a PMOSFET region. That is, the single-height cell SHC can have a CMOS structure disposed between the first power line POR1 and the second power line POR2.

[0023] The semiconductor device of the comparative example according to the present invention can be a two-dimensional device, and transistors in the front-end process (FEOL) layer can be arranged two-dimensionally. For example, the NMOSFET of the lower active region LAR and the PMOSFET of the upper active region UAR can be spaced apart from each other in the first direction D1.

[0024] Each of the lower active region (LAR) and the upper active region (UAR) can have a first width (W1) in the first direction (D1). The length of the single-height cell (SHC) of the comparative example according to the invention in the first direction (D1) can be defined as a first height (HE1). The first height (HE1) can be substantially equal to the distance (e.g., pitch) between the first electric field line (POR1) and the second electric field line (POR2).

[0025] A single-height cell (SHC) can constitute a logic unit. In this specification, a logic unit can refer to a logic device that performs a specific function (e.g., AND gate, OR gate, XOR gate, XNOR gate, inverter, etc.). That is, a logic unit may include transistors for constructing the logic device and wiring connecting the transistors to each other.

[0026] Since the single-height unit SHC of the comparative example according to the present invention can include a two-dimensional device, the lower active region LAR and the upper active region UAR can not overlap each other vertically and can be spaced apart from each other in the first direction D1. Therefore, the first height HE1 of the single-height unit SHC can be defined as including both the lower active region LAR and the upper active region UAR spaced apart from each other in the first direction D1. As a result, the area of ​​the single-height unit SHC of the comparative example according to the present invention may be relatively large.

[0027] Figure 2 This is a conceptual diagram used to explain the logic unit of a semiconductor device according to an embodiment of the present invention.

[0028] Reference Figure 2 A single-height cell SHC including three-dimensional devices can be provided. The single-height cell SHC including three-dimensional devices may include stacked transistors. Specifically, a first electric field line POR1 and a second electric field line POR2 can be disposed on the substrate 100. The single-height cell SHC can be defined between the first electric field line POR1 and the second electric field line POR2.

[0029] A single-height cell (SHC) may include a lower active region (LAR) and an upper active region (UAR). One of the lower active region (LAR) and the upper active region (UAR) may be a PMOSFET region, and the other of the lower active region (LAR) and the upper active region (UAR) may be an NMOSFET region.

[0030] The semiconductor device according to embodiments of the present invention can be a three-dimensional device, and transistors of the FEOL layer can be stacked vertically. The lower active region (LAR) can be positioned as the bottom layer on the substrate 100, and the upper active region (UAR) can be stacked on the lower active region (LAR) and can be positioned as the top layer. For example, an NMOSFET in the lower active region (LAR) can be disposed on the substrate 100, and a PMOSFET in the upper active region (UAR) can be stacked on top of the NMOSFET. The lower active region (LAR) and the upper active region (UAR) can be spaced apart from each other in a vertical direction (e.g., third direction D3).

[0031] Each of the lower active region (LAR) and the upper active region (UAR) can have a first width (W1) in the first direction (D1). The length of the single-height unit (SHC) in the first direction (D1) according to an embodiment of the present invention can be defined as a second height (HE2).

[0032] A single-height cell SHC according to an embodiment of the present invention may include a three-dimensional device that can contain stacked transistors, and the lower active region LAR and the upper active region UAR can be vertically stacked on top of each other. Therefore, the second height HE2 of the single-height cell SHC may have a dimension including the first width W1. The second height HE2 of the single-height cell SHC according to an embodiment of the present invention may be smaller than... Figure 1 The first height HE1 of the single-height cell SHC. That is, the area of ​​the single-height cell SHC according to the embodiment of the present invention can be relatively small. Given the relatively small area of ​​the single-height cell SHC, the integration density of the single-height cell SHC in a semiconductor device can be improved.

[0033] Figure 3 This is a plan view used to explain embodiments of a three-dimensional semiconductor device according to the present invention. Figures 4A to 4D These are diagrams illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention, and are cross-sectional views taken along lines A-A', B-B', C-C', and D-D', respectively. Lines A-A', B-B', C-C', and D-D' show... Figure 3 middle.

[0034] Reference Figure 3 and Figures 4A to 4D A single-height cell (SHC) can be disposed on the substrate 100. Each single-height cell (SHC) can be a logic cell constituting a logic circuit. Each single-height cell (SHC) can include the above-mentioned references. Figure 2 The logical unit of the described three-dimensional device. A single-height unit SHC can be arranged in the first direction D1.

[0035] The substrate 100 may include a first surface 100t and a second surface 100b facing each other. The first surface 100t may be the upper surface (or front surface) of the substrate 100. The second surface 100b may be the lower surface (or rear surface) of the substrate 100. For example, the substrate 100 may be an insulating substrate comprising a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). Alternatively, the substrate 100 may be a semiconductor substrate comprising silicon, germanium, silicon-germanium, etc.

[0036] Each single-height cell (SHC) may include a lower active region (LAR) and an upper active region (UAR) sequentially stacked on a substrate 100. One of the lower active region (LAR) and the upper active region (UAR) may be a PMOSFET region. The other of the lower active region (LAR) and the upper active region (UAR) may be an NMOSFET region. The lower active region (LAR) may be located in the bottom layer of the FEOL layer, and the upper active region (UAR) may be located in the top layer of the FEOL layer. The NMOSFETs and PMOSFETs of the lower active region (LAR) and the upper active region (UAR) may be vertically stacked to form a three-dimensional stacked transistor. For example, the lower active region (LAR) may be an NMOSFET region, and the upper active region (UAR) may be a PMOSFET region.

[0037] Each of the lower active region (LAR) and the upper active region (UAR) may have a strip or line extending in a second direction D2 intersecting the first direction D1, wherein the first direction D1 and the second direction D2 may be perpendicular to a third direction D3. Each of the gate dicing patterns (CTPs), which will be described subsequently, may be disposed between single-height cells (SHCs) adjacent to each other in the first direction D1. Thus, the single-height cells (SHCs) may be spaced apart from each other in the first direction D1.

[0038] The lower active region (LAR) of each single-height cell (SHC) may include a lower channel pattern (LCH) and a lower source / drain pattern (LSD). Each of the lower channel patterns (LCH) may be positioned between a pair of lower source / drain patterns (LSD). Each of the lower channel patterns (LCH) may connect a pair of lower source / drain patterns (LSD) to each other.

[0039] Each of the lower channel patterns (LCH) may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked and spaced apart from each other. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Specifically, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be a nanosheet. According to an embodiment, each of the lower channel patterns (LCH) may also include one or more semiconductor patterns stacked and spaced apart from the first semiconductor pattern SP1. The first semiconductor pattern SP1 may be the lowest semiconductor pattern among the semiconductor patterns.

[0040] The lower source / drain pattern LSD can be disposed on the substrate 100. Each of the lower source / drain pattern LSDs can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper surface of the lower source / drain pattern LSD can be higher than the upper surface of the second semiconductor pattern SP2 of each of the lower channel patterns LCH.

[0041] The lower source / drain patterned LSD may be doped with impurities to have a first conductivity type. The first conductivity type may be N-type or P-type, and more specifically, the first conductivity type may be N-type. The lower source / drain patterned LSD may include silicon (Si) and / or silicon germanium (SiGe).

[0042] The first interlayer insulating layer 110 can be disposed on the lower source / drain pattern LSD. The first interlayer insulating layer 110 can cover the lower source / drain pattern LSD.

[0043] Lower active contacts (LACs) can be disposed below the lower source / drain patterns (LSDs). Each of the lower active contacts (LACs) can be electrically connected to the corresponding lower source / drain pattern (LSD). The lower active contacts (LACs) can be buried in the substrate 100. The lower active contacts (LACs) can extend from the second surface 100b of the substrate 100 to the first surface 100t in a third direction D3. For example, the lower active contacts (LACs) can include at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0044] An active region UAR can be disposed on the first interlayer insulating layer 110. The active region UAR may include an upper channel pattern UCH and an upper source / drain pattern USD. The upper channel pattern UCH may vertically overlap with the lower channel pattern LCH. The upper source / drain patterns USD may each vertically overlap with the lower source / drain patterns LSD. Each of the upper channel patterns UCH may be disposed between a pair of upper source / drain patterns USD. Each of the upper channel patterns UCH may connect a pair of upper source / drain patterns USD to each other.

[0045] Each of the upper channel pattern UCH may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked and spaced apart from each other. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may include semiconductor materials substantially the same as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be a nanosheet. According to an embodiment, each of the upper channel pattern UCH may also include one or more semiconductor patterns stacked and spaced apart from the third semiconductor pattern SP3.

[0046] A pseudo-channel pattern DSP can be disposed between a lower channel pattern LCH and an upper channel pattern UCH that are vertically stacked together. A portion of the first interlayer insulating layer 110 can be disposed between the pseudo-channel pattern DSPs. Therefore, the pseudo-channel pattern DSP can be spaced apart from the lower source / drain pattern LSD and the upper source / drain pattern USD. That is, the pseudo-channel pattern DSP can be unconnected to any source / drain pattern and can be isolated from the source / drain pattern. For example, the pseudo-channel pattern DSP can include semiconductor materials (such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe)) or silicon-based insulating materials (such as silicon oxide or silicon nitride).

[0047] The seed layer SDL can be set between the pseudo-channel pattern DSP and the upper channel pattern UCH.

[0048] The upper source / drain pattern USD can be disposed on the upper surface of the first interlayer insulating layer 110. Each of the upper source / drain patterns USD can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper surface of the upper source / drain pattern USD can be higher than the upper surface of the fourth semiconductor pattern SP4 of each of the upper channel patterns UCH.

[0049] The upper source / drain pattern (USD) may be doped with impurities to have a second conductivity type. This second conductivity type may differ from the first conductivity type of the lower source / drain pattern (LSD). For example, the second conductivity type may be P-type. The upper source / drain pattern (USD) may include silicon germanium (SiGe) and / or silicon (Si).

[0050] The second interlayer insulating layer 120 may be disposed on the upper source / drain pattern USD. The second interlayer insulating layer 120 may cover the upper source / drain pattern USD. The second interlayer insulating layer 120 may have an upper surface with substantially the same height as the upper surface of the gate cap pattern GP, ​​which will be described subsequently.

[0051] Multiple gate electrodes GE can be disposed on a single-height cell SHC. When viewed in a plan view, each of the gate electrodes GE can have a stripe extending in a first direction D1. For example, the gate electrodes GE can be disposed on a stacked lower channel pattern LCH and upper channel pattern UCH. The gate electrodes GE can vertically overlap with the stacked lower channel pattern LCH and upper channel pattern UCH.

[0052] Each of the gate electrodes GE may be disposed on the upper surface, lower surface, and two sidewalls of each of the first semiconductor patterns SP1 to the fourth semiconductor patterns SP4. According to some embodiments, the transistor may include a three-dimensional field-effect transistor (e.g., an MBCFET or a GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0053] Each of the gate electrodes GE may include a lower gate electrode LGE disposed in the lower active region LAR and an upper gate electrode UGE disposed in the upper active region UAR. The lower gate electrode LGE and the upper gate electrode UGE can be distinguished based on the pseudo-channel pattern DSP. The lower gate electrode LGE and the upper gate electrode UGE may be connected to each other, but are not limited thereto.

[0054] The lower gate electrode LGE may include a first internal electrode PO1 between the first lower insulating pattern LIP and the first semiconductor pattern SP1, which will be described later; a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2; and a third internal electrode PO3 between the second semiconductor pattern SP2 and the pseudo-channel pattern DSP.

[0055] The upper gate electrode UGE may include a fourth inner electrode PO4 between the pseudo-channel pattern DSP and the third semiconductor pattern SP3, a fifth inner electrode PO5 between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and an outer electrode PO6 on the fourth semiconductor pattern SP4.

[0056] A pair of gate spacers GS can be disposed on the sidewalls of the gate electrode GE. For example, a pair of gate spacers GS can be disposed on the two sidewalls of the outer electrode PO6. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The upper surface of the gate spacers GS can be higher than the upper surface of the gate electrode GE. The upper surface of the gate spacers GS can be coplanar with the upper surface of the gate capping pattern GP, ​​which will be described later. For example, the gate spacers GS can include at least one of SiCN, SiCON, and SiN. Alternatively, the gate spacers GS can include a multilayer formed of at least two of SiCN, SiCON, and SiN.

[0057] A gate capping pattern GP can be disposed on each of the gate electrodes GE. Each of the gate capping patterns GP can extend along the gate electrode GE in a first direction D1. For example, the gate capping pattern GP can include at least one of SiON, SiCN, SiCON, and SiN.

[0058] A gate insulating layer GI can be disposed between the gate electrode GE and the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4. For example, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. Alternatively, the gate insulating layer GI may include a silicon oxide layer directly covering the surfaces of the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4, and a high-k dielectric layer on the silicon oxide layer. That is, the gate insulating layer GI may include multiple layers of silicon oxide layers and high-k dielectric layers.

[0059] The high-k dielectric layer of the gate insulating layer GI may include a high-k dielectric material having a higher dielectric constant than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0060] According to an embodiment, the lower gate electrode LGE may further include a first work function metal pattern on a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The upper gate electrode UGE may further include a second work function metal pattern on a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4. Each of the first and second work function metal patterns may include a metal comprising at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The first and second work function metal patterns may have different work functions. Additionally, the gate electrode GE may also include a low-resistance metal (e.g., at least one of tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)) on the first and second work function metal patterns. In this case, the external electrode PO6 may include a low-resistance metal and a second work function metal pattern.

[0061] The third interlayer insulating layer 130 may be disposed on the gate cap pattern GP. The upper surface of the third interlayer insulating layer 130 may be coplanar with the upper surface of the active contact UAC, which will be described later.

[0062] The gate contact GC can penetrate the third interlayer insulating layer 130 and the gate cap pattern GP. The gate contact GC can be electrically connected to the upper gate electrode UGE. For example, the upper active contact UAC and the gate contact GC can include a metal comprising at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0063] The gate diced pattern CTP may intersect with the gate electrode GE extending in the first direction D1. For example, the gate diced pattern CTP may extend in the second direction D2. Each of the gate diced patterns CTP may extend in the second direction D2 and may be configured to separate the gate electrode GE extending in the first direction D1. The gate diced pattern CTP may penetrate the gate electrode GE in the third direction D3. For example, the upper surface CTPt of the gate diced pattern CTP may be coplanar with the upper surface of the gate capping pattern GP on the gate electrode GE. The lower surface CTPb of the gate diced pattern CTP may be coplanar with the second surface 100b of the substrate 100 below the gate electrode GE. That is, the upper surface CTPt of the gate diced pattern CTP may be higher than the upper surface GEt of the gate electrode GE. The lower surface CTPb of the gate diced pattern CTP may be lower than the lower surface GEb of the gate electrode GE.

[0064] The vertical length of each of the gate diced patterns CTP can be greater than the vertical length of each of the gate electrodes GE. The gate electrodes GE can be separated by the gate diced patterns CTP in a first direction D1. When viewed in a plan view, each of the gate diced patterns CTP can have a strip or line extending in a second direction D2. The gate diced patterns CTP can be spaced apart from each other in the first direction D1.

[0065] Each of the gate diced patterns CTP may have an upper width TW on its upper surface CTPt in the first direction D1. Each of the gate diced patterns CTP may have a lower width BW on its lower surface CTPb in the first direction D1. The upper width TW and the lower width BW may be different from each other. For example, the upper width TW may be smaller than the lower width BW, but is not limited thereto. According to an embodiment, the upper width TW and the lower width BW may be substantially the same.

[0066] Each of the gate dicing patterns (CTPs) may include a buried insulating layer (FIL) and a liner layer (DMP). The buried insulating layer (FIL) and the liner layer (DMP) may be in contact with each other. The liner layer (DMP) may be disposed on the sidewalls of the buried insulating layer (FIL) and may surround the sidewalls of the buried insulating layer (FIL). For example, the liner layer (DMP) may be disposed on opposite sidewalls of the buried insulating layer (FIL) spaced apart in a first direction D1. The buried insulating layer (FIL) and the liner layer (DMP) may include at least one of SiO, SiON, SiCN, SiCON, and SiN. Alternatively, the liner layer (DMP) may be an insulating layer consisting of one or more layers. According to an embodiment, the buried insulating layer (FIL) and the liner layer (DMP) may include different insulating materials. In this case, the buried insulating layer (FIL) and the liner layer (DMP) may have etch selectivity relative to each other.

[0067] Additionally, the buried insulating layer (FIL) of each of the gate diced patterns (CTPs) may include a first portion P1 and a second portion P2. The first portion P1 may be disposed on the second portion P2. For example, the first portion P1 may correspond to the upper portion of each of the gate diced patterns (CTPs), and the second portion P2 may correspond to the lower portion of each of the gate diced patterns (CTPs). The first portion P1 may be adjacent to the upper active region (UAR), and the second portion P2 may be adjacent to the lower active region (LAR). Furthermore, the first portion P1 and the second portion P2 may be in contact with each other. According to an embodiment, the first portion P1 and the second portion P2 may comprise the same insulating material. In this case, the interface formed by the contacting first portion P1 and the second portion P2 may be invisible.

[0068] A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. A first metal layer M1 may be disposed in the fourth interlayer insulating layer 140. The first metal layer M1 may include an upper interconnect UMI. The first metal layer M1 may also include an upper via UVI. The upper via UVI can electrically connect the upper interconnect UMI to an upper active contact UAC or a gate contact GC. Each of the upper interconnect UMI and the upper via UVI may include a metal comprising at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0069] According to an embodiment, multiple metal layers (e.g., M2, M3, M4, etc.) may be disposed on the first metal layer M1. In this case, the first metal layer M1 and the multiple metal layers on the first metal layer M1 may form the back-end process (BEOL) layer of a three-dimensional semiconductor device. For example, the multiple metal layers on the first metal layer M1 may include wiring for connecting adjacent logic cells to each other.

[0070] A first lower interlayer insulating layer 200 may be disposed on a second surface 100b of a substrate 100. A second lower interlayer insulating layer 210 may be disposed below the first lower interlayer insulating layer 200. A back-side metal layer BSM may be disposed within the second lower interlayer insulating layer 210. The back-side metal layer BSM may include a lower interconnect LMI. The back-side metal layer BSM may also include a lower via LVI. The lower via LVI may electrically connect a lower active contact LAC and a lower interconnect LMI. Each of the lower interconnect LMI and the lower via LVI may include a metal comprising at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0071] According to an embodiment, multiple lower metal layers may be disposed below the back metal layer (BSM). For example, the multiple lower metal layers may include a power transmission network layer. The power transmission network layer may include a wiring network for applying source voltage and / or drain voltage to the back metal layer (BSM). In this case, one of the source voltage and drain voltage may be applied to the lower source / drain pattern (LSD) via the lower interconnect (LMI), lower via (LVI), and lower active contact (LAC). The other of the source voltage and drain voltage may be applied from the back metal layer (BSM) to the first metal layer (M1) via a power tap unit. The voltage applied to the first metal layer (M1) via the power tap unit may be applied to the upper source / drain pattern (USD) via the upper interconnect (UMI), upper via (UVI), and upper active contact (UAC).

[0072] Figures 5A to 5C This is a diagram illustrating the gate dicing pattern of a three-dimensional semiconductor device according to an embodiment of the present invention, and is... Figure 4C A magnified view of region 'M'.

[0073] Reference Figure 5A The buried insulating layer (FIL) of the gate dicing pattern (CTP) may include a first portion P1 and a second portion P2 below the first portion P1. Each of the first portion P1 and the second portion P2 may have a shape extending in the third direction D3. For example, the first portion P1 and the second portion P2 may be in contact with each other to form a buried insulating layer (FIL) extending in the third direction D3.

[0074] Each of the first part P1 and the second part P2 may have a width in the first direction D1. The width of each of the first part P1 and the second part P2 may vary depending on the height (or horizontal direction). For example, the first part P1 may have a width that decreases as it moves closer to the second part P2. The second part P2 may have a width that decreases as it moves closer to the first part P1.

[0075] The first portion P1 may have a first width WD1 at the interface where the first portion P1 contacts the second portion P2. The second portion P2 may have a second width WD2 at the interface where the second portion P2 contacts the first portion P1. The first width WD1 and the second width WD2 may be substantially the same as each other. The first width WD1 and the second width WD2 may be smaller than the upper width TW of the upper part of the gate diced pattern CTP. The first width WD1 and the second width WD2 may be smaller than the lower width BW of the lower part of the gate diced pattern CTP. For example, the first portion P1 may have a first width WD1, which may be the minimum width at the interface where the first portion P1 contacts the second portion P2. The second portion P2 may have a second width WD2, which may be the minimum width at the interface where the second portion P2 contacts the first portion P1. The first width WD1 and the second width WD2 may be substantially the same as each other. Therefore, the gate diced pattern CTP may have an intermediate width MWD at the interface where the first portion P1 and the second portion P2 contact each other. The intermediate width MWD may be the minimum width of the gate diced pattern CTP, but the embodiments are not limited thereto.

[0076] The first portion P1 and the second portion P2 of the buried insulating layer FIL can each be tapered to the portion where the first portion P1 and the second portion P2 intersect. For example, in the third direction, the buried insulating layer FIL can have a converging shape at the portion corresponding to the second portion P2 and a diverging shape at the portion corresponding to the first portion P1.

[0077] The first part P1 may have a first upper sidewall SW1a and a second upper sidewall SW1b facing each other in a first direction D1. The second part P2 may have a first lower sidewall SW2a and a second lower sidewall SW2b facing each other in a first direction D1. The first upper sidewall SW1a and the first lower sidewall SW2a may be connected to each other. The second upper sidewall SW1b and the second lower sidewall SW2b may be connected to each other. The first upper sidewall SW1a may extend from the first lower sidewall SW2a, and the first upper sidewall SW1a and the first lower sidewall SW2a may extend substantially in a third direction D3 with corresponding tapers. The second upper sidewall SW1b may extend from the second lower sidewall SW2b, and the second upper sidewall SW1b and the second lower sidewall SW2b may extend substantially in a third direction D3 with corresponding tapers. For example, the sidewalls of the buried insulating layer FIL may not have steps.

[0078] The first part P1 may have a first central axis CA1 passing through the center of the first part P1 along the first direction D1. The second part P2 may have a second central axis CA2 passing through the center of the second part P2 along the first direction D1. Each of the first central axis CA1 and the second central axis CA2 may extend in the third direction D3. The first central axis CA1 and the second central axis CA2 may not be spaced apart from each other in the first direction D1 and may be aligned with each other.

[0079] The inner liner layer DMP can be disposed between the first portion P1 and the second portion P2 and the second interlayer insulation layer 120. The inner liner layer DMP can have a uniform thickness and can cover the first upper sidewall SW1a and the second upper sidewall SW1b of the first portion P1 and the first lower sidewall SW2a and the second lower sidewall SW2b of the second portion P2.

[0080] Reference Figure 5B The buried insulating layer (FIL) of the gate diced pattern CTP may include a first portion P1 and a second portion P2, and each of the first portion P1 and the second portion P2 may have a different width in a first direction D1. Additionally, the first portion P1 and the second portion P2 may have a width that decreases as the first portion P1 and the second portion P2 become adjacent to each other.

[0081] The first portion P1 may have a first width WD1 at the interface where it contacts the second portion P2. The second portion P2 may have a second width WD2 at the interface where it contacts the first portion P1. The first width WD1 and the second width WD2 may be different widths. The first width WD1 and the second width WD2 may be smaller than the upper width TW of the gate diced pattern CTP. The first width WD1 and the second width WD2 may be smaller than the lower width BW of the gate diced pattern CTP. For example, the first portion P1 may have a first width WD1, which may be the minimum width at the interface where it contacts the second portion P2. The second portion P2 may have a second width WD2, which may be the minimum width at the interface where it contacts the first portion P1. The first width WD1 and the second width WD2 may be different from each other. For example, the first width WD1 may be smaller than the second width WD2. Figure 5A Similarly, the gate diced pattern CTP can have an intermediate width MWD at the interface where the first portion P1 and the second portion P2 contact each other. The intermediate width MWD can be the minimum width of the gate diced pattern CTP, but the embodiments are not limited thereto. One of the first width WD1 and the second width WD2 can be associated with the intermediate width MWD at the interface where the first portion P1 and the second portion P2 contact each other. For example, Figure 5BThe illustration shows a first width WD1 associated with an intermediate width MWD; however, the embodiment is not limited to this. For example, a second width WD2 may be associated with an intermediate width MWD.

[0082] The gate diced pattern CTP may have a first stepped surface SSa between the first upper sidewall SW1a and the first lower sidewall SW2a, and a second stepped surface SSb between the second upper sidewall SW1b and the second lower sidewall SW2b. For example, the first stepped surface SSa or the second stepped surface SSb may be omitted. That is, the gate diced pattern CTP may have at least one stepped surface between the sidewall of the first portion P1 and the sidewall of the second portion P2.

[0083] The first portion P1 along the first central axis CA1 of the first direction D1 and the second portion P2 along the second central axis CA2 of the first direction D1 can be aligned with each other. However, the inventive concept is not limited thereto. For example, the first central axis CA1 and the second central axis CA2 can be spaced apart from each other in the first direction D1.

[0084] The inner liner layer DMP can be disposed between the first portion P1 and the second portion P2 and the second interlayer insulation layer 120. The inner liner layer DMP can cover the buried insulation layer FIL with a uniform thickness. For example, the inner liner layer DMP can cover the first upper sidewall SW1a and the second upper sidewall SW1b, the first lower sidewall SW2a and the second lower sidewall SW2b, and the first step surface SSa and the second step surface SSb. Therefore, the inner liner layer DMP can also have a step surface adjacent to the interface that contacts the first portion P1 and the second portion P2.

[0085] Reference Figure 5C The buried insulating layer (FIL) of the gate dicing pattern (CTP) may include a first portion P1 and a second portion P2. The first portion P1 may have a first central axis CA1 passing through its center along a first direction D1, and the second portion P2 may have a second central axis CA2 passing through its center along the first direction D1. The first central axis CA1 and the second central axis CA2 may be spaced apart from each other in the first direction D1. That is, the first central axis CA1 and the second central axis CA2 may be offset in the first direction D1. Therefore, the first portion P1 may vertically overlap a portion of the second portion P2.

[0086] and Figure 5ASimilarly, each of the first portion P1 and the second portion P2 may have a first width WD1 and a second width WD2 at the interface where the first portion P1 and the second portion P2 contact each other. Additionally, the first width WD1 and the second width WD2 may be substantially the same. For example, the first portion P1 may have a first width WD1 at the interface where the first portion P1 contacts the second portion P2. The second portion P2 may have a second width WD2 at the interface where the second portion P2 contacts the first portion P1. The first width WD1 and the second width WD2 may be substantially the same as each other. The first width WD1 and the second width WD2 may be smaller than the upper width TW of the gate diced pattern CTP. The first width WD1 and the second width WD2 may be smaller than the lower width BW of the gate diced pattern CTP. Therefore, the gate diced pattern CTP may have an intermediate width MWD at the interface where the first portion P1 and the second portion P2 contact each other. The intermediate width MWD may be the minimum width of the gate diced pattern CTP, but the embodiments are not limited to this.

[0087] Since the first central axis CA1 of the first portion P1 and the second central axis CA2 of the second portion P2 are spaced apart from each other in the buried insulating layer FIL, the first portion P1 and the second portion P2 can have stepped surfaces between them. For example, the first stepped surface SSa can be disposed between the first upper sidewall SW1a and the first lower sidewall SW2a, and the second stepped surface SSb can be disposed between the second upper sidewall SW1b and the second lower sidewall SW2b. The first stepped surface SSa and the second stepped surface SSb can be coplanar, but are not limited thereto. According to an embodiment, the first stepped surface SSa and the second stepped surface SSb can be disposed at different levels.

[0088] The inner liner layer DMP between the buried insulation layer FIL and the second interlayer insulation layer 120 can cover the buried insulation layer FIL with a uniform thickness. Therefore, the inner liner layer DMP can also have a stepped surface adjacent to the interface that contacts the first portion P1 and the second portion P2.

[0089] Refer again Figures 4A to 4D and Figures 5A to 5CAccording to an embodiment of the present invention, a first portion P1 of the gate diced pattern CTP can be formed on a first surface 100t of the substrate 100, and a second portion P2 can be formed on a second surface 100b of the substrate 100. The first portion P1 and the second portion P2 can be formed separately to form a buried insulating layer (FIL). Therefore, the width of the gate diced pattern CTP can be relatively small at the interface where the first portion P1 and the second portion P2 contact each other. That is, the gate diced pattern CTP can have a minimum width at the midpoint MWD between the upper surface CTPt and the lower surface CTPb of the gate diced pattern CTP. Furthermore, since the first portion P1 and the second portion P2 can be formed by different processes, a gate diced pattern CTP with a high aspect ratio can be filled with insulating material while suppressing or preventing voids. Therefore, the electrical characteristics and reliability of the three-dimensional semiconductor device can be improved.

[0090] In other words, since the gate diced pattern CTP for separating the gate electrode GE can be formed through multiple processes, the size of the recess used to form the gate diced pattern CTP can be smaller. Furthermore, the recess used to form the first portion P1 can be smaller than the recess used to form the second portion P2. The upper width TW of the gate diced pattern CTP can be smaller than its lower width BW, and the distance between the semiconductor circuit patterns integrated on the first surface 100t of the substrate 100 can be narrowed. Therefore, the integration density of the three-dimensional semiconductor device can be improved.

[0091] Figure 6A and Figure 6B , Figures 7A to 7C , Figures 8A to 8D , Figures 9A to 9D , Figures 10A to 10D ,as well as Figures 11A to 11D These are illustrations used to explain a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 3 A cross-sectional view taken from line B-B'. Figure 7B , Figure 8C , Figure 9C and Figure 10C as well as Figure 11C It is along Figure 3 The cross-sectional view taken by line C-C', and Figure 6B , Figure 7C , Figure 8D , Figure 9D , Figure 10D and Figure 11D It is along Figure 3 The cross-sectional view taken by line D-D'.

[0092] Reference Figure 6A and Figure 6B A semiconductor substrate 105 may be provided. The semiconductor substrate 105 may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the semiconductor substrate 105 may be a single-crystal silicon wafer.

[0093] A first lower insulating layer LIL1 may be formed on the semiconductor substrate 105. The first lower insulating layer LIL1 may include a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (e.g., Si or SiGe).

[0094] A first sacrificial layer SAL1 and a first active layer ACL1 may be alternately formed on a first lower insulating layer LIL1. The first sacrificial layer SAL1 may comprise at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the first active layer ACL1 may comprise at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the first sacrificial layer SAL1 may comprise silicon-germanium (SiGe), and the first active layer ACL1 may comprise silicon (Si). The concentration of germanium (Ge) in each of the first sacrificial layers SAL1 may be from approximately 10 at% to approximately 30 at%.

[0095] A separation layer DSL can be formed on the uppermost first sacrificial layer SAL1. For example, the thickness of the separation layer DSL can be greater than the thickness of each of the first sacrificial layers SAL1. The separation layer DSL can include silicon (Si) or silicon germanium (SiGe). When the separation layer DSL includes silicon germanium (SiGe), the concentration of germanium (Ge) in the separation layer DSL can be greater than the concentration of germanium (Ge) in the first sacrificial layer SAL1. For example, the concentration of germanium (Ge) in the separation layer DSL can be from approximately 40 at% to approximately 90 at%.

[0096] A seed layer SDL can be formed on the separation layer DSL. The seed layer SDL may contain the same material as the first active layer ACL1. A second sacrificial layer SAL2 and a second active layer ACL2 can be alternately formed on the seed layer SDL. The second sacrificial layer SAL2 may contain the same material as the first sacrificial layer SAL1, and the second active layer ACL2 may contain the same material as the first active layer ACL1.

[0097] A stacked pattern STP can be formed by patterning the first sacrificial layer SAL1 and the second sacrificial layer SAL2, the first active layer ACL1 and the second active layer ACL2, and the separator layer DSL. Forming the stacked pattern STP may include: forming a hard mask pattern on the uppermost layer of the second active layer ACL2; and using the hard mask pattern as an etch mask to etch the first sacrificial layer SAL1 and the second sacrificial layer SAL2, the active layers ACL1 and ACL2, and the separator layer DSL to partially remove the first sacrificial layer SAL1 and the second sacrificial layer SAL2, the active layers ACL1 and ACL2, and the separator layer DSL. When forming the stacked pattern STP, the upper part of the semiconductor substrate 105 may be patterned to form a trench TR defining a single-height cell SHC. The stacked pattern STP may have a strip or line extending in the second direction D2.

[0098] The stacked pattern STP may include a lower stacked pattern STP1 on a first lower insulating layer LIL1, an upper stacked pattern STP2 on the lower stacked pattern STP1, and a separator layer DSL between the lower stacked pattern STP1 and the upper stacked pattern STP2. The lower stacked pattern STP1 may include a first sacrificial layer SAL1 and a first active layer ACL1 stacked alternately. The upper stacked pattern STP2 may include a seed layer SDL, a second sacrificial layer SAL2 stacked alternately on the seed layer SDL, and a second active layer ACL2.

[0099] Although stacked pattern STP in Figure 6B The diagram is shown as a lower stacked pattern STP1 having two active layers ACL1 and three first sacrificial layers SAL1, and an upper stacked pattern STP2 having two active layers ACL2 and two second sacrificial layers SAL2, but the number of layers can be varied. For example, the number of active layers and / or the number of sacrificial layers can be varied to control the number of layers in the channel pattern and / or the subsequently formed gate electrode.

[0100] A device isolation layer 107 can be formed in the trench TR on an exposed portion of the semiconductor substrate 105. For example, the device isolation layer 107 can be formed on the semiconductor substrate 105 to fill the lower portion of the trench TR. Forming the device isolation layer 107 may include: forming an insulating layer covering a stacked pattern STP on the surface of the semiconductor substrate 105; and recessing the insulating layer at least until the stacked pattern STP is exposed. For example, the upper surface of the device isolation layer 107 may be coplanar with the upper surface of the semiconductor substrate 105. Furthermore, the insulating layer may cover the stacked pattern STP on the surface of the semiconductor substrate 105.

[0101] Reference Figure 7A , Figure 7B and Figure 7CA plurality of first sacrificial patterns PP1 intersecting the stacked pattern STP can be formed on the stacked pattern STP. Each of the first sacrificial patterns PP1 can be formed as a line extending in a first direction D1. Forming the first sacrificial pattern PP1 may include: forming a sacrificial layer on the surface of the semiconductor substrate 105; forming a hard mask pattern MP on the sacrificial layer; and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. For example, the sacrificial layer may include amorphous silicon and / or polycrystalline silicon formed on the entire surface of the semiconductor substrate 105.

[0102] A pair of gate spacers GS can be formed on the two sidewalls of the first sacrificial pattern PP1. Specifically, a spacer layer can be formed on the surface of the semiconductor substrate 105. The spacer layer can be formed across the entire surface of the semiconductor substrate 105 to achieve a uniform thickness. The spacer layer can cover both the first sacrificial pattern PP1 and the hard mask pattern MP. The gate spacers GS can be formed by anisotropically etching the spacer layer. For example, the spacer layer can include at least one of SiCN, SiCON, and SiN.

[0103] Subsequently, an etching process using gate spacers GS and hard mask patterns MP as etching masks can be performed on the stacked pattern STP. Due to the etching process, recesses can be formed between the first sacrificial patterns PP1 that are adjacent to each other in the second direction D2. The stacked pattern STP can have a shape extending in the third direction D3 due to the recesses.

[0104] A sacrificial contact pattern PLH can be formed in the semiconductor substrate 105 exposed by the recess. The sacrificial contact pattern PLH can be formed in a contact shape. The sacrificial contact pattern PLH can be arranged in a second direction D2. The sacrificial contact pattern PLH can include a material with etch selectivity relative to the semiconductor substrate 105, such as silicon germanium (SiGe). The sacrificial contact pattern PLH can be formed using an epitaxial growth process.

[0105] The release layer DSL can be replaced with a silicon-based insulating material to form the pseudo-channel pattern DSP. For example, the release layer DSL exposed by recesses can be selectively removed. A silicon-based insulating material (e.g., silicon nitride) can be formed in areas where the release layer DSL has been removed. For example, areas where the release layer DSL has been removed can be filled with a silicon-based insulating material.

[0106] A second lower insulating layer LIL2 can be formed on the sacrificial contact pattern PLH. The upper surface of the second lower insulating layer LIL2 can be coplanar with the upper surface of the first lower insulating layer LIL1. The second lower insulating layer LIL2 can be formed of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0107] The lower source / drain pattern (LSD) can be formed on the second lower insulating layer (LIL2). The lower source / drain pattern (LSD) can be formed using a selective epitaxial growth process that uses the sidewalls exposed by the recesses of the lower stacked pattern (STP1) as a seed layer. For example, the first active layer (ACL1) can be used as a seed to grow the lower source / drain pattern (LSD).

[0108] While the lower source / drain patterned LSD is being formed, impurities can be implanted in situ into the lower source / drain patterned LSD. Alternatively, impurities can be implanted into the lower source / drain patterned LSD after its formation. For example, the lower source / drain patterned LSD can be doped to have a first conductivity type (e.g., N-type).

[0109] The first interlayer insulating layer 110 can be formed to cover the lower source / drain pattern LSD. According to an embodiment, the first interlayer insulating layer 110 can be formed after the insulating layer covering the lower source / drain pattern LSD is formed. For example, the first interlayer insulating layer 110 can be formed on the insulating layer covering the lower source / drain pattern LSD with a uniform thickness.

[0110] The first interlayer insulating layer 110 can expose the sidewalls of the upper stacked pattern STP2. An upper source / drain pattern USD can be formed on the first interlayer insulating layer 110. The upper source / drain pattern USD can be formed using a selective epitaxial growth process that uses the exposed sidewalls of the upper stacked pattern STP2 as a seed layer. For example, a second active layer ACL2 can be used as a seed to grow the upper source / drain pattern USD. The upper source / drain pattern USD can be doped to have a second conductivity type (e.g., P-type) different from the first conductivity type.

[0111] Reference Figure 8A , Figure 8B , Figure 8C and Figure 8D A second interlayer insulating layer 120 can be formed on the upper source / drain pattern USD. The second interlayer insulating layer 120 can cover the upper source / drain pattern USD. For example, the second interlayer insulating layer 120 may include a silicon oxide layer.

[0112] A planarization process can be performed on the second interlayer insulating layer 120 at least until the upper surface of the first sacrificial pattern PP1 is exposed. For example, the planarization process may include an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP on the first sacrificial pattern PP1 can be removed by the planarization process. Therefore, the upper surface of the second interlayer insulating layer 120 may be coplanar with the upper surface of the first sacrificial pattern PP1 and the upper surface of the gate spacer GS.

[0113] The exposed first sacrificial pattern PP1 can be selectively removed. Removing the first sacrificial pattern PP1 may include a wet etching process using an etchant that selectively removes polysilicon. The first sacrificial pattern PP1 can be removed, and the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can be exposed to the outside.

[0114] After removing the first sacrificial pattern PP1, an etching process can be performed to selectively remove the exposed first sacrificial layer SAL1 and the second sacrificial layer SAL2. Specifically, only the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can be removed, while leaving the first semiconductor pattern to the fourth semiconductor pattern SP1, SP2, SP3, and SP4, as well as the dummy channel pattern DSP, intact. The etching process used to remove the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can have a high etch rate for silicon-germanium. For example, the etching process can have a high etch rate for silicon-germanium, where the germanium concentration can be greater than approximately 10 at%.

[0115] The gate insulating layer GI can be located in the space where the first sacrificial pattern PP1 and the first sacrificial layer SAL1 and the second sacrificial layer SAL2 have been removed. The gate insulating layer GI can be formed with a uniform thickness. A gate electrode GE can be formed on the gate insulating layer GI. Forming the gate electrode GE may include: forming a first inner electrode to a fifth inner electrode PO1, PO2, PO3, PO4 and PO5 between the first semiconductor pattern to the fourth semiconductor pattern SP1, SP2, SP3 and SP4; and forming an outer electrode PO6 in the region where the first sacrificial pattern PP1 has been removed.

[0116] A gate cap pattern GP can be formed on the gate electrode GE. A planarization process can be performed on the gate cap pattern GP. The planarization process can be performed so that the upper surface of the gate cap pattern GP is coplanar with the upper surface of the second interlayer insulating layer 120.

[0117] A lower active region (LAR) comprising a lower channel pattern (LCH) and a lower source / drain pattern (LSD) can be formed, as well as an upper active region (UAR) comprising an upper channel pattern (UCH) and an upper source / drain pattern (USD). Each of the lower channel patterns (LCH) may include a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2), and the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) can be formed by a first active layer (ACL1). Each of the upper channel patterns (UCH) may include a third semiconductor pattern (SP3) and a fourth semiconductor pattern (SP4), and the third semiconductor pattern (SP3) and the fourth semiconductor pattern (SP4) can be formed by a second active layer (ACL2).

[0118] A first recess RS1 can be formed between single-height cells SHC. The first recess RS1 can be formed on the second interlayer insulating layer 120 and the gate cap pattern GP using an etching process employing a mask pattern. When viewed in plan view, the first recesses RS1 can be spaced apart from each other in a first direction D1, and each of the first recesses RS1 can extend in a second direction D2. Each of the first recesses RS1 can have an upper width TW at its upper end in the first direction D1.

[0119] The first recess RS1 can penetrate the second interlayer insulating layer 120 and the gate cap pattern GP. For example, the first recess RS1 can extend through the second interlayer insulating layer 120 and into the first interlayer insulating layer 110. Alternatively, the first recess RS1 can extend through the gate cap pattern GP into the gate electrode GE. That is, the first recess RS1 can penetrate a portion of the first interlayer insulating layer 110 and a portion of the gate electrode GE. Therefore, the bottom surface RS1L of the first recess RS1 can be disposed in the first interlayer insulating layer 110 and the gate electrode GE.

[0120] However, the present invention is not limited thereto. For example, the bottom surface RS1L of the first recess RS1 may be coplanar with the upper surface of the first interlayer insulating layer 110 or the lower surface of the second interlayer insulating layer 120. Alternatively, the bottom surface RS1L of the first recess RS1 may be disposed in the second interlayer insulating layer 120.

[0121] Reference Figure 9A , Figure 9B , Figure 9C and Figure 9D A first initial liner layer DMPa and a first initial portion P1a can be formed inside the first recess RS1. Forming the first initial liner layer DMPa and the first initial portion P1a may include: forming the first initial liner layer DMPa on the surface of the first interlayer insulating layer 110; forming an insulating material on the first initial liner layer DMPa in the first recess RS1; and performing a planarization process on the insulating material. The first initial liner layer DMPa can be formed with a uniform thickness across the entire surface of the first interlayer insulating layer 110. The insulating material can fill the first recess RS1. Through the planarization process, the upper surface of the first initial portion P1a can be coplanar with the upper surfaces of the second interlayer insulating layer 120 and the gate cap pattern GP.

[0122] A third interlayer insulating layer 130 can be formed on the second interlayer insulating layer 120, and an active contact UAC can be formed through the third interlayer insulating layer 130. The active contact UAC can be connected to the upper source / drain patterns USD, respectively. Additionally, a gate contact GC can be formed through the third interlayer insulating layer 130 and the gate cap pattern GP, ​​and the gate contact GC can be connected to the gate electrode GE. For example, the active contact UAC and the gate contact GC can be formed of a metal including at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0123] The fourth interlayer insulating layer 140 may be formed to cover the third interlayer insulating layer 130. A first metal layer M1 including an upper interconnect UMI may be formed in the fourth interlayer insulating layer 140. An upper via UVI may be formed in the first metal layer M1 to electrically connect the upper interconnect UMI to a gate contact GC or an upper active contact UAC. A BEOL layer including multiple metal layers may be formed on the first metal layer M1.

[0124] Reference Figure 10A , Figure 10B , Figure 10C and Figure 10D The semiconductor substrate 105 can be flipped to expose its back surface. A planarization process can be performed on the back surface of the semiconductor substrate 105 at least until the sacrificial contact pattern PLH and device isolation layer 107 are exposed. The height of the semiconductor substrate 105 can be reduced by the planarization process. The semiconductor substrate 105 can be replaced with a substrate 100. The substrate 100 can be an insulating substrate comprising a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride).

[0125] A second recess RS2 can be formed between single-height units SHC. The second recess RS2 can be formed on the second surface 100b of the substrate 100 by an etching process using a mask pattern. When viewed in plan view, the second recesses RS2 can be spaced apart from each other in a first direction D1, and each of the second recesses RS2 can extend in a second direction D2. Each of the second recesses RS2 can have a lower width BW at its upper end in the first direction D1. For example, each of the second recesses RS2 can be aligned with a reference... Figures 8A to 8D The first recess RS1 is described as vertically overlapping, and the lower width BW can be greater than the upper width TW.

[0126] The second recess RS2 can extend through the device isolation layer 107 and the first interlayer insulating layer 110 into the second interlayer insulating layer 120 or the gate electrode GE. For example, the second recess RS2 can extend in the third direction D3 at least until a portion of the first initial inner liner layer DMPa and a portion of the first initial portion P1a are removed. A first portion P1 can be formed, and the first portion P1 can be exposed to the outside through the second recess RS2.

[0127] A second initial inner liner layer DMPb can be formed on the second surface 100b of the substrate 100. The second initial inner liner layer DMPb can be disposed on the inner wall and bottom surface RS2L of the second recess RS2. The second initial inner liner layer DMPb can cover the inner wall and bottom surface RS2L of the second recess RS2 with a uniform thickness. The second initial inner liner layer DMPb can be in contact with the first portion P1 and the first initial inner liner layer DMPb in the second recess RS2.

[0128] Reference Figure 11A , Figure 11B , Figure 11C and Figure 11D An etching-back process can be performed on the second initial inner liner layer DMPb. The second initial inner liner layer DMPb on the second surface 100b of the substrate 100 can be removed by the etching-back process. Additionally, the portion of the second initial inner liner layer DMPb located on the bottom surface RS2L of the second recess RS2 can also be removed. As a result, the second initial inner liner layer DMPb can be formed only on the inner wall of the second recess RS2, and the first portion P1 can be exposed again. The first initial inner liner layer DMPb and the second initial inner liner layer DMPb can form an inner liner layer DMP disposed on the sidewall of the buried insulating layer FIL, which will be described subsequently.

[0129] After forming the inner liner layer DMP, a second portion P2 can be formed in the second recess RS2. Forming the second portion P2 may include forming an insulating material in the second recess RS2. The insulating material of the second portion P2 can be formed in a single process or through multiple processes. The second recess RS2 can be filled with the insulating material. A planarization process can be performed on the insulating material. The planarization process can be performed at least until the second surface 100b of the substrate 100 and the device isolation layer 107 are exposed. The first portion P1 and the second portion P2 can be as referenced Figures 5A to 5C The various forms described are in contact with each other. A buried insulating layer FIL comprising a first portion P1 and a second portion P2 that are in contact with each other can be formed, and a gate dicing pattern CTP comprising a buried insulating layer FIL and an inner liner layer DMP can be formed.

[0130] A first lower interlayer insulating layer 200 can be formed on the second surface 100b of the substrate 100. The first lower interlayer insulating layer 200 can be disposed on the second portion P2 of the device isolation layer 107 and the buried insulating layer FIL. For example, the first lower interlayer insulating layer 200 can cover the device isolation layer 107 and the second portion P2 of the buried insulating layer FIL.

[0131] The first lower interlayer insulating layer 200 can be patterned to expose the sacrificial contact pattern PLH. The exposed sacrificial contact pattern PLH can be replaced with a lower active contact LAC. For example, the sacrificial contact pattern PLH can be selectively removed. An etching process can be performed in the space where the sacrificial contact pattern PLH has been removed to expose the lower source / drain pattern LSD. Lower active contacts LACs connected to each of the exposed lower source / drain patterns LSD can be formed. The lower active contacts LACs can be formed using a self-aligned method using the sacrificial contact pattern PLH, but are not limited thereto.

[0132] Refer again Figure 4A , Figure 4B , Figure 4C and Figure 4D A second lower interlayer insulating layer 210 may be formed below the first lower interlayer insulating layer 200. A back metal layer BSM may be formed in the second lower interlayer insulating layer 210. The back metal layer BSM may include a lower interconnect LMI. A lower via LVI that electrically connects a lower active contact LAC and a lower interconnect LMI may be formed in the back metal layer BSM. Multiple back metal layers may be formed on the back metal layer BSM. For example, the multiple back metal layers may include a power transmission network layer. The power transmission network layer may include a wiring network for applying source voltage and / or drain voltage to the back metal layer BSM.

[0133] A method for manufacturing a three-dimensional semiconductor device according to embodiments of the present invention may include forming a first portion P1 and a second portion P2 of a gate diced pattern CTP using different processes. For example, the first portion P1 of the gate diced pattern CTP may be formed on a first surface 100t of a substrate 100, and the second portion P2 may be formed on a second surface 100b of the substrate 100. Therefore, in a gate diced pattern CTP with a high aspect ratio, insulating material can be filled without gaps. Additionally, the dimensions of the recesses RS1 and RS2 used to form the first portion P1 and the second portion P2 can be reduced. Therefore, the electrical characteristics and integration density of the three-dimensional semiconductor device can be improved.

[0134] According to embodiments of the present invention, a gate dicing pattern may include a first portion formed on the front surface of a substrate and a second portion formed on the rear surface of the substrate. That is, since the first and second portions are formed through different processes, insulating material can be easily filled into the gate dicing pattern with a large aspect ratio without gaps. Furthermore, since the gate dicing pattern can be formed through multiple processes, the size of the recesses used to form the first and second portions can be reduced. Therefore, the integration density, electrical characteristics, and reliability of the three-dimensional semiconductor device can be improved.

[0135] Although embodiments have been described above, those skilled in the art will understand that many modifications and changes can be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: A first active region is located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; A second active region is located on top of the first active region, and the second active region includes an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern. A gate electrode is located on the lower channel pattern and the upper channel pattern; as well as The gate dicing pattern penetrates the gate electrode, and The gate dicing pattern has an intermediate width between its upper and lower surfaces, which is smaller than the upper width of the upper part of the gate dicing pattern and the lower width of the lower part of the gate dicing pattern.

2. The three-dimensional semiconductor device according to claim 1, wherein, The gate electrode extends in a first direction, and The gate dicing pattern extends in a second direction that intersects with the first direction.

3. The three-dimensional semiconductor device according to claim 1, wherein, The upper width is the width at the upper surface of the gate dicing pattern, and the lower width is the width at the lower surface of the gate dicing pattern. Wherein, the upper width is smaller than the lower width.

4. The three-dimensional semiconductor device according to claim 1, wherein, The lower surface of the gate dicing pattern is coplanar with the lower surface of the substrate.

5. The three-dimensional semiconductor device according to claim 1, wherein, The gate dicing pattern includes a buried insulating layer and an inner liner layer located on the sidewall of the buried insulating layer.

6. The three-dimensional semiconductor device according to claim 1, wherein, The vertical length of the gate dicing pattern is greater than the vertical length of the gate electrode.

7. The three-dimensional semiconductor device according to claim 1, wherein, Each of the upper channel pattern and the lower channel pattern includes a plurality of semiconductor patterns spaced apart from each other, and The gate electrode surrounds the plurality of semiconductor patterns.

8. A three-dimensional semiconductor device, comprising: A first active region is located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; A second active region is located on top of the first active region, and the second active region includes an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern. A gate electrode is disposed on the lower channel pattern and the upper channel pattern and extends in a first direction; as well as A gate dicing pattern that penetrates the gate electrode. The gate dicing pattern includes: The first part, which is adjacent to the second active region; and The second part is adjacent to the first active region, and Each of the first portion and the second portion has a width that decreases as the first portion and the second portion are adjacent to each other.

9. The three-dimensional semiconductor device according to claim 8, wherein, The gate dicing pattern extends in a second direction intersecting the first direction. Wherein, the first portion has a first central axis along the first direction, and The second part has a second central axis along the first direction.

10. The three-dimensional semiconductor device according to claim 9, wherein, The first central axis and the second central axis are aligned with each other.

11. The three-dimensional semiconductor device according to claim 9, wherein, The first central axis and the second central axis are spaced apart from each other.

12. The three-dimensional semiconductor device according to claim 8, wherein, The gate dicing pattern has a stepped surface located between the sidewall of the first portion and the sidewall of the second portion.

13. The three-dimensional semiconductor device according to claim 12, wherein, The gate dicing pattern includes an inner liner layer located on the sidewall of the first portion, the sidewall of the second portion, and the surface of the step.

14. The three-dimensional semiconductor device according to claim 8, wherein, The gate dicing pattern has an upper width at its upper surface and a lower width at its lower surface, and The upper width and the lower width are different from each other.

15. The three-dimensional semiconductor device according to claim 8, wherein, The middle width of the gate dicing pattern is the minimum width located at the interface where the first part and the second part contact each other.

16. A three-dimensional semiconductor device, comprising: A first active region is located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; A second active region is located on top of the first active region, and the second active region includes an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern. The lower active contact is connected to the lower source / drain pattern; There is an active contact element that is connected to the upper source / drain pattern; A gate electrode is disposed on the lower channel pattern and the upper channel pattern and extends in a first direction; A gate contact connected to the gate electrode; as well as A gate dicing pattern extends in a second direction intersecting the first direction and penetrates the gate electrode. The gate dicing pattern includes a first portion and a second portion below the first portion, and The gate dicing pattern has a middle width at the interface where the first portion and the second portion contact each other, and the middle width is smaller than the upper width of the first portion of the gate dicing pattern and the lower width of the second portion of the gate dicing pattern.

17. The three-dimensional semiconductor device according to claim 16, wherein, The first part and the second part comprise the same insulating material, and The central axis of the first part and the central axis of the second part are spaced apart from each other.

18. The three-dimensional semiconductor device according to claim 16, wherein, The upper width is the width at the upper surface of the gate dicing pattern, and the lower width is the width at the lower surface of the gate dicing pattern. Wherein, the upper width is smaller than the lower width.

19. The three-dimensional semiconductor device according to claim 16, wherein, The minimum width of the first part and the minimum width of the second part are different from each other.

20. The three-dimensional semiconductor device according to claim 16, wherein, The upper surface of the gate dicing pattern is higher than the upper surface of the gate electrode, and Wherein, the lower surface of the gate dicing pattern is lower than the lower surface of the gate electrode.

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