Semiconductor device

Abstract

A semiconductor device may include a substrate including a first region and a second region; a first device on the first region; and a second device on the second region. The first device may include a channel structure including an insulating isolation pattern, a first semiconductor pattern stacked under a lower surface of the insulating isolation pattern and including silicon germanium, and a second semiconductor pattern stacked on an upper surface of the insulating isolation pattern and including silicon. The second device may include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack may include an intermediate semiconductor layer, first and second lower semiconductor layers alternately stacked under a lower surface of the intermediate semiconductor layer, and first and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate to a semiconductor device. BACKGROUND

[0002] As demands for high performance, high speed, and / or multi-functionality of semiconductor devices have increased, the integration density of semiconductor devices has increased. To overcome limitations of operating characteristics due to size reduction of planar metal oxide semiconductor field effect transistors (MOSFETs), semiconductor devices including a gate-all-around type field effect transistor (FET) including a nanosheet surrounded by a gate and a FinFET including a fin-shaped channel have been developed. SUMMARY

[0003] Example embodiments of the present disclosure provide a semiconductor device having improved electrical characteristics and reliability.

[0004] According to example embodiments of the present disclosure, a semiconductor device can include a substrate including a first region and a second region, a semiconductor device on the first region of the substrate, and a semiconductor stack on the second region of the substrate. The semiconductor device can include a channel structure including an insulating isolation pattern, first semiconductor patterns stacked and spaced apart from each other in a vertical direction below a lower surface of the insulating isolation pattern, and second semiconductor patterns stacked and spaced apart from each other in the vertical direction on an upper surface of the insulating isolation pattern, first source / drain patterns on both sides of the channel structure in a first direction and connected to both sides of the first semiconductor patterns, respectively, second source / drain patterns on the both sides of the channel structure and connected to both sides of the second semiconductor patterns, respectively, a first gate structure extending in a second direction crossing the first direction and surrounding the first semiconductor patterns, and a second gate structure extending in the second direction and surrounding the second semiconductor patterns. The semiconductor stack can include an intermediate semiconductor layer at a level corresponding to a level of the insulating isolation pattern, first lower semiconductor layers and second lower semiconductor layers alternately stacked below a lower surface of the intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer. The first semiconductor patterns and the second lower semiconductor layers can include a first semiconductor material, and the second semiconductor patterns and the second upper semiconductor layers can include a second semiconductor material. One of the first semiconductor material and the second semiconductor material can include silicon, and the other of the first semiconductor material and the second semiconductor material can include silicon germanium including germanium at a first concentration. The first lower semiconductor layers and the first upper semiconductor layers can include silicon germanium including germanium at a second concentration. The second concentration can be higher than the first concentration. The intermediate semiconductor layer can include silicon germanium at a third concentration, and the third concentration can be higher than the second concentration.

[0005] According to example embodiments of the present disclosure, a semiconductor device can include a substrate including a first region and a second region; a first device on the first region of the substrate; and a second device on the second region of the substrate. The first device can include a channel structure including an insulating isolation pattern, a first semiconductor pattern stacked in a vertical direction below a lower surface of the insulating isolation pattern and spaced apart from each other, and a second semiconductor pattern stacked in the vertical direction on an upper surface of the insulating isolation pattern and spaced apart from each other, the first semiconductor pattern and the second semiconductor pattern including silicon germanium and silicon, respectively; a pair of first source / drain patterns on both sides of the channel structure in a first direction and connected to both sides of the first semiconductor pattern, respectively; a pair of second source / drain patterns on both sides of the channel structure and connected to both sides of the second semiconductor pattern, respectively; and a gate structure extending in a second direction, the second direction crossing the first direction, the gate structure surrounding the first semiconductor pattern and the second semiconductor pattern. The second device can include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack can include an intermediate semiconductor layer, a first lower semiconductor layer and a second lower semiconductor layer alternately stacked below a lower surface of the intermediate semiconductor layer, and a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on an upper surface of the intermediate semiconductor layer. The intermediate semiconductor layer, the first lower semiconductor layer, the second lower semiconductor layer, and the first upper semiconductor layer can include silicon germanium. The second upper semiconductor layer can include silicon. The first semiconductor pattern and the second lower semiconductor layer can have the same germanium concentration.

[0006] According to example embodiments of the present disclosure, a semiconductor device can include a substrate including a first region and a second region, the second region being at a periphery of the first region; a semiconductor device on the first region of the substrate; and a semiconductor stack on the second region of the substrate. The semiconductor device can include an insulating isolation pattern, a first semiconductor pattern stacked in a vertical direction below a lower surface of the insulating isolation pattern and spaced apart from each other, and a second semiconductor pattern stacked in the vertical direction on an upper surface of the insulating isolation pattern and spaced apart from each other, the first semiconductor pattern and the second semiconductor pattern including silicon germanium and silicon, respectively. The semiconductor stack can include an intermediate semiconductor layer at a level corresponding to a level of the insulating isolation pattern, a first lower semiconductor layer and a second lower semiconductor layer alternately stacked below a lower surface of the intermediate semiconductor layer, and a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on an upper surface of the intermediate semiconductor layer. The intermediate semiconductor layer, the first lower semiconductor layer, the second lower semiconductor layer, and the first upper semiconductor layer can include silicon germanium. The second upper semiconductor layer can include silicon. The first semiconductor pattern and the second lower semiconductor layer can include a first concentration of germanium. The first lower semiconductor layer and the first upper semiconductor layer can include a second concentration of germanium. The second concentration can be higher than the first concentration. The intermediate semiconductor layer can include a third concentration of germanium. The third concentration can be higher than the second concentration. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0009] Figure 2A , Figure 2B and Figure 2C It is shown Figure 1 A cross-sectional view of the first region A of the semiconductor device in the image, taken along lines I-I', II1-II1' and II2-II2';

[0010] Figure 3A and Figure 3B yes Figure 1 A cross-sectional view of the second region B of the semiconductor device along lines III1-III1' and IV-IV';

[0011] Figure 4 This is a cross-sectional view taken from the side, showing circuitry that may be used in a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figure 5 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0013] Figure 6 It is shown Figure 5 A cross-sectional view taken along line III2-III2' of the second region of the semiconductor device;

[0014] Figure 7 This is a cross-sectional view taken from the side, showing circuitry that may be used in a semiconductor device according to an exemplary embodiment of the present disclosure;

[0015] Figure 8 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0016] Figure 9 It shows the semiconductor device along Figure 8 A cross-sectional view taken from line V-V';

[0017] Figures 10A to 10H This is a cross-sectional view illustrating a portion of the process of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; and

[0018] Figures 11A to 11G This is a cross-sectional view illustrating another part of the process of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the disclosure will be described below with reference to the accompanying drawings.

[0020] Figure 1 is a plan view illustrating a semiconductor device according to an example embodiment. Figure 2A 、 Figure 2B and Figure 2C are cross-sectional views illustrating a first region A of the semiconductor device in Figure 1 along lines I-I', II1-II1', and II2-II2'. Figure 3A and Figure 3B are cross-sectional views illustrating a second region B of the semiconductor device in Figure 1 along lines III1-III1' and IV-IV'.

[0021] Referring to Figure 1 , the semiconductor device 200 according to an example embodiment can include a substrate 101 including a first region A and a second region B arranged in a horizontal direction (e.g., an X direction or a Y direction). In an example embodiment, a first device 100A (also referred to as a "logic device") can be disposed in the first region A of the substrate 101, and a second device 100B (also referred to as a "circuit device") can be disposed in the second region B of the substrate 101. The first device 100A can be referred to as a semiconductor device.

[0022] Referring to Figure 1 and Figures 2A to 2C , the first device 100A of the semiconductor device 200 according to an example embodiment can include a channel structure CS extending in a first direction (e.g., an X direction) and a first gate structure GS1 and a second gate structure GS2 extending in a second direction (e.g., a Y direction) that spans one region of the channel structure CS and intersects the first direction (e.g., the X direction). Here, the channel structure CS can be divided into a lower channel structure including a first semiconductor pattern 131 and an upper channel structure including a second semiconductor pattern 132.

[0023] The substrate 101 can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 can include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer. In some example embodiments, the substrate 101 can be an insulating substrate including an insulating material. For example, after a substrate that is a semiconductor is removed, a layer of the insulating material can be formed in the removed area, thereby providing the insulating substrate. The insulating material included in the insulating substrate can include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxycarbinitride.

[0024] As shown in FIG. 1A, the active pattern 105 can have a fin-type structure extending from the substrate 101 in a first direction (e.g., the X direction). As shown in FIG. 1A, the device isolation layer 110 can define the active pattern 105 in the substrate 101. The device isolation layer 110 can be disposed on the substrate 101, and a portion of the active pattern 105 can protrude from an upper surface of the device isolation layer 110. The device isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. The device isolation layer 110 can include an insulating material. For example, the device isolation layer 110 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Figure 2A Figures 2B to 2C In example embodiments, the active pattern 105 can be configured to be a portion of the substrate 101 that is a semiconductor, as a semiconductor pattern, but example embodiments thereof are not limited thereto. In some example embodiments, the active pattern 105 can be replaced with an insulating pattern including an insulating material. In a process of forming the above-described insulating substrate, a portion or all of the active pattern 105 can be removed, and a space in which the portion or all of the active pattern 105 is removed can be filled with the insulating material, such that the semiconductor device 200 can have an insulating pattern corresponding to the active pattern 105. For example, the insulating material included in the insulating pattern can include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxycarbinitride. In some example embodiments, the insulating pattern and / or the insulating substrate can include the same material as that of the device isolation layer 110.

[0025] In example embodiments, the active pattern 105 can be configured to be a portion of the substrate 101 that is a semiconductor, as a semiconductor pattern, but example embodiments thereof are not limited thereto. In some example embodiments, the active pattern 105 can be replaced with an insulating pattern including an insulating material. In a process of forming the above-described insulating substrate, a portion or all of the active pattern 105 can be removed, and a space in which the portion or all of the active pattern 105 is removed can be filled with the insulating material, such that the semiconductor device 200 can have an insulating pattern corresponding to the active pattern 105. For example, the insulating material included in the insulating pattern can include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxycarbinitride. In some example embodiments, the insulating pattern and / or the insulating substrate can include the same material as that of the device isolation layer 110.

[0026] ​In an example embodiment, the first device 100A can include a first transistor TR1 and a second transistor TR2 stacked on the first region A of the substrate 101. The first transistor TR1 disposed at the lower portion can include a first semiconductor pattern 131, a first gate structure GS1, and a first source / drain pattern 150A (which can be a lower channel structure), and the second transistor TR2 disposed at the upper portion can include a second semiconductor pattern 132, a second gate structure GS2, and a second source / drain pattern 150B (which can be an upper channel structure). Each of the first transistor TR1 and the second transistor TR2 can be a multi-bridge channel FET (MBCFET TM ).

[0027] The first transistor TR1 can be one of an N-type MOSFET and a P-type MOSFET, and the second transistor TR2 can be the other of the P-type MOSFET and the N-type MOSFET. In an example embodiment, the first transistor TR1 can be a P-type MOSFET, and the second transistor TR2 can be an N-type MOSFET.

[0028] In detail, referring to Figure 2A , the channel structure CS can include an insulating separation pattern 160, the first semiconductor patterns 131 stacked and spaced apart from each other in a third direction (e.g., a Z direction) which is a vertical direction below a lower surface of the insulating separation pattern 160, and the second semiconductor patterns 132 stacked and spaced apart from each other in the third direction (e.g., a Z direction) on an upper surface of the insulating separation pattern 160.

[0029] Among the first semiconductor patterns 131, the insulating separation pattern 160 can be disposed on the uppermost first semiconductor pattern, and the second semiconductor patterns 132 can be stacked and spaced apart from each other on the insulating separation pattern 160. The insulating separation pattern 160 can be arranged to overlap the first semiconductor patterns 131 and the second semiconductor patterns 132 in the third direction (e.g., a Z direction) which is a vertical direction.

[0030] In some example embodiments, a plurality of first semiconductor patterns 131 (e.g., two or three first semiconductor patterns) can be provided. The first semiconductor patterns 131 can include silicon germanium (SiGe). A plurality of second semiconductor patterns 132 (e.g., two or three second semiconductor patterns) can be provided. For example, the second semiconductor patterns 132 can include silicon (Si). In some example embodiments, one of the first semiconductor patterns 131 and the second semiconductor patterns 132 can include silicon, and the other of the first semiconductor patterns 131 and the second semiconductor patterns 132 can include silicon germanium.

[0031] To improve the carrier mobility (e.g., hole mobility), the SiGe of the first semiconductor pattern 131 can include a first concentration of germanium. For example, the first concentration can be in a range from 4 atomic % to 7 atomic %. Further, in terms of improving the carrier mobility, the upper surface of the first semiconductor pattern 131 can be a (110) crystal plane. The first semiconductor pattern 131 can be grown, for example, on an upper surface of a silicon substrate that is a (110) crystal plane. The upper surface of the second semiconductor pattern 132 can be a (110) crystal plane.

[0032] The insulating isolation pattern 160 can include an insulating material, and can include, for example, at least one of silicon nitride, silicon oxynitride, and silicon carbonitride. The insulating isolation pattern 160 can be a single layer of insulating material, but in some example embodiments, the insulating isolation pattern 160 can include multiple layers of insulating material.

[0033] The gate structure GS employed in the example embodiments can include a first gate structure GS1 and a second gate structure GS2.

[0034] Referring to Figure 1 , Figure 2A and Figure 2C , the first gate structure GS1 can span one region of the active pattern 105, and can extend in the second direction (e.g., the Y direction), and similarly, the second gate structure GS2 can extend in the second direction (e.g., the Y direction).

[0035] In particular, referring to Figure 2A and Figure 2B , the first gate structure GS1 employed in the example embodiments can include a first gate electrode 145A surrounding the first semiconductor pattern 131 and a first gate insulating film 142A between the first semiconductor pattern 131 and the first gate electrode 145A. In some example embodiments, the first gate insulating film 142A can be formed between the first semiconductor pattern 131 and the first gate electrode 145A, and can also extend in the second direction (e.g., the Y direction) along a lower surface of the insulating isolation pattern 160.

[0036] Similarly, the second gate structure GS2 employed in the example embodiments can include a second gate electrode 145B surrounding the second semiconductor pattern 132, a second gate insulating film 142B between the second semiconductor pattern 132 and the second gate electrode 145B, a gate spacer 141 disposed on both sidewalls of the second gate electrode 145B, and a gate cap layer 147 disposed on the second gate electrode 145B between the gate spacers 141.

[0037] The first gate electrode 145A and the second gate electrode 145B employed in example implementations can include different conductive materials. For example, the first gate electrode 145A and the second gate electrode 145B can include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. In some example implementations, the first gate electrode 145A and the second gate electrode 145B can include a semiconductive material, such as doped polysilicon. At least one of the first gate electrode 145A and the second gate electrode 145B can include a multi-layer structure formed of different materials.

[0038] The first gate insulating film 142A and the second gate insulating film 142B can include a dielectric material. For example, each of the first gate insulating film 142A and the second gate insulating film 142B can include at least one of an oxide, a nitride, and a high-k material. The high-k material can be, for example, at least one of aluminum oxide (AI2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x y O x y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x y ), lanthanum hafnium oxide (LaHf x y ), hafnium aluminum oxide (HfAl x y ), and praseodymium oxide (Pr2O3). The first gate insulating film 142A and the second gate insulating film 142B can include the same dielectric material or can include different dielectric materials.

[0039] The gate spacers 141 can include the same insulating material or a plurality of insulating materials that are partially different. For example, the gate spacers 141 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some example implementations, the gate spacers 141 can include a multi-layer structure including different materials. The gate cap layer 147 can include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

[0040] ​​​​​The first device 100A according to the example embodiment can further include a pair of first source / drain patterns 150A disposed on both sides of the first semiconductor pattern 131 in the first direction (e.g., the X direction) and a pair of second source / drain patterns 150B disposed on both sides of the second semiconductor pattern 132 in the first direction (e.g., the X direction). The first source / drain patterns 150A and the second source / drain patterns 150B can be arranged to overlap each other in a third direction (e.g., the Z direction) that is a vertical direction.

[0041] The first source / drain patterns 150A can include epitaxial layers grown from both side surfaces of the first semiconductor pattern 131. Similarly, the second source / drain patterns 150B can include epitaxial layers grown from both side surfaces of the second semiconductor pattern 132.

[0042] The first source / drain patterns 150A and the second source / drain patterns 150B can include impurities of different types and / or having different concentrations. In some example embodiments, the first source / drain patterns 150A can include epitaxial layers doped with impurities of a first conductivity type, and the second source / drain patterns 150B can include epitaxial layers doped with impurities of a second conductivity type.

[0043] When the first transistor TR1 is provided as a P-MOSFET, the first source / drain patterns 150A can include silicon germanium (SiGe) doped with P-type impurities. When the second transistor TR2 is provided as an N-MOSFET, the second source / drain patterns 150B can include silicon or silicon germanium (SiGe) doped with N-type impurities.

[0044] In some example embodiments, cross sections of the first source / drain patterns 150A and the second source / drain patterns 150B in the second direction (e.g., the Y direction) can have different shapes. For example, a cross section of the first source / drain patterns 150A can have a pentagonal shape, and a cross section of the second source / drain patterns 150B can have a polygonal shape with gentle edges (see Figure 2B ).

[0045] The first device 100A according to the example embodiment can include an isolation insulating layer 170 disposed on the device isolation layer 110 and covering the first source / drain patterns 150A. As Figure 2B indicated, the isolation insulating layer 170 can be disposed on the first source / drain patterns 150A and can electrically isolate the first source / drain patterns 150A and the second source / drain patterns 150B from each other. The first device 100A according to the example embodiment can include an interlayer insulating layer 180 covering the second source / drain patterns 150B and disposed on the isolation insulating layer 170.

[0046] The isolation insulating layer 170 and the interlayer insulating layer 180 can be silicon oxide. For example, the isolation insulating layer 170 and the interlayer insulating layer 180 can include a spin-on hard mask (SOH), a flowable oxide (FOX), a Tokyo Ohka Kogyo silicon azane (TOSZ), an undoped silica glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma-enhanced tetraethyl orthosilicate (PETEOS), a fluorosilicate glass (FSG), a high-density plasma (HDP) oxide, a plasma-enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof. The isolation insulating layer 170 and the interlayer insulating layer 180 can be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin-on process.

[0047] The first device 100A according to the example embodiment can further include a first lower contact 250A connected to the first source / drain pattern 150A and a first upper contact 260A connected to the second source / drain pattern 150B. The first lower contact 250A can penetrate the substrate 101 and can be connected to the first source / drain pattern 150A. The first lower contact 250A employed in the example embodiment can include a conductive via 230 penetrating the substrate 101 and a conductive connection portion 220 formed by selectively removing the buried sacrificial pattern 220P. The buried sacrificial pattern 220P can remain in a lower portion of the first source / drain pattern 150A in which the first lower contact 250A is not formed. The first device 100A can further include a gate contact (not shown) connected to the first gate electrode 145A and / or the second gate electrode 145B. For example, the first lower contact 250A and the first upper contact 260A can include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0048] Referring to Figure 1 , the semiconductor device 200 according to the example embodiment can include a second device 100B included in a peripheral circuit in a second region B. The second region B can be a peripheral region of the semiconductor device 200, but example embodiments thereof are not limited thereto, and the second device 100B can be disposed in a main region together with the first device 100A.

[0049] Referring to Figure 3A and Figure 3B , the second device 100B employed in the example embodiment can include a semiconductor stack SL in which semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions are stacked.

[0050] The semiconductor stack SL can be provided as a main structure of the second device 100B to configure passive devices (e.g., resistors, capacitors, etc.) or active devices (e.g., PN diodes, bipolar junction transistors (BJTs), etc.) required for a circuit configuration. In some example embodiments, the semiconductor stack SL can include at least one of a first-conductivity-type impurity region W1 and a second-conductivity-type impurity region W2. In example embodiments, the semiconductor stack SL can include the first-conductivity-type impurity region W1 and the second-conductivity-type impurity region W2 surrounding the first-conductivity-type impurity region W1.

[0051] The second device 100B according to the example embodiments can further include a plurality of gate structures GS2' extending over the semiconductor stack SL in a second direction (Y direction). The gate structure GS2' employed in the example embodiments can have a structure corresponding to the second gate structure GS2, but can be understood as a dummy structure not involved in driving. The gate structure GS2' employed in the example embodiments can include a second gate electrode 145B extending in a second direction (e.g., Y direction) on an upper surface of the semiconductor stack SL, a second gate insulating film 142B between the upper surface of the semiconductor stack SL and the second gate electrode 145B, a gate spacer 141 provided on both sidewalls of the second gate electrode 145B, and a gate cap layer 147 provided on the second gate electrode 145B between the gate spacers 141. In some example embodiments (see Figure 7 ), the gate structure GS2' of the second device 100B can be left as a dummy gate structure or a passive gate structure.

[0052] In example embodiments, the plurality of gate structures GS2' can be arranged at the same pitch as the pitch of the second gate structure GS2 of the first device 100A and / or at the same width as the width of the second gate structure GS2 of the first device 100A. However, in some example embodiments (see Figures 5 to 7 ), the plurality of gate structures GS2' can be arranged at a width greater than the width of the second gate structure GS2 of the first device 100A and / or at a pitch greater than the pitch of the second gate structure GS2 of the first device 100A.

[0053] Referring to Figure 3A and Figure 3B , the semiconductor stack SL employed in the example embodiments can include an intermediate semiconductor layer 125L, a lower stack SL1 including first lower semiconductor layers 121L and second lower semiconductor layers 131L alternately stacked below a lower surface of the intermediate semiconductor layer 125L, and an upper stack SL2 including first upper semiconductor layers 122L and second upper semiconductor layers 132L alternately stacked on an upper surface of the intermediate semiconductor layer 125L.

[0054] The semiconductor stack SL of the second device 100B can be understood as a structure corresponding to the semiconductor stack (SL) in the channel structure CS forming the first device 100A. Figure 10A

[0055] Specifically, the intermediate semiconductor layer 125L can be disposed at a level corresponding to the level of the insulating isolation pattern 160 of the first device 100A. Similarly, the second lower semiconductor layer 131L and the second upper semiconductor layer 132L can be disposed at levels corresponding to the levels of the first semiconductor pattern 131 and the second semiconductor pattern 132, respectively.

[0056] The second lower semiconductor layer 131L can correspond to the first semiconductor pattern 131 included in the lower channel structure of the first device 100A, respectively. Each second lower semiconductor layer 131L can include a material layer substantially the same as that of the first semiconductor pattern 131, and can have a thickness substantially the same as that of the first semiconductor pattern 131. Similarly, the second upper semiconductor layer 132L can correspond to the second semiconductor pattern 132 included in the upper channel structure of the first device 100A, respectively. Each second upper semiconductor layer 132L can include a material layer substantially the same as that of the second semiconductor pattern 132, and can have a thickness substantially the same as that of the second semiconductor pattern 132. The viewpoint of "substantially the same" can mean that the elements can be exactly the same, or can be determined to be the same considering errors or deviations occurring during the process.

[0057] The first lower semiconductor layer 121L and the first upper semiconductor layer 122L can correspond to the first and second sacrificial patterns (121 and 122) in the lower channel structure and the upper channel structure for forming the first device 100A, respectively. Figure 11A Figure 11B In addition, the intermediate semiconductor layer 125L can correspond to the intermediate sacrificial pattern (125) in the lower channel structure and the upper channel structure for forming the insulating isolation pattern 160 of the first device 100A. Figure 11A Figure 11B

[0058] ​​​​In example embodiments, the semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions can have different germanium concentrations. The second lower semiconductor layer 131L can include substantially the same silicon germanium as the silicon germanium of the first semiconductor pattern 131, and the second upper semiconductor layer 132L can include substantially the same semiconductor as the semiconductor of the second semiconductor pattern 132, i.e., silicon. As described above, the second lower semiconductor layer 131L can include germanium at a first concentration that is substantially similar to the germanium concentration of the first semiconductor pattern 131. For example, the second lower semiconductor layer 131L can include a germanium concentration in a range from 4 atomic % to 7 atomic %.

[0059] Each of the first lower semiconductor layer 121L and the first upper semiconductor layer 122L can include silicon germanium having germanium at a second concentration other than the first concentration. For example, the second concentration can be in a range from 10 atomic % to 20 atomic %. In example embodiments, the first lower semiconductor layer 121L can have a greater germanium concentration than the germanium concentration of each of the first upper semiconductor layers 122L, but example embodiments are not limited thereto, and the first lower semiconductor layer 121L and the first upper semiconductor layer 122L can have the same germanium concentration.

[0060] The intermediate semiconductor layer 125L can include silicon germanium having germanium at a third concentration other than the second concentration of each of the first lower semiconductor layer 121L and the first upper semiconductor layer 122L. For example, the third concentration can be in a range from 30 atomic % to 45 atomic %.

[0061] During a manufacturing process, some elements (e.g., Ge) can diffuse to other semiconductor layers adjacent thereto in the semiconductor stack SL, and thus, in a final structure, the concentration of some elements can slightly change in each of the semiconductor layers 121L, 122L, 125L, 131L, and 132L. For example, the second lower semiconductor layer 131L can include substantially the same germanium concentration as the germanium concentration of the first semiconductor pattern 131, and the germanium concentration of the second lower semiconductor layer 131L at a center in a thickness direction can approach the germanium concentration of the first semiconductor pattern 131. Similarly, the second upper semiconductor layer 132L can include substantially the same silicon as the silicon of the second semiconductor pattern 132, but a relatively lower concentration of germanium distribution can occur in a region of the second upper semiconductor layer 132L adjacent to the other semiconductor layers 122L and 125L.

[0062] In some example embodiments, the thickness of the intermediate semiconductor layer 125L can be greater than the thickness of each of the first lower semiconductor layer 121L and the second lower semiconductor layer 131L or each of the first upper semiconductor layer 122L and the second upper semiconductor layer 132L.

[0063] The semiconductor stack SL can have recesses in a portion of the region between the plurality of gate structures, and the first-conductivity-type epitaxial pattern 150E1 and the two second-conductivity-type epitaxial patterns 150E2 and 150E2 can be formed in the recesses, respectively.

[0064] As described above, the semiconductor stack SL can include a first-conductivity-type impurity region W1 and a second-conductivity-type impurity region W2 surrounding the first-conductivity-type impurity region W1. The first-conductivity-type impurity region W1 can be an N-type impurity region, and the second-conductivity-type impurity region W2 can be a P-type impurity region. In an example embodiment, the first-conductivity-type epitaxial pattern 150E1, like the first source / drain pattern 150A, can be a P-type epitaxial layer, and the second-conductivity-type epitaxial pattern 150E2, like the second source / drain pattern 150B, can be an N-type epitaxial layer.

[0065] With the above arrangement, as shown in FIG. 1B, in the second device 100B according to an example embodiment, the second-conductivity-type epitaxial pattern 150E2 can be an emitter and a collector of an NPN bipolar transistor, respectively, and the first-conductivity-type epitaxial pattern 150E1 can be a base of the NPN bipolar transistor. Figure 3A and Figure 3B As shown in FIG. 1B, in the second device 100B according to an example embodiment, the second-conductivity-type epitaxial pattern 150E2 can be an emitter and a collector of an NPN bipolar transistor, respectively, and the first-conductivity-type epitaxial pattern 150E1 can be a base of the NPN bipolar transistor.

[0066] In an example embodiment, the first-conductivity-type epitaxial pattern 150E1 and the second-conductivity-type epitaxial pattern 150E2 can be epitaxial layers grown in the same process as a process of forming the first source / drain pattern 150A and the second source / drain pattern 150B of the first device 100A, respectively.

[0067] In an example embodiment, the recesses of the semiconductor stack SL in which the first-conductivity-type epitaxial pattern 150E1 and the second-conductivity-type epitaxial pattern 150E2 are formed can have a depth lower than a depth of the recesses of the first device 100A (see FIG. 1A), but example embodiments thereof are not limited thereto, and at least one of the recesses of the semiconductor stack SL can be formed to have the same depth as the depth of the recesses of the first device 100A. Further, in an example embodiment, the recesses for the first-conductivity-type epitaxial pattern 150E1 and the second-conductivity-type epitaxial pattern 150E2 can have the same depth, but example embodiments thereof are not limited thereto, and the recesses can have different depths. For example, the recess for the first-conductivity-type epitaxial pattern 150E1 can have a different depth from a depth of the recess for the second-conductivity-type epitaxial pattern 150E2 (see FIG. 1B). Figure 10D Figure 4

[0068] ​​Similar to the first upper contact 260A of the first device 100A, the second device 100B according to the example embodiment can further include a plurality of second upper contacts 260B1, 260B2, and 260B3 that penetrate the interlayer insulation layer 180 and are connected to the first conductive type epitaxial pattern 150E1 and the second conductive type epitaxial pattern 150E2. The plurality of second upper contacts 260B1, 260B2, and 260B3 can serve as emitter electrodes, base electrodes, and collector electrodes. For example, the second upper contacts 260B1, 260B2, and 260B3 can include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0069] The semiconductor device 200 according to the example embodiment can include a first interconnection structure 280 (also referred to as a “back interconnection structure”) disposed below the lower surface of the substrate 101 and a second interconnection structure 290 (also referred to as a “front interconnection structure”) disposed on the interlayer insulation layer 180. The first interconnection structure 280 and the second interconnection structure 290 can be configured to electrically connect the first device 100A to the second device 100B across the first region A and the second region B.

[0070] The first interconnection structure 280 can include a first interconnection insulation layer 281 disposed below the lower surface of the substrate 101 and a first interconnection line M1a disposed in the first interconnection insulation layer 281. In the first region A, the first interconnection line M1a can be connected to the first lower contact 250A (see Figure 2A ) of the first device 100A. The first interconnection line M1a can be a power supply line. In the example embodiment, an etching stop film 285 can be disposed between the substrate 101 and the first interconnection insulation layer 281. The etching stop film 285 can be used in a process of forming the first interconnection line M1a.

[0071] Similarly, the second interconnection structure 290 can include second interconnection insulation layers 291 and 292 disposed on the interlayer insulation layer 180 and second interconnection lines M2a and M2b disposed in the second interconnection insulation layer 292. In the first region A, the second interconnection line M2a can be connected to the first upper contact 260A (see Figure 2A ) of the first device 100A through a metal via V2a, and in the second region B, the second interconnection line M2b can be connected to the second upper contacts 260B1, 260B2, and 260B3 (see Figure 3A ) of the second device 100B through metal vias V2b, respectively.

[0072] For example, the first interconnect insulating layer 281, and the second interconnect insulating layers 291 and 292 can include silicon oxide, silicon oxynitride, SiOC, SiCOH, or a combination thereof. For example, the interconnect lines M1a, M2a, M2b, and the metal vias V2a, V2b can include copper or a copper-containing alloy. In some example embodiments, the interconnect lines M2a and M2b can be formed using a dual damascene process together with the respective metal vias V2a and V2b.

[0073] In example embodiments, the first transistor TR1 can be implemented as a P-type MOSFET and the second transistor TR2 can be implemented as an N-type MOSFET, but conversely, in some example embodiments, the first transistor TR1 can be implemented as an N-type MOSFET and the second transistor TR2 can be implemented as a P-type MOSFET. For example, the second lower semiconductor layer 131L can include substantially the same silicon as the silicon of the first semiconductor pattern 131, and the second upper semiconductor layer 132L can include substantially the same silicon germanium as the silicon germanium of the second semiconductor pattern 132. Here, the second upper semiconductor layer 132L can include a first concentration of germanium that is substantially similar to a germanium concentration of the second semiconductor pattern 132. For example, the first concentration can include a germanium concentration in a range from 4 atomic % to 7 atomic %. Further, the first source / drain pattern 150A can include silicon and the second source / drain pattern 150B can include silicon germanium.

[0074] Figure 4 is a cross-sectional view taken from a side showing a circuit device employable in a semiconductor device according to an example embodiment.

[0075] Referring to Figure 4 , the second device 100B1 according to an example embodiment can be employed instead of the second device 100B in the semiconductor device 200 in Figure 1 , or can be employed together with the second device 100B, and unless otherwise indicated, detailed descriptions of the second device 100B1 according to an example embodiment can be combined with the descriptions of the second device 100B shown in Figure 3A and Figure 3B .

[0076] Similar to the semiconductor stack SL of the second device 100B in the foregoing example embodiments, the second device 100B1 according to an example embodiment can include a semiconductor stack SL in which semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions are disposed, and a plurality of gate structures GS2' extending to the semiconductor stack SL. However, unlike the second device 100B in the foregoing example embodiments, the second device 100B1 according to an example embodiment can be implemented as a PN diode or a P-i-N diode.

[0077] The semiconductor stack SL can include, for example, a region doped with a low concentration of N-type impurities, or can include a region that is unintentionally doped.

[0078] In the example embodiment, the recess for the first-conductivity-type epitaxial pattern 150E1 can be formed to have a depth greater than a depth of the recess for the second-conductivity-type epitaxial pattern 150E2. The recess for the first-conductivity-type epitaxial pattern 150E1 can be formed to have the same depth as a depth of the recess for the first source / drain pattern 150A and the second source / drain pattern 150B of the first device 100A (RS1) in Figure 10D The first-conductivity-type epitaxial pattern 150E1, like the first source / drain pattern 150A, can be a P-type epitaxial layer, and the second-conductivity-type epitaxial pattern 150E2, like the second source / drain pattern 150B, can be an N-type epitaxial layer.

[0079] Like the first lower contact 250A of the first device 100A according to the aforementioned example embodiment, the second lower contact 250B can penetrate the substrate 101 and can be connected to the first-conductivity-type epitaxial pattern 150E1. The second lower contact 250B employed in the example embodiment can include a conductive via 230 that penetrates the substrate 101 and a conductive connection portion 220 formed by selectively removing a buried sacrificial pattern. The second lower contact 250B can be formed together in the process of forming the first lower contact 250A.

[0080] The second lower contact 250B and the second upper contact 260B can be connected to the first-conductivity-type epitaxial pattern 150E1 and the second-conductivity-type epitaxial pattern 150E2, respectively, and can be electrically connected to the first interconnection structure 280 and the second interconnection structure 290. Accordingly, the second device 100B1 implemented with a PN diode according to the example embodiment can form an electrical circuit of the semiconductor device 200 together with the first device 100A.

[0081] Figure 5 is a plan view illustrating a semiconductor device according to an example embodiment. Figure 6 is a plan view illustrating Figure 5 is a cross-sectional view taken along line III2-III2' of the second region of the semiconductor device in

[0082] Referring to Figure 5 and Figure 6 , the semiconductor device 200A according to the example embodiment can be similar to Figures 1 to 3BThe illustrated semiconductor device 200 differs from the configuration in which the second device 100B2 has the gate structure GS2" having a pitch P2 and a width d2 that are larger than the pitch P1 and the width d1 of the gate structure GS of the first device 100A, and in which the epitaxial patterns 150E1' and 150E2' and the contact structure of the second device 100B2 are changed. Further, the components in the example embodiment can be understood by referring to the description of the same or similar components of the second device 100B illustrated in Figure 3A and Figure 3B the same or similar components of the second device 100B illustrated in

[0083] Similar to the semiconductor stack SL of the second device 100B in the foregoing example embodiment, the second device 100B2 according to the example embodiment can include a semiconductor stack SL in which semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions are provided. In the example embodiment, the semiconductor stack SL can include, for example, a region doped with a low concentration of N-type impurities, or can include a region that is not intentionally doped.

[0084] Further, the gate structure GS2" of the second device 100B2 can be arranged to have a pitch P2 and a width d2 that are larger than the pitch P1 and the width d1 of the gate structure GS of the first device 100A. The recesses of the second device 100B2 can also have a relatively large width compared to the width of the recesses of the first device 100A. The first-conductivity-type epitaxial pattern 150E1' can be provided in the left recess, and the second-conductivity-type epitaxial pattern 150E2' can be provided in the right recess. The first-conductivity-type epitaxial pattern 150E1' can be formed together in the process of forming the first source / drain pattern 150A of the first device 100A, and the second-conductivity-type epitaxial pattern 150E2' can be formed together in the process of forming the second source / drain pattern 150B of the first device 100A. As described above, the width of the recesses of the second device 100B2 can be larger than the width of the recesses of the first device 100A, so that the first-conductivity-type epitaxial pattern 150E1' and the second-conductivity-type epitaxial pattern 150E2' can have a height that is lower than the height of the first source / drain pattern 150A and the second source / drain pattern 150B of the first device 100A, respectively.

[0085] In the example embodiment, the first-conductivity-type epitaxial pattern 150E1' can include a first epitaxial layer 150A1 and a second epitaxial layer 150A2 having different compositions, and the second-conductivity-type epitaxial pattern 150E2' can include a first epitaxial layer 150B1 and a second epitaxial layer 150B2 having different compositions. For example, in the first-conductivity-type epitaxial pattern 150E1', the first epitaxial layer 150A1 and the second epitaxial layer 150A2 can be SiGe, and the second epitaxial layer 150A2 can have a higher germanium concentration than the germanium concentration of the first epitaxial layer 150A1.

[0086] Figure 7 is a cross-sectional view taken from the side showing a circuit device employable in a semiconductor device according to an example embodiment.

[0087] Referring to Figure 7 , the second device 100B3 according to an example embodiment can be employed instead of the second device 100B2 in the semiconductor device 200A in Figure 5 and Figure 6 , or can be employed together with the second device 100B2, and unless otherwise indicated, the detailed description of the second device 100B3 according to an example embodiment can be combined with the description of the second device 100B2 shown in Figure 5 and Figure 6 .

[0088] The gate structure of the second device 100B3 according to an example embodiment can be a dummy gate structure DG including polysilicon. The dummy gate structure DG can be obtained by not applying a process of forming a gate structure (see Figure 11E and Figure 11F ) in the second region B.

[0089] Similar to the semiconductor stack SL of the second device 100B2 in the foregoing example embodiments, the second device 100B3 according to an example embodiment can include a semiconductor stack SL in which semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions are stacked, and a plurality of dummy gate structures DG extending to the semiconductor stack SL and having a width and a pitch different from those of the gate structure GS of the first device 100A.

[0090] In the example embodiment, the first-conductivity-type epitaxial pattern 150E1' and the second-conductivity-type epitaxial pattern 150E2' can be sequentially formed in each of the recesses on both sides. As described above, the width of the recesses of the second device 100B3 can be greater than the width of the recesses of the first device 100A, so that the stack height of the first-conductivity-type epitaxial pattern 150E1' and the second-conductivity-type epitaxial pattern 150E2' can be lower than the stack height of the first source / drain pattern 150A and the second source / drain pattern 150B of the first device 100A, respectively. Also, as in the example embodiment, the second device 100B3 can not include the isolation insulating layer 170, so that the first-conductivity-type epitaxial pattern 150E1' and the second-conductivity-type epitaxial pattern 150E2' can be in contact with each other.

[0091] Similar to the second lower contact 250B of the second device 100B1 according to the aforementioned example embodiment, the second lower contact 250B of the second device 100B3 can penetrate the substrate 101 and can be connected to the first-conductivity-type epitaxial pattern 150E1'. The second lower contact 250B employed in the example embodiment can include the conductive via 230 penetrating the substrate 101 and the conductive connection portion 220 formed by selectively removing the buried sacrificial pattern. The second lower contact 250B can be formed together in the process of forming the first lower contact 250A. The second lower contact 250B and the second upper contact 260B can be connected to the first-conductivity-type epitaxial pattern 150E1' of the left recess and the second-conductivity-type epitaxial pattern 150E2' of the right recess, respectively, and can be electrically connected to other devices through the first interconnection structure 280 and the second interconnection structure 290.

[0092] Figure 8 is a plan view illustrating a semiconductor device according to an example embodiment. Figure 9 is a cross-sectional view taken along line V-V' of Figure 8 the semiconductor device.

[0093] Referring to Figure 8 , the semiconductor device 200B according to the example embodiment can include a main region DA in which the first device 100A is formed and a scribe lane region SLR disposed around the main region DA. Also, the semiconductor device 200B can include an alignment key AK disposed in a peripheral region thereof. In the semiconductor device 200B according to the example embodiment, the semiconductor stack SL for forming a channel structure (CS) in Figure 2A may also be disposed on the scribe lane region SLR and / or the alignment key AK.

[0094] Figure 9A cross-sectional structure of the alignment key and the remaining scribe lane region is shown from the edge of the main region. Since the semiconductor stack is formed on the entire substrate, the semiconductor stack can also be disposed on the alignment key and the remaining scribe lane region. The alignment key employed in the example embodiment can include a trench structure, and the semiconductor stack can be formed along the inner surface of the trench.

[0095] The semiconductor stack SL can include semiconductor layers 121L, 122L, 125L, 131L, and 132L including germanium of different concentrations. In the example embodiment, the second lower semiconductor layer 131L can include substantially the same silicon germanium as the silicon germanium of the first semiconductor pattern 131 included in the lower channel structure. Accordingly, the hole mobility can be improved in the lower channel structure. Similar to the first semiconductor pattern 131, the second lower semiconductor layer 131L employed in the example embodiment can have an upper surface that can be a (110) crystal plane. Further, the second upper semiconductor layer 132L can include substantially the same silicon as the silicon of the second semiconductor pattern 132 included in the upper channel structure. As described above, the second lower semiconductor layer 131L can include germanium of a first concentration substantially similar to the germanium concentration of the first semiconductor pattern 131. For example, the second lower semiconductor layer 131L can include a germanium concentration in a range from 4 atomic % to 7 atomic %. Each of the first lower semiconductor layer 121L and the first upper semiconductor layer 122L can include silicon germanium including germanium of a second concentration other than the first concentration. For example, the second concentration can be in a range from 10 atomic % to 20 atomic %. In the example embodiment, the first lower semiconductor layer 121L can have a germanium concentration greater than the germanium concentration of each of the first upper semiconductor layers 122L. Further, the intermediate semiconductor layer 125L can include silicon germanium having germanium of a third concentration other than the second concentration of each of the first lower semiconductor layer 121L and the first upper semiconductor layer 122L. For example, the third concentration can be in a range from 30 atomic % to 45 atomic %.

[0096] Hereinafter, a method of manufacturing a semiconductor device according to an example embodiment can be described.

[0097] Figures 10A to 10H is a cross-sectional view illustrating a part of a process of a method of manufacturing a semiconductor device according to an example embodiment. The manufacturing method according to the example embodiment can be a method of manufacturing a semiconductor device 200 shown in Figures 1 to 3B . Each cross-section can correspond to a figure in Figure 2A and Figure 3A .

[0098] Figures 10A to 10H is a cross-sectional view illustrating a part of a process of a method of manufacturing a semiconductor device according to an example embodiment, illustrating a main process of forming a first source / drain pattern and a second source / drain pattern. Figures 11A to 11Gis a cross-sectional view illustrating another part of a process of a method of manufacturing a semiconductor device according to an example embodiment, illustrating main processes of forming a gate structure and a contact structure.

[0099] Referring to Figure 10A A semiconductor stack SL can be formed on the upper surface of the substrate 101, i.e., on the first region A and the second region B.

[0100] The substrate 101 can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 101 can include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer. The upper surface of the substrate 101 employed in the example embodiments can be a (110) crystal plane.

[0101] The semiconductor stack SL can be formed by alternately stacking semiconductor layers 121L, 122L, 125L, 131L, and 132L having different compositions on the substrate 101. The semiconductor layers can include: an intermediate semiconductor layer 125L; a lower stack SL1 including first sacrificial layers 121L (also referred to as "first lower semiconductor layers") and first semiconductor layers 131L (also referred to as "second lower semiconductor layers") alternately stacked below a lower surface of the intermediate semiconductor layer 125L; and an upper stack SL2 including second sacrificial layers 122L (also referred to as "first upper semiconductor layers") and second semiconductor layers 132L (also referred to as "second upper semiconductor layers") alternately stacked on an upper surface of the intermediate semiconductor layer 125L.

[0102] In the example embodiments, the second lower semiconductor layers 131L can include silicon-germanium having germanium at a first concentration, and the second upper semiconductor layers 132L can include silicon. For example, the first concentration can be in a range from 4 atomic % to 7 atomic %. Each of the first lower semiconductor layers 121L and the first upper semiconductor layers 122L can include silicon-germanium containing germanium at a second concentration other than the first concentration. For example, the second concentration can be in a range from 10 atomic % to 20 atomic %. In the example embodiments, the first lower semiconductor layers 121L can have a germanium concentration greater than that of each of the first upper semiconductor layers 122L. Further, the intermediate semiconductor layer 125L can include silicon-germanium having germanium at a third concentration other than the second concentration of each of the first lower semiconductor layers 121L and the first upper semiconductor layers 122L. For example, the third concentration can be in a range from 30 atomic % to 45 atomic %. In some example embodiments, a thickness t1 of the intermediate semiconductor layer 125L can be greater than a thickness of each of the first lower semiconductor layers 121L and the second lower semiconductor layers 131L and the first upper semiconductor layers 122L and the second upper semiconductor layers 132L.

[0103] Thereafter, referring to Figure 10BThe fin-type structures FS extending in the first direction can be formed by etching the semiconductor stack SL on the first region A, and the desired impurity regions W1 and W2 can be formed in the semiconductor stack SL on the second region B.

[0104] The process of forming the fin-type structures FS can be selectively performed only in the first region A. To this end, during the process of forming the fin-type structures, the second region B can be covered with a mask (not shown). In the first region A, the fin-type structures FS can extend on the substrate 101 in the first direction (e.g., the X direction), and a plurality of the fin-type structures FS can be formed and arranged in the second direction (e.g., the Y direction).

[0105] Thereafter, in the second region B, the first-conductivity-type impurity region W1 and the second-conductivity-type impurity region W2 can be formed in the semiconductor stack SL using an ion implantation process to form a circuit device. The ion implantation process can be selectively performed only in the second region B. During the ion implantation process, the first region A can be covered with a mask (not shown). Similarly to Figure 1 As shown in the second device 100B, in a plan view, the first-conductivity-type impurity region W1 can be formed in a partial region of the semiconductor stack SL of the second region B, and the second-conductivity-type impurity region W2 can be formed by counter-doping in the first-conductivity-type impurity region W1.

[0106] Thereafter, referring to Figure 10C A plurality of dummy gate structures DG can be formed in the first region A and the second region B.

[0107] The plurality of dummy gate structures DG can extend in the second direction (e.g., the Y direction) and can be arranged in the first direction (e.g., the X direction). In an example embodiment, the plurality of dummy gate structures DG can be differently arranged in the first region A with a first pitch and a first width and in the second region B with a second pitch and a second width. In some example embodiments, the first pitch and the second pitch can be the same, but example embodiments thereof are not limited thereto.

[0108] The plurality of dummy gate structures DG in the first region A can be formed to cross the fin-type structures FS (see Figure 1 ), and the plurality of dummy gate structures DG in the second region B can be formed on a planar surface of the semiconductor stack SL.

[0109] In this process, gate spacers 141 can be formed on both sides of dummy gate structures DG together with dummy gate structures DG. Dummy gate structures DG can be provided as sacrificial structures that provide space for forming gate structures GS that will be formed in a respective subsequent process. Dummy gate structures DG can include a dummy material layer 245 and a mask pattern layer 247. Mask pattern layer 247 can be used to pattern dummy material layer 245. Dummy material layer 245 can be an insulating layer and a conductive layer, respectively, and in some example embodiments, dummy material layer 245 can include polysilicon. Mask pattern layer 247 can include silicon oxide and / or silicon nitride. However, example embodiments are not limited thereto, dummy material layer 245 can include a plurality of different material layers. For example, dummy material layer 245 can include an additional insulating film, such as silicon oxide, under the polysilicon.

[0110] Gate spacers 141 can be formed on both sidewalls of dummy gate structures DG. Gate spacers 141 can be formed by forming a film with a uniform thickness along the upper surface and side surfaces of substrate 101 on which dummy gate structures DG are formed and performing anisotropic etching. Gate spacers 141 can be formed of a low dielectric constant material and can include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0111] Thereafter, with reference to Figure 10D A first recess RS1 can be formed in first region A by removing portions of fin-type structures FS between dummy gate structures DG, and a second recess RS2 can be formed in second region B by removing some of portions of semiconductor stacks SL between dummy gate structures DG.

[0112] The processes of forming first recess RS1 and second recess RS2 can be performed sequentially. The process of forming first recess RS1 can be selectively performed only on first region A, and during this process, second region B can be covered with a mask (not shown).

[0113] This process can include removing exposed regions of the fin-type structure FS using dummy gate structures DG and gate spacers 141 as masks. Through this process, the first semiconductor pattern 131 and the second semiconductor pattern 132 can have a desired channel length in the first direction (e.g., the X direction). The side of the first semiconductor pattern 131 exposed by the first recess RS1 can be provided as a region for forming a first source / drain pattern, and the side of the second semiconductor pattern 132 exposed by the first recess RS1 can be provided as a region for forming a second source / drain pattern. Further, in an example embodiment, the first recess RS1 can be formed to a sufficient depth in the substrate 101. The first recess RS1 can provide a region in which a buried sacrificial pattern (220P in Figure 10F

[0114] Thereafter, in the second region B, a second recess RS2 can be formed in the semiconductor stack SL. The process of forming the second recess RS2 can be selectively performed only on the second region B, and during this process, the first region A can be covered with a mask (not shown).

[0115] In an example embodiment, the second recess RS2 can be formed to have a lower depth than the depth of the first recess RS1. For example, the second recess RS2 can be formed to extend from the upper stack SL2 to a partial region of the intermediate sacrificial layer 125L. This process can include removing exposed regions of the semiconductor stack SL using dummy gate structures DG and gate spacers 141 as masks. The second recess RS2 can provide space for the first conductive type epitaxial pattern and the second conductive type epitaxial pattern.

[0116] Thereafter, with reference to Figure 10E a dielectric pattern 191P can be formed in the first recess RS1, and a first barrier insulating layer 310 can be formed across the first region A and the second region B.

[0117] First, a first gap fill insulating layer 191 can be formed between the dummy gate structures DG, such that the first recess RS1 and the second recess RS2 can be filled. The process of forming the first gap fill insulating layer 191 can include depositing an insulating material to fill the space between the dummy gate structures DG and performing a planarization process such as chemical mechanical polishing (CMP). Thereafter, a dielectric pattern 191P having a desired height can be formed by selectively applying a back-etching process to the first gap fill insulating layer 191 only in the first region A. The dielectric pattern 191P can define a region in which a buried sacrificial pattern (220P in Figure 10F

[0118] ​​Thereafter, the first barrier insulating layer 310 can be conformally formed across the first region A and the second region B. The first barrier insulating layer 310 can be formed along the upper surface and the side surface of the dummy gate structure DG and the region between the dummy gate structures DG. Also, the first barrier insulating layer 310 can be formed on the dielectric pattern 191P as well. For example, the first barrier insulating layer 310 can include silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

[0119] Thereafter, referring to Figure 10F The first barrier insulating layer 310 can be selectively removed to expose the upper surface of the dielectric pattern 191P, the dielectric pattern 191P can be removed, and a buried sacrificial pattern 220P can be formed in the region in which the dielectric pattern 191P is removed.

[0120] The process of selectively removing the first barrier insulating layer 310 can include anisotropic etching such as dry etching. The portion of the first barrier insulating layer 310 disposed on the first region A on the upper surface of the dielectric pattern 191P and the upper surface of the dummy gate structure DG can be selectively removed, and the first barrier insulating layer 310 disposed on the second region B can be completely removed.

[0121] Thereafter, the dielectric pattern 191P can be removed from the first recess RS1', and a buried sacrificial pattern 220P can be formed in the region in which the dielectric pattern 191P is removed. The buried sacrificial pattern 220P can include silicon germanium. The germanium concentration in the buried sacrificial pattern 220P can be at least higher than the germanium concentration in the first sacrificial layer 121L. During an epitaxial growth process for the buried sacrificial pattern 220P, epitaxial layer growth in unintended regions can be prevented by the first barrier insulating layer 310P.

[0122] Thereafter, referring to Figure 10G The first barrier insulating layer 310P can be removed, a second barrier insulating layer 320P can be formed so that the first semiconductor pattern 131 can be opened, and a first source / drain pattern 150A can be formed in the first recess RS1'. In the process of forming the first source / drain pattern 150A, a first conductive type epitaxial pattern 150E1 can be formed in the opened second recess RS2' of the second region B.

[0123] After the first barrier insulating layer 310P is removed, similarly to referring to Figure 10E and Figure 10FThe process described can form the second barrier insulating layer 320P. First, a second gap fill insulating layer (not shown) can be formed in the first region A between the dummy gate structures DG, after which a dielectric pattern (not shown) defining an area in which the first source / drain pattern 150A is formed can be formed by applying a back-etching process to the second gap fill insulating layer (not shown) in the first recess RS1'. After this, the second barrier insulating layer 320P can be formed conformally across the first region A and the second region B, the dielectric pattern (not shown) can be opened by applying an anisotropic etch, the dielectric pattern (not shown) can be removed, and the side surfaces of the first semiconductor pattern 131 and the side surfaces of the first sacrificial pattern 121 can be opened. After this, the desired first source / drain pattern 150A can be formed by growing an epitaxial layer from the side surfaces of the first semiconductor pattern 131 and the side surfaces of the first sacrificial pattern 121. During the epitaxial growth process, epitaxial layer growth can be prevented in the portions in which the second barrier insulating layer 320P is formed.

[0124] In this process, the first conductive type epitaxial pattern 150E1 can be formed simultaneously with the process of forming the first source / drain pattern 150A by selectively opening a portion of the second recess RS2' in the second region. Even when the first source / drain pattern 150A and the first conductive type epitaxial pattern 150E1 are disposed at different levels, these patterns can be formed by the same epitaxial growth process. The first conductive type epitaxial pattern 150E1 can grow from the side surfaces of the first upper semiconductor layer 122L and the side surfaces of the second upper semiconductor layer 132L that are opened by the second recess RS2'. The first source / drain pattern 150A and the first conductive type epitaxial pattern 150E1 can include the same conductive type semiconductor material.

[0125] After this, with reference to Figure 10H The second barrier insulating layer 320P can be removed, the isolation insulating layer 170 can be formed, and a second gap fill insulating layer 192 can be formed in the second region B such that the other second recesses RS2" are opened. After this, a second source / drain pattern 150B can be formed in the first recess RS1", and a second conductive type epitaxial pattern 150E2 can be formed in the opened second recess RS2".

[0126] After the second blocking insulating layer 320P and the first gap filling insulating layer 191 are removed, a second gap filling insulating layer 192 can be formed between dummy gate structures DG by depositing an insulating material in the first region A and the second region B, and the second gap filling insulating layer 192 can be selectively removed so that the first recess RS1” and the second recess RS2” are re-opened. Thereafter, an isolation insulating layer 170 covering the first source / drain pattern 150A can be formed in the first region A, a second source / drain pattern 150B can be formed in the first recess RS1”, and a second conductive type epitaxial pattern 150E2 can be formed in the second recess RS2”. The second conductive type epitaxial pattern 150E2 can be formed simultaneously with the process of forming the second source / drain pattern 150B in the first recess RS1”. The second source / drain pattern 150B can grow from the side surface of the second semiconductor pattern 132 and the side surface of the second sacrificial pattern 122 that are opened by the first recess RS1”, and the second conductive type epitaxial pattern 150E2 can grow from the side surface of the first upper semiconductor layer 122L and the side surface of the second upper semiconductor layer 132L that are opened by the second recess RS2”. As such, the second source / drain pattern 150B and the second conductive type epitaxial pattern 150E2 can be formed by the same epitaxial growth process and can include the same conductive type semiconductor material.

[0127] Figures 11A to 11G FIG. 7 is a cross-sectional view illustrating another part of a process of a method of manufacturing a semiconductor device according to an example embodiment.

[0128] Referring to Figure 11A A process of partially removing the dummy gate structures DG can be performed. In Figure 10H In the example shown, an interlayer insulating layer 180 can be formed to fill the space between the dummy gate structures DG, and a CMP process can be performed to remove the mask pattern layer 247 (e.g., until the PL line). After this process, the dummy material layer 245 can be exposed in the dummy gate structures DG.

[0129] Thereafter, referring to Figure 11B The dummy material layer 245 can be removed from the first region A, and the intermediate sacrificial layer 125L can be removed in the first region A by applying a selective etching process through the first space DH1. Accordingly, a first gap O1 from which the intermediate sacrificial layer 125L is removed can be formed.

[0130] Thereafter, referring to Figure 11C In the first region A, an insulating isolation pattern 160 can be formed by filling the first gap O1 with an insulating material. The insulating isolation pattern 160 can include silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

[0131] Thereafter, referring to Figure 11D A gap (not shown) can be formed between the first semiconductor patterns 131 by selectively removing the first sacrificial patterns 121 from the first region A, and a first gate structure GS1 can be formed by depositing a first gate insulating film 142A and a first gate electrode 145A to surround the first semiconductor patterns 131 exposed by the gap (not shown).

[0132] Thereafter, referring to Figure 11E A second gap 02 between the second semiconductor patterns 132 can be formed by selectively removing the second sacrificial patterns 122 from the first region A.

[0133] Prior to this process, a second space DH2 can be formed by removing the dummy material layer 245 from the second region B. The sacrificial layers of the semiconductor stacks SL can not be removed from the second region B at the same time as the second sacrificial patterns 122 in the first region A are removed. Unlike the first region A, the semiconductor stacks SL of the second region B can not be of a fin-type structure, such that only the upper surfaces of the semiconductor stacks SL (i.e., the second upper semiconductor layers 132L) can be exposed by the second space DH2. Therefore, during the process of selectively removing the sacrificial patterns from the first region A, the sacrificial layers of the semiconductor stacks SL in the second region B can not be etched.

[0134] Thereafter, referring to Figure 11F A second gate insulating film 142B can be formed in the first region A to surround the second semiconductor patterns 132 exposed by the second gap 02. In addition, the second gate insulating film 142B can also be formed on the inner surfaces of the first space DH1 and the second space DH2. Thereafter, a second gate electrode 145B can be formed to fill the second gap 02 as well as the first space DH1 and the second space DH2. After a gate cap layer 147 is formed on the second gate electrode 145B, by performing a CMP process, a second gate structure GS2 and GS2' can be formed in the first region A and the second region B.

[0135] Thereafter, referring to Figure 11G A first upper contact 260A as well as second upper contacts 260B1, 260B2, and 260B3 can be formed in the first region A and the second region B, and a front interconnect structure 290 can be formed. Thereafter, in the first region A, a via can be formed to connect to the buried sacrificial pattern 220P on one side, the connected buried sacrificial pattern 220P can be removed, and the via can be filled with a conductive material, thereby forming a first lower contact 250A. Thereafter, by forming a back interconnect structure 280 electrically connected to the first lower contact 250A under the lower surface of the substrate 101, the semiconductor device 200 shown in FIGS. 1A and 1B can be manufactured. Figure 2A and Figure 3A the semiconductor device 200 shown in FIGS. 1A and 1B can be manufactured.

[0136] According to the foregoing example embodiments, in order to improve the carrier mobility, a channel layer can be formed of silicon germanium, and in order to introduce the structure, the germanium concentration in each of the sacrificial layers can be appropriately changed. Further, circuit devices such as passive devices and peripheral regions can include a semiconductor stack having a changed structure.

[0137] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure defined by the appended claims.

[0138] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0064051, filed May 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device, comprising: The substrate includes a first region and a second region; A semiconductor device on the first region of the substrate; as well as Semiconductor stacks are disposed on the second region of the substrate. The semiconductor device includes The channel structure includes an insulating isolation pattern, a first semiconductor pattern stacked and spaced apart from each other in a vertical direction below the lower surface of the insulating isolation pattern, and a second semiconductor pattern stacked and spaced apart from each other in a vertical direction on the upper surface of the insulating isolation pattern. The first source / drain pattern is located on both sides of the channel structure in the first direction and is respectively connected to both sides of the first semiconductor pattern. The second source / drain pattern is located on both sides of the channel structure and is respectively connected to both sides of the second semiconductor pattern. A first gate structure extends in a second direction intersecting the first direction and surrounds the first semiconductor pattern, and A second gate structure extends in the second direction and surrounds the second semiconductor pattern. Wherein, the semiconductor stack includes The intermediate semiconductor layer, at a level corresponding to the level of the insulating isolation pattern, A first lower semiconductor layer and a second lower semiconductor layer are alternately stacked below the lower surface of the intermediate semiconductor layer, and A first upper semiconductor layer and a second upper semiconductor layer are alternately stacked on the upper surface of the intermediate semiconductor layer. Wherein, the first semiconductor pattern and the second lower semiconductor layer comprise a first semiconductor material, and the second semiconductor pattern and the second upper semiconductor layer comprise a second semiconductor material, wherein one of the first semiconductor material and the second semiconductor material comprises silicon, and the other of the first semiconductor material and the second semiconductor material comprises silicon-germanium containing a first concentration of germanium, and Wherein, the first lower semiconductor layer and the first upper semiconductor layer comprise silicon germanium containing germanium of a second concentration. The second concentration is higher than the first concentration. The intermediate semiconductor layer comprises silicon-germanium of a third concentration, and The third concentration is higher than the second concentration.

2. The semiconductor device according to claim 1, wherein The first semiconductor material includes silicon germanium containing the first concentration of germanium, and The second semiconductor material includes silicon.

3. The semiconductor device according to claim 2, wherein The first source / drain pattern includes silicon and germanium, and The second source / drain pattern comprises silicon.

4. The semiconductor device according to claim 2, wherein The upper surface of the first semiconductor pattern is a (110) crystal plane, and The upper surface of the second semiconductor pattern is the (110) crystal plane.

5. The semiconductor device according to claim 1, wherein The first concentration is in the range of 4 atomic% to 7 atomic%. The second concentration is in the range of 10 atomic% to 20 atomic% and The third concentration is in the range of 30 atomic% to 45 atomic%.

6. The semiconductor device according to claim 1, wherein The first lower semiconductor layer has a higher germanium concentration than the first upper semiconductor layer.

7. The semiconductor device according to claim 1, further comprising: A circuit device comprising the semiconductor stack as its body on the second region of the substrate.

8. The semiconductor device according to claim 7, wherein, The semiconductor stack includes at least one of a first conductivity type impurity region and a second conductivity type impurity region.

9. The semiconductor device according to claim 7, wherein, The second region further includes a plurality of gate structures extending in the second direction on the semiconductor stack.

10. The semiconductor device according to claim 9, wherein, The plurality of gate structures include passive gate structures.

11. The semiconductor device according to claim 9, wherein, The plurality of gate structures include polycrystalline silicon.

12. The semiconductor device according to claim 9, in, The semiconductor stack includes a first recess and a second recess between the plurality of gate structures, and The circuit device includes a first conductivity type epitaxial pattern and a second conductivity type epitaxial pattern respectively in the first recess and the second recess, and the first conductivity type epitaxial pattern and the second conductivity type epitaxial pattern are connected to the semiconductor stack.

13. The semiconductor device according to claim 12, in, The material in the first conductivity type epitaxial pattern is the same material as the material in the first source / drain pattern, and The material in the second conductivity type epitaxial pattern is the same as the material in the second source / drain pattern.

14. The semiconductor device according to claim 1, wherein, The second region is the peripheral region of the substrate.

15. The semiconductor device according to claim 1, wherein, The second region includes a trench structure, and the semiconductor stack is formed along the inner surface of the trench structure.

16. A semiconductor device, comprising: The substrate includes a first region and a second region; The first device is located on the first region of the substrate; as well as The second device is located on the second region of the substrate. The first device includes The channel structure includes an insulating isolation pattern, a first semiconductor pattern stacked and spaced apart from each other in a vertical direction below the lower surface of the insulating isolation pattern, and a second semiconductor pattern stacked and spaced apart from each other in a vertical direction on the upper surface of the insulating isolation pattern, wherein the first semiconductor pattern and the second semiconductor pattern respectively comprise silicon germanium and silicon. A pair of first source / drain patterns are located on both sides of the channel structure in the first direction and are respectively connected to both sides of the first semiconductor pattern. A pair of second source / drain patterns are located on both sides of the channel structure and respectively connected to both sides of the second semiconductor pattern. A gate structure extends in a second direction, which intersects the first direction, and the gate structure surrounds the first semiconductor pattern and the second semiconductor pattern. The second device includes a semiconductor stack at a level corresponding to the level of the channel structure, and The semiconductor stack includes an intermediate semiconductor layer, a first lower semiconductor layer and a second lower semiconductor layer alternately stacked below the lower surface of the intermediate semiconductor layer, and a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on the upper surface of the intermediate semiconductor layer. The intermediate semiconductor layer, the first lower semiconductor layer, the second lower semiconductor layer, and the first upper semiconductor layer comprise silicon and germanium. The second upper semiconductor layer includes silicon, and The first semiconductor pattern and the second lower semiconductor layer have the same germanium concentration.

17. The semiconductor device of claim 16, wherein Each of the first semiconductor pattern and the second lower semiconductor layer includes an upper surface having a (110) crystal plane and silicon germanium with a germanium concentration in the range of 4 atomic% to 7 atomic%.

18. The semiconductor device of claim 17, wherein Each of the first lower semiconductor layer and the first upper semiconductor layer has a germanium concentration in the range of 10 atomic% to 20 atomic% and The intermediate semiconductor layer has a germanium concentration in the range of 30 atomic% to 45 atomic%.

19. The semiconductor device of claim 16, further comprising: Multiple gate structures extend in the second region to the semiconductor stack and extend in the second direction; as well as Multiple conductive epitaxial patterns are formed in multiple recesses in the region between the multiple gate structures of the semiconductor stack, respectively. The material of each of the plurality of conductive type epitaxial patterns is the same as the material of one of the first source / drain patterns and the second source / drain patterns.

20. A semiconductor device, comprising: The substrate includes a first region and a second region, wherein the second region is located on the periphery of the first region; A semiconductor device on the first region of the substrate; as well as Semiconductor stacks are disposed on the second region of the substrate. The semiconductor device includes an insulating isolation pattern, a first semiconductor pattern stacked and spaced apart from each other in a vertical direction below the lower surface of the insulating isolation pattern, and a second semiconductor pattern stacked and spaced apart from each other in a vertical direction on the upper surface of the insulating isolation pattern. The first semiconductor pattern and the second semiconductor pattern respectively comprise silicon germanium and silicon. The semiconductor stack includes an intermediate semiconductor layer at a level corresponding to the level of the insulating isolation pattern, a first lower semiconductor layer and a second lower semiconductor layer alternately stacked below the lower surface of the intermediate semiconductor layer, and a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on the upper surface of the intermediate semiconductor layer. Wherein, the intermediate semiconductor layer, the first lower semiconductor layer, the second lower semiconductor layer, and the first upper semiconductor layer comprise silicon and germanium, the second upper semiconductor layer comprises silicon, and The first semiconductor pattern and the second lower semiconductor layer comprise germanium of a first concentration, the first lower semiconductor layer and the first upper semiconductor layer comprise germanium of a second concentration, the second concentration being higher than the first concentration, and the intermediate semiconductor layer comprises germanium of a third concentration, the third concentration being higher than the second concentration.

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