Semiconductor device, manufacturing method thereof and semiconductor equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and semiconductor equipment, relates to the technical field of semiconductors, and aims to reduce the distance between a first transistor and a second transistor along the thickness of a substrate, reduce the parasitic resistance and parasitic capacitance of the semiconductor device and improve the working performance of the semiconductor device. The semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor and the second transistor are arranged on the substrate at intervals in the thickness direction of the substrate, and the second transistor is located above the first transistor. Wherein the first active structure included in the first transistor and the second active structure included in the second transistor are distributed at intervals in the direction parallel to the surface of the substrate. Each of the first active structure and the second active structure comprises a channel region and source and drain regions located on the two sides of the channel region in the length direction. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a manufacturing method thereof, and a semiconductor device. BACKGROUND

[0002] The three-dimensional stacked transistor includes two transistors vertically stacked along the thickness direction of the substrate, and the lateral spacing of the two transistors is eliminated, which allows the effective channel width to be further increased, thereby improving the working performance and integration of the semiconductor device.

[0003] However, in the existing three-dimensional stacked transistor, the spacing of the upper and lower two transistors along the thickness direction of the substrate is large, which increases the parasitic resistance and parasitic capacitance of the semiconductor device, and is not conducive to improving the working performance of the semiconductor device. SUMMARY

[0004] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a manufacturing method thereof, and a semiconductor device.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a semiconductor device, comprising: a substrate, a first transistor and a second transistor. The first transistor and the second transistor are arranged on the substrate along the thickness direction of the substrate, and the second transistor is located above the first transistor. Wherein, along the direction parallel to the surface of the substrate, the first active structure included in the first transistor and the second active structure included in the second transistor are spaced apart. The first active structure and the second active structure each include a channel region and a source-drain region located on both sides of the channel region along the length direction.

[0006] In the case of adopting the above technical solution, the semiconductor device includes a first transistor and a second transistor which are spaced apart along the thickness direction of the substrate. Obviously, the first transistor and the second transistor can constitute a three-dimensional stacked transistor (CFET device) to improve the integration of the semiconductor device.

[0007] In addition, along the direction parallel to the substrate surface, the first active structure included in the first transistor and the second active structure included in the second transistor are spaced apart, and among the first transistor and the second transistor, the two source-drain regions located on the same side along the length direction of the gate stack structure can be spaced apart along the direction parallel to the substrate surface; in other words, along the thickness direction of the substrate, the source-drain region located below can be completely exposed outside the source-drain region located above, which is beneficial to make the source-drain contact structures formed subsequently electrically connected to the corresponding source-drain regions through the spacing of the two, which not only can prevent the device from failing due to the overlap of different source-drain contact structures, but also does not need to set a conductive structure for leading out between the two, which is beneficial to reduce the thickness of the isolation material (which can be the second isolation structure below) for electrically insulating the source-drain regions included in the first transistor and the second transistor, thereby reducing the parasitic capacitance of the semiconductor device, and at the same time, due to the small thickness of the isolation material, the length of the source-drain contact structure for leading out the source-drain region below (or the length of the source-drain contact structure for leading out the source-drain region above) is also small, which reduces the parasitic resistance of the semiconductor device and is beneficial to improve the working performance of the semiconductor device. In addition, among the first transistor and the second transistor, the two source-drain regions located on the same side along the length direction of the gate stack structure can be completely spaced apart along the direction parallel to the substrate surface without overlapping, which can reduce the precision requirement of manufacturing the source-drain contact structure and improve the yield of the semiconductor device.

[0008] In an example, along the width direction of the channel region, in the first active structure, the source-drain region close to the side of the second transistor and the channel region close to the side of the second transistor both extend along the thickness direction of the substrate. And / or, along the width direction of the channel region, in the second active structure, the source-drain region close to the side of the first transistor and the channel region close to the side of the second transistor both extend along the thickness direction of the substrate.

[0009] In an example, along the width direction of the channel region, in the first active structure, the source-drain region close to the side of the second transistor is aligned with the channel region close to the side of the second transistor; the side of the source-drain region away from the second transistor is protruded outward relative to the side of the channel region close to the second transistor. And / or, along the width direction of the channel region, in the second active structure, the source-drain region close to the side of the first transistor is aligned with the channel region close to the side of the second transistor; the side of the source-drain region away from the first transistor is protruded outward relative to the side of the channel region close to the first transistor.

[0010] In an example, the semiconductor device further includes a first isolation structure disposed on the substrate. Along the width direction of the channel region, the first isolation structure is located at least on the side of the source-drain region included in the first active structure close to the second transistor and extends upward along the thickness direction of the substrate to the side of the source-drain region included in the second active structure close to the first transistor.

[0011] In an example, along a width direction of the channel region, the first isolation structure is further located at a side of the channel region included in the first active structure close to the second transistor, and extends upward along a thickness direction of the substrate to a side of the channel region included in the second active structure close to the first transistor.

[0012] In an example, the portions of the first isolation structure are integrally continuous.

[0013] In an example, along a direction parallel to a surface of the substrate, there is a first gap between the channel region included in the first active structure and the first isolation structure, and the gate stack structure included in the first transistor is further disposed in the first gap.

[0014] In an example, along a direction parallel to a surface of the substrate, there is a second gap between the channel region included in the second active structure and the first isolation structure, and the gate stack structure included in the second transistor is further disposed in the second gap.

[0015] In an example, in a case that there is a first gap between the channel region included in the first active structure and the first isolation structure, and there is a second gap between the channel region included in the second active structure and the first isolation structure, the first isolation structure includes a first isolation portion and a second isolation portion. The thickness of the second isolation portion is equal to the width of the first gap and / or the second gap. In a portion of the first isolation structure located between the source / drain region included in the first active structure and the source / drain region included in the second active structure, the second isolation portion is located below the first isolation portion and extends upward to both sides of the first isolation portion along a width direction of the channel region. In a portion of the first isolation structure located between the channel region included in the first active structure and the channel region included in the second active structure, the second isolation portion is only located below the first isolation portion.

[0016] In an example, the material of the first isolation portion and the second isolation portion are different.

[0017] In an example, along a width direction of the channel region, a side of the channel region included in the first active structure close to the second transistor is in direct contact with the first isolation structure; and / or, a side of the channel region included in the second active structure close to the first transistor is in direct contact with the first isolation structure.

[0018] In an example, the semiconductor device further includes a second isolation structure. Along a thickness direction of the substrate, the second isolation structure is disposed between the source / drain region included in the first active structure and the source / drain region included in the second active structure. The second isolation structure extends along a direction parallel to a surface of the substrate.

[0019] In an example, along a thickness direction of the substrate, the thickness of the second isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm.

[0020] In one example, the portions of the second isolation structure are integrally formed.

[0021] In one example, the semiconductor device further includes a first semiconductor portion and a second isolation structure. The first semiconductor portion and the first active structure are laterally distributed along the surface of the substrate. The second active structure is disposed above the first semiconductor portion. The second isolation structure directly covers both sides of the first semiconductor portion along the length direction and covers the source / drain regions included in the first transistor, and the second isolation structure is located below the source / drain regions included in the second transistor.

[0022] In one example, the channel region included in the first active structure is parallel to the first semiconductor portion.

[0023] In one example, the channel region included in the first active structure is the same in shape and / or material as the first semiconductor portion.

[0024] In one example, in the case where the first isolation structure is also located between the channel region included in the first active structure and the channel region included in the second active structure, the first semiconductor portion is in direct contact with the first isolation structure on the side close to the first transistor; or, in the direction parallel to the surface of the substrate, there is a third gap between the first semiconductor portion and the first isolation structure, and the gate stack structure included in the first transistor is also disposed in the third gap.

[0025] In one example, the semiconductor device further includes a second semiconductor portion. The second semiconductor portion is disposed above the first active structure, and the second semiconductor portion and the second active structure are laterally distributed along the direction parallel to the surface of the substrate.

[0026] In one example, the channel region included in the second active structure is parallel to the second semiconductor portion.

[0027] In one example, the channel region included in the second active structure is the same in shape and / or material as the second semiconductor portion.

[0028] In one example, in the case where the semiconductor device further includes a first semiconductor portion, the channel region included in the second active structure is aligned with the first semiconductor portion. And / or, the channel region included in the first active structure is aligned with the second semiconductor portion.

[0029] In one example, in the case where the first isolation structure is also located between the channel region included in the first active structure and the channel region included in the second active structure, the second semiconductor portion is in direct contact with the first isolation structure on the side close to the second transistor; or, in the direction parallel to the surface of the substrate, there is a fourth gap between the second semiconductor portion and the first isolation structure, and the gate stack structure included in the second transistor is also disposed in the fourth gap.

[0030] In an example, the first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure. The first source-drain contact structure is in electrical contact with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is in electrical contact with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side of the gate stack structure included in the first transistor and / or the second transistor along a length direction, and are spaced apart along a surface direction of the substrate. The first source-drain contact structure and the second source-drain contact structure extend along a direction perpendicular to the surface direction of the substrate.

[0031] In an example, the first source-drain contact structure and the second source-drain contact structure extend to the upper surfaces of the source-drain regions included in the first active structure and the second active structure, respectively, from the same side of the substrate along a thickness direction. Alternatively, the first source-drain contact structure and the second source-drain contact structure extend to the lower surfaces of the source-drain regions included in the first active structure and the second active structure, respectively, from the same side of the substrate along the thickness direction.

[0032] In an example, the first transistor and the second transistor further include a third source-drain contact structure. The third source-drain contact structure includes a vertical extension and a lateral extension in electrical contact with the vertical extension. The vertical extension is located above and in electrical contact with another one of the source-drain regions included in the first active structure. The lateral extension is located above or below another one of the source-drain regions included in the second active structure, and is configured to electrically connect the vertical extension with another one of the source-drain regions included in the second active structure.

[0033] In an example, the vertical extension extends along a direction perpendicular to the surface direction of the substrate.

[0034] In an example, the first transistor and the second transistor are of opposite conductivity types.

[0035] In a second aspect, the present application provides a semiconductor device. The semiconductor device includes the semiconductor device provided in the first aspect and various implementation manners thereof. The semiconductor device includes a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0036] The beneficial effects of the second aspect and various implementation manners thereof can be analyzed with reference to the beneficial effects of the first aspect and various implementation manners thereof, which will not be repeated here.

[0037] In a third aspect, the present application provides a semiconductor device manufacturing method, which comprises: first, forming a first fin structure, a second fin structure and a first isolation structure on a substrate. The first fin structure and the second fin structure are distributed in space along a direction parallel to the surface of the substrate, and the first isolation structure is filled in the space between the first fin structure and the second fin structure. Along the thickness direction of the substrate, the first fin structure and the second fin structure each comprise a lower fin portion, a semiconductor isolation portion and an upper fin portion arranged in sequence. Next, the upper fin portion included in the first fin structure and the second fin structure is protected, and a source-drain region is epitaxially formed on both sides of the lower fin portion included in the first fin structure and the second fin structure. Next, the source-drain region on both sides of the lower fin portion included in the second fin structure is etched and removed. Next, the lower fin portion included in the first fin structure and the second fin structure is protected, and a source-drain region is epitaxially formed on both sides of the upper fin portion included in the first fin structure and the second fin structure. Next, the source-drain region on both sides of the upper fin portion included in the first fin structure is etched and removed.

[0038] In an example, the protection of the upper fin portion included in the first fin structure and the second fin structure comprises: forming a first mask structure spanning over the first fin structure and the second fin structure. Next, the portions of the first fin structure and the second fin structure exposed outside the first mask structure are etched and removed. Next, a second mask structure covering the lower fin portion included in the lower fin portion and the upper fin portion along both sides in the length direction is formed on the substrate. Next, a third mask structure covering the upper fin portion included in the lower fin portion and the upper fin portion along both sides in the length direction is formed. The material of the third mask structure is different from that of the second mask structure. Next, the second mask structure is selectively removed.

[0039] In an example, the protection of the lower fin portion included in the first fin structure and the second fin structure comprises: forming a second isolation structure covering both sides in the length direction of the lower fin portion included in the second fin structure, and covering the source-drain region that has been formed.

[0040] In an example, after the source-drain region on both sides of the upper fin portion included in the first fin structure is etched and removed, the semiconductor device manufacturing method further comprises: using a semiconductor process to form a first transistor based on the remaining lower fin portion in the first fin structure and the source-drain region adjacent thereto, and to form a second transistor based on the remaining upper fin portion in the second fin structure and the source-drain region adjacent thereto.

[0041] In one example, the forming the first transistor based on the remaining lower fin portion of the first fin structure and the source / drain region adjacent to the first fin structure and the forming the second transistor based on the remaining upper fin portion of the second fin structure and the source / drain region adjacent to the second fin structure includes: removing at least part of the first mask structure. Next, the forming the channel region of the first transistor based on the remaining lower fin portion of the first fin structure and the forming the channel region of the second transistor based on the remaining upper fin portion of the second fin structure. Next, etching and removing at least part of the first isolation structure between the channel region of the first transistor and the remaining lower fin portion of the second fin structure and etching and removing at least part of the first isolation structure between the channel region of the second transistor and the remaining upper fin portion of the first fin structure. Next, forming the gate stack structure around the channel region.

[0042] In one example, after the forming the first transistor and the second transistor, the method further includes: forming a first source / drain contact structure electrically connected to one of the source / drain regions of the first transistor. Next, forming a second source / drain contact structure electrically connected to one of the source / drain regions of the second transistor. The first source / drain contact structure and the second source / drain contact structure are located on the same side of the gate stack structure of the first transistor and / or the second transistor along the length direction and are spaced apart. The first source / drain contact structure extends along the direction perpendicular to the surface of the substrate.

[0043] In one example, after the forming the first transistor and the second transistor, the method further includes: forming a third source / drain contact structure electrically connected to the other one of the source / drain regions of the first transistor and the other one of the source / drain regions of the second transistor. The third source / drain contact structure includes a vertical extension and a lateral extension electrically connected to the vertical extension. The vertical extension is located above the other one of the source / drain regions of the first transistor and is electrically connected to the other one of the source / drain regions of the first transistor. The lateral extension is located above or below the other one of the source / drain regions of the second transistor and is used to electrically connect the vertical extension to the other one of the source / drain regions of the second transistor.

[0044] The beneficial effects of the third aspect of the present application and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0046] Figure 1Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 1 ;

[0047] Figure 2 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 2 ;

[0048] Figure 3 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 3 ;

[0049] Figure 4 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 4 ;

[0050] Figure 5 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 5 ;

[0051] Figure 6 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 6 ;

[0052] Figure 7 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 7 ;

[0053] Figure 8 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application

[0054] Figure 9 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 9 ;

[0055] Figure 10 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0056] Figure 11 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0057] Figure 12 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0058] Figure 13 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0059] Figure 14 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Four;

[0060] Figure 15 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Five;

[0061] Figure 16 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Six;

[0062] Figure 17 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Seven;

[0063] Figure 18 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Eight;

[0064] Figure 19 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 10 Nine;

[0065] Figure 20 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Ten;

[0066] Figure 21 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Eleven;

[0067] Figure 22 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Twelve;

[0068] Figure 23 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Thirteen;

[0069] Figure 24 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Fourteen;

[0070] Figure 25 Structure of semiconductor device in manufacturing process for embodiment of the present application Figure 2 Fifteen;

[0071] Figure 26Structure of semiconductor device in manufacturing process according to an embodiment of the present application Figure 2 Sixteen;

[0072] Figure 27 Structure of semiconductor device in manufacturing process according to an embodiment of the present application Figure 2 Seventeen;

[0073] Figure 28 Structure of semiconductor device in manufacturing process according to an embodiment of the present application Figure 2 Eighteen.

[0074] The reference signs: 11 is a substrate, 12 is a first transistor, 13 is a second transistor, 14 is a first isolation structure, 15 is a channel region, 16 is a source / drain region, 17 is a gate stack structure, 18 is a gate side wall, 19 is a first well region, 20 is a second well region, 21 is an isolation region, 22 is a source / drain contact structure, 23 is an insulating dielectric layer, 24 is a third source / drain contact structure, 25 is a first source / drain contact structure, 26 is a second source / drain contact structure, 27 is a first fin structure, 28 is a second fin structure, 29 is a sacrificial layer, 30 is a channel layer, 31 is a lower fin portion, 32 is an upper fin portion, 33 is a semiconductor isolation portion, 34 is a first mask structure, 35 is a sacrificial gate, 36 is a second isolation structure, 37 is a shallow trench isolation structure, 38 is a third isolation structure, 39 is a first semiconductor portion, 40 is a second semiconductor portion. DETAILED DESCRIPTION

[0075] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present application, but not intended to limit the scope of the present application. Furthermore, in the following description, well-known functions or constructions are not described in detail since they would obscure the application in unnecessary detail.

[0076] In the drawings, various structural diagrams according to embodiments of the present application are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0077] In the context of the present application, when one layer / element is said to be located "on" another layer / element, the layer / element can be located directly on the other layer / element, or there can be an intervening layer / element. In addition, if one layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0078] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0079] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, it can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0080] The three-dimensional stacked transistor includes two transistors vertically stacked along the thickness direction of the substrate, eliminates the lateral spacing of the two transistors, allows the effective channel width to be further increased, and thus helps to improve the working performance and integration of the semiconductor device.

[0081] However, in the existing three-dimensional stacked transistor, the source-drain regions included in the upper and lower transistors are substantially aligned along the direction parallel to the surface of the substrate. In this case, if the upper transistor is led out upward, the source-drain region included in the lower transistor cannot be exposed outside the source-drain region included in the upper transistor. If the upper transistor is led out downward, the source-drain region included in the upper transistor cannot be exposed outside the source-drain region included in the lower transistor. In the above case, a conductive structure for leading out needs to be arranged between the source-drain regions included in the upper and lower transistors to electrically connect the source-drain regions that are blocked, so as to ensure that the source-drain contact structures electrically connected to the source-drain regions on the same side of the gate stack structure along the length direction of the gate stack structure of the upper and lower transistors are isolated, thereby preventing the device from failing. However, the arrangement of the conductive structure for leading out between the source-drain regions included in the upper and lower transistors causes the thickness of the isolation structure for isolating the source-drain regions included in the upper and lower transistors to be large, thereby increasing the parasitic capacitance of the semiconductor device. In addition, the increase in the thickness of the isolation structure also causes the leading-out length of the source-drain contact structure to increase, thereby increasing the parasitic resistance of the semiconductor device, which is not conducive to improving the working performance of the semiconductor device.

[0082] To solve the above technical problems, embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and a semiconductor device. In the semiconductor device provided by the embodiments of the present application, the first active structure included in the first transistor and the second active structure included in the second transistor are spaced apart along the direction parallel to the surface of the substrate, so as to facilitate reducing the thickness of the first isolation structure, thereby reducing the parasitic resistance and the parasitic capacitance of the semiconductor device, and facilitating improving the working performance of the semiconductor device.

[0083] In a first aspect, embodiments of the present application provide a semiconductor device. As shown in Figures 22 to 25 The semiconductor device includes a substrate 11, a first transistor 12, and a second transistor 13. The first transistor 12 and the second transistor 13 are spaced apart along the thickness direction of the substrate 11 and arranged on the substrate 11, and the second transistor 13 is located above the first transistor 12. In the direction parallel to the surface of the substrate 11, the first active structure included in the first transistor 12 and the second active structure included in the second transistor 13 are spaced apart. The first active structure and the second active structure each include a channel region 15 and source-drain regions 16 located on both sides of the channel region 15 along the length direction.

[0084] In the case of adopting the above technical solution, as shown in Figures 22 to 25 The first transistor 12 and the second transistor 13 included in the semiconductor device are spaced apart along the thickness direction of the substrate 11. Apparently, the first transistor 12 and the second transistor 13 can constitute a three-dimensional stacked transistor (CFET device) to improve the integration of the semiconductor device. In addition, as shown in Figures 22 to 28As shown, along the direction parallel to the surface of the substrate 11, the first active structure included by the first transistor 12 and the second active structure included by the second transistor 13 are spaced apart, at this time, in the first transistor 12 and the second transistor 13, two source-drain regions 16 located at the same side along the length direction of the gate stack structure 17 can be spaced apart along the direction parallel to the surface of the substrate 11; in other words, along the thickness direction of the substrate 11, the lower source-drain region 16 can be completely exposed outside the upper source-drain region 16, which is beneficial to make the source-drain contact structure 22 formed subsequently manufactured to be electrically connected with the corresponding source-drain region 16 through the spacing offset between them, not only can prevent the device from failure caused by the overlap of different source-drain contact structures 22, but also there is no need to set a conductive structure for leading out between them, which is beneficial to reduce the thickness of the isolation material (which can be the second isolation structure 36 below) for electrically insulating the source-drain regions 16 included by the first transistor 12 and the second transistor 13, thereby reducing the parasitic capacitance of the semiconductor device, and at the same time, due to the small thickness of the isolation material, the length of the source-drain contact structure 22 for leading out the lower source-drain region 16 upward (or the length of the source-drain contact structure 22 for leading out the upper source-drain region 16 downward) is also small, which reduces the parasitic resistance of the semiconductor device and is beneficial to improve the working performance of the semiconductor device. In addition, in the first transistor 12 and the second transistor 13, two source-drain regions 16 located at the same side along the length direction of the gate stack structure 17 can be completely offset along the direction parallel to the surface of the substrate 11 without overlapping, which can reduce the precision requirement of manufacturing the source-drain contact structure 22 and improve the yield of the semiconductor device.

[0085] In actual application process, the structure and material of the substrate are not specifically limited in the embodiments of the present application, as long as they can be applied to the semiconductor device provided by the embodiments of the present application.

[0086] For example, the substrate can be a substrate of any one of semiconductor materials such as silicon, silicon-germanium or germanium.

[0087] For example, the substrate can be a substrate of any one of semiconductor materials such as silicon, silicon-germanium or germanium.

[0088] The material of the substrate can be determined according to the manufacturing process of the first transistor and the second transistor, and the leading-out direction of the source-drain contact structure included by the first transistor and the second transistor. For example, when the source-drain contact structure included by the first transistor and the second transistor is led out in the upward direction (i.e. in the manner from the first transistor to the second transistor), the substrate can be a substrate of semiconductor material. When the source-drain contact structure included by the first transistor and the second transistor is led out in the downward direction (i.e. in the manner from the second transistor to the first transistor), the substrate can be a substrate of insulating material.

[0089] In some cases, such as Figure 22 , and Figures 26 to 28As shown, the semiconductor device can further include a second isolation structure 36. The second isolation structure 36 is disposed between the source / drain region 16 included in the first transistor 12 and the source / drain region 16 included in the second transistor 13 along the thickness direction of the substrate 11, so as to prevent electric leakage and device failure. The second isolation structure 36 extends along a direction parallel to the surface of the substrate 11.

[0090] Optionally, as shown in FIG. 1C, the surface of the substrate 11 can include a first well region 19 and a second well region 20 which are spaced apart, and an isolation region 21 which is located between the first well region 19 and the second well region 20. In this case, the first transistor 12 is directly disposed on the first well region 19, and the second transistor 13 is disposed above the second well region 20. In this case, the second isolation structure 36 can directly cover the second well region 20 and the source / drain region 16 included in the first transistor 12, and be located below the source / drain region 16 included in the second transistor 13. Alternatively, the semiconductor device can further include an insulating material which directly covers the second well region 20, and the second isolation structure 36 covers the insulating material and the source / drain region 16 included in the first transistor 12. Figures 22 to 28

[0091] The material of the second isolation structure can include any one of silicon oxide, silicon nitride, silicon oxynitride, etc. The second isolation structure can be a single-layer structure in which the same material is used in each part, or a stacked-layer structure including multiple materials (the distribution of different materials can be set according to actual requirements, which is not specifically limited here).

[0092] The thickness of the second isolation structure can be determined according to the requirements for the electrical insulation of the second isolation structure in the actual application scenario, and the requirements for the parasitic capacitance and parasitic resistance of the semiconductor device, which is not specifically limited here.

[0093] For example, the thickness of the second isolation structure can be greater than or equal to 5 nm and less than or equal to 30 nm along the thickness direction of the substrate. For example, the thickness of the second isolation structure can be 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, or 30 nm, etc.

[0094] Optionally, as shown in FIG. 1C, the surface of the substrate 11 can include a first well region 19 and a second well region 20 which are spaced apart, and an isolation region 21 which is located between the first well region 19 and the second well region 20. In this case, the first transistor 12 is directly disposed on the first well region 19, and the second transistor 13 is disposed above the second well region 20. In this case, the second isolation structure 36 can directly cover the second well region 20 and the source / drain region 16 included in the first transistor 12, and be located below the source / drain region 16 included in the second transistor 13. Alternatively, the semiconductor device can further include an insulating material which directly covers the second well region 20, and the second isolation structure 36 covers the insulating material and the source / drain region 16 included in the first transistor 12. Figure 22

[0095] In some cases, as shown in FIG. 1C, each part of the second isolation structure 36 can be integrally formed (i.e., formed simultaneously in the same step), so as to simplify the manufacturing process of the semiconductor device and improve the manufacturing efficiency of the semiconductor device. Figure 22 ​​As shown, the semiconductor device can further include an insulating medium layer 23 to reduce the risk of leakage of the semiconductor device and improve the yield of the source-drain region 16 included in the second transistor 13 and improve the working performance of the semiconductor device. The insulating medium layer 23 covers the second transistor 13 and the portion of the second isolation structure 36 corresponding to the first transistor 12.

[0096] Optionally, as shown, the insulating medium layer 23 can also directly contact the source-drain region 16 included in the second active structure on the side of the source-drain region 16 included in the second active structure along the width direction of the channel region 15 and close to the first transistor 12. In addition, the insulating medium layer 23 can also continue to extend downward to the side of the source-drain region 16 included in the first active structure along the width direction of the channel region 15 and close to the second transistor 13, and directly contact the side of the source-drain region 16 included in the first active structure along the width direction of the channel region 15 and close to the second transistor 13. Figure 15

[0097] The material of the insulating medium layer can include any one of silicon oxide, silicon nitride, or silicon oxynitride, etc., as long as it can be applied to the semiconductor device provided by the embodiment of the present application.

[0098] For the first transistor and the second transistor, in terms of the conduction type, the conduction type of the first transistor and the second transistor can be the same or opposite. The specific conduction type of the first transistor and the second transistor can be set according to actual needs.

[0099] In terms of the device type, the embodiment of the present application does not make specific limitation on the device type of the first transistor and the second transistor, as long as it can be applied to the semiconductor device provided by the embodiment of the present application. The device type of the first transistor and the second transistor can be the same or different.

[0100] For example, the first transistor and / or the second transistor can be a fin-like field effect transistor or a gate-all-around transistor. Specifically, the first transistor and / or the second transistor includes a source-drain region, a channel region, and a gate stack structure. The source-drain region is arranged on both sides of the channel region along the length direction, and the gate stack structure covers the outer periphery of the channel region. In the case where the first transistor and / or the second transistor is a gate-all-around transistor, the embodiment of the present application does not make specific limitation on the number of layers of the nanostructure included in the channel region.

[0101] It should be noted that the source region included in the second transistor can be located on the same side as the source region included in the first transistor along the length direction of the gate stack structure, or the drain region included in the second transistor can be located on the same side as the source region included in the first transistor along the length direction of the gate stack structure.

[0102] ​Secondly, since the first active structure of the first transistor and the second active structure of the second transistor are spaced apart along a surface direction parallel to the substrate, when the first mask structure is selectively removed, the channel regions of the first transistor and the second transistor can be released respectively, forming the gate stack structure of the first transistor and the second transistor respectively. This facilitates obtaining the first transistor and the second transistor with gate stack structures of different materials and / or thicknesses, thereby enabling the regulation of the driving voltage of the first transistor and the second transistor.

[0103] For example, such as Figures 22 to 25 As shown, along the width direction of the channel region 15, in the first active structure, both sides of the channel region 15 can extend along the thickness direction of the substrate 11; the source / drain regions 16 near the side of the second transistor 13 can also extend along the thickness direction of the substrate 11.

[0104] Optional, such as Figures 22 to 25 As shown, along the width direction of the channel region 15, in the first active structure, the source / drain region 16 is close to the side of the second transistor 13 and can be aligned with the side of the channel region 15 close to the second transistor 13; while the source / drain region 16 is away from the side of the second transistor 13 and can protrude outward relative to the side of the channel region 15 close to the second transistor 13.

[0105] Alternatively, along the width direction of the channel region, in the first active structure, the side of the source / drain region near the second transistor may protrude slightly outward relative to the side of the channel region near the second transistor. The distance of this protrusion (the magnitude of which can be determined based on a numerical range where the thickness of the portion of the first isolation structure exposed outside the first mask structure before forming the source / drain region included in the first transistor is minimally affected by operations such as etching and cleaning) is less than the distance of the outward protrusion of the side of the source / drain region away from the second transistor relative to the side of the channel region near the second transistor.

[0106] For example, such as Figures 22 to 25 As shown, in the second active structure, along the width direction of the channel region 15, both sides of the channel region 15 can extend along the thickness direction of the substrate 11; the source / drain regions 16 near the side of the second transistor 13 can also extend along the thickness direction of the substrate 11.

[0107] Optional, such as Figures 22 to 25 As shown, along the width direction of the channel region 15, in the second active structure, the source / drain region 16 is close to the side of the first transistor 12 and can be aligned with the side of the channel region 15 close to the first transistor 12; while the source / drain region 16 is away from the side of the first transistor 12 and can protrude outward relative to the side of the channel region 15 close to the first transistor 12.

[0108] Alternatively, along the width direction of the channel region, in the second active structure, the source-drain region close to the side of the first transistor can also slightly protrude outward relative to the side of the channel region close to the first transistor. The distance of the side protrusion (the size of the distance can be determined according to the thickness range of the portion of the first isolation structure exposed outside the first mask structure before the source-drain region included in the second transistor is formed, which is slightly affected by etching and cleaning operations) is smaller than the distance of the outward protrusion of the source-drain region away from the side of the first transistor relative to the side of the channel region close to the first transistor.

[0109] Notably, along the width direction of the channel region, in the first active structure, the source-drain region is aligned with the side of the channel region close to the second transistor, and both extend along the thickness direction of the substrate; in the second active structure, the source-drain region is aligned with the side of the channel region close to the first transistor, and both extend along the thickness direction of the substrate. Meanwhile, in the first active structure and the second active structure, the other side of the source-drain region protrudes outward relative to the other side of the channel region. In this case, as shown in Figures 8 to 25 , by controlling the extension range of the side of the source-drain region 16 of the first transistor 12 and the second transistor 13 close to each other along the direction parallel to the surface of the substrate 11 through the blocking effect of the isolation material (i.e., the first isolation structure 14 appearing below) between the source-drain regions 16 included in the first active structure and the second active structure when the source-drain regions 16 are manufactured, it is beneficial to make the source-drain regions 16 of the first transistor 12 and the second transistor 13 spaced apart, and at the same time, by adjusting the thickness of the first isolation structure 14, the distance of the source-drain regions 16 of the first transistor 12 and the second transistor 13 along the direction parallel to the surface of the substrate 11 can be accurately controlled, which improves the yield of the semiconductor device and also reduces the manufacturing difficulty of the semiconductor device.

[0110] For example, as shown in Figures 22 to 24 , the semiconductor device can further include a first isolation structure 14 disposed on the substrate 11. Along the width direction of the channel region 15, the first isolation structure 14 is at least located on the side of the source-drain region 16 included in the first active structure close to the second transistor 13, and extends upward along the thickness direction of the substrate 11 to the side of the source-drain region 16 included in the second active structure close to the first transistor 12.

[0111] In terms of formation range, the first isolation structure can be located only between the source-drain region included in the first active structure and the source-drain region included in the second active structure. At this time, as shown in Figure 25 , along the width direction of the channel region 15, the gate stack structure 17 included in the first transistor 12 and the second transistor 13 can be in direct contact with the sides of the two channel regions 15 adjacent to each other.

[0112] Alternatively, as shown inFigures 22 to 24 As shown, the first isolation structure 14 is not only disposed between the source / drain region 16 included in the first active structure and the source / drain region 16 included in the second active structure, but also located on the side of the channel region 15 included in the first active structure near the second transistor 13, and extends upward along the thickness direction of the substrate 11 to the side of the channel region 15 included in the second active structure near the first transistor 12.

[0113] Wherein, when the first isolation structure is located between the channel region included in the first active structure and the channel region included in the second active structure, such as Figure 23 As shown, along the width direction of the channel region 15, the side of the channel region 15 included in the first active structure that is close to the second transistor 13 can directly contact the first isolation structure 14; and / or, the side of the channel region 15 included in the second active structure that is close to the first transistor 12 can directly contact the first isolation structure 14. In this case, the gate stack structure 17 included in the first transistor 12 and / or the second transistor 13 cannot be disposed on the inner side of the channel region 15 (i.e., the side close to the first isolation structure 14). For example, when the first transistor 12 and / or the second transistor 13 are fin-type field-effect transistors, the gate stack structure 17 is only disposed on the top of the channel region 15 and on the side of the channel region 15 away from the first isolation structure 14. As another example, when the first transistor 12 and / or the second transistor 13 are ring-gate transistors, the gate stack structure 17 can only cover the top and bottom of each nanostructure layer and the side of itself away from the first isolation structure 14.

[0114] Or, such as Figure 24 As shown, along a direction parallel to the surface of the substrate 11, the channel region 15 of the first active structure and the first isolation structure 14 may also have a first gap, and the gate stack structure 17 of the first transistor 12 is also disposed within the first gap, and can directly contact the side of the channel region 15 of the first active structure near the first isolation structure 14. For example, when the channel region 15 of the first transistor 12 includes at least one layer of suspended nanostructure, the gate stack structure 17 can surround the outer periphery of each nanostructure layer. In this case, the first transistor 12 is a ring-gate transistor to improve the gate control capability of the first transistor 12.

[0115] like Figure 24 As shown, along a direction parallel to the surface of the substrate 11, the channel region 15 of the second active structure may also have a second gap with the first isolation structure 14, and the gate stack structure 17 of the second transistor 13 is also disposed in the second gap and can directly contact the side of the channel region 15 of the second active structure near the first isolation structure 14 to improve the gate control capability of the second transistor 13.

[0116] In practical applications, the various parts of the first isolation structure can be integrally continuous, meaning that the various parts of the first isolation structure can be formed simultaneously in the same operation step. Alternatively, different parts of the first isolation structure can have interfaces, for example: the portion of the first isolation structure located between the source / drain regions included in the first active structure and the second active structure has an interface with the portion of the first isolation structure located between the channel regions included in the first active structure and the second active structure.

[0117] In addition, the first isolation structure can be a single-layer structure or a stacked structure including multiple isolation parts.

[0118] For example, such as Figure 24 As shown, the first isolation structure 14 includes a first isolation section and a second isolation section. The materials of the first isolation section and the second isolation section can be the same or different. The thickness and material type of the first isolation section and the second isolation section can be set according to actual needs.

[0119] Optional, such as Figure 5 and Figure 24 As shown, when there is a first gap between the channel region 15 included in the first active structure and the first isolation structure 14, and a second gap between the channel region 15 included in the second active structure and the first isolation structure 14, the thickness of the second isolation portion can be equal to the width of the first gap and / or the second gap. Furthermore, in the portion of the first isolation structure 14 located between the source / drain region 16 included in the first active structure and the source / drain region 16 included in the second active structure, the second isolation portion is located below the first isolation portion and extends upward to both sides of the first isolation portion along the width direction of the channel region 15. In the portion of the first isolation structure 14 located between the channel region 15 included in the first active structure and the channel region 15 included in the second active structure, the second isolation portion is located only below the first isolation portion. In this case, as... Figure 20 As shown, the first and second gaps can be released by removing the exposed second isolation portion after removing the sacrificial gate. Based on this, when the materials of the first and second isolation portions are different, the exposed portion of the second isolation portion can be selectively removed while the exposed portion of the first isolation portion remains, thereby facilitating the control of the dimensions of the first and second gaps and improving the yield of semiconductor devices.

[0120] It should be noted that, as Figure 22 As shown, in the case where the semiconductor device provided in this embodiment of the invention further includes a first isolation structure 14, the side of the source / drain region 16 in the first active structure near the second transistor 13 and the side of the source / drain region 16 in the second active structure near the first transistor 12 are both in contact with the first isolation structure 14 and will not be in contact with the insulating dielectric layer 23. Figure 15As shown in FIG. 1, the semiconductor device provided by the embodiment of the present application does not include the first isolation structure 14, and the insulating medium layer 23 can be arranged between and in contact with the source-drain regions 16 of the first active structure and the source-drain regions 16 of the second active structure. In actual manufacturing process, as shown in FIG. 2, after the source-drain regions 16 of the second transistor 13 are formed, the portions of the first isolation structure 14 exposed outside the first mask structure 34 are etched and removed; as shown in FIG. 3, after at least part of the first mask structure 34 is removed, the portions of the first isolation structure 14 between the channel regions 15 are etched and removed. Figure 12 、 Figure 13 and Figure 15 As shown in FIG. 1, the semiconductor device provided by the embodiment of the present application does not include the first isolation structure 14, and the insulating medium layer 23 can be arranged between and in contact with the source-drain regions 16 of the first active structure and the source-drain regions 16 of the second active structure. In actual manufacturing process, as shown in FIG. 2, after the source-drain regions 16 of the second transistor 13 are formed, the portions of the first isolation structure 14 exposed outside the first mask structure 34 are etched and removed; as shown in FIG. 3, after at least part of the first mask structure 34 is removed, the portions of the first isolation structure 14 between the channel regions 15 are etched and removed. Figure 21

[0121] In addition, as shown in FIG. 1, the semiconductor device can further include a first semiconductor part 39 arranged on the substrate 11, and the first semiconductor part 39 and the first active structure are distributed along the surface of the substrate 11 in a transverse direction. The second active structure is arranged above the first semiconductor part 39. The second isolation structure 36 directly covers both sides of the first semiconductor part 39 in a length direction and covers the source-drain regions 16 included in the first active structure, and the first isolation structure 14 is below the source-drain regions 16 included in the second active structure. Figures 22 to 25 In actual manufacturing process, as shown in FIG. 1, the first semiconductor part 39 can be at least part of the upper fin part 32 included in the first fin structure 27 remaining after the channel regions 15 included in the first transistor 12 and the second transistor 13 are formed. The first semiconductor part 39 is arranged above the first well region 19.

[0122] Figures 1 to 25 Specifically, as shown in FIG. 1, the channel regions 15 included in the first active structure can be distributed in parallel with the first semiconductor part 39. Alternatively, the extension direction of the channel regions 15 included in the first active structure can intersect with the extension direction of the first semiconductor part 39, but the channel regions 15 included in the first active structure are distributed in a spaced-apart manner from the first semiconductor part 39.

[0123] Secondly, as shown in FIG. 1 and FIG. 2, in the case that the semiconductor device further includes the first semiconductor part 39 and the first isolation structure 14, and the first isolation structure 14 is also between the channel regions 15 included in the first active structure and the channel regions 15 included in the second active structure, the side of the first semiconductor part 39 close to the first transistor 12 can be in direct contact with the first isolation structure 14. Alternatively, as shown in FIG. 3, the side of the first semiconductor part 39 close to the first transistor 12 can be in direct contact with the first isolation structure 14. Figures 22 to 25

[0124] Figure 22 Figure 23 Figure 24 ​​​​​​As shown, along a direction parallel to the surface of the substrate 11, there is a third gap between the first semiconductor portion 39 and the first isolation structure 14, and the gate stack structure 17 included in the first transistor 12 is also disposed within the third gap.

[0125] As for the positional relationship between the side of the first semiconductor section near the first transistor and the first isolation structure, it can be set according to the positional relationship between the source and drain regions of the second active structure near the first transistor and the first isolation structure, as well as actual needs, and is not specifically limited here.

[0126] In addition, such as Figures 22 to 25 As shown, the semiconductor device may further include a second semiconductor portion 40 disposed above the first active structure, and the second semiconductor portion 40 and the second active structure are laterally distributed along a surface direction parallel to the substrate 11.

[0127] In the actual manufacturing process, such as Figures 1 to 25 As shown, the second semiconductor portion 40 may be at least a portion of the lower fin portion 31 of the remaining second fin structure 28 after the channel region 15 included in the first transistor 12 and the second transistor 13 has been formed. The second semiconductor portion 40 is disposed on the second well region 20. Furthermore, the channel region 15 included in the second active structure may be distributed parallel to the second semiconductor portion 40. Alternatively, the extending direction of the channel region 15 included in the second active structure may intersect with the extending direction of the second semiconductor portion 40, but the channel region 15 included in the second active structure and the second semiconductor portion 40 are spaced apart.

[0128] Secondly, such as Figure 22 and Figure 23 As shown, when the semiconductor device further includes a second semiconductor portion 40 and a first isolation structure 14, and the first isolation structure 14 is located between the channel region 15 included in the first active structure and the channel region 15 included in the second active structure, the side of the second semiconductor portion 40 closest to the second transistor 13 can directly contact the first isolation structure 14; or, as... Figure 24 As shown, along a direction parallel to the surface of the substrate 11, there is a fourth gap between the second semiconductor portion 40 and the first isolation structure 14, and the gate stack structure 17 included in the second transistor 13 is also disposed within the fourth gap.

[0129] As for the positional relationship between the side of the second semiconductor section near the second transistor and the first isolation structure, it can be set according to the positional relationship between the source and drain regions of the first active structure near the second transistor and the first isolation structure, as well as actual needs, and is not specifically limited here.

[0130] The structure and materials of the first and second semiconductor sections can be set according to actual needs.

[0131] As shown in FIG. 1, the first active structure includes a channel region 15 and a first semiconductor portion 39. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be formed simultaneously. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be self-aligned. Figures 22 to 25 As shown in FIG. 1, the first active structure includes a channel region 15 and a first semiconductor portion 39. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be formed simultaneously. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be self-aligned.

[0132] As shown in FIG. 1, the second active structure includes a channel region 15 and a second semiconductor portion 40. The second active structure includes the channel region 15 and the second semiconductor portion 40 can be formed simultaneously. The second active structure includes the channel region 15 and the second semiconductor portion 40 can be self-aligned. Figures 22 to 25 As shown in FIG. 1, the second active structure includes a channel region 15 and a second semiconductor portion 40. The second active structure includes the channel region 15 and the second semiconductor portion 40 can be formed simultaneously. The second active structure includes the channel region 15 and the second semiconductor portion 40 can be self-aligned.

[0133] As shown in FIG. 1, the first active structure includes a channel region 15 and a first semiconductor portion 39. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be formed simultaneously. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be self-aligned. Figures 1 to 25 As shown in FIG. 1, the first active structure includes a channel region 15 and a first semiconductor portion 39. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be formed simultaneously. The first active structure includes the channel region 15 and the first semiconductor portion 39 can be self-aligned.

[0134] The specific structure of the first semiconductor portion can be determined according to the type of the first transistor. For example, when the first transistor is a fin-like field effect transistor, the first semiconductor portion has the same structure and material as the channel region of the first transistor. When the first transistor is a gate-all-around transistor, the first semiconductor portion can have the same structure and material as the channel region of the first transistor; or the first semiconductor portion not only includes nanostructures of the same material as the channel region of the first transistor, but also includes a sacrificial layer between the nanostructures (the sacrificial layer is not removed in the process of forming the channel region of the second transistor).

[0135] As for the second semiconductor section, its specific structure can be determined based on the device type of the second transistor. For example, when the second transistor is a fin-type field-effect transistor, the structure and material of the second semiconductor section are the same as those of the channel region included in the second transistor. When the second transistor is a gate-to-ring type transistor, the structure and material of the second semiconductor section can be the same as those of the channel region included in the second transistor; or the second semiconductor section may include not only nanostructures made of the same material as those included in the channel region of the second transistor, but may also include sacrificial layers located between the nanostructures (the sacrificial layers were not removed during the formation of the channel region included in the first transistor).

[0136] In practical applications, such as Figure 26 and Figure 27 As shown, the first transistor 12 and the second transistor 13 also include a first source-drain contact structure 25 and a second source-drain contact structure 26. The first source-drain contact structure 25 is electrically contacted with one of the source-drain regions 16 included in the first active structure, and the second source-drain contact structure 26 is electrically contacted with one of the source-drain regions 16 included in the second active structure. The first source-drain contact structure 25 and the second source-drain contact structure 26 are located on the same side of the gate stack structure 17 along the length direction and are spaced apart along the surface direction of the substrate 11. The first source-drain contact structure 25 and the second source-drain contact structure 26 extend in a direction perpendicular to the surface of the substrate 11. In this case, since the first active structure and the second active structure are staggered in a direction parallel to the surface of the substrate 11, there is no need to provide a lead structure between them, which helps to reduce the thickness of the first isolation structure 14 and reduce the parasitic capacitance and parasitic resistance of the semiconductor device. At the same time, it also helps to reduce the space occupied by the first source-drain contact structure 25 and the second source-drain contact structure 26, which is beneficial for the miniaturization of the semiconductor device.

[0137] Specifically, such as Figure 26 As shown, the first source-drain contact structure 25 and the second source-drain contact structure 26 can extend from the substrate 11 along the same side of the thickness direction to the upper surface of the source-drain region 16 included in the first active structure and the second active structure, respectively. Alternatively, as... Figure 27 As shown, the first source-drain contact structure 25 and the second source-drain contact structure 26 can also extend from the same side of the substrate 11 along the thickness direction to the lower surface of the source-drain region 16 included in the first active structure and the second active structure, respectively. In this case, the wiring difficulty on the front side of the semiconductor device can be reduced, electrical interference can be avoided, and the electrical performance of the device can be improved.

[0138] For example, such as Figure 28As shown, the first transistor 12 and the second transistor 13 can further include a third source-drain contact structure 24. The third source-drain contact structure 24 includes a vertical extension and a lateral extension in electrical contact with the vertical extension. The vertical extension is located above and in electrical contact with the other one of the source-drain regions 16 included by the first active structure. The lateral extension is located above or below the other one of the source-drain regions 16 included by the second active structure, and is used to electrically connect the vertical extension with the other one of the source-drain regions 16 included by the second active structure.

[0139] The vertical extension can extend along a direction perpendicular to the surface of the substrate, so as to reduce the space occupied by the third source-drain contact structure and facilitate the miniaturization of the semiconductor device. The extending direction of the lateral extension can be parallel to the surface direction of the substrate.

[0140] In addition, if the other source-drain region included by the first transistor and the second transistor has a small spacing along the surface direction of the substrate, the electrical connection between the two can also be achieved by only one vertical extension, which can simplify the structure of the semiconductor device and reduce the manufacturing difficulty of the semiconductor device.

[0141] In an example, as shown in Figures 22 to 25 The semiconductor device can further include a third isolation structure 38. The third isolation structure 38 is arranged between the gate stack structure 17 included by the first transistor 12 and the gate stack structure 17 included by the second transistor 13, so as to reduce the electrical interference between the first transistor 12 and the second transistor 13 and improve the electrical performance of the semiconductor device. The material of the third isolation structure 38 can include any one of silicon oxide, silicon nitride, or the like.

[0142] In some cases, as shown in Figure 22 The semiconductor device provided by the embodiment of the present application can further include a gate side wall 18. The gate side wall 18 is arranged on both sides of the gate stack structure 17 included by the first transistor 12 and the second transistor 13 along the length direction, so as to separate the gate stack structure 17 from the adjacent other conductive structures and reduce the risk of leakage. The material of the gate side wall 18 can include any one of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0143] In some cases, as shown in Figure 22 The semiconductor device provided by the embodiment of the present application can further include a shallow trench isolation structure 37. The shallow trench isolation structure 37 is formed on the substrate 11, so as to define a well region of the substrate 11, reduce the risk of leakage, and further improve the yield and working performance of the semiconductor device.

[0144] As for the material of the shallow trench isolation structure, it can include any one of silicon oxide, silicon nitride, silicon oxynitride, or the like, which is not specifically limited here.

[0145] Secondly, embodiments of the present invention provide a semiconductor device. This semiconductor device includes the semiconductor devices provided in the first aspect and its various implementations described above. The semiconductor device includes smartphones, personal computers, tablet computers, artificial intelligence devices, wearable devices, or power banks.

[0146] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0147] Thirdly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as the structure of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the second aspect and its various implementations in the present invention can be analyzed with reference to the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0148] The following will be based on Figures 1 to 28 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0149] First, such as Figures 1 to 5 As shown, a first fin structure 27, a second fin structure 28, and a first isolation structure 14 are formed on a substrate 11. The first fin structure 27 and the second fin structure 28 are spaced apart along a direction parallel to the surface of the substrate 11, and the first isolation structure 14 fills the space between the first fin structure 27 and the second fin structure 28. Along the thickness direction of the substrate 11, both the first fin structure 27 and the second fin structure 28 include a lower fin portion 31, a semiconductor isolation portion 33, and an upper fin portion 32 arranged sequentially.

[0150] In the actual manufacturing process, the lower fin of the first fin structure is used to manufacture the first transistor. Therefore, the specific structure of the lower fin of the first fin structure and the second fin structure can be determined according to the device type and structure of the first transistor.

[0151] For example, when the first transistor is a fin-type field-effect transistor, the lower fin portion of the first fin structure and the second fin structure can be a single-layer elongated semiconductor structure; or, it can be an elongated semiconductor structure including multiple semiconductor layers. Furthermore, the material and width of the lower fin portion of the first fin structure and the second fin structure are the same as the material and width of the channel region included in the first transistor.

[0152] Exemplarily, in the case that the first transistor is a ring-gate transistor, the lower fin portions of the first fin structure and the second fin structure can include alternately stacked sacrificial layers and channel layers. In the alternately stacked sacrificial layers and channel layers, the bottom layer and the top layer are both sacrificial layers. The channel layers included in the lower fin portions of the first fin structure and the second fin structure are used to manufacture the nanostructure in the channel region of the first transistor, and thus the width of the lower fin portions and the material of the channel layers included in the lower fin portions can be determined according to the material and the width of the channel region of the first transistor. As for the sacrificial layers included in the lower fin portions, the channel region of the first transistor needs to be released by removing the sacrificial layers of the lower fin portions covered by the first mask structure. In addition, the upper fin portions (or the channel layers included in the upper fin portions) are retained when the sacrificial layers included in the lower fin portions are selectively removed, and thus the material of the sacrificial layers included in the lower fin portions can be any semiconductor material different from the material of the channel layers included in the lower fin portions and the upper fin portions (or the channel layers included in the upper fin portions). For example, in the case that the material of the channel layers included in the lower fin portions and the upper fin portions is silicon, the material of the sacrificial layers included in the lower fin portions can be germanium-silicon or germanium.

[0153] Similarly, the upper fin portions of the second fin structure are used to manufacture the second transistor, and thus the specific structure of the upper fin portions of the first fin structure and the second fin structure can be determined according to the device type and the structure of the second transistor.

[0154] Exemplarily, in the case that the second transistor is a fin field effect transistor, the upper fin portions of the first fin structure and the second fin structure can be single-layer long strip-shaped semiconductor structures, or can also be long strip-shaped semiconductor structures including multiple semiconductor layers. In addition, the material and the width of the upper fin portions are respectively the same as the material and the width of the channel region of the second transistor.

[0155] Exemplarily, in the case that the second transistor is a ring-gate transistor, the upper fin part in the first fin structure and the second fin structure can include at least one semiconductor layer. Each semiconductor layer includes a sacrificial layer and a channel layer on the sacrificial layer. The channel layer included in the upper fin part is used to manufacture a nanostructure in the channel region included in the second transistor, and thus the material of the channel layer included in the upper fin part of the first fin structure and the second fin structure can be determined according to the material of the channel region included in the second transistor. As for the sacrificial layer included in the upper fin part, the channel region included in the second transistor needs to be released by removing the sacrificial layer of the upper fin part covered by the first mask structure. In addition, when the sacrificial layer included in the upper fin part is selectively removed, the lower fin part (or the channel layer included in the lower fin part) remains, and thus the material of the sacrificial layer included in the upper fin part can be any semiconductor material different from the channel layer included in the upper fin part and the lower fin part (or the channel layer included in the lower fin part). In addition, in the case that the first transistor and the second transistor are both ring-gate transistors, the material of the sacrificial layer included in the lower fin part and the upper fin part can be the same, so as to reduce the limitation of the epitaxial critical thickness and improve the formation quality of the semiconductor device. Of course, the materials of the lower fin part and the upper fin part can also be different.

[0156] As for the semiconductor isolation part included in the first fin structure and the second fin structure, the semiconductor isolation part plays a pre-occupying role, and the semiconductor isolation part not covered by the first mask structure will be removed later, and after the source-drain region included in the first transistor is formed, a second isolation structure 36 is formed on the source-drain region included in the first transistor and the substrate. Thus the thickness of the semiconductor isolation part can be determined according to the thickness requirement of the second isolation structure 36. As for the material of the semiconductor isolation part, it can be any semiconductor material different from the lower fin part and the upper fin part, which is not limited here.

[0157] As for the first isolation structure, the first isolation structure is used to isolate the first fin structure and the second fin structure, and the thickness of the first isolation structure can be determined according to the distance between the first active structure and the second active structure along the direction parallel to the surface of the substrate in the actual application scenario, which is not limited here.

[0158] Exemplarily, as shown in FIG. 4, an epitaxial process or the like can be used to form the sacrificial layer 29 and the channel layer 30 used to manufacture the lower fin part 31 and the upper fin part 32 along the thickness direction of the substrate 11, and form the semiconductor isolation layer used to manufacture the semiconductor isolation part 33. Then, as shown in FIG. 5, a photolithography and etching process or the like is used to perform a patterning process on the above-mentioned sacrificial layer 29, channel layer 30, semiconductor isolation layer, and part of the substrate 11, to form at least two Fin structures distributed in a spaced manner. Next, as shown in FIG. 6, a photolithography and etching process or the like is used to perform a patterning process on the sacrificial layer 29 and the channel layer 30 included in the Fin structure, to form the lower fin part 31 and the upper fin part 32. Figure 1 Figure 2 Figure 3 ​​As shown, shallow trench isolation structures 37 for defining active regions can be formed between adjacent fin structures using processes such as deposition and etching. The top height of the shallow trench isolation structure 37 is less than or equal to the bottom height of the underlying sacrificial layer 29. The portions of at least two fin structures exposed outside the shallow trench isolation structure 37 include a first fin structure 27 and a second fin structure 28. Next, as... Figure 4 and Figure 5 As shown, a deposition process can be used to form an isolation material covering the formed structure; then the portion of the isolation material except for the portion located in the first fin structure 27 and the second fin structure 28 is etched away, and the remaining isolation material forms the first isolation structure 14.

[0159] It should be noted that when the manufactured semiconductor device does not include the shallow trench isolation structure mentioned above, only the sacrificial layer, the channel layer and the semiconductor isolation layer can be patterned; and after the patterning process, the first fin structure and the second fin structure can be directly obtained.

[0160] Next, the upper fin portion included in the first and second fin structures is protected.

[0161] For example, such as Figure 6 As shown, a first mask structure 34 can be formed across the first fin structure 27 and the second fin structure 28 using processes such as deposition and etching. The specific structure and material of the first mask structure 34 can be set according to actual needs, as long as it can provide mask protection in the future.

[0162] For example, such as Figure 6 As shown, the first mask structure 34 may include a sacrificial gate 35. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon.

[0163] For example, such as Figure 6 As shown, the first mask structure 34 may include a sacrificial gate 35 and gate sidewalls 18 located at least on both sides of the sacrificial gate 35 along its length. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon. The material of the gate sidewalls 18 can be referred to above.

[0164] For example, the first mask structure described above may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include silicon oxide or the like.

[0165] In one example, after forming the first mask structure, the semiconductor device manufacturing method further includes: removing the remaining semiconductor isolation portion using processes such as dry etching or wet etching. Next, as... Figure 6As shown, a third isolation structure 38 is formed between the remaining lower fin portions 31 and the remaining upper fin portions 32 by using deposition and etching processes.

[0166] It should be noted that the gate sidewalls on both sides of the first mask structure in the length direction can be formed at the same time when the third isolation structure is formed, so as to improve the manufacturing efficiency of the semiconductor device. Alternatively, the third isolation structure can be formed after the gate sidewalls are formed by using deposition and etching processes.

[0167] Next, as shown in Figure 7 the first fin structure 27 and the second fin structure 28 exposed outside the first mask structure 34 can be removed by using dry etching or wet etching processes (if the third isolation structure 38 is formed at this time, the third isolation structure 38 also needs to be selectively etched).

[0168] Next, a second mask structure covering both sides of the lower fin portions included in the first fin structure and the second fin structure in the length direction can be formed on the substrate by using deposition and etching processes. The material of the second mask structure is not limited in the embodiments of the present application. The top of the second mask structure needs to be greater than the top height of the lower fin portion and less than the bottom height of the upper fin portion.

[0169] Next, a third mask structure covering both sides of the upper fin portions included in the first fin structure and the second fin structure in the length direction can be formed by using deposition and etching processes; the material of the third mask structure is different from that of the second mask structure. The material of the third mask structure is not limited in the embodiments of the present application, as long as it is different from that of the second mask structure and is easy to remove.

[0170] For example, the material of the second mask structure can include silicon oxide, and the material of the third mask structure can include silicon nitride.

[0171] Next, the second mask structure can be selectively removed by using wet etching or dry etching processes, so as to expose the lower fin portions.

[0172] Next, as shown in Figure 8 the source-drain regions 16 can be formed on both sides of the lower fin portions included in the first fin structure and the second fin structure by epitaxy under the protection of the third mask structure (not shown in the figure).

[0173] Alternatively, in actual application, the source-drain regions can be directly formed on both sides of the remaining lower fin portions in the first fin structure and the second fin structure by using epitaxy processes. Then, the source-drain regions located outside the periphery of the remaining upper fin portions are removed by using etching processes (when the semiconductor isolation portions are formed, the source-drain regions on both sides of the semiconductor isolation portions also need to be removed).

[0174] It should be noted that, asFigure 8 As shown, under the blocking effect of the first isolation structure 14, the side of the epitaxially formed source-drain region 16 in contact with the first isolation structure 14 can extend along the thickness direction of the substrate 11, limiting the epitaxial range of the source-drain region 16, thereby facilitating the subsequent etching removal of the source-drain region 16 located on both sides of the lower fin portion of the second fin structure.

[0175] Next, as shown in FIG. 4B, the source-drain region 16 located on both sides of the lower fin portion of the second fin structure is etched and removed. Figure 9

[0176] In actual manufacturing process, deposition and etching processes can be used to form a mask material covering the source-drain region located on both sides of the lower fin portion of the first fin structure. The source-drain region located on both sides of the lower fin portion of the second fin structure is exposed. Then, dry etching or wet etching process is used to selectively remove the source-drain region located on both sides of the lower fin portion of the second fin structure. Next, the mask material covering the source-drain region located on both sides of the lower fin portion of the first fin structure is removed.

[0177] Next, as shown in FIG. 4C, the lower fin portion of the first fin structure and the second fin structure is protected. Figure 10

[0178] For example, as shown in FIG. 4D, deposition and etching processes can be used to form a second isolation structure 36 covering the substrate 11 and the source-drain region 16 located on both sides of the lower fin portion 31 of the first fin structure. Figure 10 Next, as shown in FIG. 4E, the source-drain region 16 is epitaxially formed on both sides of the upper fin portion of the first fin structure and the second fin structure.

[0179] Figure 11

[0180] Next, as shown in FIG. 4F, the source-drain region 16 located on both sides of the upper fin portion of the first fin structure is etched and removed. The operation process of this step can refer to the operation process of etching and removing the source-drain region 16 located on both sides of the lower fin portion 31 of the second fin structure described above, which will not be described here. Figure 12 It should be noted that if the manufactured semiconductor device does not include the first isolation structure, as shown in FIG. 4G, after the source-drain region is formed, dry etching or wet etching process can be used to etch and remove the portion of the first isolation structure exposed.

[0181] Figure 13 Next, as shown in FIG. 4H and FIG. 41, the upper fin portion of the first fin structure and the second fin structure is protected.

[0182] Figure 14 Figure 15 ​​​​​​​As shown, an insulating dielectric layer 23 covering the substrate 11 can be formed using processes such as deposition and planarization. The top of this insulating dielectric layer 23 is flush with the top of the first mask structure 34. The material of the insulating dielectric layer 23 can be referred to the previous text and will not be repeated here.

[0183] It should be noted that if the exposed portion of the first isolation structure has been etched away before the formation of the insulating dielectric layer, then as... Figure 15 As shown, the insulating dielectric layer 23 is also deposited between the source and drain regions 16 included in the first transistor and the second transistor.

[0184] Next, as Figure 16 As shown, dry etching or wet etching processes can be used to remove at least part of the first mask structure.

[0185] It should be noted that the decision to remove the entire first mask structure or only a portion thereof can be determined based on the specific structure of the first mask structure. For example, if the first mask structure includes only a sacrificial gate or only a sacrificial gate and a gate oxide layer, the entire first mask structure needs to be removed. If the first mask structure includes both a sacrificial gate and a gate sidewall, the gate sidewall needs to be retained, meaning only a portion of the first mask structure needs to be removed.

[0186] Next, as Figures 17 to 25 As shown, a first transistor 12 is formed based on the remaining lower fin portion in the first fin structure and the source / drain region 16 adjacent to itself, and a second transistor 13 is formed based on the remaining upper fin portion in the second fin structure and the source / drain region 16 adjacent to itself.

[0187] The specific execution method of this operation can be set according to the device types of the first and second transistors and actual needs. For example, when the first and second transistors are fin-type field-effect transistors, after removing the first mask structure, the remaining lower fin in the first fin structure forms the channel region included in the first transistor. The remaining upper fin in the second fin structure forms the channel region included in the second transistor.

[0188] For example, in the case where the first transistor and / or the second transistor are quasi-gate ring transistors, such as Figures 17 to 19 As shown, after removing the first mask structure, the remaining sacrificial layer also needs to be removed to release the channel region.

[0189] It should be noted that after removing at least part of the first mask structure, and before forming the gate stack structure, as... Figure 20 and Figure 21 As shown, at least a portion of the first isolation structure 14 located between the channel regions 15 can be etched away to allow the subsequently formed gate stack structure to contact the inner surface of the channel region 15 through the gap, thereby improving gate control capability.

[0190] Next, as shown in FIG. 1C, a gate stack structure 17 can be formed around the channel region 15 by atomic layer deposition or other processes. Figures 22 to 25

[0191] Next, as shown in FIG. 1D, a source / drain contact structure 22 electrically connected to the source / drain regions 16 included in the first transistor 12 and the second transistor 13 can be formed. The specific formation process of the source / drain contact structure 22 can be determined according to the specific structure thereof and the direction of the lead, which is not specifically limited here. Figures 26 to 28 Exemplarily, as shown in FIG. 1E, a first source / drain contact structure 25 can be formed by etching and deposition or other processes, which penetrates the first isolation structure 14 and covers one of the source / drain regions 16 included in the first transistor 12 in a direction perpendicular to the surface of the substrate 11, and penetrates the insulating medium layer 23 to the same height as the second transistor 13. The first source / drain contact structure 25 is electrically connected to one of the source / drain regions 16 included in the first transistor 12.

[0192] Figure 26 Next, as shown in FIG. 1F, a second source / drain contact structure 26 can be formed by etching and deposition or other processes, which covers one of the source / drain regions 16 included in the second transistor 13 in a direction perpendicular to the surface of the substrate 11. The second source / drain contact structure 26 is electrically connected to the other of the source / drain regions 16 included in the second transistor 13. The first source / drain contact structure 25 and the second source / drain contact structure 26 are arranged on the same side of the first transistor 12 and the second transistor 13 along the length direction of the gate stack structure 17, and the first source / drain contact structure 25 and the second source / drain contact structure 26 are spaced apart. Figure 26 In this case, the present embodiment does not specifically limit the formation sequence of the first source / drain contact structure and the second source / drain contact structure. The first source / drain contact structure can be formed first, and then the second source / drain contact structure can be formed. Alternatively, the second source / drain contact structure can be formed first, and then the first source / drain contact structure can be formed.

[0193] Exemplarily, in the case where the source / drain contact structure includes the first source / drain contact structure and the second source / drain contact structure, and the first source / drain contact structure and the second source / drain contact structure are led downward, as shown in FIG. 1G, a first source / drain contact structure 25 can be formed by penetrating the substrate 11 in a direction perpendicular to the surface of the substrate 11, and the first source / drain contact structure 25 is electrically connected to one of the source / drain regions 16 included in the first transistor 12. Next, as shown in FIG. 1H, a second source / drain contact structure 26 can be formed by penetrating the substrate 11 in a direction perpendicular to the surface of the substrate 11, and the second source / drain contact structure 26 is electrically connected to the other of the source / drain regions 16 included in the second transistor 13.

[0194] Figure 27 Figure 27 ​​​​As shown, the second source-drain contact structure 26 is formed to penetrate the substrate 11 along a direction perpendicular to the surface of the substrate 11, and to penetrate the first isolation structure 14 and the first transistor 12 at the same height. The second source-drain contact structure 26 is electrically connected to one of the source-drain regions 16 included in the second transistor 13.

[0195] In the actual manufacturing process, in the case where the first source-drain contact structure and the second source-drain contact structure are led downward, the substrate can be thinned by using a chemical mechanical polishing, a dry etching, a wet etching, or the like. The contact hole can be formed by using an etching, or the like, and the first source-drain contact structure and the second source-drain contact structure filled in the contact hole can be formed by using a physical vapor deposition, or the like. In other embodiments of the present application, in the actual etching of the contact hole, the top or the bottom of the source-drain region can also be etched into a plane, so that the contact surface between the first source-drain contact structure and the second source-drain contact structure and the top or the bottom of the source-drain region becomes a plane. In other embodiments, the cross section of the contact hole can also be larger than the surface of the source-drain region.

[0196] For example, as shown in FIG. 4, the third source-drain contact structure 24 is formed to be electrically connected to the other one of the source-drain regions 16 included in the first transistor 12 and the other one of the source-drain regions 16 included in the second transistor 13. Figure 28 As shown, the third source-drain contact structure 24 is formed to be electrically connected to the other one of the source-drain regions 16 included in the first transistor 12 and the other one of the source-drain regions 16 included in the second transistor 13. The third source-drain contact structure 24 includes a vertical extension and a lateral extension electrically connected to the vertical extension. The vertical extension is located above the other one of the source-drain regions 16 included in the first transistor 12 and is electrically connected to the other one of the source-drain regions 16 included in the first transistor 12. The lateral extension is located above or below the other one of the source-drain regions 16 included in the second transistor 13 and is used to electrically connect the vertical extension to the other one of the source-drain regions 16 included in the second transistor 13. In this way, in the SRAM cell and the inverter, the common-drain connection can be achieved without wasting the overall area of the transistor, and the capacitance caused by the device contact is also reduced.

[0197] Specifically, a mask material can be formed on part of the insulating medium layer by using a photolithography and an etching, or the like. Then, the contact hole is formed under the protection of the mask material. Next, the third source-drain contact structure filled in the contact hole is formed by using a physical vapor deposition, or the like.

[0198] It should be noted that the above is only a brief introduction to the manufacturing process of the source-drain contact structure, so that the person skilled in the art can easily implement the embodiments provided by the present application. The person skilled in the art can completely conceive other ways to manufacture the source-drain contact structure.

[0199] The beneficial effects of the third aspect and various implementation manners thereof in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and various implementation manners thereof, which will not be described herein again.

[0200] In the above description, the technical details of patterning, etching, etc. for each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0201] The embodiments of the present application are described above. However, these embodiments are only for a clearer illustration, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present application, and all such substitutions and modifications shall fall within the scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a first transistor, and a second transistor; the first transistor and the second transistor are disposed on the substrate at a distance along the thickness direction of the substrate, and the second transistor is located above the first transistor; Wherein, along a direction parallel to the substrate surface, the first active structure of the first transistor and the second active structure of the second transistor are distributed at intervals; both the first active structure and the second active structure include a channel region and source / drain regions located on both sides of the channel region along the length direction.

2. The semiconductor device according to claim 1, characterized in that, Along the width direction of the channel region, in the first active structure, the side of the source / drain region near the second transistor and the side of the channel region near the second transistor both extend along the thickness direction of the substrate. And / or, along the width direction of the channel region, in the second active structure, the source / drain regions near the side of the first transistor and the channel region near the side of the second transistor both extend along the thickness direction of the substrate.

3. The semiconductor device according to claim 2, characterized in that, Along the width direction of the channel region, in the first active structure, the source / drain region near the side of the second transistor is aligned with the side of the channel region near the second transistor; The source and drain regions are away from the side of the second transistor and protrude outward relative to the side of the channel region that is closer to the second transistor. And / or, along the width direction of the channel region, in the second active structure, the side of the source / drain region near the first transistor is aligned with the side of the channel region near the second transistor; The source and drain regions are away from the side of the first transistor and protrude outward relative to the side of the channel region closest to the first transistor.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first isolation structure disposed on the substrate; Along the width direction of the channel region, the first isolation structure is located at least on the side of the source / drain region of the first active structure near the second transistor, and extends upward along the thickness direction of the substrate to the side of the source / drain region of the second active structure near the first transistor.

5. The semiconductor device according to claim 4, characterized in that, Along the width direction of the channel region, the first isolation structure is also located on the side of the channel region included in the first active structure near the second transistor, and extends upward along the thickness direction of the substrate to the side of the channel region included in the second active structure near the first transistor.

6. The semiconductor device according to claim 5, characterized in that, All parts of the first isolation structure are integral and continuous.

7. The semiconductor device according to claim 5, characterized in that, Along a direction parallel to the surface of the substrate, the channel region of the first active structure and the first isolation structure have a first gap, and the gate stack structure of the first transistor is also disposed within the first gap. And / or, along a direction parallel to the surface of the substrate, the channel region of the second active structure has a second gap between it and the first isolation structure, and the gate stack structure of the second transistor is also disposed within the second gap.

8. The semiconductor device according to claim 7, characterized in that, When the first active structure includes a channel region with a first gap between it and the first isolation structure, and the second active structure includes a channel region with a second gap between it and the first isolation structure, The first isolation structure includes a first isolation portion and a second isolation portion; the thickness of the second isolation portion is equal to the width of the first gap and / or the second gap; In the portion of the first isolation structure located between the source / drain region included in the first active structure and the source / drain region included in the second active structure, the second isolation portion is located below the first isolation portion and extends upward to both sides of the first isolation portion along the width direction of the channel region. In the portion of the first isolation structure located between the channel region included in the first active structure and the channel region included in the second active structure, the second isolation portion is located only below the first isolation portion.

9. The semiconductor device according to claim 8, characterized in that, The first isolation section and the second isolation section are made of different materials.

10. The semiconductor device according to claim 5, characterized in that, Along the width direction of the channel region, the side of the channel region included in the first active structure that is close to the second transistor is in direct contact with the first isolation structure; And / or, along the width direction of the channel region, the second active structure includes a side of the channel region near the first transistor that is in direct contact with the first isolation structure.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The semiconductor device further includes a second isolation structure; along the thickness direction of the substrate, the second isolation structure is disposed between the source / drain regions included in the first active structure and the source / drain regions included in the second active structure; the second isolation structure extends along a surface direction parallel to the substrate.

12. The semiconductor device according to claim 11, characterized in that, Along the thickness direction of the substrate, the thickness of the second isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm; And / or, the various parts of the second isolation structure are integrally formed.

13. The semiconductor device according to any one of claims 1 to 10, characterized in that, The semiconductor device further includes a first semiconductor portion and a second isolation structure; the first semiconductor portion and the first active structure are laterally distributed along the surface of the substrate. The second active structure is disposed above the first semiconductor portion; the second isolation structure directly covers both sides of the first semiconductor portion along its length and covers the source and drain regions included in the first transistor, and the second isolation structure is located below the source and drain regions included in the second transistor.

14. The semiconductor device according to claim 13, characterized in that, The channel region included in the first active structure is distributed parallel to the first semiconductor portion; And / or, the channel region included in the first active structure has the same shape and / or material as the first semiconductor portion.

15. The semiconductor device according to claim 13, characterized in that, When the first isolation structure is located between the channel region included in the first active structure and the channel region included in the second active structure, The side of the first semiconductor portion closest to the first transistor is in direct contact with the first isolation structure; Alternatively, along a direction parallel to the surface of the substrate, there is a third gap between the first semiconductor portion and the first isolation structure, and the gate stack structure included in the first transistor is also disposed within the third gap.

16. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a second semiconductor portion; the second semiconductor portion is disposed above the first active structure, and the second semiconductor portion and the second active structure are laterally distributed along a surface direction parallel to the substrate.

17. The semiconductor device according to claim 16, characterized in that, The channel region included in the second active structure is distributed in parallel with the second semiconductor portion; And / or, the channel region included in the second active structure has the same shape and / or material as the second semiconductor portion.

18. The semiconductor device according to claim 16, characterized in that, When the semiconductor device further includes a first semiconductor portion, the channel region included in the second active structure is aligned with the first semiconductor portion; And / or, the channel region included in the first active structure is aligned with the second semiconductor portion.

19. The semiconductor device according to claim 16, characterized in that, When the first isolation structure is located between the channel region included in the first active structure and the channel region included in the second active structure, The side of the second semiconductor portion closest to the second transistor is in direct contact with the first isolation structure; Alternatively, along a direction parallel to the surface of the substrate, the second semiconductor portion has a fourth gap between it and the first isolation structure, and the gate stack structure included in the second transistor is also disposed within the fourth gap.

20. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure; the first source-drain contact structure is electrically contacted with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is electrically contacted with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the gate stack structure included in the first transistor and / or the second transistor, and are spaced apart along the surface direction of the substrate; the first source-drain contact structure and the second source-drain contact structure extend along the surface direction perpendicular to the substrate.

21. The semiconductor device according to claim 20, characterized in that, The first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the upper surface of the source-drain region included in the first active structure and the second active structure, respectively; Alternatively, the first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the lower surface of the source-drain region included in the first active structure and the second active structure, respectively.

22. The semiconductor device according to claim 20, characterized in that, The first transistor and the second transistor further include a third source-drain contact structure; the third source-drain contact structure includes a vertical extension and a lateral extension electrically in contact with the vertical extension; the vertical extension is located above the other of the source-drain regions included in the first active structure and is electrically in contact with the other of the source-drain regions included in the first active structure. The lateral extension is located above or below the other of the source / drain regions included in the second active structure, and is used to electrically connect the vertical extension to the other of the source / drain regions included in the second active structure.

23. The semiconductor device according to claim 22, characterized in that, The vertical extension extends along a surface direction perpendicular to the substrate.

24. A semiconductor device, characterized in that, Includes: semiconductor devices as described in any one of claims 1 to 23; The semiconductor devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

25. A method for manufacturing a semiconductor device, characterized in that, include: A first fin-like structure, a second fin-like structure, and a first isolation structure are formed on the substrate; The first fin structure and the second fin structure are spaced apart along a direction parallel to the surface of the substrate, and the first isolation structure fills the space between the first fin structure and the second fin structure; along the thickness direction of the substrate, both the first fin structure and the second fin structure include a lower fin, a semiconductor isolation portion and an upper fin arranged sequentially. The upper fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the lower fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the lower fin portion included in the second fin structure are etched away; The lower fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the upper fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the upper fin portion of the first fin structure are etched away.

26. The method for manufacturing a semiconductor device according to claim 25, characterized in that, The protection of the upper fin portion included in the first fin structure and the second fin structure includes: A first mask structure is formed that spans the first fin structure and the second fin structure; Etching removes the portions of the first fin structure and the second fin structure that are exposed outside the first mask structure; A second mask structure is formed on the substrate, covering both sides of the lower fin along the length direction, including the lower fin and the upper fin. A third mask structure is formed covering both sides of the upper fin along the length direction, including the lower fin and the upper fin; the material of the third mask structure is different from the material of the second mask structure; The second mask structure is selectively removed.

27. The method for manufacturing a semiconductor device according to claim 25, characterized in that, The protection of the lower fin portion included in the first fin structure and the second fin structure includes: A second isolation structure is formed covering both sides of the lower fin portion of the second fin structure along its length and covering the already formed source / drain region.

28. The method for manufacturing a semiconductor device according to claim 26, characterized in that, The method for manufacturing the semiconductor device after etching away the source / drain regions on both sides of the upper fin portion of the first fin structure further includes: Using semiconductor technology, a first transistor is formed based on the remaining lower fin portion of the first fin structure and the source / drain region adjacent to it, and a second transistor is formed based on the remaining upper fin portion of the second fin structure and the source / drain region adjacent to it.

29. The method for manufacturing a semiconductor device according to claim 28, characterized in that, Using semiconductor technology, a first transistor is formed based on the remaining lower fin portion of the first fin structure and the source / drain region adjacent to it, and a second transistor is formed based on the remaining upper fin portion of the second fin structure and the source / drain region adjacent to it, comprising: Remove at least a portion of the first mask structure; The channel region of the first transistor is formed based on the remaining lower fin portion in the first fin structure; and the channel region of the second transistor is formed based on the remaining upper fin portion in the second fin structure. At least a portion of the first isolation structure located between the channel region included in the first transistor and the remaining lower fin in the second fin structure is etched away, and at least a portion of the first isolation structure located between the channel region included in the second transistor and the remaining upper fin in the first fin structure is etched away. A grid stack structure is formed on the outer periphery of the channel region.

30. The method for manufacturing a semiconductor device according to claim 28, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A first source-drain contact structure is formed that is electrically connected to one of the source-drain regions included in the first transistor; A second source-drain contact structure is formed to electrically contact one of the source-drain regions included in the second transistor; the first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the first transistor and / or the gate stack structure included in the second transistor, and are spaced apart; the first source-drain contact structure extends along a surface direction perpendicular to the substrate.

31. The method for manufacturing a semiconductor device according to claim 28, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A third source-drain contact structure is formed that is electrically connected to both the other source-drain region included in the first transistor and the other source-drain region included in the second transistor. The third source-drain contact structure includes a vertical extension and a lateral extension electrically contacting the vertical extension. The vertical extension is located above and electrically contacting the other source-drain region included in the first transistor. The lateral extension is located above or below the other source-drain region included in the second transistor and is used to electrically connect the vertical extension to the other source-drain region included in the second transistor.

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