Electrostatic protection semiconductor device

Abstract

The invention discloses an electrostatic protection semiconductor device, which comprises a well region located at the upper part of a substrate; the drain electrode region and the source electrode region are located at the first end and the second end, opposite to each other, of the upper portion of the well region respectively, the source electrode region is grounded, and the drain electrode region is connected with a device pin; the grid electrode layer is located above the well region, adjacent to the source electrode region and electrically connected with the source electrode region; the field plate layer is located above the well region, the first end of the field plate layer is adjacent to and electrically connected with the drain region, and a gap is formed between the second end of the field plate layer and the gate layer; the adjacent first N + doped region and first P + doped region are located in the well region below the gap, and the first N + doped region is electrically connected with the second end of the field plate layer; and the second N + doped region and the second P + doped region are positioned in the field plate layer and are alternately distributed. And the second N + doped region and the second P + doped region in the field plate layer form at least one forward PN junction and / or at least one reverse PN junction. Therefore, the breakdown voltage and withstand voltage of the semiconductor device can be freely adjusted, and the electrostatic protection capability is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an electrostatic discharge (ESD) protection semiconductor device. Background Technology

[0002] ESD (Electro-Static Discharge) is a natural phenomenon that occurs throughout the entire product lifecycle. While not easily perceived by the human body, ESD poses a serious threat to integrated circuit products. During chip manufacturing, packaging, testing, and application, both the external environment and internal structure accumulate static charge, making them vulnerable to electrostatic discharge. Therefore, ESD protection devices must be placed at each pin in chip design. GGNMOS (Gate-grounded NMOS) structures are frequently used as ESD protection devices.

[0003] Figure 1 A schematic cross-sectional view of an existing GGNMOS electrostatic protection semiconductor device is shown. (e.g.) Figure 1 As shown, the semiconductor device includes a substrate 10 and a well region 20 located on top of the substrate 10, and also includes a drain region and a source region located at both ends of the top of the well region 20. The drain region is an N+ doped region 31, the source region is an N+ doped region 32, the body region is in contact with the source region, and the body region is a P+ doped region 33. Both the substrate 10 and the well region 20 are P-type doped. The semiconductor device also includes a gate layer 41, which is, for example, a field plate layer made of polysilicon, located between the drain region and the source region. The drain region is connected to the pin of the protected device, i.e., the I / O port, and the source region, gate region, and body region are all grounded or connected to the GND pin.

[0004] When the drain region receives a large electrostatic pulse, avalanche breakdown first occurs between the drain region (N+ doped region 31) and the well region 20 (P-type well region), generating a current in the well region 20. This creates a voltage drop across the resistance in the well region, causing the NPN transistor between the N+ doped region 31, the well region 20, and then the N+ doped region 32 to conduct, forming a current discharge path from the drain to the source. The breakdown voltage BV of this semiconductor device depends on the breakdown voltage of the junction formed between the N+ doped region 31 and the P-type well region 20, and is basically equal to the breakdown voltage of conventional NMOS devices. The high breakdown voltage requires a high trigger voltage, resulting in poor protection. Therefore, current GGNMOS structure electrostatic discharge protection devices have poor electrostatic discharge protection capabilities. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide an electrostatic discharge (ESD) protected semiconductor device to solve the problems in the prior art.

[0006] According to one aspect of the present invention, an electrostatic discharge (ESD) protected semiconductor device is provided, comprising: a well region located in an upper portion of a substrate; a drain region and a source region located at opposite first and second ends in the upper portion of the well region, respectively, the source region being grounded and the drain region being connected to a device pin; a gate layer located above the well region, adjacent to and electrically connected to the source region; a field plate layer located above the well region, the first end of the field plate layer being adjacent to and electrically connected to the drain region, and a gap being formed between the second end of the field plate layer and the gate layer; adjacent first N+ doped regions and first P+ doped regions located in the well region below the gap; and second N+ doped regions and second P+ doped regions located in the field plate layer and alternately distributed, wherein the second N+ doped regions and second P+ doped regions in the field plate layer form at least one forward PN junction and / or at least one reverse PN junction.

[0007] Optionally, the first and second ends of the field plate layer are both distributed with the second N+ doped region, and the second N+ doped region at the first end of the field plate layer is electrically connected to the drain region, and the second N+ doped region at the second end of the field plate layer is electrically connected to the first N+ doped region in the well region.

[0008] Optionally, the electrostatic discharge (ESD) protection semiconductor device further includes: a conductive layer covering a portion of the first N+ doped region and the first and second ends of the field plate layer, wherein the first N+ doped region and the first P+ doped region not covered by the conductive layer form a PN junction, and the second N+ doped region and the second P+ doped region not covered by the conductive layer form a PN junction.

[0009] Optionally, when the electrostatic discharge semiconductor device is in operation, the drain region receives an electrostatic pulse, which turns on the PN junction in the field plate layer. The reverse PN junction formed by the first N+ doped region and the first P+ doped region is broken down, and the current flows from the well region to the source region, so that the transistor composed of the drain region, the well region and the source region turns on to form a current discharge path.

[0010] Optionally, from the first end to the second end of the field plate layer, adjacent second P+ doped regions and second N+ doped regions not covered by the conductive layer form a forward PN junction, while adjacent second N+ doped regions and second P+ doped regions not covered by the conductive layer form a reverse PN junction.

[0011] Optionally, when multiple PN junctions are formed within the field plate layer, the multiple PN junctions are connected in series.

[0012] Optionally, the first P+ doped region partially surrounds the first N+ doped region, and the conductive layer exposes the entire surface of the first P+ doped region and a portion of the surface of the first N+ doped region adjacent to the first P+ doped region.

[0013] Optionally, the first N+ doped region is adjacent to the gate layer, and the first P+ doped region is located between the first N+ doped region and the field plate layer; or, the first N+ doped region is adjacent to the field plate layer, and the first P+ doped region is located between the first N+ doped region and the gate layer.

[0014] Optionally, a second P+ doped region is formed between the second N+ doped region at the first end of the field plate layer and the second N+ doped region at the second end of the field plate layer. When the conductive layer completely exposes the second P+ doped region and partially exposes the second N+ doped regions at the first end of the field plate layer and the second N+ doped regions at the second end of the field plate layer, adjacent reverse PN junctions and forward PN junctions are formed within the field plate layer. When the conductive layer only exposes a portion of the second N+ doped region and a portion of the second P+ doped region at the second end of the field plate layer, a forward PN junction is formed within the field plate layer. When the conductive layer only exposes a portion of the second N+ doped region and a portion of the second P+ doped region at the first end of the field plate layer, a reverse PN junction is formed within the field plate layer.

[0015] Optionally, when a plurality of second P+ doped regions are formed between the second N+ doped region at the first end of the field plate layer and the second N+ doped region at the second end of the field plate layer, and the conductive layer only covers a portion of the second N+ doped region at the first end of the field plate layer and a portion of the second N+ doped region at the first end of the field plate layer, the reverse PN junctions and forward PN junctions are alternately distributed within the field plate layer.

[0016] Optionally, the conductive layer is a metal silicide, and the field plate layer is a polycrystalline silicon layer.

[0017] According to another aspect of the present invention, an integrated circuit is provided, comprising: the above-described electrostatic discharge (ESD) protection semiconductor device.

[0018] The electrostatic discharge (ESD) protected semiconductor device provided by this invention, based on a GGNMOS structure, forms adjacent first N+ doped regions and first P+ doped regions within the well region, causing the breakdown junction to shift from the N+ doped region to the P-type well region and then to the first N+ doped region and then to the first P+ doped region. Because the concentration of the first P+ doped region is high, the breakdown voltage is low, thus reducing the device's breakdown voltage and improving its ESD protection capability. To simultaneously ensure the device's breakdown voltage capability, a field plate layer, separated from the gate layer, is also provided above the well region. A second N+ doped region and a second P+ doped region are distributed within the field plate layer to form forward or reverse PN junctions. This improves the device's breakdown voltage while reducing the breakdown voltage, enhancing ESD protection capability while preventing false triggering.

[0019] Furthermore, a conductive layer is disposed above the field plate layer. This conductive layer exposes portions of the surface of the second N+ doped region and the second P+ doped region, while the second N+ doped region and the second P+ doped region not covered by the conductive layer can form a PN junction. Therefore, the orientation and number of PN junctions within the field plate layer can be adjusted by changing the position of the conductive layer and the number of doped regions it covers, thus achieving free adjustment of the device's withstand voltage. This allows for the protection of devices operating at different voltages, broadening the application scenarios and enhancing applicability. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of the cross-sectional structure of an existing GGNMOS electrostatic protection semiconductor device is shown.

[0022] Figure 2 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a first embodiment of the present invention is shown.

[0023] Figure 3 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a second embodiment of the present invention is shown.

[0024] Figure 4 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a third embodiment of the present invention is shown.

[0025] Figure 5 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a fourth embodiment of the present invention is shown.

[0026] Figure 6 A cross-sectional structural schematic diagram of an electrostatic discharge (ESD) protection semiconductor device according to a fifth embodiment of the present invention is shown. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0028] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region. In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0029] Unless otherwise specified below, the various layers or regions of a semiconductor device may be made of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, and SiC, and group IV semiconductors such as Si and Ge. Gate conductors and electrode layers may be formed of various conductive materials, such as metal layers, doped polysilicon layers, or stacked gate conductors comprising metal layers and doped polysilicon layers, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of these conductive materials.

[0030] Figure 2 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a first embodiment of the present invention is shown.

[0031] like Figure 2As shown, the electrostatic discharge (ESD) protected semiconductor device 100 of this embodiment includes a substrate 10 and a well region 20 located in the upper part of the substrate 10, as well as a drain region and a source region located in the upper part of the well region 20. The substrate 10 and the well region 20 are, for example, P-type doped. The drain region and the source region are located at opposite first and second ends in the upper part of the well region, respectively, and the source region is grounded (GND), while the drain region is connected to a device pin (I / O port). The drain region includes at least an N+ doped region 31, the source region includes at least an N+ doped region 32, and there is also a P+ doped region 33 adjacent to the N+ doped region 32 in the well region 20, serving as a body region. A gate layer 41 is distributed above the well region 20 between the source region and the drain region. The gate layer is, for example, a polysilicon layer, adjacent to and electrically connected to the source region. The gate layer 41, the source region, and the body region are all led out through interconnects and connected to a reference ground. In this embodiment, a field plate layer 42, separated from the gate layer, is also distributed above the well region 20. The first end of the field plate layer 42 is adjacent to and electrically connected to the drain region, and a gap exists between the second end of the field plate layer 42 and the gate layer 41. The field plate layer 42 is, for example, a polysilicon layer, and can be formed in the same process step as the gate layer 41. Adjacent first N+ doped regions 72 and first P+ doped regions 71 are also distributed in the well region 20 below the gap between the gate layer 41 and the field plate layer 42. The first N+ doped region 72 is electrically connected to the second end of the field plate layer 42.

[0032] The field layer 42 has alternating distributions of a second N+ doped region and a second P+ doped region, which form at least one forward PN junction and / or at least one reverse PN junction. Specifically, a second N+ doped region 61 is distributed at the first end of the field layer 42, and an N+ doped region 63 is distributed at the second end of the field layer 42. The second N+ doped region 61 at the first end of the field layer is electrically connected to the drain region, and the second N+ doped region 63 at the second end of the field layer is electrically connected to the first N+ doped region 72 in the well region.

[0033] Furthermore, the electrostatic discharge (ESD) protected semiconductor device 100 also includes a conductive layer 50, which covers the well region 20, the gate layer 41, and the field plate layer 42, and exposes at least a portion of the field plate layer 42 and a portion of the well region 20 below the gap (the gap being the gap between the gate layer 41 and the field plate layer 42 mentioned above). For example, the conductive layer 50 covers a portion of the first N+ doped region 72 and the first and second ends of the field plate layer 42. The second N+ doped region and the second P+ doped region within the field plate layer 42 not covered by the conductive layer 50 form a PN junction, and the first N+ doped region 72 and the first P+ doped region 71 within the well region 20 below the gap not covered by the conductive layer 50 form a PN junction. When the electrostatic discharge (ESD) protected semiconductor device 100 is operating, if the drain region receives an ESD pulse, adjacent second P+ doped regions and second N+ doped regions not covered by the conductive layer 50 form a forward PN junction from the first end to the second end of the field plate layer 42, while adjacent second N+ doped regions and second P+ doped regions not covered by the conductive layer 50 form a reverse PN junction. The conductive layer 50 is, for example, a metal silicide, and can be interconnected via wires. Inside the well region, the PN junction formed by the first N+ doped region 72 and the first P+ doped region 71 not covered by the conductive layer 50 breaks down in the reverse direction. Figure 2 A second P+ doped region 62 is formed between the second N+ doped region 61 at the first end of the field plate layer and the second N+ doped region 63 at the second end of the field plate layer. When the conductive layer 50 exposes only a portion of the second N+ doped region 63 and a portion of the second P+ doped region 62 at the second end of the field plate layer, a forward PN junction is formed within the field plate layer 42, that is, a forward PN junction is formed between the second P+ doped region 62 and the second N+ doped region 63. Therefore, when there is an electrostatic pulse in the drain region, the electrostatic current first travels from the drain region through the conductive layer 50 to the second N+ doped region 61 and the second P+ doped region 62, then through the forward PN junction to the second N+ doped region 63, and finally through the conductive layer 50 to the first N+ doped region 72.

[0034] In this embodiment, the first P+ doped region 71 partially surrounds the first N+ doped region 72, and its surface is not covered by the conductive layer 50. The conductive layer 50 also exposes a portion of the surface of the first N+ doped region 72 adjacent to the first P+ doped region 71. For example, the first N+ doped region 72 is adjacent to the field plate layer 42, and the first P+ doped region 71 is located within the well region 20 between the gate layer 41 and the first N+ doped region 72. The conductive layer 50 exposes the entire upper surface of the first P+ doped region 71 and a portion of the surface of the first N+ doped region 72 adjacent to the first P+ doped region 71. At this time, the PN junction between the first N+ doped region 72 and the first P+ doped region 71, which are not covered by the conductive layer 50, breaks down in the reverse direction, allowing current to flow through the well region 20 and exit from the source region. Thus, the NPN transistor structure composed of the N+ doped region 31 (drain region), the well region 20, and the N+ doped region 32 (source region) is turned on. This forms a current discharge path from the drain region to the source region. The drain region can be considered as the anode, and the source region can be considered as the cathode. In other embodiments, the first N+ doped region 72 is adjacent to the gate layer 41, and the first P+ doped region 71 is located in the well region 20 between the first N+ doped region 72 and the field plate layer 42. The conductive layer 50 exposes the entire surface of the first P+ doped region 71 and a portion of the surface of the first N+ doped region 72 adjacent to the first P+ doped region 71. The current discharge path of the electrostatic discharge semiconductor device during operation is the same as described above and will not be repeated here. In other embodiments, the first P+ doped region 71 and the first N+ doped region 72 are located side by side between the gate layer 41 and the field plate layer 42. Taking the extension direction from the gate layer 41 to the field plate layer 42 as the device length direction, the device width direction is perpendicular to the length direction, and the first P+ doped region 71 and the first N+ doped region 72 can be arranged along the device width direction.

[0035] Therefore, in this embodiment, the single-layer polysilicon structure of GGNMOS is changed to a double-layer polysilicon structure by adding a field plate layer 42. The newly added field plate layer 42 contains a second N+ doped region and a second P+ doped region. The areas of these two regions not covered by the conductive layer 50 can form forward or reverse PN junctions. When the electrostatic discharge (ESD) semiconductor device 100 is operating, the drain region receives an ESD pulse, causing the PN junction in the field plate layer 42 to conduct. The PN junction formed by the first N+ doped region 72 and the first P+ doped region 71 is reverse-broken down, allowing current to flow through the well region 20. This current flows from the well region 20 to the source region, causing the NPN transistor structure composed of the source region, well region 20, and source region to conduct, thus forming a current discharge path from the drain region to the source region. Since the first N+ doped region 72 and the first P+ doped region 71 are both highly doped regions, the breakdown voltage BV between them is very low, easily triggering ESD protection. Furthermore, the overall withstand voltage capability of the electrostatic discharge protection semiconductor device 100 is improved by adding a PN junction in the field plate layer 42, making it suitable for applications with higher operating voltages.

[0036] Furthermore, the number and orientation of PN junctions in the field plate layer 42 can be adjusted according to requirements to obtain a suitable breakdown voltage value BV. When multiple PN junctions are formed in the field plate layer 42, they are connected in series, causing the PN junction in the well region to break down in the reverse direction. Current is generated in the well region, causing the NPN transistor structure formed by the drain region, well region, and source region to conduct, thus forming a current discharge path from the anode to the cathode. The presence of PN junctions in the field plate layer 42 and the well region 20 is to adjust the trigger voltage of the electrostatic discharge protection semiconductor device, so that the NPN transistor structure can conduct as needed for current discharge. In this embodiment, if multiple forward PN junctions need to be connected in series (in Figure 6 As introduced in the text, to save device area and process costs, multiple series-connected forward PN junctions can be replaced with a few reverse PN junctions, for example... Figure 3 Electrostatic discharge (ESD) protection semiconductor devices.

[0037] Figure 3 A schematic cross-sectional view of an electrostatic protection semiconductor device according to a second embodiment of the present invention is shown.

[0038] like Figure 3 As shown, the electrostatic discharge (ESD) protected semiconductor device 100 of this embodiment also includes a substrate 10, a well region 20, a drain region (N+ doped region 31), a source region (N+ doped region 32), a body region (P+ doped region 32), a gate layer 41, a field plate layer 42, a conductive layer 50, a first N+ doped region 72, a first P+ doped region 71, second N+ doped regions 61 and 63, and a second P+ doped region 62. Their positional distribution is similar to... Figure 2The embodiments are the same, except that in this embodiment, the conductive layer 50 covers the second N+ doped region 63 and part of the second P+ doped region 62 at the second end of the field plate layer, and covers part of the second N+ doped region 61 at the first end of the field plate layer. At this time, the second N+ doped region 61 and the second P+ doped region 62 not covered by the conductive layer 50 in the field plate layer 42 form a reverse PN junction. When the electrostatic discharge semiconductor device 100 is working, the drain region receives an electrostatic pulse, and from the first end to the second end of the field plate layer 42, the adjacent second P+ doped region 62 and the second N+ doped region 61 not covered by the conductive layer form a reverse PN junction. Moreover, the PN junction between the first N+ doped region 72 and the first P+ doped region 71 is reversed and a current flows through the well region 20, so that the NPN transistor structure composed of the drain region, the well region 20 and the source region is turned on, so as to form a current discharge path from the anode (drain region) to the cathode (source region). The current flowing through the well region 20 can be regarded to some extent as the conduction control current of the NPN transistor.

[0039] Similarly, the number of reverse PN junctions in the field plate layer 42 can be adjusted to obtain a suitable breakdown voltage value BV, depending on the requirements. When multiple reverse PN junctions are formed in the field plate layer 42, the multiple reverse PN junctions are connected in series.

[0040] Figure 4 A schematic cross-sectional view of an electrostatic discharge (ESD) protection semiconductor device according to a third embodiment of the present invention is shown.

[0041] like Figure 4 The electrostatic discharge (ESD) protected semiconductor device 100 of this embodiment also includes a substrate 10, a well region 20, a drain region (N+ doped region 31), a source region (N+ doped region 32), a body region (P+ doped region 32), a gate layer 41, a field plate layer 42, a conductive layer 50, a first N+ doped region 72, a first P+ doped region 71, second N+ doped regions 61 and 63, and a second P+ doped region 62. Their positional distribution is... Figure 2 The embodiments are the same, except that in this embodiment, when the conductive layer 50 fully exposes the second P+ doped region 62 and partially exposes the second N+ doped region 61 at the first end of the field plate layer and the second N+ doped region 63 at the second end of the field plate layer 42, adjacent reverse PN junctions and forward PN junctions are formed within the field plate layer 42. That is, when the electrostatic discharge (ESD) semiconductor device 100 is operating, the drain region receives an ESD pulse, causing both a reverse PN junction and a forward PN junction within the field plate layer 42 to conduct, and then causing the PN junction in the well region 20 to break down in the reverse direction. Afterward, the NPN transistor conducts, forming a current discharge path from the drain region to the source region.

[0042] Figure 5 A cross-sectional structural schematic diagram of an electrostatic protection semiconductor device according to a fourth embodiment of the present invention is shown.

[0043] like Figure 5 The electrostatic discharge (ESD) protected semiconductor device 100 of this embodiment also includes a substrate 10, a well region 20, a drain region (N+ doped region 31), a source region (N+ doped region 32), a body region (P+ doped region 32), a gate layer 41, a field plate layer 42, a conductive layer 50, a first N+ doped region 72, a first P+ doped region 71, second N+ doped regions 61 and 63, and a second P+ doped region 62. Their positional distribution is... Figure 2 The embodiments are the same, except that in this embodiment, multiple second P+ doped regions are formed between the second N+ doped region 61 at the first end of the field plate layer and the second N+ doped region 63 at the second end of the field plate layer. Specifically, from the first end to the second end of the field plate layer 42, the second N+ doped region 61, the second P+ doped region 62, the second N+ doped region 65, the second P+ doped region 64, and the second N+ doped region 63 are distributed sequentially. In this embodiment, when the conductive layer 50 covers part of the second N+ doped region 61 at the first end of the field plate layer 42, and covers the second N+ doped region 63 and part of the second P+ doped region 62 at the first end of the field plate layer, the reverse PN junctions and forward PN junctions are alternately distributed within the field plate layer. Specifically, the second P+ doped region 62 and the second N+ doped region 65 form a forward PN junction, the second N+ doped region 65 and the second P+ doped region 64 form a reverse PN junction, and the second P+ doped region 64 and the second N+ doped region 63 form a forward PN junction.

[0044] Figure 6 A cross-sectional structural schematic diagram of an electrostatic discharge (ESD) protection semiconductor device according to a fifth embodiment of the present invention is shown.

[0045] like Figure 6 As shown, the electrostatic discharge (ESD) protected semiconductor device 100 of this embodiment also includes a substrate 10, a well region 20, a drain region (N+ doped region 31), a source region (N+ doped region 32), a body region (P+ doped region 32), a gate layer 41, a field plate layer 42, a conductive layer 50, a first N+ doped region 72, a first P+ doped region 71, second N+ doped regions 61, 63, and 65, and second P+ doped regions 62 and 64. Their positional distribution is similar to... Figure 5 The embodiments are the same, except that in this embodiment, the conductive layer 50 covers the second N+ doped region 61 and part of the second P+ doped region 62 at the first end of the field plate layer, and covers part of the second N+ doped region 63 at the second end of the field plate layer, and also covers the surface portion adjacent to the second N+ doped region 65 and the second P+ doped region 64. This forms multiple series-connected forward PN junctions in the field plate layer 42. Specifically, a forward PN junction is formed between the second P+ doped region 62 and the second N+ doped region 65, and a forward PN junction is also formed between the second P+ doped region 64 and the second N+ doped region 63.

[0046] In summary, the required withstand voltage can be obtained based on the actual operating voltage of the protected device. Then, the direction and number of PN junctions in the field plate layer 42 can be adjusted to obtain a suitable breakdown voltage value BV. When multiple PN junctions are formed within the field plate layer, they are connected in series. Thus, the electrostatic discharge (ESD) protection semiconductor device of this embodiment changes the single-layer polysilicon structure of GGNMOS to a double-layer polysilicon structure, introducing a high-concentration first N+ doped region and a first P+ doped region between the two polysilicon sections, and then introducing one or more forward or reverse PN junctions within the field plate layer 42. This changes the junction breakdown between the N+ doped region and the P-type well region to a junction breakdown between the high-concentration N+ doped region and the P+ doped region, while simultaneously adjusting the withstand voltage through one or more PN junctions within the field plate layer 42. The combination of these two parts allows for the adjustment of the required breakdown voltage value BV. It is stable and reliable under both low-frequency and high-frequency signals, achieving superior protection for the internal circuitry of the chip.

[0047] In addition, the present invention also provides an integrated circuit comprising the electrostatic discharge protection semiconductor device described in the above embodiments.

[0048] In summary, the electrostatic discharge (ESD) protected semiconductor device and integrated circuit of this embodiment, based on the GGNMOS structure, form adjacent first N+ doped regions and first P+ doped regions within the well region, causing the breakdown junction to shift from the N+ doped region to the P-type well region and then to the first N+ doped region and finally to the first P+ doped region. Because the concentration of the first P+ doped region is high, the breakdown voltage is low, thus reducing the device's breakdown voltage and improving its ESD protection capability. To simultaneously ensure the device's withstand voltage capability, a field plate layer, separated from the gate layer, is also provided above the well region. A second N+ doped region and a second P+ doped region are distributed within the field plate layer to form forward or reverse PN junctions. The presence of multiple PN junctions makes it easier for the NPN transistor to conduct, thereby achieving ESD protection as needed, reducing the breakdown voltage while improving the device's withstand voltage, and enhancing ESD protection capability while preventing false triggering.

[0049] Furthermore, a conductive layer is disposed above the field plate layer. This conductive layer exposes portions of the surface of the second N+ doped region and the second P+ doped region, while the second N+ doped region and the second P+ doped region not covered by the conductive layer can form a PN junction. Therefore, the orientation and number of PN junctions within the field plate layer can be adjusted by changing the position of the conductive layer and the number of doped regions it covers, thus achieving free adjustment of the device's withstand voltage. This allows for the protection of devices operating at different voltages, broadening the application scenarios and enhancing applicability.

[0050] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electrostatic discharge (ESD) protection semiconductor device, comprising: The well region is located in the upper part of the substrate; The drain region and the source region are located at opposite first and second ends in the upper part of the well region, respectively. The source region is grounded and the drain region is connected to the device pin. A gate layer is located above the well region, adjacent to and electrically connected to the source region; A field plate layer is located above the well region. The first end of the field plate layer is adjacent to and electrically connected to the drain region, and a gap exists between the second end of the field plate layer and the gate layer. The adjacent first N+ doped region and the first P+ doped region are located in the well region below the void; as well as The second N+ doped region and the second P+ doped region are located within the field plate layer and are alternately distributed. The second N+ doped region and the second P+ doped region within the field plate layer form at least one forward PN junction and / or at least one reverse PN junction.

2. The electrostatic discharge (ESD) protection semiconductor device according to claim 1, wherein, The first and second ends of the field plate layer are both distributed with the second N+ doped region, and the second N+ doped region at the first end of the field plate layer is electrically connected to the drain region, and the second N+ doped region at the second end of the field plate layer is electrically connected to the first N+ doped region in the well region.

3. The electrostatic discharge protection semiconductor device according to claim 2, further comprising: A conductive layer covers a portion of the first N+ doped region and the first and second ends of the field plate layer. The first N+ doped region and the first P+ doped region not covered by the conductive layer form a PN junction, and the second N+ doped region and the second P+ doped region not covered by the conductive layer form a PN junction.

4. The electrostatic discharge (ESD) protection semiconductor device according to claim 1, wherein, When the electrostatic discharge semiconductor device is in operation, the drain region receives an electrostatic pulse, which turns on the PN junction in the field plate layer. The reverse PN junction formed by the first N+ doped region and the first P+ doped region is broken down, and the current flows from the well region to the source region, so that the transistor composed of the drain region, the well region and the source region turns on to form a current discharge path.

5. The electrostatic discharge protection semiconductor device according to claim 3, wherein, From the first end to the second end of the field plate layer, adjacent second P+ doped regions and second N+ doped regions not covered by the conductive layer form a forward PN junction, while adjacent second N+ doped regions and second P+ doped regions not covered by the conductive layer form a reverse PN junction.

6. The electrostatic discharge (ESD) protection semiconductor device according to claim 1 or 5, wherein, When multiple PN junctions are formed within the field plate layer, the multiple PN junctions are connected in series.

7. The electrostatic discharge (ESD) protection semiconductor device according to claim 3, wherein, The first P+ doped region partially surrounds the first N+ doped region, and the conductive layer exposes the entire surface of the first P+ doped region and a portion of the surface of the first N+ doped region adjacent to the first P+ doped region.

8. The electrostatic discharge (ESD) protection semiconductor device according to claim 7, wherein, The first N+ doped region is adjacent to the gate layer, and the first P+ doped region is located between the first N+ doped region and the field plate layer; or, the first N+ doped region is adjacent to the field plate layer, and the first P+ doped region is located between the first N+ doped region and the gate layer.

9. The electrostatic discharge protection semiconductor device according to claim 3, wherein, A second P+ doped region is formed between the second N+ doped region at the first end of the field plate layer and the second N+ doped region at the second end of the field plate layer. When the conductive layer fully exposes the second P+ doped region and partially exposes the second N+ doped region at the first end of the field plate layer and the second N+ doped region at the second end of the field plate layer, adjacent reverse PN junctions and forward PN junctions are formed within the field plate layer. When the conductive layer exposes only a portion of the second N+ doped region and a portion of the second P+ doped region at the second end of the field plate layer, a forward PN junction is formed within the field plate layer; When the conductive layer exposes only a portion of the second N+ doped region and a portion of the second P+ doped region at the first end of the field plate layer, a reverse PN junction is formed within the field plate layer.

10. The electrostatic discharge (ESD) protection semiconductor device according to claim 3, wherein, A plurality of second P+ doped regions are formed between the second N+ doped region at the first end of the field plate layer and the second N+ doped region at the second end of the field plate layer. When the conductive layer only covers a portion of the second N+ doped region at the first end of the field plate layer and a portion of the second N+ doped region at the first end of the field plate layer, the reverse PN junctions and forward PN junctions are alternately distributed within the field plate layer.

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