Solar cell and preparation method thereof

Abstract

The invention provides a heterojunction solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate; forming a first functional layer on the first side of the semiconductor substrate, wherein the material of the first functional layer comprises a semiconductor doping material and an intrinsic material; forming a second functional layer on the second side of the semiconductor substrate, wherein the material of the first functional layer comprises a semiconductor doping material and an intrinsic material; wherein the first side is opposite to the first side, the second side is opposite to the first side, at least one of the first functional layer and the second functional layer comprises an amorphous matrix and unit cells dispersed in the amorphous matrix, the material of the amorphous matrix comprises the intrinsic material, and the material of the unit cells comprises the semiconductor doping material. According to the embodiment of the invention, the intrinsic material and the semiconductor doped material are formed in the same preparation process, so that the replacement frequency of the heterojunction solar cell in different process chambers can be reduced in the preparation process, the cross contamination phenomenon is improved, the exposure time of an intermediate product in the air is reduced, and the pollution is further reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of batteries, in particular, to a solar cell and a preparation method thereof. BACKGROUND

[0002] A solar cell is a kind of semiconductor device that can convert solar energy into electrical energy. Under the condition of light, a photogenerated current is generated inside the solar cell, and the electrical energy is output through electrodes. In recent years, the production technology of solar cells has been continuously improved, the production cost has been continuously reduced, the conversion efficiency has been continuously improved, and the application of solar cell power generation has become increasingly widespread and has become an important energy source for power supply. Heterojunction solar cells are one of the new and efficient battery technologies, which combines the advantages of single crystal silicon solar cells and amorphous silicon solar cells, and has the characteristics of low preparation process temperature, high conversion efficiency, good high temperature characteristics, etc. Because the temperature degradation coefficient of heterojunction solar cells is small, and the double-sided power generation, the annual power generation can be 15-30% higher than that of polycrystalline silicon cells under the same area conditions, so it has great market potential.

[0003] The traditional heterojunction solar cell structure from the front to the back is: front electrode, front transparent conductive layer, front doped layer, front intrinsic layer, single crystal silicon substrate, back intrinsic layer, back doped layer, back transparent conductive layer and back electrode. The front doped layer, the front intrinsic layer, the back intrinsic layer and the back doped layer are prepared by plasma enhanced chemical vapor deposition (PECVD), which is also the most critical and important step in the preparation process of heterojunction solar cells.

[0004] How to improve the preparation efficiency of heterojunction solar cells is a problem that has been pursued in the field. SUMMARY

[0005] The present disclosure aims to solve one of the technical problems in the related art to some extent. To this end, the present disclosure provides a preparation method of a solar cell, and a solar cell prepared by the preparation method, wherein the preparation method includes relatively fewer steps, and can improve the preparation efficiency of the solar cell.

[0006] In order to achieve the above-mentioned purpose, as a first aspect of the present disclosure, a preparation method of a solar cell is provided, comprising:

[0007] providing a semiconductor substrate;

[0008] forming a first functional layer on a first side of the semiconductor substrate, the material of the first functional layer comprising a semiconductor doped material and an intrinsic material;

[0009] forming a second functional layer on a second side of the semiconductor substrate, the material of the first functional layer comprising a semiconductor doping material and an intrinsic material; wherein the second side is opposite to the first side, at least one of the first functional layer and the second functional layer comprises an amorphous matrix and a unit cell dispersed in the amorphous matrix, wherein the material of the amorphous matrix comprises the intrinsic material, and the material of the unit cell comprises the semiconductor doping material.

[0010] Optionally, forming the first functional layer on the first side of the semiconductor substrate comprises: in the same process chamber, based on a plasma enhanced chemical vapor deposition method, sequentially introducing process gas required for forming the intrinsic material, process gas required for forming one of the N-type semiconductor doping material and the P-type semiconductor doping material, to form the first functional layer.

[0011] Optionally, forming the second functional layer on the second side of the semiconductor substrate comprises: in the same process chamber, based on a plasma enhanced chemical vapor deposition method, sequentially introducing process gas required for forming the intrinsic material, process gas required for forming the other one of the N-type semiconductor doping material and the P-type semiconductor doping material, to form the second functional layer.

[0012] Optionally, the first functional layer comprises the intrinsic material and the N-type semiconductor doping material, the process gas required for forming the intrinsic material comprises hydrogen and silane, and the process gas required for forming the N-type semiconductor doping material comprises phosphine.

[0013] Optionally, the temperature in the process chamber is 150-250℃, the pressure in the process chamber is 0.1-10mbar, the gas flow of the hydrogen is 1000-20000sccm, the gas flow of the silane is 50-500sccm, and the gas flow of the phosphine is 20-300sccm.

[0014] Optionally, the second functional layer comprises the intrinsic material and the P-type semiconductor doping material, the process gas required for forming the intrinsic material comprises hydrogen and silane, and the process gas required for forming the P-type semiconductor doping material comprises borane.

[0015] Optionally, the temperature in the process chamber is 150-250℃, the pressure in the process chamber is 0.1-10mbar, the gas flow of the hydrogen is 1000-20000sccm, the gas flow of the silane is 50-500sccm, and the gas flow of the borane is 20-300sccm.

[0016] Optionally, the first functional layer has a thickness of 10-30 nm, and / or the second functional layer has a thickness of 10-30 nm.

[0017] Optionally, the preparation method further comprises:

[0018] forming a first transparent conductive layer on a side of the first functional layer away from the semiconductor substrate;

[0019] forming a second transparent conductive layer on a side of the second functional layer away from the semiconductor substrate.

[0020] Optionally, the preparation method further comprises:

[0021] forming at least one first electrode on a side of the first transparent conductive layer away from the semiconductor substrate;

[0022] forming at least one second electrode on a side of the second transparent conductive layer away from the semiconductor substrate.

[0023] As a second aspect of the present disclosure, a solar cell is provided, wherein the solar cell is formed by the preparation method provided in the first aspect of the present disclosure.

[0024] In the preparation method of the solar cell provided in the present disclosure, the intrinsic material and the semiconductor-doped material are formed in the same preparation process. It should be understood that different preparation processes are formed in different process chambers in a vacuum environment, while the same preparation process does not require chamber replacement. In this way, the number of chamber replacements during the preparation process can be reduced, the cross-contamination phenomenon can be improved, and the exposure time of the intermediate product in the air can be reduced, further reducing pollution; at the same time, the first functional layer and the second functional layer are formed on opposite sides of the semiconductor substrate, and each functional layer includes the semiconductor-doped material and the intrinsic material, which can reduce the number of flip times during the preparation process and reduce the chip rate. Based on this, the film layer quality, the preparation efficiency, and the product yield can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A flowchart of a preparation method of a solar cell provided in an embodiment of the present disclosure is shown.

[0026] Figure 2 A structure diagram of a solar cell provided in an embodiment of the present disclosure is shown.

[0027] Figure 3 A flowchart of another preparation method of a solar cell provided in an embodiment of the present disclosure is shown.

[0028] Figure 4aA cross-sectional structure diagram of part of the film layers in a heterojunction solar cell provided in the related art.

[0029] Figure 4b An effect diagram of part of the film layers in a heterojunction solar cell provided in the related art.

[0030] Figure 5a A contact interface structure diagram of intrinsic material and semiconductor doped material provided in an embodiment of the present disclosure.

[0031] Figure 5b An effect diagram of the contact interface of intrinsic material and semiconductor doped material provided in an embodiment of the present disclosure.

[0032] Legend of reference signs:

[0033] 11: semiconductor substrate 11; 21: first functional layer; 22: second functional layer; 31: first transparent conductive layer; 32: second transparent conductive layer; 41: first electrode; 42: second electrode. DETAILED DESCRIPTION

[0034] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Examples of the embodiments are shown in the drawings, in which the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. Based on the embodiments in the embodiments, it is intended to explain the present disclosure, and cannot be understood as a limitation of the present disclosure.

[0035] In this specification, "one embodiment" or "an embodiment" or "example" or "exemplary" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearance of the phrase "in one embodiment" in various places in the specification is not necessarily all referring to the same embodiment.

[0036] In the related art, the front surface doped layer, the front surface intrinsic layer, the back surface intrinsic layer, and the back surface doped layer of the solar cell are prepared in different process chambers of a vacuum device respectively, and only one film layer can be formed at a time. Therefore, the preparation process steps of the solar cell are complex and numerous, and the process takes a long time and has low preparation efficiency.

[0037] Therefore, an embodiment of the present disclosure provides a preparation method of a solar cell, Figure 1 A flowchart of a preparation method of a solar cell provided in an embodiment of the present disclosure, Figure 2 A structure diagram of a solar cell provided in an embodiment of the present disclosure.

[0038] As Figure 1 , Figure 2 indicated, the preparation method of the solar cell provided in the embodiment of the present disclosure includes:

[0039] In step S1, a semiconductor substrate 11 is provided.

[0040] In step S2, a first functional layer 21 is formed on a first side of the semiconductor substrate 11, a material of the first functional layer including a semiconductor doping material and an intrinsic material.

[0041] In step S3, a second functional layer 22 is formed on a second side of the semiconductor substrate 12, a material of the second functional layer 22 including a semiconductor doping material and an intrinsic material.

[0042] The first side and the second side are opposite, and at least one of the first functional layer 21 and the second functional layer 22 includes an amorphous matrix and a unit cell dispersed in the amorphous matrix, a material of the amorphous matrix including the intrinsic material, and a material of the unit cell including the semiconductor doping material.

[0043] In the method for manufacturing a solar cell provided by the embodiments of the present disclosure, the intrinsic material and the semiconductor doping material are formed in the same manufacturing process, and a unit cell dispersed in an amorphous material is formed on a contact interface between the two materials. The amorphous matrix is formed by the intrinsic material, and the unit cell is formed by the semiconductor doping material. That is, the two materials do not have a clear boundary in the formation process and can naturally transition to form.

[0044] It should be understood that different manufacturing processes are formed in different process chambers in a vacuum environment, and the same manufacturing process does not need to change the chamber. In this way, the number of changes between different process chambers and the wafer test during the manufacturing process can be reduced to improve the generation efficiency, and the cross-contamination phenomenon can be improved, and the exposure time of the intermediate product in the air is reduced, further reducing pollution, improving the quality of the film layer, and ultimately improving the quality and yield of the solar cell.

[0045] As an optional implementation, the first functional layer and the second functional layer both include the semiconductor doping material and the intrinsic material, which can further reduce the wafer test frequency during the manufacturing process and reduce the wafer breakage rate.

[0046] In some embodiments, the material of the semiconductor substrate 11 can include any one of N-type single crystal silicon, P-type single crystal silicon, or intrinsic single crystal silicon.

[0047] In some embodiments, the thickness of the semiconductor substrate 11 can be 50 μm to 200 μm, for example, the thickness of the semiconductor substrate 11 is 100 μm or 165 μm, which is not limited by the embodiments of the present disclosure.

[0048] In addition, it should be noted that, in the preparation of the solar cell, the surface impurities of the semiconductor substrate 11 need to be removed to eliminate the surface damage layer of the semiconductor substrate 11; at the same time, in order to reduce the reflection of the light on the surface of the solar cell and increase the absorption of light energy, a concave-convex structure needs to be formed on the surface of the semiconductor substrate 11.

[0049] Therefore, in step S1, the surface of the semiconductor substrate 11 needs to be cleaned and textured, and a four-sided pyramid structure with multiple crystal surfaces, i.e., a pyramid structure, is formed on the surface, which is densely distributed on the surface of the semiconductor substrate 11 to form a surface texture, so that the reflectivity of the cell sheet can be reduced, the uneven texture can increase the secondary reflection, change the optical path and the incidence mode, and increase the light energy absorption.

[0050] Figure 3 Another flowchart of a method for preparing a solar cell is provided in the embodiments of the present disclosure. In some embodiments, the semiconductor doping material in the first functional layer is selected from one of an N-type semiconductor doping material and a P-type semiconductor doping material, and the semiconductor doping material in the second functional layer is selected from the other of the N-type semiconductor doping material and the P-type semiconductor doping material.

[0051] Correspondingly, as shown in Figure 3 The above step S2 can specifically include: in the same process chamber, based on a plasma-enhanced chemical vapor deposition method, process gas required for forming intrinsic material, process gas required for forming one of the N-type semiconductor doping material and the P-type semiconductor doping material are sequentially introduced to form the first functional layer 21.

[0052] As shown in Figure 3 The above step S3 can specifically include: in the same process chamber, based on a plasma-enhanced chemical vapor deposition method, process gas required for forming intrinsic material, process gas required for forming the other of the N-type semiconductor doping material and the P-type semiconductor doping material are sequentially introduced to form the second functional layer 22.

[0053] Figure 4a A cross-sectional structure diagram of part of the film layer in the heterojunction solar cell provided in the related art is shown. Figure 4bThis is a schematic diagram illustrating the effect of a portion of the film layers in a heterojunction solar cell provided in related technologies. It should be understood that the intrinsic material is amorphous silicon, and the semiconductor dopant is a crystalline material after crystallization treatment. In related technologies, since the intrinsic layer 41 and the doped layer 42 are formed in different process chambers, the interface contact and lattice matching between the two materials must be considered during the fabrication of the intrinsic layer 41 and the doped layer 42. Simultaneously, to avoid contamination of the already formed intrinsic layer 41 during the transfer process between different chambers, and to avoid the problem that the intrinsic material and the semiconductor dopant have different lattice properties after transfer, preventing the direct growth of the doped layer 42, a transition layer 40 needs to be grown on the intrinsic layer 41.

[0054] In one example, such as Figure 4a , Figure 4b As shown, the total thickness of the intrinsic layer 41 and the transition layer 40 is 5 nm to 15 nm; the thickness of the doped layer 42 is 15 nm to 25 nm.

[0055] Figure 5a This is a schematic diagram of the contact interface structure between the intrinsic material and the semiconductor doped material provided in the embodiments of this disclosure. Figure 5b This is a schematic diagram illustrating the effect of the contact interface between the intrinsic material and the semiconductor doped material provided in an embodiment of this disclosure. In this embodiment, the intrinsic material and the semiconductor doped material are formed in the same process chamber, such as... Figure 5a , Figure 5b As shown, the interface between the semiconductor doped material and the intrinsic material includes an amorphous substrate and unit cells dispersed within the amorphous substrate, wherein the amorphous substrate is formed by the intrinsic material and the unit cells are formed by the semiconductor doped material. In other words, the intrinsic material 51 and the semiconductor doped material 52 can transition naturally without the need for a separate transition layer, which improves the growth adhesion between film layers and reduces process defects. Simultaneously, the removal of the transition layer reduces the thickness of the first or second functional layer.

[0056] In some embodiments, the thickness of the first functional layer 21 or the second functional layer 22 is 10 nm to 30 nm. For example, the thickness of the first functional layer 21 can be selected from any one of 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm. The second functional layer 22 is similar, and will not be described in detail in this embodiment.

[0057] In addition, such as Figure 5b As shown, since the intrinsic material 51 and the semiconductor doped material 52 are grown in the same film layer, the first functional layer 21 or the second functional layer 22 is equivalent to a polycrystalline material.

[0058] In some embodiments, the fabrication process of the first functional layer 21 and the second functional layer 22 can be either chemical vapor deposition or physical vapor deposition, and this disclosure does not limit this process.

[0059] Taking the first functional layer 21 as an example, intrinsic materials and N-type semiconductor doping are sequentially prepared in a vacuum environment process chamber. In this way, compared with related technologies, there is no need to change the process chamber when preparing intrinsic materials and semiconductor doped materials, avoiding the exposure of intermediate products to air and avoiding cross-contamination between different process chambers, which is conducive to improving the quality of the film and increasing the preparation yield.

[0060] In addition, such as Figure 2 As shown, although the first functional layer 21, the semiconductor substrate 11, and the second functional layer 22 are stacked in the final product structure, in terms of the manufacturing process, the first functional layer 21 and the second functional layer 22 are formed on opposite sides of the semiconductor substrate 11. Therefore, there is no strict order in which the first functional layer 21 and the second functional layer 22 are manufactured. That is to say, step S2 can be executed first and then step S3, or step S3 can be executed first and then step S2. This embodiment does not limit this.

[0061] Combining steps S2 and S3, it can be seen that this method can complete the fabrication of intrinsic materials and semiconductor doped materials on both sides of the semiconductor substrate with just one flip within the same process chamber. In contrast, related technologies require changing the process chamber once, and flipping the substrate once within each chamber to complete the fabrication of all intrinsic materials and semiconductor doped materials. Therefore, compared to related technologies, this method not only reduces the number of vacuum chamber changes during fabrication but also reduces the number of flips, thus lowering the breakage rate.

[0062] In some embodiments, the thickness of the first functional layer 21 is 10 nm to 100 nm; the thickness of the second functional layer 22 is 10 nm to 100 nm.

[0063] In some embodiments, the first functional layer 21 includes an intrinsic material and an N-type semiconductor doped material, wherein the process gas required to form the intrinsic material includes hydrogen and silane; and the process gas required to form the N-type semiconductor doped material includes phosphine.

[0064] In some embodiments, the second functional layer 22 includes an intrinsic material and a P-type semiconductor doped material, wherein the process gas required to form the intrinsic material includes hydrogen and silane; and the process gas required to form the P-type semiconductor doped material includes borane.

[0065] It should be understood that the heterojunction solar cell can take advantage of the high mobility of the crystalline silicon, which is mainly due to the insertion of the intrinsic material between the semiconductor substrate and the semiconductor doped material. As known from the above, the semiconductor substrate adopts a single crystal silicon material, and the inclusion of the intrinsic material can buffer and passivate the surface of the single crystal silicon wafer (semiconductor substrate), thereby improving the interface characteristics of the semiconductor substrate, and after forming the N-type semiconductor doped material or the P-type semiconductor doped material, the electron mobility and the photoelectric conversion efficiency can be improved.

[0066] In some embodiments, in the process of preparing the first functional layer 21, the gas flow of each process gas required is as follows: the gas flow of hydrogen is 1000-20000sccm, the gas flow of silane is 50-500sccm, and the gas flow of phosphine is 20-300sccm.

[0067] In some embodiments, in the process of preparing the second functional layer 22, the gas flow of each process gas required is as follows: the gas flow of hydrogen is 1000-20000sccm, the gas flow of silane is 50-500sccm, and the gas flow of borane is 20-300sccm.

[0068] In addition, in the process of preparing the first functional layer 21 and the second functional layer 22, the process materials required can also include one or more of carbon dioxide, methane, water vapor, etc.

[0069] In some embodiments, the structure of the first functional layer 21 or the second functional layer 22 includes any one of an amorphous structure, a polycrystalline structure, and a nanocrystalline structure, which is not limited in the embodiments of the present disclosure.

[0070] Specifically, the first semiconductor doped material in the first functional layer 21 is an N-type semiconductor doped material, and the structure of the first functional layer 21 includes any one of N-type amorphous silicon, N-type polycrystalline silicon, or N-type nanocrystalline silicon, and the process materials required to form correspondingly include hydrogen, silane, and phosphine; the second semiconductor doped material in the second functional layer 22 is a P-type semiconductor doped material, and the structure of the second functional layer 22 includes any one of P-type amorphous silicon, P-type polycrystalline silicon, or P-type nanocrystalline silicon, and the process materials required to form correspondingly include hydrogen, silane, and borane.

[0071] In some embodiments, in the process of forming the first functional layer 21 and the second functional layer 22, the temperature in the process chamber is 150-250℃.

[0072] In some embodiments, in the process of forming the first functional layer 21 and the second functional layer 22, the pressure in the process chamber is 0.1-10mbar.

[0073] In some embodiments, the power of the radio frequency power source is 500-5000 W during the formation of the first functional layer 21 and the second functional layer 22.

[0074] The optimization of the environmental parameters and the equipment parameters in the above preparation process improves the stability of the preparation equipment during operation, so that intrinsic material and doped material can be formed in the same process chamber, the number of chamber replacements and the number of wafer flips in the same chamber are reduced, the wafer breakage rate is reduced, and the cross-contamination phenomenon is improved.

[0075] The range values of the temperature, the pressure of the process chamber and the power of the equipment are the optimal range values obtained by the person skilled in the art according to experimental results, and can be adjusted according to actual conditions when the application conditions change. The embodiments of the present disclosure do not limit this.

[0076] In some embodiments, as shown in FIG. 1, the preparation method of the heterojunction solar cell further comprises: Figure 3

[0077] In step S4, a first transparent conductive layer 31 is formed on the side of the first functional layer 21 away from the semiconductor substrate 11.

[0078] In step S5, a second transparent conductive layer 32 is formed on the side of the second functional layer 22 away from the semiconductor substrate 11.

[0079] It should be understood that, in order to ensure the photoelectric conversion effect of the solar cell, the materials of the first transparent conductive layer 31 and the second transparent conductive layer 32 can be indium tin oxide (ITO), aluminum zinc oxide, etc.

[0080] Specifically, the required process materials for forming the first transparent conductive layer 31 and the second transparent conductive layer 32 include one or more of the following: oxygen, argon, water vapor, tin-doped indium oxide, tungsten-doped indium oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, silicon dioxide, silicon nitride, etc.

[0081] In some embodiments, the formation process of the first transparent conductive layer 31 and the second transparent conductive layer 32 is any one of the following: vapor deposition, magnetron sputtering, and pulsed laser deposition.

[0082] ​In one example, the forming process of the first transparent conductive layer 31 adopts a magnetron sputtering method, and the process gas includes oxygen, argon, tin-doped indium oxide, and the gas flow of oxygen is 5-50 sccm, the gas flow of argon is 500-2000 sccm, and the mass ratio of tin to indium in the tin-doped indium oxide is 0.01-0.1.

[0083] In the same example as the above example, the temperature in the process chamber for forming the first transparent conductive layer 31 is 100-300°C, the pressure is 0.1-5 Pa, and the power of the radio frequency power source is 3000-10000 W, all of which can be flexibly set by those skilled in the art according to actual conditions, and the present disclosure does not limit them.

[0084] Further, the second transparent conductive layer 32 is prepared in the same way as the first transparent conductive layer 31, which is not described here.

[0085] In some embodiments, the thickness of the first transparent conductive layer 31 and the second transparent conductive layer 32 is 50-150 nm, for example, the thickness of the first transparent conductive layer 31 / second transparent conductive layer 32 is 50 nm, 100 nm or 150 nm.

[0086] It should be noted that the first transparent conductive layer 31 and the second transparent conductive layer 32 are arranged on the two sides of the semiconductor substrate 11, and thus the order of their preparation is not limited. The first transparent conductive layer 31 can be prepared first and then the second transparent conductive layer 32, or the second transparent conductive layer 32 can be prepared first and then the first transparent conductive layer 31.

[0087] Further, the first transparent conductive layer 31 and the second transparent conductive layer 32 are prepared in the same process chamber in step S3, and are different from the process chamber for forming the first functional layer 21 and the second functional layer 22 in step S2.

[0088] In some embodiments, as shown in Figure 3 The preparation method of the solar cell further includes:

[0089] In step S5, at least one first electrode 41 is formed on the side of the first transparent conductive layer 31 away from the semiconductor substrate 11, and at least one second electrode 42 is formed on the side of the second transparent conductive layer 32 away from the semiconductor substrate 11.

[0090] In some embodiments, the materials of the first electrode 41 and the second electrode 42 are both metal materials, and specifically, the required process materials for forming the two include one or more of silver, copper and aluminum.

[0091] In some embodiments, the forming process of the first electrode 41 and the second electrode 42 is any one of a screen printing method, a vacuum evaporation plating method, and an electroplating method.

[0092] As shown in FIG. 1, the number of the first electrodes 41 can be two, the number of the second electrodes 42 is the same as that of the first electrodes 41, and the projection of each second electrode 42 and the corresponding first electrode 41 on the plane of the semiconductor substrate 11 respectively overlaps. Figure 2

[0093] In one example, the first electrode 41 is a protruding block electrode formed on the first transparent conductive layer 31, the protruding height of the first electrode 41 is 5 μm to 50 μm, the orthographic projection of the first electrode 41 on the first transparent conductive layer 31 can be a rectangle, and the length of any side of the rectangle is 5 μm to 50 μm; of course, the surface of the first electrode 41 away from the first transparent conductive layer 31 can also be arc-shaped, and the specific shape of the first electrode 41 is not limited in the embodiments of the present disclosure.

[0094] In one example, the forming process of the first electrode 41 is a screen printing method, the material includes silver, the protruding height of the first electrode 41 is 5 μm to 30 μm, for example, 10 μm or 20 μm, the orthographic projection of the first electrode 41 on the first transparent conductive layer 31 is a rectangle, and the length of any side of the rectangle is 5 μm to 30 μm, for example, 10 μm or 20 μm.

[0095] The second electrode 42 has the same preparation process and structure shape as the first electrode 41, and details are not repeated here.

[0096] The preparation method of the solar cell provided in the embodiments of the present disclosure forms the intrinsic material and the semiconductor doping material in the same film layer, that is, the intrinsic material and the semiconductor doping material are formed in the same vacuum chamber. Compared with the preparation method in the related art, the embodiments of the present disclosure can reduce the number of replacements between different process chambers in the preparation process, improve the cross-contamination phenomenon, and reduce the exposure time of the intermediate product in the air, further reducing pollution; omit the preparation of the transition layer, reduce the film layer thickness, and simplify the process steps of the solar cell, reduce the consumption of process gas and resources, shorten the process time, and be conducive to energy saving and cost reduction.

[0097] ​Meanwhile, the first functional layer and the second functional layer are formed on opposite sides of the semiconductor substrate, and each of the functional layers comprises a semiconductor-doped material and an intrinsic material, that is, after the intrinsic material is prepared, the N-type semiconductor-doped material can be continuously prepared thereon, and then the intrinsic material and the P-type semiconductor-doped material are formed after being flipped. In the related art, the first intrinsic material film and the transition material film are prepared, then the second intrinsic material film and the transition material film are prepared after being flipped, then the vacuum chamber is replaced, the first semiconductor-doped material film is prepared, and the second semiconductor-doped material film is prepared after being flipped. That is, the preparation of the intrinsic material and the semiconductor-doped material on both sides of the semiconductor substrate can be completed by flipping once in the same process chamber in the present solution, while in the related art, the vacuum chamber needs to be replaced once, and the intrinsic material and the semiconductor-doped material need to be flipped once in each chamber to complete the preparation of all the intrinsic material and the semiconductor-doped material. Therefore, compared with the related art, the present solution not only reduces the replacement frequency of the vacuum chamber in the preparation process, but also reduces the flipping frequency in the preparation process and reduces the chip breakage rate. Therefore, the film quality, the preparation efficiency and the product yield can be improved.

[0098] Based on the same or similar inventive concept, the present disclosure also provides a solar cell prepared by the preparation method provided in any of the above embodiments.

[0099] Specifically, as shown in the figure, Figure 2 The solar cell comprises a semiconductor substrate 11, a first functional layer 21, a second functional layer 22, a first transparent conductive layer 31, a second transparent conductive layer 32, at least one first electrode 41 and at least one second electrode 42.

[0100] The first functional layer 21 and the second functional layer 22 are respectively located on both sides of the semiconductor substrate 11, and each of the first functional layer 21 and the second functional layer 22 comprises an intrinsic material and a semiconductor-doped material. The first functional layer 21 comprises one of a P-type semiconductor-doped material and an N-type semiconductor-doped material, and the second functional layer 22 comprises the other of the P-type semiconductor-doped material and the N-type semiconductor-doped material.

[0101] The first transparent conductive layer 31 is located on the side of the first functional layer 21 away from the semiconductor substrate 11, and the second transparent conductive layer 32 is located on the side of the second functional layer 22 away from the semiconductor substrate 11. The first electrode 41 is located on the first transparent conductive layer 31, and the second electrode 42 is located on the second transparent conductive layer 32. The specific materials and preparation methods of each film layer structure are described in the preparation method embodiments, and are not repeated here.

[0102] In the present disclosure, the solar cell can be a heterojunction cell.

[0103] The above merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and those skilled in the art should understand that the present disclosure includes but is not limited to the contents described in the above specific embodiments and the drawings. Any modification not deviating from the functional and structural principles of the present disclosure will be included in the scope of the claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: Provide semiconductor substrates; A first functional layer is formed on a first side of the semiconductor substrate, wherein the material of the first functional layer includes a semiconductor doping material and an intrinsic material; A second functional layer is formed on a second side of the semiconductor substrate. The material of the first functional layer includes a semiconductor doping material and an intrinsic material. The second side is opposite to the first side. At least one of the first functional layer and the second functional layer includes an amorphous substrate and a unit cell dispersed in the amorphous substrate. The material of the amorphous substrate includes the intrinsic material, and the material of the unit cell includes the semiconductor doping material.

2. The preparation method according to claim 1, characterized in that, Forming a first functional layer on a first side of the semiconductor substrate includes: in the same process chamber, based on plasma-enhanced chemical vapor deposition, sequentially introducing process gas required for forming the intrinsic material, process gas required for forming one of N-type semiconductor doped material and P-type semiconductor doped material, to form the first functional layer; Forming a second functional layer on the second side of the semiconductor substrate includes: in the same process chamber, sequentially introducing a process gas required for forming the intrinsic material and a process gas required for forming another of the N-type semiconductor doped material and the P-type semiconductor doped material based on plasma-enhanced chemical vapor deposition to form the second functional layer.

3. The preparation method according to claim 2, characterized in that, The first functional layer includes the intrinsic material and the N-type semiconductor doped material. The process gas required to form the intrinsic material includes hydrogen and silane; the process gas required to form the N-type semiconductor doped material includes phosphine.

4. The preparation method according to claim 3, characterized in that, The temperature in the process chamber is 150℃~250℃; the pressure in the process chamber is 0.1mbar~10mbar; the gas flow rate of hydrogen is 1000sccm~20000sccm, the gas flow rate of silane is 50sccm~500sccm, and the gas flow rate of phosphine is 20sccm~300sccm.

5. The preparation method according to claim 2, characterized in that, The second functional layer includes the intrinsic material and the P-type semiconductor doped material, and the process gases required to form the intrinsic material include hydrogen and silane; The process gas required to form the P-type semiconductor doped material includes borane.

6. The preparation method according to claim 5, characterized in that, The temperature in the process chamber is 150℃~250℃; the pressure in the process chamber is 0.1mbar~10mbar; the gas flow rate of hydrogen is 1000sccm~20000sccm, the gas flow rate of silane is 50sccm~500sccm, and the gas flow rate of borane is 20sccm~300sccm.

7. The preparation method according to any one of claims 1 to 6, characterized in that, The thickness of the first functional layer is 10nm to 30nm, and / or the thickness of the second functional layer is 10nm to 30nm.

8. The preparation method according to any one of claims 1 to 6, characterized in that, The preparation method further includes: A first transparent conductive layer is formed on the side of the first functional layer away from the semiconductor substrate; A second transparent conductive layer is formed on the side of the second functional layer away from the semiconductor substrate.

9. The preparation method according to claim 8, characterized in that, The preparation method further includes: At least one first electrode is formed on the side of the first transparent conductive layer away from the semiconductor substrate; At least one second electrode is formed on the side of the second transparent conductive layer away from the semiconductor substrate.

10. A solar cell, characterized in that, The solar cell is formed using the preparation method described in any one of claims 1-9.

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