Image forming apparatus

Abstract

[Problem] To provide an imaging device with low current consumption. [Solution] An imaging device according to an embodiment of the present invention comprises: a pixel unit including a plurality of pixels that photoelectrically convert incident light to generate a pixel signal; a first signal line that transmits a pixel signal from the pixel portion; a second signal line that transmits a control signal for causing a current to flow through the first signal line; a capacitance element connected between the first signal line and the second signal line; a first switching element connected between the second signal line and the first power supply; and a second switching element and a current source connected in series between the second signal line and the second power supply.

Description

Technical Field

[0001] This disclosure relates to an imaging device. Background Technology

[0002] Imaging devices, such as complementary metal-oxide-semiconductor (CMOS) image sensors, include pixel regions and peripheral circuitry. In the imaging region, multiple pixels, including photodiodes and pixel circuitry, are arranged, and pixel signals, converted from photoelectric signals in the photodiodes, are output. The peripheral circuitry includes CMOS transistors and processes the pixel signals output from the imaging region.

[0003] A current source or capacitor is connected to the signal line that transmits the pixel signal, and current flows through the signal line when analog-to-digital (AD) conversion is performed on the pixel signal.

[0004] Citation List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 4967489

[0007] Patent Document 2: WO 2022 / 200348 A Summary of the Invention

[0008] The problem the invention aims to solve

[0009] In traditional imaging devices, charging / discharging and stabilizing the signal lines requires relatively large currents. The goal is to minimize this current consumption.

[0010] Therefore, this disclosure provides an imaging device with low current consumption.

[0011] Solution to the problem

[0012] An imaging apparatus according to one aspect of this disclosure includes: a pixel unit comprising a plurality of pixels that perform photoelectric conversion on incident light to generate a pixel signal; a first signal line transmitting the pixel signal from the pixel unit; a second signal line transmitting a control signal for causing current to flow through the first signal line; a capacitor element connected between the first signal line and the second signal line; a first switching element connected between the second signal line and a first power source; and a second switching element and a current source connected in series between the second signal line and the second power source.

[0013] The imaging device also includes a third switching element connected between the second signal line and the second power supply.

[0014] Multiple first signal lines are provided, and the capacitor element, the first switching element, the second switching element, and the current source are provided in each first signal line.

[0015] The plurality of pixels constitute a plurality of pixel columns, the plurality of first signal lines are respectively configured corresponding to the plurality of pixel columns, and a second signal line is configured together for the plurality of pixel columns.

[0016] A second signal line is set up for all of the multiple first signal lines.

[0017] When the second switching element is in the on state, the current source causes current to flow through the capacitor element so that the voltage of the control signal changes with a first slope.

[0018] After setting the voltage of the first signal line to a voltage corresponding to the pixel signal, the current source changes the voltage of the control signal with a first slope.

[0019] When the first switching element is in the on state, the first power supply charges the second signal line and the capacitor element.

[0020] When one of the first switching element and the second switching element is in the on state, the other of the first switching element and the second switching element is in the off state.

[0021] The third switching element is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0022] When a pixel signal generated in a pixel in a reset state is output to the first signal line, a first gate voltage is applied to the gate of the third switching element. When a pixel signal generated in a pixel in a state of receiving incident light is output to the first signal line, a second gate voltage is applied to the gate of the third switching element, and the first gate voltage is higher than the second gate voltage.

[0023] The plurality of pixels are connected between a third power supply and a fourth power supply, wherein the voltage of the third power supply is lower than the voltage of the first power supply, and the voltage of the fourth power supply is lower than the voltage of the second power supply.

[0024] The voltage difference between the third and fourth power sources is approximately equal to the voltage difference between the first and second power sources.

[0025] The imaging apparatus further includes: a reference signal generator that generates a reference signal that varies with a second slope; a comparator that compares a pixel signal from a first signal line with the reference signal; and a counter connected to the output of the comparator and counting from the beginning of the variation of the reference signal until the pixel signal and the reference signal cross, wherein the reference signal generator changes the voltage of the reference signal with a second slope in a direction opposite to the voltage variation of the pixel signal relative to the incident light intensity variation.

[0026] When the voltage of the pixel signal decreases as the intensity of the incident light increases, the reference signal generator changes the voltage of the reference signal from a voltage lower than the voltage of the pixel signal to a voltage higher than the voltage of the pixel signal with a second slope.

[0027] The imaging device also includes a fourth switching element connected between the first signal line and the second signal line.

[0028] The fourth switching element is turned on just before the third switching element is about to turn on.

[0029] The imaging device further includes: a second capacitor element, one end of which is connected to the first node and the other end of which is connected to the second power supply; a fifth switching element, which is connected between the first node and the current source; a sixth switching element, which is connected between the first node and the first signal line; and a seventh switching element, which is connected between the first node and the second signal line.

[0030] In the pre-charge operation prior to the detection of the pixel signal, at least one of the fifth to seventh switching elements is turned on. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus including an imaging element and a signal processing unit according to a first embodiment.

[0032] Figure 2 This is a diagram showing an example of the configuration of a certain column of imaging elements.

[0033] Figure 3 This is a diagram illustrating an example of the configuration of a ramp generator according to the first embodiment.

[0034] Figure 4 This is a timing diagram illustrating an operational example of the pixel and ramp generator according to the first embodiment.

[0035] Figure 5A This is a diagram showing an example of the configuration of the switching element SW3 according to the second embodiment.

[0036] Figure 5B This is a timing diagram illustrating an operational example of the pixel and ramp generator according to the second embodiment.

[0037] Figure 6 This is a diagram illustrating an example of the configuration of a pixel, a ramp generator, a sampling and holding circuit, and a buffer circuit according to the third embodiment.

[0038] Figure 7 This is a diagram showing the range of voltage levels at each node of the floating diffuser, data signal line, sample and hold circuit output, and buffer circuit output according to the third embodiment.

[0039] Figure 8 This is a block diagram illustrating an example of the configuration of a pixel, ramp generator, comparator, DAC, and counter according to the fourth embodiment.

[0040] Figure 9 This is a timing diagram illustrating an operational example of the pixel, ramp generator, comparator, DAC, and counter according to the fourth embodiment.

[0041] Figure 10 This is a diagram illustrating an example of the configuration of a ramp generator according to the fifth embodiment.

[0042] Figure 11 This is a timing diagram illustrating an operational example of the pixel and ramp generator according to the fifth embodiment.

[0043] Figure 12 This is a diagram illustrating an example of the configuration of a ramp generator according to the sixth embodiment.

[0044] Figure 13 This is a timing diagram showing an operational example of the ramp generator according to the sixth embodiment.

[0045] Figure 14 The figures show variations of the second to fourth embodiments.

[0046] Figure 15 This is a block diagram illustrating an example of the schematic configuration of a vehicle control system.

[0047] Figure 16 This is an example diagram illustrating the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0048] In the following description, specific embodiments to which this technology applies will be detailed with reference to the accompanying drawings. The drawings are schematic or conceptual, and the scale of the parts, etc., may not necessarily be the same as the actual figures. In the specification and drawings, elements similar to those described above with respect to the previously described drawings are indicated by the same reference numerals, and their detailed descriptions are appropriately omitted.

[0049] (First Implementation Plan)

[0050] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus 90 according to a first embodiment, including an imaging element 10 and a signal processing unit 80. The imaging element 10 includes a pixel array 11, a row decoder 12, a pixel driver 13, a column signal processing unit 14, and a controller 15.

[0051] The pixel array 11 is constructed by arranging multiple pixels 100 in a two-dimensional manner in the row and column directions. Figure 1It shows a pixel of 100.

[0052] Multiple pixels 100 arranged in the column direction of pixel array 11 are connected to the same data signal line VSL and form a pixel column. Multiple pixels 100 included in a pixel column are selected sequentially by selection signal SEL, and pixel signals are output sequentially to data signal line VSL.

[0053] Multiple pixels 100 arranged in the row direction of pixel array 11 are connected to different data signal lines VSL and form a pixel row. Multiple pixels 100 in a pixel row are connected to different data signal lines VSL, and pixel signals are simultaneously output to the corresponding data signal lines VSL.

[0054] The row decoder 12 and pixel driver 13 drive multiple pixels 100 for each pixel row. For example, the row decoder 12 supplies a selection signal to the pixel driver 13 based on an address signal from the controller 15 to select multiple pixels 100 arranged in the row direction. The pixel driver 13 drives transistors 101-103 and 109 of the multiple pixels 100 within a pixel row based on a timing signal from the controller 15 and the selection signal from the row decoder 12. The row decoder 12 and pixel driver 13 can sequentially drive the pixel rows in the pixel column direction, so that the pixel signals of all pixels 100 from the pixel array 11 are output to the data signal line VS without overlap.

[0055] The data signal line VSL, which serves as the first signal line, transmits the output voltage Vout corresponding to the pixel signal of pixel 100 to the column signal processing unit 14. Hereinafter, the output voltage Vout corresponding to the pixel signal is also referred to as the pixel signal Vout.

[0056] The column signal processing unit 14 is configured corresponding to the pixel columns of the pixel 100, that is, for each data signal line VSL. The column signal processing unit 14 includes an analog-to-digital converter (ADC) 20. The ADC 20 performs digital conversion on the pixel signal Vout received from the data signal line VSL to output to the signal processing unit 80. The ADC 20 includes a comparator 23, a digital-to-analog converter (DAC) 22, and a counter 24. The number of ADCs 20 can be greater than or less than the number of data signal lines VSL. When the number of ADCs 20 is less than the number of data signal lines VSL, the ADCs 20 are shared by multiple data signal lines VSL, and the multiple data signal lines VSL are multiplexed.

[0057] The controller 15 controls the components of the imaging element 10. The controller 15 generates an address and sends it to the line decoder 12, or generates a timing signal and sends it to the pixel driver 13. The controller 15 controls the ADC 20 to perform AD conversion on the pixel signal Vout. Furthermore, the controller 15 also controls the ramp generator 220 to generate the ramp signal Vrmp.

[0058] Pixel 100 includes a photodiode (photoelectric conversion element) PD, a transmission transistor 101, a reset transistor 102, an amplification transistor 103, and a selection transistor 109. The transmission transistor 101, reset transistor 102, amplification transistor 103, and selection transistor 109 include, for example, n-type MOS field-effect transistors (MOSFETs). The transmission transistor 101, reset transistor 102, amplification transistor 103, and selection transistor 109 control the electrical signal output from the photodiode PD and output this electrical signal as a pixel signal to the data signal line VSL.

[0059] A photodiode (PD) performs photoelectric conversion on incident light and generates an electrical signal corresponding to the intensity of the incident light. The amount of charge generated in the photodiode (PD) corresponds to the intensity of the incident light. The incident light can include visible light, infrared light, and / or ultraviolet light.

[0060] A transfer transistor 101 is connected between a photodiode PD and a floating diffuser FD. The transfer transistor 101 transfers charge from the photodiode PD to the floating diffuser FD. The floating diffuser FD temporarily accumulates charge. A transfer signal TG is supplied to the gate of the transfer transistor 101, and the transfer transistor 101 is controlled by the transfer signal TG.

[0061] A reset transistor 102 is connected between the floating diffuser FD and the power supply line supplied with the power supply voltage VDD. A reset signal RES is supplied to the gate of the reset transistor 102. As a result, the reset transistor 102 resets the potential Vfd of the floating diffuser FD to the power supply voltage VDD.

[0062] The floating diffuser FD is connected to the gate of the amplifying transistor 103. The floating diffuser FD serves as the input node of the amplifying transistor 103. The floating diffuser FD temporarily holds the charge accumulated in the photodiode PD.

[0063] Amplifying transistor 103 and selecting transistor 109 are connected in series between the power supply line VDD and the data signal line VSL. As a result, amplifying transistor 103 is connected to the data signal line VSL via selecting transistor 109.

[0064] The selection signal SEL is supplied to the gate of the selection transistor 109. When the selection transistor 109 is turned on, the amplification transistor 103 amplifies the potential Vfd of the floating diffuser FD and outputs the voltage corresponding to the potential Vfd as the pixel signal Vout to the data signal line VSL. The data signal line VSL transmits the pixel signal Vout from the pixel 100 to the column signal processing unit 14.

[0065] For each pixel row, the gates of the transmission transistor 101, the reset transistor 102, and the select transistor 109 are all connected to the pixel driver 13. Therefore, the pixel driver 13 can simultaneously drive multiple pixels 100 included in a pixel row.

[0066] The data signal line VSL is connected to a constant current circuit 200, which includes a capacitor element 210 and a ramp generator 220. The constant current circuit 200 is configured as a capacitor current source to supply a constant current to the data signal line VSL, at least temporarily. The configuration of the capacitor element 210 and the constant current circuit 200 will be described in more detail later.

[0067] During the period when the constant current circuit 200 makes a constant current flow through the data signal line VSL, the amplifying transistor 103 transmits the pixel signal Vout corresponding to the potential Vfd of the floating diffuser FD to the data signal line VSL. The ADC 20 converts the received pixel signal Vout into digital pixel data DPXS and outputs it to the signal processing unit 80.

[0068] Figure 2 This is a diagram showing an example configuration of a column of imaging elements 10. Imaging element 10 generates a pixel signal Vout having a voltage corresponding to the intensity of the incident light. During the selection period when the signal SEL is activated to a high level, pixel 100 outputs the pixel signal Vout to the data signal line VSL.

[0069] Capacitor 210 is connected between the data signal line VSL and the ramp generator 220. For example, one first electrode of capacitor 210 is connected to the data signal line VSL and the ramp generator 220. The other second electrode of capacitor 210 is connected to the ramp generator 220. Note that the ramp generator 220 and capacitor 210 can be directly connected. Alternatively, a component or circuit that allows signal transmission, such as a FET, switch, and / or resistor, can be inserted between the ramp generator 220 and capacitor 210.

[0070] During the reset operation prior to the selection period, capacitor element 210 is charged by the power supply voltage VDD. During the selection period, capacitor element 210 receives a ramp signal Vrmp from ramp generator 220 and causes a constant current to flow through data signal line VSL according to the voltage change of ramp signal Vrmp. As a result, amplifying transistor 103 acts as a source follower and outputs a pixel signal Vout having a voltage corresponding to the potential Vfd of floating diffuser FD to data signal line VSL.

[0071] The ramp generator 220 generates a ramp signal Vrmp as a control signal based on the signal received from the controller 15 during the selection period, and outputs the ramp signal Vrmp to the second electrode of the capacitor element 210.

[0072] The ramp generator 220 linearly changes the voltage of the ramp signal Vrmp with a first ramp. As a result, the ramp signal Vrmp, which changes linearly with the first ramp, is input to the second electrode of the capacitor element 210, and a constant current flows from the first electrode of the capacitor element 210 to the data signal line VSL. As a result, the amplifying transistor 103 acts as a source follower and generates a pixel signal Vout in the data signal line VSL with a voltage corresponding to the potential Vfd of the floating diffuser FD.

[0073] Figure 3 This is a diagram illustrating an example configuration of a ramp generator 220 according to a first embodiment. The ramp generator 220 includes a ramp signal line Lrmp, switching elements SW1 to SW3, and a current source CSrmp.

[0074] The ramp signal line Lrmp, acting as the second signal line, transmits current through the ramp signal Vrmp of the data signal line VSL. The ramp signal line Lrmp can be set for each pixel column corresponding to a specific data signal line in the VSL. However, a single ramp signal line Lrmp can be shared for multiple data signal lines VSL (i.e., for multiple pixel columns). By sharing a single ramp signal line Lrmp among multiple data signal lines VSL, the constant current Irmp in multiple pixel columns is averaged, and variations and noise can be suppressed. By suppressing variations and noise in the constant current Irmp, variations and noise in the ramp signal Vrmp and the pixel signal Vout can be suppressed.

[0075] Switching element SW1, acting as the first switching element, is connected between the power supply voltage VDD and the ramp signal line Lrmp. Switching element SW1 is controlled by the inverted signal rmpenb of the signal rmpen to be either on (conducting state) or off (non-conducting state). Switching element SW2, acting as the second switching element, is connected between the current source CSrmp and the ramp signal line Lrmp. Switching element SW2 is controlled by the signal rmpen to be either on (conducting state) or off (non-conducting state).

[0076] Switching elements SW1 and SW2 are controlled by signals rmpenb and rmpen, which are logically opposite to each other. Therefore, when one of the switching elements SW1 and SW2 is on, the other is off. Switching elements SW1 and SW2 can be MOSFETs. Switching elements SW1 and SW2 include, for example, n-type MOSFETs.

[0077] Switching element SW3 is connected between the data signal line VSL (the first electrode of capacitor element 210) and ground GND. Switching element SW3 is controlled to be turned on or off by signal prch. When switching element SW3 is turned on, the data signal line VSL (the first electrode of capacitor element 210) is pre-charged to the reference voltage (ground voltage) of ground GND.

[0078] A current source CSrmp is connected between the switching element SW2 and ground GND. That is, the switching element SW2 and the current source CSrmp are connected in series between the ramp signal line Lrmp and ground GND. When the switching element SW2 is turned on, the current source CSrmp causes a constant current Irmp to flow from the ramp signal line Lrmp and the second electrode of the capacitor element 210. As a result, the current source CSrmp linearly changes the voltage of the ramp signal Vrmp with a first slope and temporarily causes a constant current to flow through the data signal line VSL via the capacitor element 210. By causing a constant current to flow through the data signal line VSL, the pixel signal Vout is set to the voltage of the pixel 100 in the reset state (hereinafter also referred to as the reset signal) or the voltage corresponding to the potential Vfd of the floating diffuser FD (hereinafter also referred to as the data signal). As described above, the operation of setting the pixel signal Vout of the data signal line VSL to the voltage of the reset signal or the data signal is also referred to as "settling". The current source CSrmp includes, for example, an n-type MOSFET.

[0079] Capacitor element 210, switching elements SW1 and SW2, and current source CSrmp are configured corresponding to each data signal line VSL of multiple pixel columns. Therefore, in each pixel column, the pixel signal Vout can be set as a reset signal or a data signal.

[0080] The switching elements SW1~SW3 and the current source CSrmp are controlled by signals rmpenb, rmpen and prch received from controller 15.

[0081] Next, the operation of pixel 100 and ramp generator 220 according to this embodiment will be explained.

[0082] Figure 4 This is a timing diagram illustrating an operational example of pixel 100 and ramp generator 220 according to the first embodiment.

[0083] First, before time point t1, select transistor 109 is turned off, and pixel 100 is electrically disconnected from data signal line VSL.

[0084] At time t1, controller 15 activates signal RST to turn on reset transistor 102 and activates signal prch to turn on switching element SW3. As a result, reset transistor 102 charges floating diffuser FD with power supply voltage VDD. Furthermore, switching element SW3 precharges the voltage of data signal line VSL (first electrode of capacitor element 210) to a reference voltage (e.g., ground voltage). As a result, during t1 to t2, pixel signal Vout is precharged from the high-level power supply voltage VDD to the reference voltage.

[0085] At this time, the signal rmpenb is activated to a high level, and switching element SW1 is turned on. On the other hand, the signal rmpen is deactivated to a low level, and switching element SW2 is turned off. Therefore, the ramp signal line Lrmp (the second electrode of capacitor element 210) is pre-charged with the power supply voltage VDD. The ramp signal Vrmp is set to, for example, a high level power supply voltage VDD. As a result, capacitor element 210 is pre-charged between a reference voltage (e.g., ground voltage) and the power supply voltage VDD.

[0086] At time t2, controller 15 invalidates signals RST and prch, and turns off reset transistor 102 and switching element SW3. As a result, the floating diffuser FD is electrically isolated from the power supply voltage VDD. Furthermore, the data signal line VSL (the first electrode of capacitor element 210) is electrically isolated from the reference voltage source (e.g., ground), and pre-charging ends.

[0087] Controller 15 activates signal SEL to turn on selection transistor 109. At this time, signal TG remains in a low-level inactive state, and transmission transistor 101 is turned off. Therefore, the potential Vfd of floating diffuser FD remains at a high-level voltage (VDD) and is in a reset state. As a result, during t2~t3, pixel 100 outputs a pixel signal (reset signal) in the reset state (dark state) to data signal line VSL.

[0088] For example, at t2, the pixel signal Vout is precharged to a reference voltage (e.g., ground voltage) and approaches a reset signal (e.g., high-level voltage) during t2~t3.

[0089] At t3, controller 15 activates signal rmpen to a high level to turn on switching element SW2 and turn off switching element SW1. As a result, current source CSrmp causes a constant current Irmp to flow from capacitor element 210 and ramp signal line Lrmp, extracting the pre-charged charge from capacitor element 210 and ramp signal line Lrmp. Consequently, ramp signal Vrmp changes linearly with a first slope.

[0090] During t3 to t4, the ramp signal Vrmp decreases linearly, causing a constant current to flow through the data signal line VSL. As a result, the pixel signal Vout is set (stabilized) to the voltage level of the reset signal.

[0091] although Figure 4 Not shown in the image, but Figure 1 The ADC 20 performs AD conversion on the pixel signal Vout during the period from when the pixel signal Vout stabilizes to the voltage level of the reset signal. For example, after stabilization, the DAC 22 starts operating the AD ramp signal RMPad. The comparator 23 compares the AD ramp signal RMPad received from the DAC 22 with the pixel signal Vout and inverts the logic of the output signal when the AD ramp signal RMPad crosses the pixel signal Vout. The counter 24 counts the clock pulses from the start of the AD ramp signal RMPad operation to the inversion of the output signal of the comparator 23. As a result, the ADC 20 can perform AD conversion on the voltage level of the reset signal that will be output to the signal processing unit 80 as digital pixel data DPXS.

[0092] After the AD conversion of the reset signal, at t4, controller 15 deactivates signal rmpen to a low level to turn off switching element SW2 and turn on switching element SW1. As a result, ramp signal line Lrmp is connected to the power supply line of power supply voltage VDD and electrically isolated from current source CSrmp. Ramp signal line Lrmp and capacitor element 210 are recharged at a high level power supply voltage VDD.

[0093] In t5~t8, the operation of selecting transistor 109 and switching elements SW1~SW3 can be the same as the operation in t1~t4.

[0094] On the other hand, at t5, controller 15 activates signal TG to turn on transmission transistor 101. As a result, transmission transistor 101 transfers the charge generated in photodiode PD to floating diffuser FD. Potential Vfd is at a voltage level corresponding to the intensity of incident light. Note that reset transistor 102 remains in the non-conducting state.

[0095] The signal SEL is in a low-level inactive state, and the selection transistor 109 is in a non-conducting state. Therefore, the pixel signal Vout from pixel 100 has not yet been transmitted to the data signal line VSL.

[0096] Other operations in t5~t6 can be the same as those in t1~t2.

[0097] At t6, controller 15 activates signal SEL to turn on selection transistor 109. At this time, the potential Vfd of floating diffuser FD is at a voltage level corresponding to the intensity of incident light. As a result, from t6 to t8, pixel 100 outputs a pixel signal (data signal) corresponding to the intensity of incident light to data signal line VSL. For example, when the intensity of incident light is low, pixel signal Vout rises to a relatively high voltage level, as shown in Slow. On the other hand, when the intensity of incident light is high, pixel signal Vout only rises to a relatively constant voltage level, as shown in Shigh.

[0098] During t7 to t8, the ramp signal Vrmp decreases linearly, causing a constant current to flow through the data signal line VSL. As a result, the pixel signal Vout is stabilized to the voltage level of the data signal.

[0099] The ADC 20 performs AD conversion on the voltage level of the data signal that will be output to the signal processing unit 80 as digital pixel data DPXS.

[0100] Other operations in t6~t8 can be the same as those in t2~t4.

[0101] The signal processing unit 80 can calculate the digital value corresponding to the intensity of the incident light by subtracting the reset signal detected in t3 to t4 from the data signal detected in t7 to t8 using the correlated double sampling (CDS) method.

[0102] As described above, according to this embodiment, the ramp generator 220 supplies a ramp signal Vrmp to the capacitor element 210 connected to the data signal line VSL, thereby allowing a constant current to flow from the capacitor element 210 to the data signal line VSL for a certain period of time. As a result, current consumption can be reduced compared to the case where the current source is directly connected to the data signal line VSL.

[0103] Note that in Figure 2In the source follower circuit shown, the pixel signal Vout returns from a low potential to a high potential when stable, which is faster than the pixel signal Vout returns from a high potential to a low potential. Therefore, as Figure 4 As shown in t2~t4 or t6~t8, by returning the pixel signal Vout from a low potential to a high potential during stabilization, the amount of current flowing through the data signal line VSL can be reduced. Therefore, it can be said that the stabilization operation shown in t2~t4 or t6~t8 is suitable for a method in which a constant current flows through the data signal line VSL via the capacitor element 210 and the ramp generator 220, as in this embodiment.

[0104] Furthermore, according to this embodiment, during the period when the capacitor element 210 generates the ramp signal Vrmp, the current source CSrmp causes a constant current Irmp to flow from the capacitor element 210 and the ramp generator 220. In this case, almost all the constant current Irmp flowing through the current source CSrmp is used to discharge (or charge) the capacitor element 210. Therefore, unnecessary current consumption is reduced and power efficiency is improved.

[0105] Furthermore, according to this embodiment, a ramp signal line Lrmp is shared by multiple ramp generators 220 or multiple data signal lines VSL corresponding to multiple pixel columns. As a result, the constant current Irmp in multiple pixel columns is averaged, thereby suppressing the variation and noise of the constant current Irmp. By suppressing the variation and noise of the constant current Irmp, the variation and noise of the pixel signal Vout of the data signal lines VSL in multiple pixel columns can also be suppressed.

[0106] (Second Implementation Plan)

[0107] Figure 5A This is a diagram showing an example of the configuration of the switching element SW3 according to the second embodiment. Figure 5B This is a timing diagram illustrating an operational example of pixel 100 and ramp generator 220 according to the second embodiment. The configuration of ramp generator 220 according to the second embodiment can be compared with... Figure 3 The configuration shown is the same. However, the second embodiment differs from the first embodiment in that the switching element SW3 includes, as shown in the first embodiment. Figure 5A The p-type MOSFET is shown. Other configurations of the second embodiment can be similar to those of the first embodiment.

[0108] In the second embodiment, the operation of the selection transistor 109, reset transistor 102, and transmission transistor 101 of pixel 100 can be the same as that in the first embodiment. Furthermore, the operation of the switching elements SW1 and SW2 of the ramp generator 220 can be the same as that in the first embodiment.

[0109] On the other hand, such as Figure 5B As shown, the operation of the switching element SW3 in the second embodiment differs from that in the first embodiment. Since the switching element SW3 is a p-type MOSFET, it is turned off when the signal prch is at a high level and turned on when the signal prch is at a low level.

[0110] In the second embodiment, during the detection of the reset signal in t1~t2, the signal prch is set to the first gate voltage Va. As a result, the pixel signal Vout of the data signal line VSL is essentially pre-charged to voltage Va + |Vtp|. Note that Vtp is the threshold voltage of the switching element SW3.

[0111] Furthermore, during the detection of data signals at t5~t6, the signal prch is set to a second gate voltage Vb that is lower than the first gate voltage Va. As a result, the pixel signal Vout of the data signal line VSL is essentially pre-charged to voltage Vb + |Vtp|. Since the first gate voltage Va is higher than the second gate voltage Vb, voltage Va + |Vtp| is higher than voltage Vb + |Vtp|. Therefore, the degree of pre-charging at t2 is weaker than the degree of pre-charging at t6.

[0112] During t3 to t4, the pixel signal Vout is stabilized to a high-level voltage for detecting the reset signal. Therefore, the pre-charge voltage Va + |Vtp| for detecting the reset signal at t2 does not need to be reduced to the pre-charge voltage Vb + |Vtp| (e.g., ground voltage) for detecting the data signal at t6. Therefore, when the reset signal is output to the data signal line VSL, the first gate voltage Va is applied as the signal prch to the gate of the switching element SW3.

[0113] On the other hand, during t7 to t8, the pixel signal Vout can be set to various voltage values ​​based on the intensity of the incident light for data signal detection. Therefore, the pre-charge voltage Vb + |Vtp| for data signal detection at t6 needs to be reduced to a voltage lower than the pre-charge voltage Va + |Vtp| for reset signal detection. Therefore, when the data signal is output to the data signal line VSL, a second gate voltage Vb, lower than the first gate voltage Va, is applied as the signal prch to the gate of the switching element SW3. As a result, the imaging device 90 can detect data signals with a wide range of voltage levels.

[0114] During the detection of the reset signal between t2 and t4, the pixel signal Vout returns from the pre-charge voltage Va + |Vtp| (closer to the stable voltage) which is relatively higher than the pre-charge voltage Vb + |Vtp| at the time of data signal detection, to the stable voltage corresponding to the reset signal. Therefore, unnecessary charging and discharging currents are suppressed during the pre-charge of the data signal line VSL. This reduces current consumption. Furthermore, the stabilization period of the pixel signal Vout on the data signal line VSL is shortened. As a result, the frame rate in imaging can be reduced.

[0115] (Third Implementation Plan)

[0116] Figure 6 This is a diagram illustrating an example of the configuration of pixel 100, ramp generator 220, sampling and holding circuit SH, and buffer circuit BF according to the third embodiment. Figure 7 This diagram illustrates the voltage level ranges of each node in the floating diffuser FD, data signal line VSL, the output SHO of the sample and hold circuit SH, and the output BFO of the buffer circuit BF according to the third embodiment. The configuration of the ramp generator 220 in the third embodiment can be the same as that in the first embodiment.

[0117] Pixel 100 is connected between the power line of the high-level voltage VDDL and the power line of the low-level voltage GND_PX, and is powered between the high-level voltage VDDL and the low-level voltage GND_PX.

[0118] The low-level voltage GND_PX is a voltage lower than the ground voltage GND, which is used as the reference voltage in the ramp generator 220, the sample and hold circuit SH, and the buffer circuit BF.

[0119] In addition, the high-level voltage VDDL is the voltage that is lower than the power supply voltage VDD by the voltage difference between the ground voltage GND and the low-level voltage GND_PX.

[0120] When a constant current source (load transistor) is directly connected to the data signal line VSL to allow a constant current to flow, a voltage Vlm is applied to the load transistor, a voltage Vir is applied to the data signal line VSL, and a gate-source voltage Vgsamp of the amplifying transistor 103 is generated in the constant current path. Therefore, it is difficult to set the power supply voltage VDD low.

[0121] On the other hand, when a constant current Irmp is generated by capacitor element 210 and ramp generator 220, the component of the voltage Vlm applied to the load transistor is eliminated because current flows from capacitor element 210. Furthermore, the current value of the constant current Irmp generated by capacitor element 210 and ramp generator 220 is less than the current value when the current source is directly connected to the data signal line VSL to allow current flow. Because the constant current Irmp is smaller, the voltage Vir applied to the data signal line VSL and the gate-source voltage Vgsamp of the amplifying transistor 103 are also smaller. Therefore, when a constant current Irmp is generated by capacitor element 210 and ramp generator 220, the power supply voltage VDD can be reduced compared to the case where the current source is directly connected to the data signal line VSL to generate a constant current.

[0122] However, for example, when the power supply voltage VDD simply drops to a high-level voltage VDDL, the power supply voltage applied to pixel 100 also becomes a high-level voltage VDDL, and the voltage difference applied to the photodiode PD decreases. For example, when the power supply voltage VDD simply drops to a high-level voltage VDDL, the voltage difference applied to the floating diffuser FD becomes VDDL - GND, and becomes less than VDD - GND, as... Figure 7 As shown in the figure. In this case, the saturation charge of the photodiode PD decreases.

[0123] Therefore, in pixel 100, such as Figure 7 As shown, the power supply voltage VDD drops to a high-level voltage VDDL, and the reference voltage (e.g., ground voltage) shifts to the negative side by a voltage difference VDD - VDDL. That is, the reference voltage of the photodiode PD is set to a low-level voltage GND_PX, for example, which is lower than the ground voltage GND by (VDD - VDDL). In this case, the low-level voltage GND_PX becomes GND - (VDD - VDDL). The voltage difference between the ground voltage GND and the low-level voltage GND_PX is approximately equal to the voltage difference between the power supply voltage VDD and the high-level voltage VDDL. That is, the voltage difference (VDDL - GND_PX) between the high-level voltage VDDL of pixel 100 and the reference voltage GND_PX is equal to the voltage difference (VDD - GND) between the power supply voltage VDD and the reference voltage GND. As a result, the saturation charge of the photodiode PD can be maintained. Furthermore, design changes to the photodiode PD and transistors 101-103 and 109 constituting pixel 100 become unnecessary.

[0124] As described above, in the third embodiment, the power supply voltages of pixel 100, ramp generator 220, sample and hold circuit SH, and buffer circuit BF are reduced from VDD to a high-level voltage VDDL. Furthermore, the reference voltage of pixel 100 is reduced from GND to a low-level voltage GND_PX, while the reference voltages of ramp generator 220, sample and hold circuit SH, and buffer circuit BF remain at ground voltage GND. As a result, the power supply voltages of pixel 100, ramp generator 220, sample and hold circuit SH, and buffer circuit BF can be reduced to VDDL without changing the design of the individual components of pixel 100.

[0125] (Fourth Implementation Plan)

[0126] Figure 8 This is a block diagram illustrating an example configuration of pixel 100, ramp generator 220, comparator 23, DAC 22, and counter 24 according to a fourth embodiment. The configuration of pixel 100, ramp generator 220, comparator 23, DAC 22, and counter 24 can be the same as that of the first embodiment. Pixel 100, ramp generator 220, comparator 23, DAC 22, and counter 24 are... Figure 1 The controller 15 in the middle is controlled.

[0127] Figure 9 This is a timing diagram illustrating an operational example of pixel 100, ramp generator 220, comparator 23, DAC 22, and counter 24 according to the fourth embodiment.

[0128] According to the fourth embodiment, the DAC 22, which serves as a reference signal generator, linearly changes the AD ramp signal RMPad, which serves as the reference signal, in a direction opposite to the direction of voltage change of the pixel signal Vout, which changes with respect to the incident light intensity, with a second slope. That is, the DAC 22 linearly changes the AD ramp signal RMPad from the pixel signal Shigh side, corresponding to high-intensity incident light, to the pixel signal Slow side, corresponding to low-intensity incident light. In other words, the DAC 22 linearly changes the AD ramp signal RMPad in a direction opposite to the stable direction of the pixel signal Vout.

[0129] Note that the AD ramp signal RMPad is supplied from DAC 22 to comparator 23, compared with the pixel signal Vout in comparator 23, and used as a reference signal for the AD conversion of the pixel signal Vout. Therefore, the AD ramp signal RMPad is a different signal from the ramp signal Vrmp used to generate the constant current Irmp.

[0130] For example, during the detection of the reset signal in t3-1 to t3-2, DAC 22 linearly changes the AD ramp signal RMPad from a voltage lower than the pixel signal Vout to a voltage higher than the pixel signal Vout. Furthermore, during the detection of the data signal in t7-1 to t7-3, DAC 22 linearly changes the AD ramp signal RMPad from a voltage lower than the pixel signals Slow and Shigh to a voltage higher than the pixel signals Slow and Shigh.

[0131] The operation of other signals in the fourth embodiment can be the same as the operation of the corresponding signals in the first embodiment.

[0132] At the ramp start time (t3-1, t7-1), the AD ramp signal RMPAD differs by an offset voltage Vofs between the detection of the reset signal and the detection of the data signal. Therefore, when performing CDS processing on the count value CNTO of counter 24, ADC 20 needs to consider the offset voltage Vofs in the calculation.

[0133] For example, in t3-1~t3-2, counter 24 outputs a count value CNTOrst corresponding to the reset signal. In t7-1~t7-2 or t7-3, counter 24 outputs a count value CNTOd (CNTOhigh or CNTOlow) corresponding to the data signal. In this case, ADC 20 uses the digital value of the pixel signal Vout as Dout and the voltage of the quantized unit (1 lsb) as Vlsb to calculate Equation 1. Dout = Vofs / Vlsb - (CNTOd - CNTOrst) (Equation 1)

[0134] In this way, ADC 20 can perform AD conversion of pixel signal Vout to digital value Dout.

[0135] The reason why the AD ramp signal RMPad changes linearly in the opposite direction to the stable direction of the pixel signal Vout is as follows.

[0136] When using the ramp signal line Lrmp and capacitor element 21 to generate a constant current Irmp, the pixel signal Vout stabilizes from a low voltage to a high voltage after pre-charging. Therefore, the AD ramp signal RMPad changes linearly from a high voltage to a low voltage. The AD ramp signal RMPad crosses quickly with the pixel signal Slow, which has a relatively long stabilization time, and slowly with the pixel signal Shigh, which has a relatively short stabilization time. In this case, the controller 15 needs to delay the start of operation of the AD ramp signal RMPad based on the stabilization time of the pixel signal Slow. This is because if the AD ramp signal RMPad crosses with the pixel signal Slow before the pixel signal Slow stabilizes, a stabilization error will occur, and an accurate count value CNTOlow cannot be obtained.

[0137] On the other hand, similar to the fourth embodiment, when the AD ramp signal RMPAD changes linearly from low voltage to high voltage, the AD ramp signal RMPAD quickly crosses with the pixel signal Shigh, which has a relatively short settling time, and slowly crosses with the pixel signal Slow, which has a relatively long settling time. In this case, the DAC 22 can advance the start of the operation of the AD ramp signal RMPAD based on the settling time of the pixel signal Shigh. Even if the operation of the AD ramp signal RMPAD starts early, the pixel signal Slow has already stabilized when the AD ramp signal RMPAD crosses with the pixel signal Slow. Therefore, the operation of the AD ramp signal RMPAD can start earlier, and the frame rate can be shortened. In addition, the settling time of the pixel signal Slow can be ensured. Therefore, according to the fourth embodiment, accurate count values ​​CNTOhigh and CNTOlow can be obtained.

[0138] Furthermore, since the AD ramp signal RMPad crosses the pixel signal Shigh relatively quickly, a stabilization error may appear in the pixel signal Shigh. However, because the pixel signal Shigh corresponds to high-intensity incident light, the noise is also relatively large. Therefore, the stabilization error is buried in the noise and is not very noticeable.

[0139] As described above, by linearly changing the AD ramp signal RMPAD from low voltage to high voltage, high-quality images can be captured at high frame rates.

[0140] (Fifth Implementation Plan)

[0141] Figure 10 This is a diagram illustrating an example configuration of a ramp generator 220 according to a fifth embodiment. The ramp generator 220 also includes a switching element SW4. Other configurations of the fifth embodiment may be similar to the corresponding configuration of the first embodiment.

[0142] Switching element SW4 is connected between the data signal line VSL (the first electrode of capacitor element 210) and the ramp signal line Lrmp. Switching element SW4 is controlled to be turned on or off by the signal bypass. Switching element SW4 is turned on just before the data signal line VSL is about to be pre-charged (just before switching element SW3 is about to be turned on), and short-circuits the ramp signal line Lrmp and the data signal line VSL. As a result, before pre-charging, the voltage of the ramp signal line Lrmp and the voltage of the data signal line VSL are neutralized, and the data signal line VSL is pre-charged to some extent by the ramp signal line Lrmp. That is, in the fifth embodiment, the pre-charging of the data signal line VSL is performed by pre-charging from inside the ramp signal line Lrmp and pre-charging from outside via switching element SW3. Switching element SW4 includes, for example, an n-type MOSFET. The signal bypass is controlled by controller 15.

[0143] Figure 11 This is a timing diagram showing an operational example of pixel 100 and ramp generator 220 according to the fifth embodiment.

[0144] The fifth embodiment differs from the second embodiment in the pre-charging operation. For example, in the pre-charging operation from t1 to t2, firstly, the activation signal bypass is used to turn on the switching element SW4 (t1 to t1-1). At this time, the data signal line VSL has a voltage corresponding to the pixel signal Vout. The ramp signal line Lrmp has been reduced to near the reference voltage (e.g., ground voltage) in the previous detection of the pixel signal Vout. By short-circuiting the ramp signal line Lrmp and the data signal line VSL through the switching element SW4, the voltages of the ramp signal line Lrmp and the data signal line VSL are neutralized to their intermediate voltage. That is, the data signal line VSL is pre-charged internally by the ramp signal line Lrmp.

[0145] Next, the signal bypass is deactivated to turn off switching element SW4, and then switching element SW3 is turned on to precharge the data signal line VSL to the reference voltage (e.g., ground voltage) (t1-1~t2). The precharging operation in t1-1~t2 can be combined with... Figure 5B The pre-charge operation in t1~t2 is the same.

[0146] Subsequently, the AD conversion operation of the reset signal in t2~t4 can be combined with... Figure 5B The operations in t2~t4 are the same.

[0147] Next, the activation signal bypass is used to turn on switching element SW4 (t5~t5-1). At this time, the data signal line VSL has a voltage corresponding to the reset signal. The ramp signal line Lrmp has been reduced to near the reference voltage (e.g., ground voltage) in the detection of the reset signal. By short-circuiting the ramp signal line Lrmp and the data signal line VSL through switching element SW4, the voltages of the ramp signal line Lrmp and the data signal line VSL are neutralized to their intermediate voltage. That is, the data signal line VSL is pre-charged internally by the ramp signal line Lrmp.

[0148] Next, the signal bypass is deactivated to turn off switching element SW4, and then switching element SW3 is turned on to precharge the data signal line VSL to the reference voltage (e.g., ground voltage) (t5-1~t6). The precharging operation in t5-1~t6 can be combined with... Figure 5B The pre-charging operation is the same in t5~t6.

[0149] Subsequently, the AD conversion operation of the data signals in t6~t8 can be combined with... Figure 5B The operations in t6~t8 are the same.

[0150] The ADC 20 performs AD conversion on the voltage level of the data signal that will be output to the signal processing unit 80 as digital pixel data DPXS.

[0151] Other operations in the fifth implementation scheme can be the same as those in the second implementation scheme.

[0152] Similar to the fifth embodiment, before the pre-charging operation of the data signal line VSL, the switching element SW4 short-circuits the data signal line VSL and the ramp signal line Lrmp, thereby allowing for some internal pre-charging of the data signal line VSL. As a result, the amount of pre-charged charge from the outside (or the amount of charge to be discharged to the outside) can be reduced. This leads to a reduction in the current consumption of the ramp generator 220.

[0153] (Sixth Implementation Plan)

[0154] Figure 12 This is a diagram illustrating an example configuration of the ramp generator 220 according to the sixth embodiment. The ramp generator 220 also includes switching elements SW5-SW7 and a capacitor element 221. Other configurations of the sixth embodiment may be similar to the corresponding configuration of the first embodiment.

[0155] One end of capacitor element 221 is connected to node Ncap, and the other end is connected to a reference voltage source (e.g., ground).

[0156] Switching element SW5 is connected between node Ncap at one end of capacitor element 221 and current source CSrmp. Switching element SW5 is controlled to be turned on or off by signal prch_prep.

[0157] Switching element SW6 is connected between data signal line VSL and node Ncap. Switching element SW6 is controlled to be on or off by signal regen1.

[0158] Switching element SW7 is connected between ramp signal line Lrmp and node Ncap. Switching element SW7 is controlled to be turned on or off by signal regen2. Switching elements SW5~SW7 include, for example, n-type MOSFETs. Signals prch_prep, regen1, and regen2 are controlled by controller 15.

[0159] During the pre-charge operation, capacitor element 221 charges (reduces) the data signal line VSL to a reference voltage via capacitor element 210. Furthermore, during the pixel signal detection operation, capacitor element 221 transmits the rise of the ramp signal line Lrmp to the data signal line VSL via capacitor element 210 to support the voltage rise of the data signal line VSL. That is, capacitor element 221 supports the voltage fluctuations of the data signal line VSL during the pre-charge operation and the pixel signal detection operation by utilizing the capacitive coupling between the ramp signal line Lrmp and the data signal line VSL via capacitor element 210. As a result, the current consumption of the ramp generator 220 can be further reduced.

[0160] Figure 13 This is a timing diagram showing an operational example of the ramp generator 220 according to the sixth embodiment.

[0161] The operation of the sixth embodiment differs from that of the first embodiment in terms of pre-charging. Until just before the drive ramp signal Vrmp (up to t3), switching elements SW6 and SW7 are in the off state, while switching element SW5 is in the on state. As a result, the constant current source CSrmp draws current from one end of capacitor element 221 (node ​​Ncap). Therefore, during t1~t2, the voltage Vcap at node Ncap decreases substantially linearly.

[0162] Here, at t1-1, switching elements SW6 and SW7 are turned on. As a result, node Ncap is connected to the data signal line VSL, and the voltage Vout of the data signal line VSL decreases similarly to the voltage Vcap of node Ncap (pre-charging).

[0163] Next, at t2, while switching elements SW5 and SW7 remain on, switching element SW6 is off. Additionally, switching element SW1 is on. As a result, node Ncap is disconnected from the data signal line VSL and capacitively coupled to the data signal line VSL via capacitor element 210. Node Ncap and ramp signal line Lrmp are charged by the power supply voltage VDD via switching element SW1. Therefore, voltages Vcap and Vrmp increase. The voltage Vout of the data signal line VSL capacitively coupled to node Ncap also increases with the increase of voltages Vout and Vrmp.

[0164] At t3, the pixel signal detection operation begins by turning off switching elements SW5 and SW7 and switching element SW2. That is, the linear change of the ramp signal Vrmp begins. At this time, since node Ncap is separated from the ramp signal line Lrmp, capacitor element 210, and data signal line VSL, node Ncap does not affect the pixel signal detection operation. Therefore, the pixel signal detection operation in t3~t4 is similar to that in the first embodiment.

[0165] At t4, switching element SW2 is turned off, and the AD conversion operation of the reset signal terminates. Simultaneously, by turning on switching elements SW6 and SW7, node Ncap is connected to the data signal line VSL and the ramp signal line Lrmp. As a result, the charge on the data signal line VSL flows to node Ncap and the ramp signal line Lrmp, and capacitor element 221 and the ramp signal line Lrmp are charged. At this time, capacitor element 221 and the ramp signal line Lrmp do not receive charge from external sources, but instead use the charge on the data signal line VSL for internal charging. This leads to a reduction in current consumption.

[0166] Next, at t4-1, switching elements SW6 and SW7 are turned off, and switching element SW5 is turned on. As a result, the current source CSrmp draws charge from node Ncap at one end of capacitor element 221, and the voltage Vcap at node Ncap decreases substantially linearly.

[0167] Here, at t5-1, switching element SW7 is turned on. As a result, node Ncap is connected to the ramp signal line Lrmp and coupled to the data signal line VSL via capacitor element 221. Consequently, during t5-1 to t6, the voltage Vout of the data signal line VSL decreases similarly to the voltage Vcap of node Ncap (pre-charging).

[0168] Next, at t6, while switching elements SW5 and SW7 remain on, switching element SW1 is further turned on. As a result, node Ncap and ramp signal line Lrmp are charged by the supply voltage VDD via switching element SW1. Therefore, voltages Vcap and Vrmp increase. The voltage Vout of the data signal line VSL, which is capacitively coupled to node Ncap, also increases with the increase of voltages Vout and Vrmp.

[0169] At t7, the pixel signal detection operation begins by turning off switching elements SW5 and SW7 and turning on switching element SW2. That is, the linear change of the ramp signal Vrmp begins. At this time, since node Ncaps is separated from the ramp signal line Lrmp, capacitor element 210, and data signal line VSL, node Ncaps does not affect the pixel signal detection operation. Therefore, the AD conversion operation of the data signal in t7~t8 is similar to that in the first embodiment.

[0170] The ADC 20 performs AD conversion on the voltage level of the data signal that will be output to the signal processing unit 80 as digital pixel data DPXS.

[0171] At t8, switching element SW2 is turned off, and the AD conversion operation of the reset signal terminates. Simultaneously, by turning on switching elements SW6 and SW7, node Ncap is connected to the data signal line VSL and the ramp signal line Lrmp. As a result, the charge on the data signal line VSL flows to node Ncap and the ramp signal line Lrmp, and capacitor element 221 and the ramp signal line Lrmp are charged. At this time, capacitor element 221 and the ramp signal line Lrmp do not receive external charge supply, but instead use the charge on the data signal line VSL for internal charging. This leads to a reduction in current consumption.

[0172] At t9, by turning off switching elements SW6 and SW7 and turning on switching element SW5, the constant current source CSRmp draws current from node Ncap at one end of capacitor element 221. Therefore, after t9, the voltage Vcap at node Ncap decreases substantially linearly.

[0173] After that, processing returns to t1, and the pre-charge operation for the next pixel signal begins.

[0174] According to the sixth embodiment, during t4 to t4-1, the data signal line VSL, node Ncap at one end of capacitor element 221, and ramp signal line Lrmp are short-circuited. As a result, the charge on the data signal line VSL after pixel signal detection can be used to internally charge capacitor element 221 and ramp signal line Lrmp. Since the voltage Vrmp of ramp signal line Lrmp can be pre-charged to some extent without using external current, this leads to a reduction in current consumption.

[0175] Furthermore, during t5~t6, the voltage Vcap of node Ncap is reduced substantially linearly by the constant current source CSrmp, and the data signal line VSL is reduced (pre-charged) via capacitive coupling through capacitor element 210. The voltage Vcap of node Ncap can internally pre-charge the voltage Vrmp of the ramp signal line Lrmp, thereby reducing current consumption.

[0176] Furthermore, during t6-t7, node Ncap and ramp signal line Lrmp are charged by the power supply voltage VDD via switching element SW1. The voltage Vout of the data signal line VSL, which is capacitively coupled to node Ncap, also increases with the increase of voltages Vcap and Vrmp. As a result, it is possible to support the voltage Vout of the data signal line VSL to become the voltage according to the pixel signal, while suppressing current consumption. In addition, since the voltage Vout of the data signal line VSL, which is capacitively coupled to node Ncap, increases due to the capacitive coupling with node Ncap, excessive increases in voltage Vout can be suppressed.

[0177] Furthermore, since the voltage Vcap of node Ncap is reduced by the constant current source CSRmp via switching element SW5 during t1~t2, t4-1~t6, and after t9, a constant current flows from capacitor element 221 to the reference voltage source, but a large current does not flow. This also leads to a reduction in current consumption.

[0178] Multiple implementation schemes selected from the first to fourth implementation schemes can be combined.

[0179] (Modified Example)

[0180] Figure 14 This diagram illustrates variations of the second to fourth embodiments. In this variation, instead of capacitor 210 and ramp generator 220, current source LM is directly connected to the data signal line VSL, and a constant current flows through the data signal line VSL. Current source LM is connected between the data signal line VSL and ground GND, which serves as a reference voltage source. The gate voltage of current source LM is controlled by controller 15 and is configured to cause a constant current to flow through current source LM. In this variation, capacitor 210 and ramp generator 220 are not provided. Other configurations of this variation can be the same as those in any of the second to fourth embodiments. As described above, this variation can be applied to any of the second to fourth embodiments.

[0181] (Examples of applications involving moving objects)

[0182] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device to be installed on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0183] Figure 15 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology is applicable according to the embodiments of this disclosure.

[0184] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 15 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0185] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device such as a drive force generating device for generating drive force for a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0186] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used instead of buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0187] The exterior information detection unit 12030 detects information related to the exterior of the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, cars, obstacles, signs, and text on the road, or detecting their distance.

[0188] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0189] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is asleep in a seated position.

[0190] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of advanced driver assistance systems (ADAS), including collision avoidance or collision mitigation, following distance-based driving, vehicle speed maintenance, vehicle collision warning, and vehicle lane departure warning.

[0191] In addition, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, so as to realize autonomous driving, where the vehicle drives itself without relying on the operation of the driver.

[0192] In addition, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the vehicle's external environment obtained by the external information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030 to perform coordinated control, thereby achieving glare prevention such as switching the high beams to low beams.

[0193] The sound / image output unit 12052 transmits at least one of sound and image output signals to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle. Figure 15 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0194] Figure 16 This is a diagram showing an example of the mounting location of the imaging unit 12031.

[0195] exist Figure 16 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0196] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, at the front of vehicle 12100, in the side mirrors, rear bumper, and rear door, as well as on the upper side of the windshield inside the vehicle. Imaging unit 12101 in the front of the vehicle and imaging unit 12105 on the upper side of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 in the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 in the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper side of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc., ahead.

[0197] Incidentally, Figure 16 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104 onto each other, a bird's-eye view of the vehicle 12100 as seen from above is obtained.

[0198] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0199] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111-12114 and the time change of that distance (relative speed relative to vehicle 12100), thereby extracting the three-dimensional object located on the driving path of vehicle 12100, particularly the closest three-dimensional object, that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more), as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-determined distance between vehicles in front of the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. Therefore, coordinated control for autonomous driving, etc., aimed at autonomous vehicle operation without relying on driver operation, is possible.

[0200] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify three-dimensional object data into three-dimensional object data for two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. When the collision risk is equal to or higher than a set value and there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 and display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can assist driving to avoid collisions.

[0201] At least one of the imaging units 12101-12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a quadrilateral outline for emphasis, superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0202] Examples of vehicle control systems applicable to the technology of this disclosure have been described above. The technology of this disclosure is applicable to the imaging unit 12031 in the above configuration.

[0203] Note that this technology can also be configured as follows.

[0204] (1) An imaging device, comprising:

[0205] A pixel unit, comprising multiple pixels that perform photoelectric conversion on incident light to generate a pixel signal;

[0206] The first signal line transmits pixel signals from the pixel unit;

[0207] The second signal line transmits a control signal for causing current to flow through the first signal line;

[0208] A capacitor element is connected between the first signal line and the second signal line;

[0209] A first switching element is connected between a second signal line and a first power supply; and

[0210] A second switching element and a current source are connected in series between the second signal line and the second power supply.

[0211] (2) The imaging device according to (1) further includes a third switching element connected between the second signal line and the second power supply.

[0212] (3) The imaging apparatus according to (1) or (2), wherein,

[0213] There are multiple first signal lines, and

[0214] The capacitor element, the first switching element, the second switching element, and the current source are disposed in each first signal line.

[0215] (4) The imaging apparatus according to (1) or (2), wherein,

[0216] The multiple pixels form multiple pixel columns.

[0217] The plurality of first signal lines are respectively configured corresponding to the plurality of pixel columns, and

[0218] A second signal line is set for all of the multiple pixel columns.

[0219] (5) The imaging apparatus according to (3) or (4), wherein a second signal line is provided for all of the plurality of first signal lines.

[0220] (6) The imaging apparatus according to (1) or (2), wherein when the second switching element is in the on state, the current source causes current to flow through the capacitor element so that the voltage of the control signal changes with a first slope.

[0221] (7) The imaging apparatus according to (6), wherein after the voltage of the first signal line is set to a voltage corresponding to the pixel signal, the current source changes the voltage of the control signal with a first slope.

[0222] (8) The imaging apparatus according to (1) or (2), wherein when the first switching element is in the on state, the first power supply charges the second signal line and the capacitor element.

[0223] (9) The imaging apparatus according to (1) or (2), wherein when one of the first switching element and the second switching element is in a conducting state, the other of the first switching element and the second switching element is in a non-conducting state.

[0224] (10) The imaging device according to (2), wherein the third switching element is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0225] (11) The imaging apparatus according to (10), wherein,

[0226] When the pixel signal generated in the pixel in the reset state is output to the first signal line, the first gate voltage is applied to the gate of the third switching element.

[0227] When the pixel signal generated in the pixel receiving incident light is output to the first signal line, the second gate voltage is applied to the gate of the third switching element, and

[0228] The first gate voltage is higher than the second gate voltage.

[0229] (12) The imaging apparatus according to any one of (1) to (11), wherein the plurality of pixels are connected between a third power supply and a fourth power supply, wherein the voltage of the third power supply is lower than the voltage of the first power supply and the voltage of the fourth power supply is lower than the voltage of the second power supply.

[0230] (13) The imaging apparatus according to (12), wherein the voltage difference between the third power supply and the fourth power supply is approximately equal to the voltage difference between the first power supply and the second power supply.

[0231] (14) The imaging apparatus according to any one of (1) to (13) further comprises:

[0232] A reference signal generator that generates a reference signal that varies with a second slope;

[0233] A comparator that compares the pixel signal from the first signal line with the reference signal; and

[0234] A counter, connected to the output of the comparator, counts from the change in the reference signal until the pixel signal and the reference signal cross, wherein...

[0235] The reference signal generator changes the voltage of the reference signal in a second slope in a direction opposite to the voltage change of the pixel signal relative to the change in incident light intensity.

[0236] (15) According to the imaging apparatus of (14), wherein when the voltage of the pixel signal decreases as the intensity of the incident light increases, the reference signal generator changes the voltage of the reference signal from a voltage lower than the voltage of the pixel signal to a voltage higher than the voltage of the pixel signal with a second slope.

[0237] (16) The imaging apparatus according to (2) further includes a fourth switching element connected between the first signal line and the second signal line.

[0238] (17) The imaging apparatus according to (6), wherein the fourth switching element is in the conducting state before the third switching element is about to be in the conducting state.

[0239] (18) The imaging apparatus according to (1) further includes:

[0240] The second capacitor element has one end connected to the first node and the other end connected to the second power source;

[0241] The fifth switching element is connected between the first node and the current source;

[0242] The sixth switching element is connected between the first node and the first signal line; and

[0243] The seventh switching element is connected between the first node and the second signal line.

[0244] (19) The imaging apparatus according to (18), wherein, during the pre-charging operation prior to the detection of the pixel signal, at least one of the fifth to seventh switching elements is turned on.

[0245] Note that this disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the essential points of this disclosure. Furthermore, the effects described in this specification are merely illustrative and not limiting, and may provide other effects.

[0246] List of reference numerals

[0247] 10 imaging elements

[0248] 11-pixel array

[0249] 12-line decoder

[0250] 13-pixel driver

[0251] 14-column signal processing unit

[0252] 15 controllers

[0253] 80 Signal Processing Unit

[0254] 90 imaging device

[0255] 100 pixels

[0256] 101 Transmission Transistor

[0257] 102 reset transistor

[0258] 103 Amplifying Transistor

[0259] 109 select transistor

[0260] 210 capacitor element

[0261] 220 ramp generator

[0262] Lrmp ramp signal line

[0263] SW1~SW3 switching elements

[0264] CSrmp current source

[0265] VSL data signal line

[0266] PD photodiode

Claims

1. An imaging device, comprising: A pixel unit, comprising multiple pixels that perform photoelectric conversion on incident light to generate a pixel signal; The first signal line transmits pixel signals from the pixel unit; The second signal line transmits a control signal for causing current to flow through the first signal line; A capacitor element is connected between the first signal line and the second signal line; The first switching element is connected between the second signal line and the first power supply; and A second switching element and a current source are connected in series between the second signal line and the second power supply.

2. The imaging apparatus according to claim 1 further includes a third switching element connected between the second signal line and the second power supply.

3. The imaging device according to claim 1, wherein, There are multiple first signal lines, and The capacitor element, the first switching element, the second switching element, and the current source are disposed in each first signal line.

4. The imaging device according to claim 1, wherein, The multiple pixels form multiple pixel columns. The plurality of first signal lines are respectively configured corresponding to the plurality of pixel columns, and A second signal line is set for all of the multiple pixel columns.

5. The imaging device according to claim 3, wherein, A second signal line is set up for all of the multiple first signal lines.

6. The imaging apparatus according to claim 1, wherein, When the second switching element is in the on state, the current source causes current to flow through the capacitor element so that the voltage of the control signal changes with a first slope.

7. The imaging apparatus according to claim 6, wherein, After setting the voltage of the first signal line to a voltage corresponding to the pixel signal, the current source changes the voltage of the control signal with a first slope.

8. The imaging apparatus according to claim 1, wherein, When the first switching element is in the on state, the first power supply charges the second signal line and the capacitor element.

9. The imaging apparatus according to claim 1, wherein, When one of the first switching element and the second switching element is in the on state, the other of the first switching element and the second switching element is in the off state.

10. The imaging apparatus according to claim 2, wherein, The third switching element is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

11. The imaging apparatus according to claim 10, wherein, When the pixel signal generated in the pixel in the reset state is output to the first signal line, the first gate voltage is applied to the gate of the third switching element. When the pixel signal generated in the pixel receiving incident light is output to the first signal line, the second gate voltage is applied to the gate of the third switching element, and The first gate voltage is higher than the second gate voltage.

12. The imaging apparatus according to claim 1, wherein, The plurality of pixels are connected between a third power supply and a fourth power supply, wherein the voltage of the third power supply is lower than the voltage of the first power supply, and the voltage of the fourth power supply is lower than the voltage of the second power supply.

13. The imaging apparatus according to claim 12, wherein, The voltage difference between the third and fourth power sources is approximately equal to the voltage difference between the first and second power sources.

14. The imaging apparatus according to claim 1, further comprising: A reference signal generator that generates a reference signal that varies with a second slope; A comparator that compares the pixel signal from the first signal line with the reference signal; and A counter, connected to the output of the comparator, counts from the change in the reference signal until the pixel signal and the reference signal cross, wherein... The reference signal generator changes the voltage of the reference signal in a second slope in a direction opposite to the voltage change of the pixel signal relative to the change in incident light intensity.

15. The imaging apparatus according to claim 14, wherein, When the voltage of the pixel signal decreases as the intensity of the incident light increases, the reference signal generator changes the voltage of the reference signal from a voltage lower than the voltage of the pixel signal to a voltage higher than the voltage of the pixel signal with a second slope.

16. The imaging apparatus according to claim 2, further comprising a fourth switching element connected between the first signal line and the second signal line.

17. The imaging apparatus according to claim 6, wherein, The fourth switching element is turned on just before the third switching element is about to turn on.

18. The imaging apparatus according to claim 1, further comprising: The second capacitor element has one end connected to the first node and the other end connected to the second power source; The fifth switching element is connected between the first node and the current source; The sixth switching element is connected between the first node and the first signal line; and The seventh switching element is connected between the first node and the second signal line.

19. The imaging apparatus according to claim 18, wherein, In the pre-charge operation prior to the detection of the pixel signal, at least one of the fifth to seventh switching elements is turned on.

Images