Silicon piezoresistive pressure sensitive chip based on SOI laminated top silicon and preparation method thereof

Abstract

The invention discloses a silicon piezoresistive pressure-sensitive chip based on SOI (Silicon On Insulator) laminated top silicon and a preparation method of the silicon piezoresistive pressure-sensitive chip, a monocrystalline silicon anisotropy chemical wet etching process is replaced by an Si-SiO2 laminated thermal bonding and dry etching combined process, lateral corrosion of a pressure-sensitive cavity is avoided, and while the maximum area benefit of the silicon-based pressure-sensitive chip is obtained, the silicon piezoresistive pressure-sensitive chip can be prepared by a single crystal silicon anisotropy chemical wet etching process. The precise thickness and uniformity of the pressure sensing diaphragm are not restricted by the thickness and uniformity initial tolerance of the substrate silicon, and on the premise of optimizing the sensitivity consistency of the sensitive chip and continuing the temperature adaptability advantage of replacing a PN junction by the S < 2 >, the chip area miniaturization and the wafer large diameter superposition are realized; and the output rate of the silicon piezoresistive pressure sensitive chip of a single wafer can be increased by several times and even in order of magnitude.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of MEMS sensor, in particular to a silicon piezoresistive pressure sensitive chip based on SOI stack top silicon and a preparation method thereof. BACKGROUND

[0002] In the MEMS pressure sensor market, silicon piezoresistive pressure sensors are widely used, and the smaller the area of the silicon piezoresistive pressure sensitive chip and the larger the diameter of the chip wafer, the higher the chip yield and the larger the chip packaging area, which is beneficial to the miniaturization and low cost of the sensor.

[0003] The popular silicon piezoresistive pressure sensitive chip is almost of the peripheral fixed support pressure sensing diaphragm structure type. In order to avoid the influence of the process limitations such as surface roughness and thickness uniformity of dry etching of the pressure sensing diaphragm, the pressure sensing diaphragm of the medium and high-end silicon piezoresistive pressure sensitive chip is made by using anisotropic chemical wet etching method.

[0004] The anisotropic chemical wet etching of the single crystal silicon crystal surface has a fixed direction selection ratio, which means that as the thickness of the pressure sensing diaphragm is continuously etched and thinned, the side length of the peripheral fixed support wall of the pressure sensing diaphragm is continuously etched and reduced. That is, when the surface area of the pressure sensing diaphragm is unchanged, the thinner the thickness of the pressure sensing diaphragm, the wider the opening side length of the pressure sensing diaphragm etching mask is needed, and the longer the side length of the sensitive chip is, which inevitably leads to the increase of the surface area of the sensitive chip. This not only limits the miniaturization of the sensitive chip and reduces the chip yield of the wafer, but also restricts the trend of doubling the diameter of the sensitive chip wafer.

[0005] In order to effectively solve the limitations in the background art, we propose a silicon piezoresistive pressure sensitive chip based on SOI stack top silicon and a preparation method thereof. SUMMARY

[0006] The present application aims to provide a silicon piezoresistive pressure sensitive chip based on SOI stack top silicon and a preparation method thereof, which maximizes the surface area efficiency and chip yield of medium and high-end silicon piezoresistive pressure sensitive chip while avoiding the process limitations of dry etching and maintaining the advantages of SOI wafer characteristics.

[0007] The core of the technical solution of the present application is that the thickness of the silicon piezoresistive pressure sensitive chip is accurately uniform, the mirror surface of the pressure sensing diaphragm and the cavity are made by using a full dry micro-machining process instead of the traditional wet etching process with lateral expansion.

[0008] The silicon pressure resistance pressure sensitive chip wafer is prepared by using a double-throw full-silicon optical wafer as the substrate silicon of the SOI laminated top silicon, dry etching a rectangular groove of a fixed pressure sensing diaphragm on the top surface, the sidewall of which is perpendicular to the top surface of the rectangular groove, and dry etching a pressure guide through hole which is connected with the rectangular groove, the center of the through hole is in the center of the rectangular groove, when the conventional substrate silicon of the sensitive chip is airtightly connected with the glass backing sheet, the pressure sensing cavity connected with the rectangular groove and the pressure guide through hole is used as the pressure reference cavity, and when the periphery of the sensitive chip laminated top silicon is airtightly connected with the glass backing sheet, the pressure sensing cavity connected with the rectangular groove and the pressure guide through hole is used as the pressure measurement cavity.

[0009] The top layer silicon of the SOI optical wafer with the same crystal direction and the same type is inverted and bonded with the top surface of the rectangular groove of the full-silicon optical wafer to form a SOI new wafer, the top layer silicon which is fixed on the vertical wall of the rectangular groove has a preset thickness, the thickness of the pressure sensing diaphragm of the sensitive chip is accurately and uniformly fixed, the initial thickness and uniformity tolerance of the substrate silicon of the full-silicon optical wafer are not restricted, and the area of the pressure sensing diaphragm of the top layer silicon is fixed at the same time, the dry method for manufacturing the pressure sensing diaphragm and the cavity avoids the transverse etching of the anisotropic chemical wet etching, the maximum chip surface area benefit and the yield of the sensitive chip with the same diameter wafer can be obtained, the top layer silicon mirror is polished, and the limitation of the roughness of the dry etching is avoided.

[0010] The thickness of the substrate silicon of the bonded full-silicon SOI optical wafer is reduced to submicron, which is negligible compared with the thickness of the pressure sensing diaphragm, the laminated top layer silicon of the SOI new wafer is used to replace the reverse PN junction, the silicon piezoresistive pressure sensitive bridge, the metal electrode and the chip top sealing peripheral sealing frame are manufactured on the laminated top layer silicon by adopting the semiconductor planar and thin film process, the laminated top layer silicon outside the sensitive bridge and the peripheral sealing frame is dry etched, the electrodes of the sensitive bridge and the peripheral sealing frame are mutually insulated and spaced, and the temperature adaptability of the sensitive chip without the PN junction is continued.

[0011] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0012] A more specific technical scheme of the silicon piezoresistive pressure sensitive chip based on the SOI laminated top layer silicon includes:

[0013] The full-silicon optical wafer is provided with a rectangular groove on the top surface of the full-silicon optical wafer for fixing the periphery of the sensitive chip pressure-sensitive diaphragm, the side wall of the rectangular groove is perpendicular to the top surface of the rectangular groove, the length of the rectangular groove is equal to the length of the sensitive chip pressure-sensitive diaphragm, the depth of the rectangular groove is greater than the maximum deflection displacement of the sensitive chip pressure-sensitive diaphragm under the upper limit pressure load of the rated range, but less than the maximum deflection displacement of the sensitive chip pressure-sensitive diaphragm under the upper limit load of the rated overload pressure, and the intersection of the diagonal line of the rectangular groove and the intersection of the diagonal line of the sensitive chip are overlapped, and one pair of the length of the rectangular groove is parallel to the cutting edge of the wafer reference surface, and the other pair of the length of the rectangular groove is perpendicular to the cutting edge of the wafer reference surface.

[0014] Further, the SOI new wafer is composed of a piece of SOI optical wafer top layer silicon surface and a piece of full-silicon optical wafer rectangular groove top surface with the same crystal direction and type high-temperature thermal bonding, the SOI optical wafer is made into the laminated top layer silicon of the SOI new wafer, and the full-silicon optical wafer is used as the substrate silicon of the SOI new wafer.

[0015] Further, the part of the top layer silicon fixed by the rectangular groove top surface is used as the pressure-sensitive diaphragm of the sensitive chip, and the thickness of the pressure-sensitive diaphragm fixed by the top layer silicon is matched with the rated range of the measured pressure, the cavity of the rectangular groove covered by the pressure-sensitive diaphragm forms the pressure-sensitive cavity of the sensitive chip.

[0016] Further, the SOI optical wafer is uniformly and precisely thinned to the substrate silicon with a thickness of sub-micron as the laminated top layer silicon of the SOI new wafer, and the thickness of the laminated top layer silicon on the pressure-sensitive diaphragm is added, and the deflection displacement of the pressure-sensitive diaphragm is negligible.

[0017] Further, the diffusion silicon piezoresistive sensitive bridge and the bridge metal electrode are arranged on the laminated top layer silicon, and the laminated top layer silicon except the diffusion silicon piezoresistive sensitive bridge and the peripheral sealing frame is etched, the electrical isolation medium between the diffusion silicon piezoresistive sensitive bridge and the pressure-sensitive diaphragm is the SiO2 buried layer which is not PN junction, and the peripheral sealing frame is arranged for the airtight sealing between the top surface of the laminated top layer silicon of the sensitive chip and the glass liner, which does not affect the airtight sealing between the bottom surface of the conventional substrate silicon of the sensitive chip and the glass liner.

[0018] Further, the bottom surface of the SOI new wafer substrate silicon is centrally provided with a pressure guide through hole connected with the rectangular groove, and the diameter of the pressure guide through hole is equal to or less than 1 mm, and when the conventional substrate silicon of the sensitive chip is airtightly sealed with the glass liner, the cavity connected with the rectangular groove and the pressure guide through hole is used as the pressure reference cavity, and when the laminated top layer silicon of the sensitive chip is airtightly sealed with the glass liner, the connected cavity is used as the pressure measurement cavity.

[0019] Further, the preparation method of the sensitive chip is as follows:

[0020] S1, dry etching a rectangular groove around the pressure-sensitive diaphragm of the fixed sensitive chip on the top surface of the full-silicon optical wafer;

[0021] S2, high-temperature thermal bonding of the top layer of the SOI optical wafer downward to the groove top surface of the full-silicon optical wafer with the same crystal orientation and type, and the upper and lower wafer reference surfaces are aligned and overlapped, and the top layer of silicon is set as the pressure-sensitive diaphragm of the sensitive chip;

[0022] S3, uniformly and precisely thinning the substrate silicon thickness of the SOI optical wafer to submicron by a physical and chemical combined process, as the stacked top layer silicon of the SOI wafer;

[0023] S4, using semiconductor planar and thin film processes to manufacture a diffused silicon piezoresistive sensitive bridge and metal electrodes and a peripheral sealing frame for top sealing of the sensitive chip on the stacked top layer silicon, and the stacked top layer silicon outside the diffused silicon piezoresistive sensitive bridge and the peripheral sealing frame is etched clean;

[0024] S5, etching a pressure guide hole with a diameter of millimeter or sub-millimeter scale in the center of the bottom surface of the full-silicon optical wafer substrate silicon.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] (1) The SOI top layer silicon is used to manufacture the pressure-sensitive diaphragm of the sensitive chip, replacing the anisotropic chemical wet etching method for manufacturing the pressure-sensitive diaphragm, eliminating the selective lateral expansion associated with the anisotropic chemical wet etching of the pressure-sensitive diaphragm, facilitating the miniaturization of the sensitive chip area, increasing the chip yield per wafer, and increasing the number of sensitive chips on a single wafer by several times or even orders of magnitude;

[0027] (2) The SOI top layer silicon pressure-sensitive diaphragm replaces the traditional substrate silicon pressure-sensitive diaphragm, and the thickness precision and uniformity can be controlled with an order of magnitude improvement, while maintaining the surface roughness of the mirror, avoiding the constraints of the initial thickness and uniformity tolerance of the substrate silicon, and optimizing the consistency of the silicon piezoresistive effect sensitive characteristics between chips and wafers;

[0028] (3) The SiO2 buried insulating medium between the top layer silicon and the stacked top layer silicon replaces the reverse PN junction, extending the high-width-temperature area signal-to-noise ratio and thermal characteristic advantages of the conventional SOI silicon piezoresistive pressure-sensitive bridge;

[0029] (4) The sensitive chip can be top airtight sealed and connected with an external electrically connected high-temperature resistant metal electrode, which significantly expands the measured pressure medium and environmental adaptability of the sensitive chip and the compatibility of pulsatile and static pressure measurement;

[0030] (5) The area of the sensitive chip that can be top airtight sealed is miniaturized, which is easy to maximize the chip packaging area and surface mount the sensor volume. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 This is a 3 / 4 cross-sectional stereoscopic diagram of a silicon piezoresistive pressure-sensitive chip based on SOI stacked top silicon.

[0032] Figure 2 This is a top view of the sensitive bridge surface of a silicon piezoresistive pressure sensor chip based on SOI stacked top silicon.

[0033] Figure 3 For silicon piezoresistive pressure-sensitive chips based on SOI stacked top silicon layer Figure 2 Schematic diagram of longitudinal section cut by dashed lines;

[0034] Figure 4 A top-view schematic diagram of the silicon surface of a silicon piezoresistive pressure-sensitive chip substrate based on SOI stacked silicon top layer;

[0035] Figure 5 For silicon piezoresistive pressure-sensitive chip substrate based on SOI stacked top silicon, the silicon pressure-sensing cavity is along... Figure 4 A schematic diagram of a longitudinal section cut by dashed lines.

[0036] In the figure: 101, top silicon layer; 102, pressure-sensitive diaphragm; 103, stacked top silicon layer; 104, diffused silicon piezoresistive sensitive bridge; 105, peripheral sealing frame; 106, SiO2 buried layer; 107, metal electrode; 201, substrate silicon; 202, rectangular groove; 203, pressure-conducting via. Detailed Implementation

[0037] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0038] like Figures 1-5 As shown, the fabrication of a silicon piezoresistive pressure sensitive chip based on SOI stacked top silicon includes fabricating a new SOI wafer with stacked top silicon. The new SOI wafer is composed of an SOI optical wafer and a co-oriented, same-type all-silicon optical wafer thermally bonded at high temperature, with the upper and lower wafer reference planes aligned and overlapping. The substrate silicon of the SOI optical wafer is thinned to form the stacked top silicon 103 of the new SOI wafer, and the all-silicon optical wafer is used as the substrate silicon 201 of the new SOI wafer.

[0039] The rectangular groove is arranged on the full-silicon optical wafer top surface for fixedly supporting the sensitive chip pressure-sensitive diaphragm 102 periphery, the side wall is perpendicular to the rectangular groove 202 top surface, the set side length of the rectangular groove 202 is equal to the length of the sensitive chip pressure-sensitive diaphragm 102, and the depth of the rectangular groove 202 is greater than the maximum deflection displacement of the sensitive chip pressure-sensitive diaphragm 102 under the upper limit pressure load of the rated range, but less than the maximum deflection displacement of the sensitive chip pressure-sensitive diaphragm 102 under the upper limit load of the rated overload pressure, and the diagonal intersection point of the rectangular groove 202 overlaps the diagonal intersection point of the sensitive chip, and one pair of side lengths of the rectangular groove 202 is parallel to the wafer reference surface cutting edge, and the other pair of side lengths is perpendicular to the wafer reference surface cutting edge.

[0040] The SOI optical wafer periphery is fixedly supported by the top layer silicon 101 part as the sensitive chip pressure-sensitive diaphragm 102 which is deflected with the measured pressure, and the sealed rectangular groove 202 and the pressure guide through hole 203 communicate the cavity to form a pressure sensing cavity, and the same thickness of the top layer silicon 101 and the pressure-sensitive diaphragm 102 matches the rated range of the measured pressure.

[0041] The SOI optical wafer is uniformly and precisely thinned to a substrate silicon of sub-micron thickness as a laminated top layer silicon 103 of the SOI new wafer, and the thickness of the laminated top layer silicon 103 on the pressure-sensitive diaphragm 102 is added, and the deflection displacement of the sensitive chip pressure-sensitive diaphragm 102 is negligible.

[0042] The laminated top layer silicon 103 is provided with a diffused silicon piezoresistive sensing bridge 104 and a peripheral sealing frame 105 for sealing the sensitive chip top, and the laminated top layer silicon 103 outside the diffused silicon piezoresistive sensing bridge 104 and the peripheral sealing frame 105 is etched clean, and the diffused silicon piezoresistive sensing bridge 104 and the peripheral sealing frame 105 are mutually insulated and spaced, the electrical isolation medium of the diffused silicon piezoresistive sensing bridge 104 and the sensitive chip pressure-sensitive diaphragm 102 is a non-PN junction SiO2 buried layer 106, and the peripheral sealing frame 105 is specially provided for the sealing of the laminated top layer silicon 103 top surface of the sensitive chip and the glass liner, which does not affect the conventional sealing of the glass liner on the bottom surface of the sensitive chip substrate silicon 201.

[0043] The bottom surface of the sensitive chip substrate silicon 201 is centrally etched with a pressure guide through hole 203 communicating with the rectangular groove 202, and the diameter of the pressure guide through hole 203 is equal to or less than 1 mm, and when the sensitive chip is conventionally packaged, the rectangular groove 202 and the pressure guide through hole 203 communicate the pressure sensing cavity as a pressure reference cavity, and when the sensitive chip peripheral sealing frame 105 is airtightly sealed with the glass liner, the communicated pressure sensing cavity serves as a pressure measurement cavity.

[0044] A specific preparation step of a silicon piezoresistive pressure sensitive chip based on SOI laminated top layer silicon includes the following:

[0045] S1, dry etching a rectangular groove 202 around the periphery of the fixed sensitive diaphragm 102 of the sensitive chip on the top surface of the full-silicon optical wafer, and the side wall of the rectangular groove 202 is 90° perpendicular to the top surface, the diagonal intersection of the rectangular groove 202 overlaps the diagonal intersection of the sensitive chip, and the side length is parallel or perpendicular to the wafer reference surface;

[0046] S2, preparing a P-type SOI optical wafer, and the thickness of the top layer silicon 101 is set to be matched with the rated range of the measured pressure;

[0047] S3, the top layer silicon 101 of the SOI optical wafer is high-temperature thermal bonded to the top surface of the rectangular groove 202 of the full-silicon optical wafer in the same crystal direction and the same type, and the upper and lower wafer reference surfaces are aligned and overlapped, and the part of the top layer silicon 101 which is fixed around the periphery is set as the pressure-sensitive diaphragm 102 of the sensitive chip, and the thickness is matched with the rated range of the measured pressure;

[0048] S4, using a physical and chemical combined process, uniformly and precisely thinning the substrate silicon thickness of the SOI optical wafer to sub-micron scale as the stacked top layer silicon 103 of the SOI new wafer;

[0049] S5, using semiconductor planar and thin film processes, diffused silicon piezoresistive sensitive bridge 104 and metal electrode 107 and peripheral sealing frame 105 for top sealing of the sensitive chip are made on the stacked top layer silicon 103, and the stacked top layer silicon 103 outside the diffused silicon piezoresistive sensitive bridge 104 and the peripheral sealing frame 105 is dry etched clean, the diffused silicon piezoresistive sensitive bridge 104 and the peripheral sealing frame 105 are mutually insulated and spaced, and the peripheral sealing frame 105 is specially set for electrostatic sealing with a glass liner;

[0050] S5, a pressure guide through hole 203 with a diameter of unit millimeter or sub-millimeter scale and communicated with the rectangular groove 202 is etched in the center of the bottom surface of the wafer substrate silicon;

[0051] S6, the bottom surface of the sensitive chip substrate silicon 201 is conventionally electrostatically sealed with a glass liner, and the pressure-sensitive cavity communicated with the rectangular groove 202 and the pressure guide through hole 203 serves as a pressure reference cavity of the sensitive chip, and when the peripheral sealing frame 105 of the sensitive chip is electrostatically sealed with the glass liner, the pressure-sensitive cavity communicated with the rectangular groove 202 and the pressure guide through hole 203 serves as a pressure measurement cavity of the sensitive chip;

[0052] S7, precisely and cuttingly slicing to divide the silicon piezoresistive pressure sensitive chip based on the SOI stacked top layer silicon.

[0053] It should be noted that the present application is a silicon piezoresistive pressure sensitive chip based on SOI stacked top layer silicon and a preparation method thereof, and the components in the present application are all known to those skilled in the art, and their structure and principle can be known by technical personnel through technical manuals or through conventional experimental methods.

[0054] The foregoing merely illustrates the principles of the application and application of its more prominent features. This application is not limited to the embodiments described herein but is applicable to various arrangements of components thereof as would be recognized by persons skilled in the relevant art. The application should therefore be construed in broadest scope in accordance with the principles and spirit of the application and the appended claims.

Claims

1. A SOI-based top-silicon-on-insulator silicon piezoresistive pressure sensitive die, characterized by: The SOI new wafer of the laminated top layer silicon of the sensitive chip is composed of an SOI wafer and a full silicon wafer which are high-temperature thermal bonded, the substrate silicon of the SOI wafer is thinned to form the laminated top layer silicon (103) of the SOI new wafer, and the full silicon wafer is used as the substrate silicon (201) of the SOI new wafer.

2. A SOI -based, top-silicon, silicon-resistive pressure sensitive die according to claim 1, wherein: A rectangular groove (202) for fixing the periphery of the sensitive chip diaphragm (102) is arranged on the top surface of the single crystal silicon of the full silicon wafer, the sidewall of the rectangular groove (202) is perpendicular to the top surface, the length of the rectangular groove (202) is the same as the length of the sensitive chip diaphragm (102), the depth of the rectangular groove (202) is greater than the maximum deflection displacement of the sensitive chip diaphragm (102) under the maximum pressure load of the rated range, but less than the maximum deflection displacement of the sensitive chip diaphragm (102) under the maximum pressure load of the rated overload, the intersection of the diagonal lines of the rectangular groove (202) overlaps the intersection of the diagonal lines of the sensitive chip, and the length of one pair of edges of the rectangular groove (202) is parallel to the wafer reference surface, and the length of the other pair of edges is perpendicular to the wafer reference surface.

3. A SOI -based, top-silicon, silicon-resistive pressure sensitive die according to claim 1, wherein: The top surface of the top layer silicon (101) of the SOI wafer is high-temperature thermal bonded with the top surface of the groove (202) on the full silicon wafer, and the top layer silicon (101) of the SOI wafer fixed by the periphery of the rectangular groove (202) is used as the sensitive chip diaphragm (102) which deflects with the measured pressure, and the thickness of the top layer silicon (101) and the sensitive chip diaphragm (102) matches the rated range of the measured pressure.

4. A SOI -based, top-silicon, silicon-resistive pressure sensitive die according to claim 1, wherein: After the substrate silicon of the SOI wafer is uniformly and precisely thinned to submicron, the laminated top layer silicon (103) of the SOI new wafer is formed, and the thickness of the laminated top layer silicon (103) on the sensitive chip diaphragm (102) is added, and the deflection displacement of the sensitive chip diaphragm (102) is negligible.

5. A silicon piezoresistive pressure-sensitive chip based on SOI stacked top silicon as described in claim 1, characterized in that: The diffusion silicon piezoresistive sensitive bridge (104), the metal electrode (107) and the sensitive chip periphery sealing frame (105) are arranged on the laminated top layer silicon (103), the laminated top layer silicon (103) outside the diffusion silicon piezoresistive sensitive bridge (104) and the periphery sealing frame (105) is etched, the electrical isolation medium between the diffusion silicon piezoresistive sensitive bridge (104) and the top layer silicon (101) and the sensitive chip diaphragm (102) is the non-PN junction SiO2 buried layer (106), and the periphery sealing frame (105) is specially arranged for the airtight sealing of the sensitive chip and the glass liner.

6. A SOI -based, top-silicon, silicon-resistive pressure sensitive die according to claim 1, wherein: A pressure guide through hole (203) which communicates with the rectangular groove (202) is arranged on the bottom surface of the substrate silicon (201) of the SOI new wafer, the diameter of the pressure guide through hole (203) is equal to or less than 1 mm, when the substrate silicon (201) of the sensitive chip is airtightly sealed with the glass liner, the communication cavity of the pressure guide through hole (203) and the rectangular groove (202) is used as a pressure reference cavity, and when the laminated top layer silicon periphery sealing frame (105) of the sensitive chip is airtightly sealed with the glass liner, the communication cavity is used as a pressure measurement cavity.

7. A SOI -on-lime piezoresistive pressure sensitive chip according to claims 1 to 6, characterized in that: The main preparation method of the sensitive chip is as follows. S1, dry etching a rectangular groove (202) around the periphery of the pressure-sensitive diaphragm (102) of the fixed sensitive chip on the top surface of the full-silicon optical wafer; S2, the top layer of silicon (101) of the SOI optical wafer is bonded to the top surface of the rectangular groove (202) of the full-silicon optical wafer in the same crystal direction and the same type at high temperature to form a new SOI wafer, and the reference surfaces of the upper and lower wafers are aligned and overlapped, and the top layer of silicon (101) around the periphery is set as the pressure-sensitive diaphragm (102) of the sensitive chip; S3, using a physical and chemical combined process, uniformly and precisely thinning the substrate silicon thickness of the SOI optical wafer to sub-micron scale, which is set as the laminated top layer of silicon (103) of the new SOI wafer; S4, using semiconductor planar and thin film processes, making a diffused silicon piezoresistive sensitive bridge (104) and metal electrodes (107) and a peripheral sealing frame (105) for the top sealing of the sensitive chip on the laminated top layer of silicon (103), and etching the laminated top layer of silicon (103) outside the diffused silicon piezoresistive sensitive bridge (104) and the peripheral sealing frame (105) to be clean; S5, etching a pressure-conducting through hole (203) with a diameter of unit millimeter or sub-millimeter scale in the center of the bottom surface of the substrate silicon (201) of the new SOI wafer.

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