Voltage detector, voltage detection circuit and power management chip

Abstract

The invention provides a voltage detector, a voltage detection circuit and a power management chip, in the voltage detector, a corresponding voltage to be detected is directly input to a corresponding input end of each comparator of the voltage detector, and a reference voltage is input to the other corresponding input end of each comparator through a first resistor and a second resistor. Therefore, on the basis that overvoltage monitoring and low-voltage monitoring can be realized at the same time, the charging and discharging process of the gate capacitor at the input end of the comparator cannot be generated, and the time delay of the circuit is reduced. In addition, the voltage detectors in different voltage domains can multiplex the same resistor string, so that the power consumption is low, and the circuit area is small.

Description

Technical Field

[0001] This invention relates to the field of voltage detection technology, and in particular to a voltage detector, a voltage detection circuit, and a power management chip. Background Technology

[0002] In electronic circuits, voltage detectors are typically installed to simultaneously monitor the high voltage directive (HVD) and low voltage directive (LVD) of the voltage to be measured (which may be the operating voltage) to prevent the electronic circuit from malfunctioning due to overvoltage or undervoltage conditions.

[0003] Please refer to Figure 1 One existing voltage detector typically uses a series of sensing resistors to divide the voltage to be measured and then compare it with a reference voltage to achieve overvoltage and undervoltage detection. Specifically, sensing resistors Rs_i, Rh_i, and Rl_i are connected in series to form a sensing resistor string. The voltage to be measured, Vs_i, is input to one end of sensing resistor Rs_i. The connection node A_i of sensing resistors Rs_i and Rh_i is connected to the positive input of a first comparator COMPh_i, and the connection node B_i of sensing resistors Rh_i and Rl_i is connected to the negative input of a second comparator COMP1_i. Both the negative input of COMPh_i and the positive input of COMP1_i are connected to the reference voltage Vref_i. Thus, the first comparator COMPh_i compares the voltage divided at connection node A_i with the reference voltage Vref_i and outputs an overvoltage detection signal V. HVD The second comparator COMP1_i compares the voltage division value of the connected node B_i with the reference voltage Vref_i, and outputs a low-voltage detection signal V. LVD .

[0004] Although the voltage detector described above can simultaneously detect overvoltage and undervoltage, the resistance values ​​of each detection resistor in the detection resistor string are relatively large due to the low power consumption requirement. Furthermore, the detection resistor string forms a charging and discharging circuit with the gate capacitors at the input terminals of the first comparator COMPh_i and the second comparator COMPl_i, respectively. This results in a large time delay for the voltage detection circuit.

[0005] Therefore, a new technical solution is needed that can not only simultaneously achieve overvoltage and undervoltage monitoring, but also reduce circuit delay. Summary of the Invention

[0006] The purpose of this invention is to provide a voltage detector, a voltage detection circuit, and a power management chip that can simultaneously achieve overvoltage and undervoltage monitoring, reduce circuit delay, and, in a further embodiment, reduce circuit size and power consumption.

[0007] To achieve the above objectives, the present invention provides a voltage detector, comprising a first comparator, a second comparator, a first resistor, and a second resistor. The first input terminal of the first comparator and the second input terminal of the second comparator are both coupled to a first voltage to be measured. The first terminal of the first resistor is directly or indirectly coupled to a corresponding reference voltage. The second input terminal of the first comparator is coupled to the first terminal of the first resistor. The second terminal of the first resistor is coupled to the first terminal of the second resistor and the first input terminal of the second comparator. The second terminal of the second resistor is grounded. The first comparator is used to compare the voltage at the first terminal of the first resistor with the first voltage to be measured to achieve overvoltage monitoring of the first voltage to be measured. The second comparator is used to compare the first voltage to be measured with the voltage at the second terminal of the first resistor to achieve undervoltage monitoring of the first voltage to be measured.

[0008] Optionally, the voltage detector further includes a third comparator and a fourth comparator. The first input terminal of the third comparator and the second input terminal of the fourth comparator are both coupled to a second voltage to be measured. The second input terminal of the third comparator is coupled to a first terminal of the first resistor, and the first input terminal of the fourth comparator is coupled to a second terminal of the first resistor. The third comparator is used to compare the voltage at the first terminal of the first resistor with the second voltage to be measured to achieve overvoltage monitoring of the second voltage to be measured. The fourth comparator is used to compare the second voltage to be measured with the voltage at the second terminal of the first resistor to achieve undervoltage monitoring of the second voltage to be measured.

[0009] Optionally, the first voltage to be measured is the operating voltage of the corresponding circuit in normal operating mode, and the second voltage to be measured is the operating voltage of the corresponding circuit in low power mode.

[0010] Optionally, the voltage detector further includes a reference voltage adjustment circuit, which includes an operational amplifier and an adjustment circuit. The first input terminal of the operational amplifier is coupled to a corresponding reference voltage, and the output terminal of the operational amplifier is used to provide the reference voltage. The adjustment circuit is coupled to the output terminal of the operational amplifier and the second input terminal of the operational amplifier, and is used to adjust the magnitude of the reference voltage output by the operational amplifier.

[0011] Optionally, the adjustment circuit includes a variable resistor string, which includes several fixed resistors and several electronic switches. The fixed resistors are connected in series, and the fixed resistors and the electronic switches are configured in parallel and correspond one-to-one. The first end of the variable resistor string is coupled to the output terminal of the operational amplifier, and the last end of the variable resistor string is grounded through a grounding resistor.

[0012] Optionally, the resistance values ​​of each resistor in the variable resistor string are incremented in binary order from beginning to end.

[0013] Based on the same inventive concept, the present invention also provides a voltage detection circuit, which includes at least two voltage detectors as described in the present invention. Each voltage detector is configured to correspond one-to-one with different voltage domains and is used to perform overvoltage monitoring and undervoltage monitoring for each voltage domain. The reference voltages corresponding to the different voltage domains are different.

[0014] Optionally, the first and second resistors in at least one voltage domain of the voltage detector are connected in series with the first and second resistors in at least another voltage domain of the voltage detector to form a voltage divider resistor string multiplexed by the voltage detectors of different voltage domains.

[0015] Optionally, the first and second resistors in all the voltage detectors of the voltage detection circuit are connected in series to form a voltage divider resistor string that is multiplexed by the voltage detectors of all voltage domains. An initial reference voltage is output as a reference voltage of different magnitudes through different nodes of the voltage divider resistor string and provided to each of the voltage detectors. The resistance values ​​of each resistor in the voltage divider resistor string are determined by a combination of factors, including the threshold voltages for overvoltage monitoring and undervoltage monitoring of each voltage detector, and the rated current of the voltage divider resistor string.

[0016] Optionally, among all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the initial reference voltage also has a third resistor, one end of which is coupled to the initial reference voltage and the other end of which is coupled to the first end of the voltage divider resistor string.

[0017] And / or, among all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the initial reference voltage also has a reference voltage adjustment circuit. The reference voltage adjustment circuit includes an operational amplifier and an adjustment circuit. The first input terminal of the operational amplifier is coupled to a corresponding reference voltage, and the output terminal of the operational amplifier is coupled to the voltage detector that receives the initial reference voltage. The adjustment circuit is coupled to the output terminal or the second input terminal of the operational amplifier and is used to adjust the magnitude of the initial reference voltage output by the operational amplifier.

[0018] Optionally, among all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the minimum reference voltage also has a third comparator and a fourth comparator. The first input terminal of the third comparator and the second input terminal of the fourth comparator are both coupled to the second test voltage of the voltage detector that receives the minimum reference voltage. The second input terminal of the third comparator is coupled to the first terminal of the first resistor of the voltage detector that receives the minimum reference voltage, and the first input terminal of the fourth comparator is coupled to the second terminal of the first resistor of the voltage detector that receives the minimum reference voltage.

[0019] Based on the same inventive concept, the present invention also provides a power management chip, which includes the voltage detection circuit as described in the present invention.

[0020] Optionally, the power management chip further includes a core digital circuit, an analog circuit, and a power amplifier circuit coupled to the voltage detection circuit, and the core digital circuit, the analog circuit, and the power amplifier circuit are distributed in different voltage domains.

[0021] Optionally, the overvoltage detection signal output by the first comparator is used to issue an interrupt to the core digital circuit; and / or, the undervoltage detection signal output by the second comparator is used to reset the power management chip or issue an interrupt to the core digital circuit.

[0022] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0023] 1. In the voltage detector, the corresponding voltage to be measured is directly input to one input terminal of each comparator. The reference voltage is input to the other input terminal of the comparator through a voltage divider formed by the first and second resistors. Thus, when each comparator is working, the terminal connected to the first resistor and the other resistor is the reference voltage terminal. This reference voltage is fixed, and there is no charging and discharging process of the gate capacitance at the comparator input terminal, resulting in a small time delay. Furthermore, by utilizing the different magnitudes of the reference voltages received by the two comparators, overvoltage and undervoltage monitoring can be achieved simultaneously.

[0024] 2. The voltage detector also includes a third comparator and a fourth comparator, and the third and fourth comparators respectively reuse the reference voltages of the first and second comparators, thereby simplifying the circuit, reducing power consumption, and enabling overvoltage monitoring and undervoltage monitoring of two different voltages under test in the same voltage domain.

[0025] 3. The first and second resistors in the voltage detectors of different voltage domains are connected in series to form a voltage divider resistor string that is multiplexed by different voltage domains. This can reduce power consumption and circuit size. In addition, one end of the comparator in each voltage detector is connected to a corresponding fixed reference voltage, with no charging and discharging process and a small time delay.

[0026] 4. The corresponding voltage detector also has a reference voltage adjustment circuit, which can adjust the reference voltage required by the voltage detector to eliminate the influence of process and mismatch, so as to make the overvoltage monitoring and undervoltage monitoring results of the voltage detector more accurate. Attached Figure Description

[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0028] Figure 1 This is a schematic diagram of an existing voltage detector.

[0029] Figure 2 This is a schematic diagram of the voltage detection circuit according to the first embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the reference voltage configuration circuit in the voltage detection circuit of the first embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the structure of a voltage detection circuit for different voltage domains in low-power mode and normal operation mode of the same circuit.

[0032] Figure 5 This is a schematic diagram of the voltage detection circuit according to the second embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of an existing voltage detection circuit for multiple voltage domains.

[0034] Figure 7 This is a schematic diagram of the voltage detection circuit according to the third embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of the reference voltage adjustment circuit in the voltage detection circuit of the third embodiment of the present invention.

[0036] Figure 9 This is a schematic diagram of the voltage detection circuit according to the fourth embodiment of the present invention. Detailed Implementation

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0039] First Embodiment

[0040] Please refer to Figure 2 This embodiment provides a voltage detector, which includes a first comparator COMPh_i, a second comparator COMP1_i, a first resistor Rh_i, and a second resistor Rl_i. The first input terminal of the first comparator COMPh_i (e.g., its non-inverting input "+") and the second input terminal of the second comparator COMP1_i (e.g., its inverting input "-") are both coupled to a corresponding first voltage to be measured, Vs_i. The second input terminal of the first comparator COMPh_i (e.g., its inverting input "-") is coupled to the first terminal of the first resistor Rh_i. The second terminal of the first resistor Rh_i is coupled to the first terminal of the second resistor Rl_i and the first input terminal of the second comparator COMP1_i (e.g., its non-inverting input "+"). The second terminal of the second resistor Rl_i is grounded. In one example, please refer to... Figure 2The voltage detector also includes a third resistor Rs_i. The first end of the first resistor Rh_i is coupled to the second end of the third resistor Rs_i. The first end of the third resistor Rs_i is coupled to the reference voltage Vref_i. At this time, the first resistor Rh_i is indirectly coupled to the reference voltage Vref_i through the third resistor Rs_i. The third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i are connected in series to form the voltage divider resistor string of the voltage detector, which divides the reference voltage Vref_i. The connection node of the third resistor Rs_i and the first resistor Rh_i (i.e., one voltage divider node of the voltage divider resistor string, and also the first end of the first resistor Rh_i) A_i outputs the node voltage VrefA_i to the first comparator COMPh_i. The connection node of the second resistor Rl_i and the first resistor Rh_i (i.e., another voltage divider node of the voltage divider resistor string, and also the second end of the first resistor Rh_i) B_i outputs the node voltage VrefB_i to the second comparator COMP1_i. Therefore, Vref_i > VrefA_i > VrefB_i. The first comparator COMPh_i compares the first voltage under test Vs_i with the node voltage VrefA_i to monitor overvoltage of the first voltage under test Vs_i. For example, when the first voltage under test Vs_i exceeds the node voltage VrefA_i, the overvoltage detection signal VHVD_i output by the first comparator COMPh_i is high, and vice versa. The second comparator COMP1_i compares the first voltage under test Vs_i with the node voltage VrefB_i to monitor undervoltage of the first voltage under test Vs_i. For example, when the first voltage under test Vs_i is lower than the node voltage VrefB_i, the undervoltage detection signal VLVD_i output is high, and vice versa. The value of Rs_i mainly depends on the threshold voltages of Vref_i and COMPh_i, the threshold voltage of COMP1_i, and the rated power consumption requirements.

[0041] In another example, please combine Figure 2The voltage detector can omit the third resistor Rs_i. In this case, the first end of the first resistor Rh_i is directly coupled to the reference voltage Vref_i, i.e., Vref_i = VrefA_i. The first resistor Rh_i and the second resistor Rl_i are connected in series to form the voltage divider resistor string of the voltage detector, which divides the reference voltage Vref_i. The first end of the voltage divider resistor string outputs the node voltage VrefA_i to the first comparator COMPh_i. The node B_i where the second resistor Rl_i and the first resistor Rh_i are connected (i.e., the other voltage divider node of the voltage divider resistor string) outputs the node voltage VrefB_i to the second comparator COMP1_i. Therefore, Vref_i = VrefA_i > VrefB_i. The first comparator COMPh_i compares the first voltage under test Vs_i with the node voltage VrefA_i (i.e., Vref_i) to achieve overvoltage monitoring of the first voltage under test in the voltage domain. For example, when the first voltage under test Vs_i is or exceeds the node voltage VrefA_i, the overvoltage detection signal VHVD_i output by the first comparator COMPh_i is high. The second comparator COMP1_i compares the first voltage under test Vs_i with the node voltage VrefB_i to achieve undervoltage monitoring of the first voltage under test in the voltage domain. For example, when the first voltage under test Vs_i is or is lower than the node voltage VrefB_i, the undervoltage detection signal VLVD_i output is high.

[0042] It should be understood that the specific input terminals of the first comparator COMPh_i and the corresponding node voltages output from the voltage divider resistor series are connected to depend on the logic requirements of the first comparator COMPh_i and the second comparator COMPl_i, and are not limited to... Figure 2 This illustrates the logical requirements and connection methods. For example, in other examples, according to the logical requirements of the first comparator COMPh_i and the second comparator COMP1_i, the "-" input terminal of the first comparator COMPh_i (as its first input terminal) and the "+" input terminal of the second comparator COMP1_i (as its second input terminal) are both coupled to the corresponding first voltage under test Vs_i. The node voltage VrefA_i is input to the "+" input terminal of the first comparator COMPh_i (as its second input terminal), and the node voltage VrefB_i is input to the "-" input terminal of the second comparator COMP1_i (as its first input terminal). Similarly, whether the first and second input terminals of the operational amplifier OP and other comparators mentioned below are their non-inverting input terminal "+" or their inverting input terminal "-" depends on their logical requirements and is not limited to the examples in the corresponding drawings of this invention.

[0043] In one example, please refer to Figure 3The reference voltage Vref_i used by this voltage detector can be provided by a corresponding reference voltage adjustment circuit. This reference voltage adjustment circuit includes an operational amplifier OP and an adjustment circuit 10. The first input terminal of the operational amplifier OP (e.g., its non-inverting input "+") is coupled to a reference voltage VBG (which can be generated by a bandgap reference circuit, etc.). The output terminal of the operational amplifier OP is coupled to the first terminal of a third resistor Rs_i, or, in the absence of a third resistor Rs_i, to the first terminal of a first resistor Rh_i (i.e., connecting node A_i) and used to output the reference voltage Vref_i. The adjustment circuit 10 is coupled to the output terminal and the second input terminal (e.g., its inverting input "-") of the operational amplifier OP and adjusts the magnitude of the reference voltage Vref_i output by the operational amplifier OP. This avoids drift in the reference voltage Vref_i caused by factors such as process technology and mismatch, thereby ensuring a more accurate reference voltage Vref_i.

[0044] The adjustment circuit 10 can be implemented using any suitable circuit design. For example, please refer to... Figure 3 The adjustment circuit 10 includes a variable resistor string and a grounding resistor. The variable resistor string includes m fixed resistors R1 to Rm and m electronic switches K1 to Km, where m is an integer greater than 1. The m fixed resistors R1 to Rm are connected in series, and the m fixed resistors R1 to Rm are set in parallel with the m electronic switches K1 to Km in a one-to-one correspondence. That is, electronic switch K1 is connected in parallel across the two ends of fixed resistor R1, electronic switch K2 is connected in parallel across the two ends of fixed resistor R2, and so on. Electronic switch Km is connected in parallel across the two ends of fixed resistor Rm. The first end of fixed resistor R1 (i.e., the beginning end of the variable resistor string) is coupled to the output terminal of operational amplifier OP. The second end of fixed resistor Rm (i.e., the end end of the variable resistor string) is coupled to the first end of grounding resistor R0 and the second input terminal (e.g., its inverting input terminal "-") of operational amplifier OP. The second end of grounding resistor R0 is grounded.

[0045] Figure 3 The working principle of the reference voltage adjustment circuit shown is as follows:

[0046] Because the operational amplifier OP has a very high gain, the voltages at its first input terminal (e.g., its non-inverting input "+") and second input terminal (e.g., its inverting input "-") are almost equal (i.e., "virtual short"). Simultaneously, the input impedance of the differential input stage of the operational amplifier OP is very high, and the current at its first input terminal (e.g., its non-inverting input "+") and second input terminal (e.g., its inverting input "-") is approximately zero (i.e., "virtual open"). Therefore, the reference voltage VBG is equivalent to being applied across the grounding resistor R0. At this time, the current in the variable resistor string is VBG / R0, and the reference voltage Vref_i output by the operational amplifier OP is:

[0047] Vref_i=(R0+K1*R1+K2*R2+……+Km*Rm)*VBG / R0.

[0048] In the formula, the values ​​of K1 to Km, under ideal conditions, are "1" when the switch is closed and conducting, and "0" when the corresponding electronic switch is open and cut off. Specifically, for example, when electronic switch K1 is conducting, K1 = 1; when electronic switch K1 is open, K1 = 0. Therefore, by controlling the conduction or cutoff of electronic switches K1 to Km, the magnitude of the reference voltage Vref_i can be controlled. In one example, electronic switches K1 to Km can all be MOSFETs. By increasing the aspect ratio of these MOSFETs and selecting appropriate resistance values ​​for R1 to Rm, the above ideal conditions can be approximated.

[0049] Furthermore, the values ​​of R1 to Rm can be the same or different. This embodiment does not impose any specific limitations on this. For example, according to the order of R1 to Rm from beginning to end, the resistance values ​​of R1 to Rm increase in binary order, i.e., R1 = 2. 0 *R, R² = 2 1 *R, R3 = 2 2 *R, and so on, Rm = 2 m-1 *R, at this point:

[0050] Vref_i=(R0+K1*R+K2*2R+……+Km*2 m-1 *Rm)*VBG / R0.

[0051] In another example, please refer to Figure 7 or Figure 9 The reference voltage Vref_i used by the voltage detector can be generated by dividing the reference voltage of other voltage domains. For details, please refer to the third and fourth embodiments below, which will not be described in detail here.

[0052] It should be understood that in this embodiment, the reference voltage Vref_i is a fixed voltage, which can be determined based on the operating voltage range of the voltage domain monitored by the voltage detector. At this time, the resistance values ​​of the third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i need to be determined comprehensively based on a variety of factors such as the threshold voltage monitored by the low-voltage LVD and the threshold voltage monitored by the overvoltage HVD of the voltage domain VDi, the reference voltage Vref_i, and the rated power consumption requirements (or the rated current of the voltage divider resistor string formed by the third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i).

[0053] The voltage detector in this embodiment can not only simultaneously perform overvoltage and undervoltage monitoring, but also, relative to Figure 1The voltage detection circuit shown inputs the first voltage to be measured in the voltage domain directly to the corresponding input terminals of the first comparator (for overvoltage HVD monitoring) and the second comparator (for undervoltage LVD monitoring) in the same voltage domain. The reference voltage Vref_i required by the voltage detector is input to the other input terminal of the first and second comparators through the first resistor Rh_i and the second resistor Rl_i connected in series. This ensures that the voltage to be measured does not have a charging and discharging process at the input terminals of the first and second comparators, thus reducing the time delay of the voltage detector in this embodiment.

[0054] Furthermore, the low-voltage detection signal V output by the voltage detector in this embodiment LVD_i and overvoltage detection signal V HVD_i These functions can be used for system reset, interruption, interrupt alarm, etc., depending on the requirements of the electronic circuit system. This invention does not impose any specific limitations on these functions.

[0055] Second Embodiment

[0056] Currently, low-power technology has been widely used in most integrated circuits to improve integrated circuit performance and extend service life. Therefore, these integrated circuits usually have two modes: low-power mode (also known as standby mode) and normal operation mode. Some circuits in these integrated circuits (such as the core circuit) will work in different modes (the voltage domain to be measured in these two modes is usually provided by different power supply devices (such as low-voltage linear regulators LDO, etc.), and their voltage range and threshold voltage are generally the same). At this time, it is necessary to perform overvoltage (HVD) monitoring and undervoltage (LVD) monitoring on the different voltage domains to be measured in these two modes.

[0057] Please refer to Figure 4 For monitoring different voltage domains in these two modes of the same circuit, existing voltage detection circuits set a voltage domain for each mode of the circuit, such as... Figure 1 The voltage detector shown is specifically designed for the voltage domain during normal operation. It includes a voltage detector VDi_RUN, comprising sensing resistors Rs_i_RUN, Rh_i_RUN, Rl_i_RUN, a first comparator COMPh_i, and a second comparator COMP1_i. The connection method of the sensing resistors Rs_i_RUN, Rh_i_RUN, Rl_i_RUN, the first comparator COMPh_i, and the second comparator COMP1_i can be found in the previous section regarding... Figure 1The details are omitted here. The first voltage to be measured, Vs_i_RUN, is input to the first terminal of the sensing resistor Rs_i_RUN. The reference voltage, Vref_i_RUN, is input to the corresponding input terminals of the first comparator COMPh_i and the second comparator COMP1_i. The first comparator COMPh_i compares the voltage division value of the connected node A_i_RUN with the reference voltage Vref_i_RUN and outputs the overvoltage detection signal VHVD_i_RUN. The second comparator COMP1_i compares the voltage division value of the connected node B_i_RUN with the reference voltage Vref_i_RUN and outputs the undervoltage detection signal VLVD_i_RUN.

[0058] Meanwhile, for the voltage domain in the low-power mode of this circuit, the voltage detection circuit sets up a voltage detector VDi_STBY. The voltage detector VDi_STBY includes sensing resistors Rs_i_STBY, Rh_i_STBY, Rl_i_STBY, a third comparator COMPh'_i, and a fourth comparator COMP1'_i. The connection method of sensing resistors Rs_i_STBY, Rh_i_STBY, Rl_i_STBY, the third comparator COMPh'_i, and the fourth comparator COMP1'_i can be referred to in the previous section on... Figure 1 The details are omitted here. The second voltage to be measured, Vs_i_STBY, is input to the first terminal of the sensing resistor Rs_i_STBY. The reference voltage, Vref_i_STBY, is input to the corresponding input terminals of the third comparator COMPh'_i and the fourth comparator COMP1'_i. The third comparator COMPh'_i compares the voltage division value of the connected node A_i_STBY with the reference voltage Vref_i_STBY and outputs the overvoltage detection signal VHVD_i_STBY. The fourth comparator COMP1'_i compares the voltage division value of the connected node B_i_STBY with the reference voltage Vref_i_STBY and outputs the undervoltage detection signal VLVD_i_STBY.

[0059] The existing voltage detection circuit described above, while capable of overvoltage and undervoltage monitoring in two modes within the same voltage domain, still has the following drawbacks:

[0060] First, its voltage detectors VDi_STBY and VDi_RUN are independent of each other, and the detection resistors Rs_i_RUN, Rh_i_RUN, Rl_i_RUN, Rs_i_STBY, Rh_i_STBY, and Rl_i_STBY are not reused, which results in a large overall area of ​​the voltage detection circuit in this voltage domain.

[0061] Secondly, the second voltage to be measured, Vs_i_STBY, is equivalent to being input to the sensing resistors Rs_i_STBY, Rh_i_STBY, and Rl_i_STBY, and the first voltage to be measured, Vs_i_RUN, is equivalent to being input to the sensing resistors Rs_i_RUN, Rh_i_RUN, and Rl_i_RUN. As a result, the sensing resistors Rs_i_RUN, Rh_i_RUN, Rl_i_RUN, Rs_i_STBY, Rh_i_STBY, and Rl_i_STBY will all consume a certain amount of power, which will lead to a large standby power consumption of the voltage detection circuit.

[0062] In addition, the detection resistor strings in voltage detectors VDi_STBY and VDi_RUN each form a charging and discharging circuit with the gate capacitance at the input of their comparators, which results in a large time delay for the voltage detection circuit.

[0063] Based on this, please refer to Figure 5 This embodiment provides a voltage detector for overvoltage and undervoltage monitoring of the same circuit in different voltage domains under different modes (i.e., the first voltage under test Vs_i_RUN in normal mode and the second voltage under test Vs_i_STBY in low-power mode). The voltage detector includes a first comparator COMPh_i, a second comparator COMP1_i, a third comparator COMPh'_i, a fourth comparator COMP1'_i, a first resistor Rh_i, and a second resistor Rl_i. The first input terminal of the first comparator COMPh_i (e.g., its non-inverting input "+") and the second input terminal of the second comparator COMP1_i (e.g., its inverting input "-") are both coupled to the corresponding first voltage under test Vs_i_RUN. The first input terminal of the third comparator COMPh'_i (e.g., its non-inverting input "+") and the second input terminal of the fourth comparator COMP1'_i (e.g., its inverting input "-") are both coupled to the corresponding second voltage under test Vs_i_STBY. The first comparator COMPh_i... The second input terminal of Ph_i (e.g., its inverting input terminal "-") and the second input terminal of the third comparator COMPh'_i (e.g., its inverting input terminal "-") are both coupled to the first terminal of the first resistor Rh_i. The second terminal of the first resistor Rh_i is coupled to the first terminal of the second resistor Rl_i, the first input terminal of the second comparator COMP1_i (e.g., its non-inverting input terminal "+"), and the first input terminal of the fourth comparator COMP1'_i (e.g., its non-inverting input terminal "+"). The second terminal of the second resistor Rl_i is grounded.

[0064] In one example, please refer to Figure 5The voltage detector also includes a third resistor Rs_i. The first terminal of the first resistor Rh_i is coupled to the second terminal of the third resistor Rs_i. The first terminal of the third resistor Rs_i is coupled to the reference voltage Vref_i. In this case, the first resistor Rh_i is indirectly coupled to the reference voltage Vref_i through the third resistor Rs_i. The third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i are connected in series to form a voltage divider resistor string for the voltage detector, which divides the reference voltage Vref_i. The third resistor Rs_i and the first resistor... The connection node of Rh_i (i.e., one voltage dividing node of the voltage divider resistor string, and also the first terminal of the first resistor Rh_i) outputs node voltage VrefA_i to the first comparator COMPh_i and the third comparator COMPh'_i. The connection node of the second resistor Rl_i and the first resistor Rh_i (i.e., another voltage dividing node of the voltage divider resistor string, and also the second terminal of the first resistor Rh_i) outputs node voltage VrefB_i to the second comparator COMP1_i and the fourth comparator COMP'l_i. Therefore, Vref_i > VrefA_i > VrefB_i. The first comparator COMPh_i compares the first voltage under test Vs_i_RUN with the node voltage VrefA_i to monitor overvoltage of the first voltage under test Vs_i_RUN. For example, when the first voltage under test Vs_i_RUN exceeds the node voltage VrefA_i, the overvoltage detection signal VHVD_i_RUN output by the first comparator COMPh_i is high, and vice versa. The second comparator COMP1_i compares the first voltage under test Vs_i_RUN with the node voltage VrefB_i to monitor undervoltage of the first voltage under test Vs_i_RUN. For example, when the first voltage under test Vs_i_RUN is lower than the node voltage VrefB_i, the undervoltage detection signal VLVD_i_RUN output is high, and vice versa. The third comparator COMPh'_i compares the second voltage under test Vs_i_STBY with the node voltage VrefA_i to monitor overvoltage of the second voltage under test Vs_i_STBY. For example, when the second voltage under test Vs_i_STBY exceeds the node voltage VrefA_i, the overvoltage detection signal VHVD_i_STBY output by the third comparator COMPh'_i is high, and vice versa. The fourth comparator COMP1'_i compares the second voltage under test Vs_i_STBY with the node voltage VrefB_i to monitor undervoltage of the second voltage under test Vs_i_STBY. For example, when the second voltage under test Vs_i_STBY is lower than the node voltage VrefB_i, the undervoltage detection signal VLVD_i_STBY output is high, and vice versa.The value of Rs_i depends primarily on Vref_i, the rated power consumption requirement, and the threshold voltages of COMPh_i and COMPl_i.

[0065] In another example, please combine Figure 5 In this voltage detector, the third resistor Rs_i can be omitted. In this case, the first terminal of the first resistor Rh_i is directly coupled to the reference voltage Vref_i, i.e., Vref_i = VrefA_i. The first resistor Rh_i and the second resistor Rl_i are connected in series to form a voltage divider resistor string for the voltage detector, which divides the reference voltage Vref_i. The first terminal of this voltage divider resistor string outputs a node voltage VrefA_i (i.e., the reference voltage Vref_i) to the first comparator COMPh_i and the third comparator COMPh'_i. The node B_i where the second resistor Rl_i and the first resistor Rh_i are connected (i.e., the other voltage divider node of this voltage divider resistor string) outputs a node voltage VrefB_i to the second comparator COMP1_i and the fourth comparator COMP1'_i. Therefore, Vref_i = VrefA_i > VrefB_i.

[0066] Optionally, the first voltage to be measured, Vs_i_RUN, is the operating voltage of the corresponding circuit in normal operating mode (or the first voltage domain to be measured), and the second voltage to be measured, Vs_i_STBY, is the operating voltage of the circuit in the low-power mode (or the second voltage domain to be measured). Thus, the voltage detector of this embodiment can realize real-time monitoring of low-voltage LVD and overvoltage HVD in different voltage domains in the low-power mode (also known as standby mode) and normal operating mode of the same circuit.

[0067] Alternatively, the first voltage under test VLVD_i_RUN and the second voltage under test VLVD_i_STBY can be output by different power supply devices (e.g., low dropout linear regulators LDO), and they have the same threshold voltage.

[0068] Furthermore, it should be understood that the reference voltage Vref_i required by the voltage detector in this embodiment can be provided by any suitable circuit design, which can be determined based on the voltage range of the operating voltage of the voltage domain monitored by the voltage detector in both modes. For example, it can be provided by... Figure 3 The reference voltage adjustment circuit shown can provide it, or it can be provided by... Figure 7 or Figure 9The reference voltages for other voltage domains shown are generated after voltage division, and will not be described in detail here. At this time, the resistance values ​​of the third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i need to be determined comprehensively based on a variety of factors, including the threshold voltage monitored by the low-voltage LVD, the threshold voltage monitored by the overvoltage HVD, the reference voltage Vref_i, and the rated power consumption requirements (or the rated current of the voltage divider resistor string formed by the third resistor Rs_i, the first resistor Rh_i, and the second resistor Rl_i).

[0069] Compared with the first embodiment, the voltage detector in this embodiment further adds a third comparator and a fourth comparator, which can realize overvoltage monitoring and undervoltage monitoring of two different voltages to be measured in the same voltage domain.

[0070] The voltage detector in this embodiment is related to... Figure 4 Compared with the prior art shown, on the one hand, the same reference voltage can be divided by the same resistor string and provided to comparators used for overvoltage and undervoltage monitoring in two different modes of the same voltage domain, which improves the reuse rate of resistors and reduces the overall area of ​​the voltage detector; on the other hand, the second voltage to be measured, Vs_i_STBY and the first voltage to be measured, Vs_i_RUN, are directly input to the input terminals of the corresponding comparators without passing through the reused resistor string. Therefore, there is no charging and discharging process at the input terminals of the two voltages to be measured, and the reused resistor string does not consume the input power corresponding to the voltage to be measured. Therefore, the voltage detector delay and power consumption of this embodiment can be greatly reduced.

[0071] Third Embodiment

[0072] Currently, more complex integrated circuits often contain multiple voltage domain circuits with different operating voltages. Power management integrated circuits (PMICs) typically provide the necessary operating voltages to these voltage domain circuits. For example, they provide low voltages (e.g., 0–1.1V) for digital circuits (such as the core digital circuit), medium voltages (e.g., 2.5V or 3.3V) for conventional analog circuits, and high voltages (e.g., 5V or 12V) for power amplifier circuits. To ensure the normal operation of circuits in each voltage domain and meet low power consumption requirements, voltage detection circuits are also needed to simultaneously monitor the operating voltage of each voltage domain in real time for both overvoltage (HVD) and undervoltage (LVD).

[0073] In existing technologies, a separate system is typically set up for each voltage domain, such as... Figure 1 The voltage detector shown. Specifically, as... Figure 6As shown, n voltage detectors VD1 to VDn are set for n different voltage domains of an integrated circuit, where n is an integer greater than 1. Each voltage detector is equipped with multiple series-connected detection resistors (used to form a detection resistor string for the voltage to be measured), a first comparator COMPh, and a second comparator COMPl. For example, a voltage detector VD1 in the first voltage domain (e.g., a low-voltage domain) has a first comparator COMPh_1, a second comparator COMP1_1, and detection resistors Rs_1, Rh_1, and Rl_1 connected in series. The detection resistor Rs_1 is connected to the voltage Vs_1 to be measured in the first voltage domain (e.g., a low-voltage domain). A voltage detector VD2 in the second voltage domain (e.g., a medium-voltage domain) has a first comparator COMPh_2, a second comparator COMP1_2, and detection resistors Rs_2, Rh_2, and Rl_2 connected in series. The detection resistor Rs_2 is connected to the voltage Vs_2 to be measured in the second voltage domain. Similarly, a voltage detector VDn in the nth voltage domain (e.g., a high-voltage domain) has a first comparator COMPh_n, a second comparator COMP1_n, and detection resistors Rs_n, Rh_n, and Rl_n connected in series. The detection resistor Rs_n is connected to the voltage Vs_n to be measured in the nth voltage domain.

[0074] While the above-described scheme can achieve overvoltage and undervoltage monitoring across n voltage domains, it still suffers from the following problems:

[0075] 1. In order to meet the requirements of low power consumption, the individual detection resistors in each voltage detector are usually of large resistance value, which results in the overall chip area occupied by the voltage detection circuit (i.e. the sum of voltage detectors in all voltage domains).

[0076] 2. Each sensing resistor in each voltage domain consumes a certain amount of power. Therefore, the contribution of the sensing resistors in all voltage domains to the chip's static power consumption, Pc_s, is approximately:

[0077]

[0078] As can be seen from the above formula, the detection resistors of the voltage detectors in these voltage domains are not reused (i.e., the detection resistors of different voltage domains are completely independent), which will result in a large standby power consumption of the product.

[0079] 3. The voltage to be measured in each voltage domain is input to the detection resistor string of the voltage detector in that voltage domain. Therefore, the detection resistor string of the voltage detector in each voltage domain will form a charging and discharging circuit with the gate capacitor at the input of the first comparator and the second comparator of the voltage detector, which will result in a large time delay for the voltage detector in each voltage domain.

[0080] Based on this, please combine Figure 2 and Figure 7This embodiment provides a voltage detection circuit, which includes n voltage detectors as described in this invention. Each of the n voltage detectors is configured to correspond one-to-one with n different voltage domains and is used for overvoltage and undervoltage monitoring of the n voltage domains, where n ≥ 2 and is an integer. The specific structure of each voltage detector can be found in [reference needed]. Figure 2 As shown, details will not be elaborated further here. Therefore, the voltage to be measured in each voltage domain is directly input to the corresponding input terminals of the first and second comparators of its corresponding voltage detector. The reference voltage required by the voltage detector is input to the other corresponding input terminal of the first and second comparators through a resistor string divider. This avoids the resistor string of each voltage detector forming a charging / discharging circuit with the gate capacitance of its first and second comparators, thereby reducing the time delay of the voltage detector in each voltage domain.

[0081] Where circuit area and power consumption allow, the n voltage detectors can be independent of each other, that is, the first resistor and the second resistor are not reused among the n voltage detectors.

[0082] Preferably, in order to reduce circuit area and power consumption, please combine Figure 2 and Figure 7 In the voltage detection circuit of this embodiment, among the n voltage detectors, some or all of the first resistors and all of the second resistors in the voltage detectors are connected in series to form a voltage divider resistor string multiplexed by these voltage detectors. Alternatively, the first and second resistors in at least one voltage domain detector are connected in series with the first and second resistors in at least another voltage domain detector to form a voltage divider resistor string multiplexed by voltage detectors in different voltage domains. This allows the first and second resistors in some or all of the voltage domain detectors to be multiplexed, thereby reducing the overall circuit area occupied by the n voltage detectors.

[0083] In one example, please refer to Figure 7 The voltage detection circuit in this embodiment includes n voltage detectors VD1 to VDn, which are configured one-to-one with n different voltage domains. Each voltage detector VD1 to VDn has a first resistor (Rh_1 to Rh_n), a second resistor (Rl_1 to Rl_n), a first comparator (COMPh_1 to COMPh_n), and a second comparator (COMP1_1 to COMPh_n). lThe n voltage detectors VD1 to VDn are connected in series, forming a voltage divider resistor string multiplexed by the n voltage detectors. Specifically, the voltage detector VDn is set for the nth voltage domain and has a first resistor Rh_n, a second resistor Rl_n, a first comparator COMPh_n, and a second comparator COMP1_n. The first end of the first resistor Rh_n (i.e., connection node A_n) is connected to the second input terminal of the first comparator COMPh_n (e.g., its inverting input terminal "-"). The second end of the first resistor Rh_n (i.e., connection node B_n) is connected to the first input terminal of the second comparator COMP1_n (e.g., the non-inverting input terminal "+"). The voltage Vs_n to be measured in the nth voltage domain is input to the first comparator C. The first input terminal of OMPh_n (e.g., its non-inverting input "+") and the second input terminal of the second comparator COMP1_n (e.g., its inverting input "-"); the voltage detector VDn-1 is set according to the (n-1)th voltage domain and has a first resistor Rh_n-1, a second resistor Rl_n-1, a first comparator COMPh_n-1 and a second comparator COMP1_n-1. The first terminal of the first resistor Rh_n-1 (i.e., the connection node A_n-1) is connected to the second input terminal of the first comparator COMPh_n-1 (e.g., its inverting input "-"). The first resistor Rh_n... The second terminal of -1 (i.e., connection node B_n-1) is connected to the first input terminal of the second comparator COMP1_n-1 (e.g., its non-inverting input terminal "+"). The voltage to be measured Vs_n-1 in the (n-1)th voltage domain is input to the first input terminal of the first comparator COMPh_n-1 (e.g., its non-inverting input terminal "+") and the second input terminal of the second comparator COMP1_n-1 (e.g., its inverting input terminal "-"); and so on. The voltage detector VD1 is set according to the first voltage domain and has a first resistor Rh_1, a second resistor Rl_1, a first comparator COMPh_1, and a second comparator. Comparator COMP1_1 has its first terminal (connection node A_1) connected to the second input terminal (e.g., its inverting input "-") of the first comparator COMP1_1, and its second terminal (connection node B_1) connected to the first input terminal (e.g., its non-inverting input "+") of the second comparator COMP1_1. The voltage to be measured, Vs_1, in the first voltage domain is input to the first input terminal (e.g., its non-inverting input "+") of the first comparator COMP1_1 and the second input terminal (e.g., its inverting input "-") of the second comparator COMP1_1. Furthermore, the first resistor Rh_n, the second resistor Rl_n, the first resistor Rh_n-1, the second resistor Rl_n-1, ..., the first resistor Rh_1 and the second resistor Rl_1 are connected in series to form a voltage divider resistor string multiplexed by voltage detectors VD1 to VDn.An initial reference voltage Vref_n is directly input to the first terminal of the first resistor Rh_n or input to the first terminal of the first resistor Rh_n via the third resistor Rs_n. The different nodes A_1~A_n and B_1~B_n of the voltage divider resistor string formed by the series connection of all the first resistors and the second resistor are output as reference voltages VrefA_1~VrefA_n and VrefB_1~VrefB_n, and are correspondingly provided to the second input terminal (e.g., its inverting input terminal "-") of the first comparator and the second input terminal (e.g., its non-inverting input terminal "+") of the second comparator of the voltage detectors VD1~VDn. Among the reference voltages VrefA_1 to VrefA_n and VrefB_1 to VrefB_n received by voltage detectors VD1 to VDn, voltage detector VDn is the voltage detector that receives the initial reference voltage Vref_n, and its first comparator COMPh_n receives the largest reference voltage VrefA_n. Voltage detector VD1 is the voltage detector that receives the smallest reference voltage, and its second comparator COMP1_1 receives the smallest reference voltage VrefB_1.

[0084] Optionally, among the voltage detectors VD1 to VDn, only the voltage detector VDn (i.e., the voltage detector that receives the initial reference voltage Vref_n) has a third resistor Rs_n. The value of Rs_n depends on Vref_n, the rated power consumption requirement, and the threshold voltages of COMPh_n and COMP1_n.

[0085] Optionally, please combine Figure 8 Of the voltage detectors VD1 to VDn, only voltage detector VDn (i.e., the voltage detector that receives the initial reference voltage Vref_n) has a reference voltage adjustment circuit. This reference voltage adjustment circuit includes an operational amplifier OP and an adjustment circuit 10. The first input terminal "+" of the operational amplifier OP is coupled to the reference voltage VBG. The output terminal of the operational amplifier OP is directly coupled to the first terminal of the first resistor Rh_n of the voltage detector VDn, or indirectly coupled to the first terminal of the first resistor Rh_n of the voltage detector VDn through a third resistor Rs_n. The output terminal of the operational amplifier OP is used to output the reference voltage Vref_n. The adjustment circuit 10 is coupled to the output terminal of the operational amplifier OP and is used to adjust the magnitude of the reference voltage Vref_n output by the operational amplifier OP. The adjustment circuit 10 includes a variable resistor string and a grounding resistor R0. The variable resistor string includes fixed resistors R1 to Rm and electronic switches K1 to Km. The fixed resistors R1 to Rm are connected in series. The electronic switches K1 to Km are set one-to-one with each fixed resistor R1 to Rm and are connected in parallel across each fixed resistor R1 to Rm. The working principle of this reference voltage adjustment circuit can be found in the above text. Figure 3 The content description will not be repeated here.

[0086] It should also be understood that, in this example, the resistance values ​​of each resistor in the voltage divider resistor string (including the first resistor, the second resistor, and the third resistor) can be determined by a combination of factors, such as the threshold voltage required for low voltage (LVD) monitoring and overvoltage (HVD) monitoring in each voltage domain, and the rated current of the voltage divider resistor string.

[0087] In addition, from Figure 7 As can be seen from the diagram, the voltage detection circuit in this example divides an initial reference voltage Vrefn (which can be a fixed voltage value) using a voltage divider resistor string consisting of first resistors Rh_1~Rh_n and Rl_1~Rl_n. This voltage is then compared with the dynamically changing test voltages Vs_1~Vs_n in different voltage domains. This enables real-time monitoring of low voltage (LVD) and overvoltage (HVD) in both different and the same voltage domains. Furthermore, it allows for the reuse of the resistors (including the first, second, and third resistors) in the voltage divider resistor string formed by different voltage domains, thereby reducing circuit power consumption and size. Since the test voltage in each voltage domain is directly sent to the input of the comparator of the voltage detector corresponding to that voltage domain, the voltage divider resistor string does not undergo a charging and discharging process, thus reducing the time delay of the voltage detection circuit.

[0088] Fourth embodiment

[0089] In some integrated circuit applications with multiple voltage domains, in order to reduce power consumption and extend lifespan, one or more voltage domain circuits in the integrated circuit may have a low-power mode (also known as a standby mode) and a normal operating mode.

[0090] Based on this, please refer to Figure 9This embodiment provides a voltage detection circuit, which sets n voltage detectors VD1 to VDn for n different voltage domains of an integrated circuit, where n is an integer greater than 1. Each voltage detector is provided with multiple series-connected detection resistors (used to form a detection resistor string for the voltage to be measured), a first comparator COMPh and a second comparator COMPl. Among the voltage detectors VD1 to VDn, the voltage detector VDi set for the voltage domain with two modes (i.e., normal operation mode and low power mode) further has a third comparator COMPh'_i and a fourth comparator COMPl'_i. In the voltage detector VDi, the first input terminal of the first comparator COMPh_i (e.g., its non-inverting input "+") and the second input terminal of the second comparator COMP1_i (e.g., its inverting input "-") are both coupled to the voltage to be measured Vs_i_RUN (i.e., the first voltage to be measured) in the corresponding voltage domain under normal operating mode. The first input terminal of the third comparator COMPh'_i (e.g., its non-inverting input "+") and the second input terminal of the fourth comparator COMP1'_i (e.g., its inverting input "-") are both coupled to the voltage to be measured Vs_i_RUN in the same voltage domain under low-power mode. STBY (i.e., the second voltage to be measured), the second input terminal of the first comparator COMPh_i (e.g., its inverting input terminal "-") and the second input terminal of the third comparator COMPh'_i (e.g., its inverting input terminal "-") are both coupled to the first terminal of the first resistor Rh_i. The second terminal of the first resistor Rh_i is coupled to the first terminal of the second resistor Rl_i, the first input terminal of the second comparator COMP1_i (e.g., its non-inverting input terminal "+"), and the first input terminal of the fourth comparator COMP1'_i (e.g., its non-inverting input terminal "+"). The second terminal of the second resistor Rl_i is grounded.

[0091] In one example, the integrated circuit includes a core digital circuit and other circuitry, such as conventional analog circuits and power amplifier circuits. In normal operation mode, the entire integrated circuit is powered on. In low-power mode, most circuits except the core digital circuit enter a sleep state. Voltage detector VD1 is used to perform real-time monitoring of low voltage and overvoltage at different operating voltages (i.e., different voltage domains in the two modes) of the core digital circuit in both normal and low-power modes. Please refer to [reference needed]. Figure 9Among the voltage detectors VD1 to VDn, only voltage detector VD1 (i.e., the voltage detector that receives the minimum reference voltage) has a third comparator COMPh'_1 and a fourth comparator COMP1'_1. The first input terminal of the third comparator COMPh'_1 (e.g., its non-inverting input "+") and the second input terminal of the fourth comparator COMP1'_1 (e.g., its inverting input "-") are both coupled to the second voltage to be measured, Vs_1_STBY (i.e., the operating voltage of the corresponding circuit (e.g., the core digital circuit) in low-power mode) of voltage detector VD1. The first input terminal of the first comparator COMPh_1 (e.g., its non-inverting input "+") and the second comparator COMPh'_1 are coupled to the second comparator COMPh'_1. The second input terminal of MP1_1 (e.g., its inverting input terminal "-") is coupled to the first voltage to be measured Vs_1_RUN of voltage detector VD1 (i.e., the operating voltage of the first voltage domain in normal operating mode). The second input terminal of the first comparator COMPh_1 (e.g., its inverting input terminal "-") and the second input terminal of the third comparator COMPh'_1 (e.g., its inverting input terminal "-") are coupled to the first terminal of the first resistor Rh_1. The first input terminal of the second comparator COMP1_1 (e.g., its non-inverting input terminal "+") and the first input terminal of the fourth comparator COMP1'_1 (e.g., its non-inverting input terminal "+") are coupled to the second terminal of the first resistor Rh_1.

[0092] The circuit structure and specific connection method of the remaining voltage detectors VD2 to VDn in this example are the same as those in the third embodiment, and will not be described again here. Figure 9 The two measured voltages and threshold voltages in VD1_RUN and VD1_STBY are the same, but they are powered by two different power supplies (e.g., low-dropout linear regulators, LDOs). For example, in normal mode, LDO_RUN is used (at this time, the VD1_RUN part of the voltage detector VD1 is working), while in low-power mode, LDO_STBY is used (at this time, the PMIC no longer supplies power to some sub-modules, and the VD1_STBY part of the voltage detector VD1 is working). Of course, in order to ensure uninterrupted power supply when switching between the two modes, LDO_RUN and LDO_STBY may operate simultaneously for a short period of time.

[0093] Please combine Figure 9Assuming n=3, the reference voltages received by voltage detector VD2 are VrefB_2 (i.e., the threshold voltage monitored by LVD in the second voltage domain) and VrefA_2 (i.e., the threshold voltage monitored by HVD in the second voltage domain); the reference voltages received by voltage detector VD3 are VrefB_3 (i.e., the threshold voltage monitored by LVD in the third voltage domain) and VrefA_3 (i.e., the threshold voltage monitored by HVD in the third voltage domain); the third resistor is Rs_3; the initial reference voltage is Vref_3; and the rated current of the voltage divider resistor string formed by voltage detectors VD1 to VD3 is I. R Then we have:

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101] In the above formula, the seven resistance parameters Rs_3, Rl_1~Rl_3, and Rh_1~Rh_3 are unknowns to be determined, while the other parameters are known. They form a linear equation system, which can be solved according to the Cramer equation or by matrix inversion. Therefore, when manufacturing the voltage detection circuit, fixed resistors with corresponding resistance values ​​are selected as Rs_3, Rl_1~Rl_3, and Rh_1~Rh_3.

[0102] In summary, the voltage detection circuit of this embodiment can combine the solutions of the second and third embodiments to realize overvoltage (HVD) monitoring and undervoltage (LVD) monitoring in two modes across multiple voltage domains.

[0103] Fifth embodiment

[0104] Based on the same inventive concept, please refer to Figures 2 to 9This embodiment also provides a power management chip, which includes a voltage detection circuit as described in any embodiment of the present invention. This voltage detection circuit can provide the required operating voltage to multi-voltage domain circuits, such as providing low voltage (e.g., 0–1.1V) for digital circuits (e.g., core digital circuits), medium voltage (e.g., 2.5V or 3.3V) for conventional analog circuits, and high voltage (e.g., 5V or 12V) for power amplifier circuits. Simultaneously, to ensure the normal operation of circuits in each voltage domain and meet low power consumption requirements, the voltage detection circuit also needs to perform real-time monitoring of overvoltage (HVD) and undervoltage (LVD) of the operating voltage in each voltage domain.

[0105] Optionally, the power management chip further includes a core digital circuit (not shown), an analog circuit (not shown), and a power amplifier circuit (not shown) coupled to the voltage detection circuit in the power management chip. The core digital circuit is located in the low-voltage domain, with an operating voltage of, for example, 0–1.5V (e.g., 0.9V or 1.1V); the analog circuit is located in at least one medium-voltage domain, with operating voltages of, for example, 2V–4V (e.g., 2.5V or 3.3V); and the power amplifier circuit is located in at least one high-voltage domain, with operating voltages of, for example, 5V–12V (e.g., 5V or 12V).

[0106] Optionally, in the power management chip, the overvoltage detection signal output by the first comparator in the voltage detector set for the low-voltage domain of the voltage detection circuit is used to issue an interrupt to its core digital circuit; and / or, the low-voltage detection signal output by the second comparator in the voltage detector set for the low-voltage domain of the voltage detection circuit is used to reset the power management chip or issue an interrupt to its core digital circuit.

[0107] The power management chip in this embodiment, due to the use of the voltage detection circuit of the present invention, can simultaneously realize power supply in multiple voltage domains as well as overvoltage monitoring and undervoltage monitoring, while having low power consumption, small circuit area, and low latency.

[0108] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A voltage detector, characterized in that, The system includes a first comparator, a second comparator, a first resistor, and a second resistor. The first input terminal of the first comparator and the second input terminal of the second comparator are both coupled to a first voltage to be measured. The first terminal of the first resistor is directly or indirectly coupled to a corresponding reference voltage. The second input terminal of the first comparator is coupled to the first terminal of the first resistor. The second terminal of the first resistor is coupled to the first terminal of the second resistor and the first input terminal of the second comparator. The second terminal of the second resistor is grounded. The first comparator compares the voltage at the first terminal of the first resistor with the first voltage to be measured to detect overvoltage. The second comparator compares the first voltage to be measured with the voltage at the second terminal of the first resistor to detect undervoltage.

2. The voltage detector as described in claim 1, characterized in that, It also includes a third comparator and a fourth comparator. The first input terminal of the third comparator and the second input terminal of the fourth comparator are both coupled to the second voltage to be measured. The second input terminal of the third comparator is coupled to the first terminal of the first resistor, and the first input terminal of the fourth comparator is coupled to the second terminal of the first resistor. The third comparator is used to compare the voltage at the first end of the first resistor with the second voltage to be measured to achieve overvoltage monitoring of the second voltage to be measured, and the fourth comparator is used to compare the second voltage to be measured with the voltage at the second end of the first resistor to achieve undervoltage monitoring of the second voltage to be measured.

3. The voltage detector as described in claim 2, characterized in that, The first voltage to be measured is the operating voltage of the corresponding circuit in normal operating mode, and the second voltage to be measured is the operating voltage of the corresponding circuit in low power mode.

4. The voltage detector as described in any one of claims 1-3, characterized in that, The voltage detector further includes a reference voltage adjustment circuit, which includes an operational amplifier and an adjustment circuit. The first input terminal of the operational amplifier is coupled to a reference voltage, and the output terminal of the operational amplifier is used to provide the reference voltage. The adjustment circuit is coupled to the output terminal of the operational amplifier and the second input terminal of the operational amplifier, and is used to adjust the magnitude of the reference voltage output by the operational amplifier.

5. The voltage detector as described in claim 4, characterized in that, The tuning circuit includes a variable resistor string, which includes several fixed resistors and several electronic switches. The fixed resistors are connected in series, and each fixed resistor and each electronic switch are configured in parallel and correspond one-to-one. The first end of the variable resistor string is coupled to the output terminal of the operational amplifier, and the last end of the variable resistor string is coupled to the first end of a grounding resistor and the second input terminal of the operational amplifier. The second end of the grounding resistor is grounded.

6. The voltage detector as described in claim 5, characterized in that, The resistance values ​​of each resistor in the variable resistor string increase in binary order from beginning to end.

7. A voltage detection circuit, characterized in that, It includes at least two voltage detectors as described in any one of claims 1-6, each voltage detector being configured one-to-one with a different voltage domain and used for overvoltage monitoring and undervoltage monitoring of the circuits in each voltage domain, wherein the different voltage domains correspond to different reference voltages.

8. The voltage detection circuit as described in claim 7, characterized in that, The first and second resistors in at least one voltage domain of the voltage detector are connected in series with the first and second resistors in at least another voltage domain of the voltage detector to form a voltage divider resistor string multiplexed by the voltage detectors of different voltage domains.

9. The voltage detection circuit as described in claim 7, characterized in that, The first and second resistors in all the voltage detectors of the voltage detection circuit are connected in series to form a voltage divider resistor string that is multiplexed by voltage detectors in all voltage domains. An initial reference voltage is output as a reference voltage of different magnitude through different nodes of the voltage divider resistor string and provided to each of the voltage detectors. The resistance values ​​of each resistor in the voltage divider resistor string are determined by a combination of factors, including the threshold voltage for overvoltage monitoring and the threshold voltage for undervoltage monitoring of each voltage detector, and the rated current of the voltage divider resistor string.

10. The voltage detection circuit as described in claim 9, characterized in that, Of all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the initial reference voltage also has a third resistor, one end of which is coupled to the initial reference voltage and the other end of which is coupled to the beginning of the voltage divider resistor string. And / or, among all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the initial reference voltage also has a reference voltage adjustment circuit. The reference voltage adjustment circuit includes an operational amplifier and an adjustment circuit. The first input terminal of the operational amplifier is coupled to a corresponding reference voltage, and the output terminal of the operational amplifier is coupled to the voltage detector that receives the initial reference voltage. The adjustment circuit is coupled to the output terminal of the operational amplifier and the second input terminal of the operational amplifier and is used to adjust the magnitude of the initial reference voltage output by the operational amplifier.

11. The voltage detection circuit as described in claim 9, characterized in that, Of all the voltage detectors in the voltage detection circuit, only the voltage detector that receives the minimum reference voltage also has a third comparator and a fourth comparator. The first input terminal of the third comparator and the second input terminal of the fourth comparator are both coupled to the second voltage to be measured of the voltage detector that receives the minimum reference voltage. The second input terminal of the third comparator is coupled to the first terminal of the first resistor of the voltage detector that receives the minimum reference voltage, and the first input terminal of the fourth comparator is coupled to the second terminal of the first resistor of the voltage detector that receives the minimum reference voltage.

12. A power management chip, characterized in that, Includes the voltage detection circuit as described in any one of claims 7-11.

13. The power management chip as described in claim 12, characterized in that, It also includes a core digital circuit, an analog circuit, and a power amplifier circuit coupled to the voltage detection circuit, and the core digital circuit, the analog circuit, and the power amplifier circuit are distributed in different voltage domains.

14. The power management chip as described in claim 13, characterized in that, The overvoltage detection signal output by the first comparator is used to send an interrupt to the core digital circuit; and / or, the undervoltage detection signal output by the second comparator is used to reset the power management chip or send an interrupt to the core digital circuit.

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