Clock calibration method, computer equipment, readable storage medium and program product

Abstract

The invention relates to a clock calibration method, computer equipment, a readable storage medium and a program product. Acquiring a sleep clock count value of the control chip; under the condition that the control chip is in the dormant state, the RC calibration circuit is charged through the control chip, and the dormant timer is triggered to carry out clock counting; if it is monitored that the first actual clock count value of the sleep timer reaches the sleep clock count value, charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined; performing clock calibration on the dormancy timer according to the actual charging time and the dormancy clock count value; calibration operation can be completed in the dormancy process of the control chip, multiple requirements of low power consumption, high precision and low cost are considered, and the problems of large dormancy timing error and inaccurate system wakeup caused by factors such as unstable clock source and environment change are avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip clock calibration, and in particular to a clock calibration method, a computer device, a readable storage medium and a program product. BACKGROUND

[0002] With the change of economic environment and the intensification of market competition, the control requirements of product cost of various industries are increasingly improved, especially in large-scale mass production products, slight optimization of hardware cost can bring significant economic benefits. Under this background, chip localization has become an important means to reduce hardware cost, especially in application scenarios with large product shipments, using domestic chips not only helps to reduce procurement costs, but also enhances the self-controllability of the supply chain. However, some low-cost chips based on 51 kernel have a big problem in low-speed clock accuracy, which is significantly affected by factors such as temperature and voltage, and the deviation of some models is even as high as ± 50%, and the deviation between chips is irregular, which seriously affects the timing stability of the system. In the traditional scheme, high-speed clock or external RTC, high-precision crystal oscillator is often used for calibration, and the cost of external components is high, which limits its application in low-cost scenarios.

[0003] In view of the problem that low-cost chips in the related art cannot balance clock calibration accuracy and hardware cost when performing clock calibration, there is currently no effective solution. SUMMARY

[0004] Therefore, it is necessary to provide a clock calibration method, a computer device, a readable storage medium and a program product in view of the above technical problems.

[0005] In a first aspect, the present application provides a clock calibration method applied to a control chip, wherein the control chip comprises a sleep timer; the method comprises:

[0006] obtaining a sleep clock count value of the control chip;

[0007] charging an RC calibration circuit and triggering the sleep timer to perform clock counting through the control chip in the case that the control chip is in a sleep state;

[0008] if a first actual clock count value of the sleep timer reaches the sleep clock count value is monitored, charging of the RC calibration circuit is stopped, and an actual charging time of the RC calibration circuit is determined;

[0009] performing clock calibration on the sleep timer according to the actual charging time and the sleep clock count value.

[0010] In one of the embodiments, the obtaining of the sleep clock count value of the control chip comprises:

[0011] obtaining a pre-calibrated low-speed clock period and a sleep reference time;

[0012] determining a sleep clock count value according to the pre-calibrated low-speed clock period and the sleep reference time.

[0013] In one embodiment, the obtaining of the pre-calibrated low-speed clock period comprises:

[0014] After each power-on of the control chip, if the control chip receives a first data frame sent by an external host, the control chip enters a sleep state and triggers the sleep timer to perform clock counting;

[0015] Until the control chip receives a next data frame, the control chip exits the sleep state and reads the clock count value of the sleep timer to obtain a second actual clock count value;

[0016] determining a first actual low-speed clock period corresponding to the sleep timer according to a data frame sending period corresponding to the external host and the second actual clock count value;

[0017] performing clock pre-calibration on a low-speed clock corresponding to the sleep timer according to the first actual low-speed clock period to obtain a pre-calibrated low-speed clock period.

[0018] In one embodiment, the RC calibration circuit comprises a capacitor and a resistor; the resistor and the capacitor are connected in series between a preset interface of the control chip and the ground; and the determining of the actual charging time of the RC calibration circuit comprises:

[0019] sampling a voltage of the capacitor to obtain a target voltage sampling value;

[0020] determining a target charging time matching the target voltage sampling value from a preset charging characteristic mapping table according to the target voltage sampling value;

[0021] determining the target charging time as the actual charging time of the RC calibration circuit.

[0022] In one embodiment, the control chip is provided with a high-speed timer; and the sampling of the voltage of the capacitor to obtain the target voltage sampling value comprises:

[0023] sampling a charging voltage of the capacitor to obtain an actual voltage sampling value;

[0024] obtaining a voltage compensation parameter corresponding to the capacitor;

[0025] performing voltage compensation on the actual voltage sampling value according to the voltage compensation parameter to obtain the target voltage sampling value.

[0026] In one of the embodiments, the preset charging characteristic mapping table comprises a correspondence between a plurality of charging times and a plurality of theoretical voltage sampling values; and the obtaining of the voltage compensation parameter corresponding to the capacitance comprises:

[0027] charging the capacitance by the control chip when the control chip is in a non-sleep state;

[0028] timing the charging time of the capacitance by a preset reference clock until the charging time of the capacitance reaches a preset timing time, and sampling the charging voltage of the capacitance to obtain a to-be-calibrated initial voltage sampling value;

[0029] determining a target theoretical voltage sampling value corresponding to the preset timing time from the preset charging characteristic mapping table;

[0030] determining a voltage compensation parameter according to a voltage sampling value deviation between the to-be-calibrated initial voltage sampling value and the target theoretical voltage sampling value.

[0031] In one of the embodiments, the clock calibration of the sleep timer according to the actual charging time and the sleep clock count value comprises:

[0032] obtaining a sleep reference time;

[0033] determining a second actual low-speed clock period according to the actual charging time and the sleep clock count value;

[0034] determining a first calibration clock count value according to the second actual low-speed clock period and the sleep reference time;

[0035] calibrating the sleep timer according to the first calibration clock count value.

[0036] In one of the embodiments, the method further comprises:

[0037] calculating, by a high-speed timer in the control chip, a program execution time required for the control chip to enter a sleep state when the control chip is in a non-sleep state;

[0038] determining a program execution clock count value according to the program execution time and a high-speed clock period of the high-speed timer;

[0039] determining a second calibration clock count value as a difference between the first calibration clock count value and the program execution clock count value;

[0040] calibrating the sleep timer according to the second calibration clock count value.

[0041] In a second aspect, the present application also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in any one of the embodiments of the first aspect when executing the computer program.

[0042] In a third aspect, the present application also provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the method in any one of the embodiments of the first aspect when executed by a processor.

[0043] In a fourth aspect, the present application also provides a computer program product, comprising a computer program, and the computer program implements the steps of the method in any one of the embodiments of the first aspect when executed by a processor.

[0044] The clock calibration method, the computer device, the readable storage medium and the program product; the sleep clock count value of the control chip is obtained; in the case that the control chip is in the sleep state, the RC calibration circuit is charged and the sleep timer is triggered to count the clock by the control chip; if the first actual clock count value of the sleep timer reaches the sleep clock count value, the charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined; the sleep timer is calibrated according to the actual charging time and the sleep clock count value. The clock is calibrated based on the RC calibration circuit, without relying on external high-cost crystal oscillator or RTC module, effectively reducing the hardware cost and system complexity; at the same time, the calibration operation can be completed during the sleep process of the control chip, meeting the multiple requirements of low power consumption, high precision and low cost, and avoiding the problems of large sleep timing error and inaccurate system wake-up caused by unstable clock source, environmental changes and other factors. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0046] Figure 1 It is a flowchart of the clock calibration method in an embodiment;

[0047] Figure 2 It is a working principle diagram of the RC calibration circuit in an embodiment;

[0048] Figure 3 It is a flowchart of the step of obtaining the pre-calibrated low-speed clock period in an embodiment;

[0049] Figure 4 Flowchart for determining actual charging time steps in one embodiment;

[0050] Figure 5 Flowchart for obtaining voltage compensation parameters in one embodiment;

[0051] Figure 6 Flowchart for clock calibration of the sleep timer in one embodiment;

[0052] Figure 7 Internal structure diagram of the computer device in one embodiment. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0054] With the change of economic environment and the intensification of market competition, the control requirements of product cost in various industries are increasing, especially in large-scale mass production products, slight optimization of hardware cost can bring significant economic benefits. Under this background, chip localization has become an important means to reduce hardware cost, especially in application scenarios with large product shipments, using domestic chips not only helps to reduce procurement costs, but also enhances the self-controllability of the supply chain. However, some low-cost chips based on 51 core have a big problem in low-speed clock accuracy, which is significantly affected by factors such as temperature and voltage, and the deviation of some models is even as high as ± 50%, and the deviation between chips is irregular, which seriously affects the stability of system timing. In the traditional scheme, high-speed clock or external RTC, high-precision crystal oscillator is often used for calibration, and the cost of external components is high, which limits its application in low-cost scenarios. Based on this, the present application provides a clock calibration method, which aims to effectively solve the clock deviation problem caused by the poor low-speed clock accuracy of the control chip under the premise of considering low-cost and low-power design, and improve the system timing accuracy and running reliability.

[0055] In one embodiment, as shown in Figure 1 Figure 1 ​Fig. 1 is a flowchart of a clock calibration method in an embodiment; the clock calibration method is applied to a control chip, wherein the control chip comprises a sleep timer; the control chip can but is not limited to comprise a 51-core control chip, which is not specifically limited herein; wherein the sleep timer is configured to count based on a low-speed clock source after the control chip enters a sleep state, and trigger wake-up when a preset value is reached. In an exemplary embodiment, when the control chip is a microchip in the CMS8S69xx series, the sleep timer is a WUT (Wake-up Timer) timer. It can be understood that, due to a large frequency deviation (up to ±50%) of the low-speed clock source (such as an internal RC oscillator) of such a control chip in a wide temperature range, the timing accuracy of the WUT timer cannot be guaranteed, which in turn makes it difficult to ensure that the control chip is accurately woken up at a predetermined time, affecting the reliable execution of system timing tasks and the real-time performance of communication responses; based on this, the clock calibration method provided by the present application can effectively solve the clock deviation problem caused by poor low-speed clock accuracy of the control chip on the premise of taking into account low-cost and low-power design; the clock calibration method comprises the following steps:

[0056] Step S101: obtaining a sleep clock count value of the control chip.

[0057] The sleep clock count value refers to a count target value of the sleep timer preset by the control chip before entering the sleep state.

[0058] In an exemplary embodiment, the sleep clock count value = sleep reference time / pre-calibrated low-speed clock period; wherein the sleep reference time refers to a target sleep duration that the system expects the control chip to maintain in a low-power sleep mode. The sleep reference time needs to be set according to specific application requirements, for example, it can be 25 ms, which is not specifically limited herein.

[0059] It should be noted that, since the low-speed clock frequency is greatly affected by factors such as temperature and voltage (e.g., ±50%), if the sleep clock count value is directly calculated based on the theoretical low-speed clock period, the actual sleep time will deviate greatly from the expected target; therefore, calculating the sleep clock count value based on the pre-calibrated low-speed clock period can provide reliable data basis for subsequent clock calibration that conforms to the actual situation.

[0060] Step S102: charging the RC calibration circuit by the control chip and triggering the sleep timer to count the clock under the condition that the control chip is in the sleep state.

[0061] The RC calibration circuit includes a capacitor and a resistor; the resistor and the capacitor are connected in series between a preset interface of the control chip and the ground; the preset interface is configured to provide a charging voltage for the RC calibration circuit. In an exemplary embodiment, the working principle diagram of the RC calibration circuit is shown in FIG. 1. The RC calibration circuit includes a resistor R1 and a capacitor C1, the resistor R1 and the capacitor C1 are connected in series between the preset interface of the control chip and the ground, forming a charging and discharging circuit; the ADC (Analog-to-Digital Converter) is configured to collect the voltage across the capacitor. The values of the resistor R1 and the capacitor C1 need to be set according to actual calibration requirements, which are not limited herein; for example, R1 = 100K and C1 = 0.1uF. Figure 2

[0062] In step S103, if the first actual clock count value of the sleep timer reaches the sleep clock count value, the charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined.

[0063] The method of determining the actual charging time of the RC calibration circuit can be: based on the charging voltage response characteristic of the RC calibration circuit, the actual charging time of the RC calibration circuit is determined by detecting the voltage across the capacitor when the charging is completed. It should be noted that during the charging process, the charging voltage V C (t) of the capacitor changes with time according to the following formula:

[0064] V C (t) = V0(1-e -t / τ );

[0065] wherein τ = R1 × C1; V C (t) is the voltage of the capacitor C1 at the charging time t; V0 is the voltage output by the preset interface of the control chip, i.e. the voltage of VCC (for example, VCC = 5V).

[0066] In step S104, the clock of the sleep timer is calibrated according to the actual charging time and the sleep clock count value.

[0067] ​In an exemplary embodiment, it is assumed that the sleep clock count value of the control chip is n; when the control chip is in the sleep state, the output of the preset interface of the control chip is configured to be high, the capacitor is charged, and the sleep timer is triggered to count the clock until the first actual clock count value of the sleep timer reaches the sleep clock count value n, the output of the preset interface of the control chip is configured to be low, the charging of the capacitor is stopped, and at the same time, the actual charging time of the RC calibration circuit is determined to be m us; further, according to the actual charging time m us and the sleep clock count value n, the current actual low-speed clock period T = m / n us can be calculated, further, it is assumed that the sleep reference time is 25 ms, then according to the current actual low-speed clock period T = m / n us, the calibration clock count value X = 25000 / T can be calculated, and further, based on the calibration clock count value X = 25000 / T, the sleep timer is calibrated, which can ensure the timing accuracy of the sleep timer, and further ensure that the control chip can be accurately awakened at the predetermined time.

[0068] It can be understood that the clock calibration process in the embodiment is carried out when the control chip enters the low-power sleep state (such as the STOP mode), which can fully utilize the limited resources during the sleep period, realize real-time calibration of the clock deviation, and fully consider the low-power design requirements of the system.

[0069] In the embodiment, the clock calibration is realized based on the RC calibration circuit, without relying on external high-cost crystal oscillators or RTC modules, which effectively reduces the hardware cost and system complexity; at the same time, the calibration operation can be completed during the sleep process of the control chip, which takes into account the multiple requirements of low power consumption, high precision and low cost, and avoids the problems of large sleep timing error and inaccurate system awakening caused by unstable clock source, environmental changes and other factors.

[0070] In an embodiment, the sleep clock count value of the control chip is obtained, including the following steps:

[0071] Step 1, obtaining the pre-calibrated low-speed clock period and the sleep reference time.

[0072] Step 2, determining the sleep clock count value according to the pre-calibrated low-speed clock period and the sleep reference time.

[0073] The pre-calibrated low-speed clock period refers to the low-speed clock period after preliminary calibration after each power-on of the control chip.

[0074] The sleep reference time refers to the target sleep time that the system expects the control chip to maintain in the low-power sleep mode. It should be noted that the sleep reference time needs to be set according to the specific application requirements, for example, the sleep reference time can be 25 ms, which is not limited here.

[0075] The sleep clock count value refers to a preliminary corrected count target value preset by the control chip for the sleep timer before entering the sleep state.

[0076] For example, assuming that the sleep reference time is 25 ms and the pre-calibrated low-speed clock period is T0, the sleep clock count value n = 25000 / T0 can be obtained.

[0077] It should be noted that although the low-speed clock has been pre-calibrated, the period T0 may still have residual deviations under actual working conditions (such as temperature and voltage changes), which may cause the sleep clock count value calculated based on the pre-calibrated low-speed clock period to be unable to completely ensure that the actual sleep duration is exactly equal to the sleep reference time. To ensure that the actual sleep duration is highly consistent with the set sleep reference time, further correction of the sleep clock count value is required to achieve high-precision clock calibration of the sleep timer.

[0078] In this embodiment, the pre-calibrated low-speed clock period and the set sleep reference time are obtained, and the sleep clock count value is determined based on the two, thereby achieving preliminary precision optimization of the sleep timer without relying on an external high-precision clock source.

[0079] In one embodiment, as shown in Figure 3 , the flowchart of the step of obtaining the pre-calibrated low-speed clock period in one embodiment is shown; obtaining the pre-calibrated low-speed clock period includes the following steps: Figure 3

[0080] Step S301: After each power-on of the control chip, if the control chip receives the first data frame sent by the external host, the control chip enters the sleep state and triggers the sleep timer to perform clock counting.

[0081] The external host can be, but is not limited to, an upper computer or a master control device with data communication and control functions; the external host is in communication connection with the control chip.

[0082] It should be noted that in this embodiment, the data frame sending period of the external host has high time accuracy. Since the UART communication frame on the external host side is driven by the internal high-precision clock source and sent according to a fixed timing mechanism, the time interval between adjacent data frames remains highly stable. Specifically, the time interval from the end of the current data frame to the start of the next frame is a fixed value, denoted as T2. For example, if the external host is set to send one frame of communication data every 100 ms, the time interval T2 = 100 ms; the constant is strictly maintained at the host end and is not affected by significant clock drift. This stable sending period characteristic makes the data frame sending period T2 an important reference for clock synchronization and calibration at the initial power-on of the control chip.​

[0083] Step S302, until the control chip receives the next data frame, exit the sleep state and read the clock count value of the sleep timer, get the second actual clock count value.

[0084] Wherein, the second actual clock count value, refers to the number of clock pulses actually accumulated by the sleep timer based on the low-speed clock source during the period from the control chip receiving the first data frame into the sleep state to being woken up by external communication.

[0085] Step S303, according to the data frame sending period corresponding to the external host and the second actual clock count value, determine the first actual low-speed clock period corresponding to the sleep timer.

[0086] Step S304, according to the first actual low-speed clock period, clock pre-calibration is performed on the low-speed clock corresponding to the sleep timer, get the pre-calibrated low-speed clock period.

[0087] Exemplarily, the RXD pin of the control chip is configured in the interrupt (such as falling edge) trigger mode for detecting the start bit of the data frame sent by the external host. After the control chip is powered on and initialized, the first data frame sent by the external host is received through the RXD pin. After the frame data is completely received and processed, the low-power sleep state (such as STOP mode) is entered, and the sleep timer (such as WUT) is started to count based on the internal low-speed clock. When the external host sends the next data frame according to the fixed data frame sending period T2, the start bit (falling edge) of the data frame triggers the interrupt through the RXD pin, so that the chip is woken up from the sleep state. After waking up, the program immediately reads the current count value of the sleep timer, which is recorded as the second actual clock count value a. Based on this, according to the data frame sending period T2 corresponding to the external host and the second actual clock count value a, the first actual low-speed clock period corresponding to the sleep timer can be determined as T2 / a.

[0088] Further, in order to ensure the accuracy of the first actual low-speed clock period, the first actual low-speed clock period can also be calibrated multiple times through software filtering. The specific calibration method can refer to the software calibration method in the prior art, which is not described here.

[0089] It should be noted that the low-speed clock cycle pre-calibration method described in this embodiment is performed only once during the power-on initialization phase of the control chip. During this process, the control chip enters a sleep state after receiving and processing the first data frame. At this time, the RXD pin is configured in edge-interrupt mode to detect the start bit of the next frame. When the host sends the second data frame, the falling edge of its start bit can trigger the chip to wake up. However, since the control chip is in a sleep state and the UART is not yet ready, it cannot complete the reception of this frame's data, and therefore, this frame's data will inevitably be lost. To avoid communication frame loss affecting normal system operation, the low-speed clock cycle pre-calibration is performed only once after the control chip powers on, and this calibration process is not repeated during subsequent normal operation, ensuring stable and reliable data interaction with the external host.

[0090] In this embodiment, the high-precision data frame transmission period of the external host is used as a time reference, and clock calibration of the internal low-speed clock during the power-on initialization phase can be achieved without additional hardware, laying the foundation for further clock calibration.

[0091] In one embodiment, such as Figure 4 As shown, Figure 4 This is a flowchart illustrating the steps for determining the actual charging time in one embodiment; determining the actual charging time of the RC calibration circuit includes the following steps:

[0092] Step S401: Sample the voltage of the capacitor to obtain the target voltage sample value.

[0093] In one exemplary embodiment, the control chip is equipped with a high-speed timer; it should be noted that the high-speed timer has a high-precision, high-speed clock source; sampling the voltage of the capacitor to obtain the target voltage sample value includes the following steps:

[0094] Step 1: Sample the charging voltage of the capacitor to obtain the actual voltage sample value.

[0095] The actual voltage sample value refers to the raw voltage data obtained by sampling the voltage across the capacitor through the ADC (analog-to-digital converter) built into the control chip.

[0096] Step 2: Obtain the voltage compensation parameters corresponding to the capacitor.

[0097] Among them, the voltage compensation parameter is used to correct the error of the actual voltage sampling value and compensate for systematic measurement deviations and RC device deviations.

[0098] Step 3: Perform voltage compensation on the actual voltage sample value according to the voltage compensation parameters to obtain the target voltage sample value.

[0099] At step S402, the target charging time matching the target voltage sampling value is determined from the preset charging characteristic mapping table according to the target voltage sampling value.

[0100] At step S403, the target charging time is determined as the actual charging time of the RC calibration circuit.

[0101] The preset charging characteristic mapping table includes the corresponding relationship between the plurality of charging times and the plurality of theoretical voltage sampling values.

[0102] It can be understood that, by pre-establishing the corresponding relationship between the theoretical voltage sampling value and the charging time and storing the preset charging characteristic mapping table in the control chip, the target charging time matching the target voltage sampling value can be directly obtained by table lookup after the target voltage sampling value is detected, avoiding the calculation overhead and delay caused by real-time solving of the charging time, reducing the calculation overhead of clock calibration, and improving the system response speed and energy efficiency.

[0103] In an exemplary embodiment, the preset charging characteristic mapping table can be established based on the following formula:

[0104] V C (t) = V0(1-e -t / τ );

[0105] Wherein, τ = R1xC1, V C (t) is the voltage of the capacitor C1 at the charging time t; V0 is the voltage output by the control chip preset interface, i.e. the voltage of VCC (for example, VCC = 5V).

[0106] Taking the scale of time t as 50us for example, when time t is equal to 50us, 100us, 150us, …, each corresponds to a V C (t) voltage value, the V C (t) voltage value is converted into an ADC sampling value and stored in the table to obtain the preset charging characteristic mapping table as shown in Table 1. Further, according to the target voltage sampling value, the target charging time matching the target voltage sampling value can be determined from the preset charging characteristic mapping table by table lookup, reducing the calculation consumption of the control chip; it can be understood that the smaller the scale of time t, the smaller the clock calibration error, and the scale of time t can be set according to actual calibration requirements, which is not specifically limited here.

[0107] Table 1: Preset charging characteristic mapping table

[0108]

[0109] It should be noted that, according to the preset charging characteristic mapping table shown in Table 1, the capacitor charging voltage gradually decreases over time, especially after exceeding 2τ (i.e., twice the time constant), the voltage change tends to saturate, and the time resolution capability decreases significantly. Therefore, to ensure the sensitivity and accuracy of charging time measurement, the charging interval within the range of 0 to 2τ is preferred as the calibration working interval.

[0110] Furthermore, to ensure accurate matching of actual charging time under all operating conditions, the preset charging characteristic mapping table should cover the maximum time drift range caused by low-speed clock deviation. For example, if the theoretically set sleep reference time is 5 ms, the actual sleep time may fluctuate between 2.5 ms and 7.5 ms because the frequency deviation of the low-speed clock can reach ±50% under wide temperature and variable voltage conditions. Therefore, the corresponding RC charging time measurement range should cover this range as much as possible.

[0111] In this embodiment, by pre-establishing the correspondence between theoretical voltage sampling values ​​and charging times and storing it in the control chip in the form of a preset charging characteristic mapping table, the target charging time can be directly obtained by looking up the table after detecting the target voltage sampling value. This avoids the computational overhead of real-time calculation of charging time, reduces the computational overhead of clock calibration, and improves system response speed and energy efficiency. Simultaneously, by obtaining voltage compensation parameters to correct errors in actual voltage sampling values, systematic measurement deviations can be effectively compensated, further ensuring the reliability of clock calibration.

[0112] In one embodiment, such as Figure 5 As shown, Figure 5 This is a flowchart illustrating the steps for obtaining voltage compensation parameters in one embodiment; obtaining the voltage compensation parameters corresponding to the capacitor includes the following steps:

[0113] Step S501: When the control chip is in a non-sleep state, the capacitor is charged through the control chip.

[0114] Step S502: The charging time of the capacitor is timed using a preset reference clock until the charging time reaches the preset timing time. The charging voltage of the capacitor is sampled to obtain the initial voltage sampling value to be calibrated.

[0115] The preset reference clock is either a high-speed clock source corresponding to the high-speed timer of the control chip, or the preset reference clock is provided by an external host.

[0116] It should be noted that the RC calibration circuit is composed of resistors and capacitors with conventional precision, and these discrete devices themselves have inherent tolerances. The precision of ordinary resistors and capacitors is generally ±5% or ±10%, and even at the same nominal value, the actual parameters can have significant deviations; while high-precision devices (such as ±0.1%) can reduce errors, but their cost increases significantly, which is not conducive to the realization of the overall cost reduction target of the product.

[0117] Therefore, in order to balance the cost and calibration accuracy, it is necessary to further compensate for the errors of the RC calibration circuit using conventional precision RC components. Generally, control chips (such as single-chip microcomputers based on 51 core) and external hosts are usually equipped with high-precision high-speed clock sources with good frequency stability and small clock deviation, which can be used to assist in calibrating the RC calibration circuit.

[0118] Among them, the preset charging time is set according to the actual calibration requirements, which is not limited here, for example, the preset charging time can be 5 ms.

[0119] Among them, the initial voltage sampling value to be calibrated refers to the original voltage data collected by the ADC (analog-to-digital converter) directly from the two ends of the capacitor in the RC calibration circuit before voltage compensation.

[0120] Step S503, determine the target theoretical voltage sampling value corresponding to the preset charging time from the preset charging characteristic mapping table.

[0121] In other exemplary embodiments, the determination method of the target theoretical voltage sampling value can also be: substituting the preset charging time into the formula V C (t) = V0(1-e -t / τ ), and directly calculating the corresponding target theoretical voltage sampling value; the determination method of the target theoretical voltage sampling value can be adaptively selected according to actual requirements, which is not limited here.

[0122] Step S504, determine the voltage compensation parameter according to the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

[0123] Exemplarily, when the control chip is in a non-sleep state, the output of the preset interface of the control chip is configured as high level to charge the capacitor. The charging time of the capacitor is timed by the preset reference clock until the charging time of the capacitor reaches the preset charging time (for example, 5 ms), the charging voltage of the capacitor is sampled to obtain the initial voltage sampling value to be calibrated; the target theoretical voltage sampling value corresponding to the preset charging time is determined from the preset charging characteristic mapping table; and the voltage compensation parameter is determined according to the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

[0124] It should be noted that the acquisition and updating of the voltage compensation parameter can be periodically performed, for example, the voltage compensation parameter acquisition process is triggered once in the system periodic wake-up window. By periodically collecting the voltage response characteristics of the RC circuit under the current environment, and combining the recalculation of the voltage compensation parameter, the measurement deviation caused by factors such as temperature drift, voltage fluctuation or device aging can be effectively compensated.

[0125] In this embodiment, by combining the high-precision time reference provided by the internal high-speed timer of the control chip or the external host, the parameter deviation of the conventional RC device can be effectively compensated without increasing the cost of high-precision components, and low-cost and high-reliability clock calibration can be realized.

[0126] In one embodiment, as shown in Figure 6 , Fig. 1 is a flowchart of the clock calibration step for the sleep timer in an embodiment; according to the actual charging time and the sleep clock count value, the sleep timer is clocked, including the following steps: Figure 6 Step S601, obtain the sleep reference time.

[0127] Step S602, according to the actual charging time and the sleep clock count value, determine the second actual low-speed clock period.

[0128] Exemplarily, the ratio result of the actual charging time and the sleep clock count value is determined as the second actual low-speed clock period, that is, the second actual low-speed clock period = actual charging time / sleep clock count value.

[0129] Step S603, according to the second actual low-speed clock period and the sleep reference time, determine the first calibration clock count value.

[0130] Exemplarily, the ratio result of the sleep reference time and the second actual low-speed clock period is determined as the first calibration clock count value, that is, the first calibration clock count value = sleep reference time / second actual low-speed clock period.

[0131] Step S604, according to the first calibration clock count value, clock the sleep timer.

[0132] Exemplarily, the sleep clock count value is updated to the first calibration clock count value, the clock of the sleep timer is calibrated, and the actual sleep time of the control chip is ensured to be consistent with the preset sleep reference time.

[0133]

[0134] ​It should be noted that the core purpose of clock calibration is to ensure that the actual sleep duration of the control chip is consistent with the preset sleep reference time. Since the sleep reference time is a fixed target value set according to application requirements, and the actual period of the low-speed clock is time-varying and belongs to a dynamic variable due to the influence of environmental factors such as temperature and voltage, if the sleep clock count value for sleep timing is still calculated based on the clock period without real-time correction, timing deviation will be accumulated.

[0135] Therefore, it is necessary to dynamically calculate and set the corresponding first calibration clock count value based on the low-speed clock period that reflects the current working condition in real time, and to calibrate the sleep timer. By including the two variables of the second actual low-speed clock period and the first calibration clock count value in the calibration logic, adaptive adjustment of the count value is realized, ensuring continuous approximation of the sleep reference time under different working conditions, and ultimately achieving high consistency between the actual sleep time and the sleep reference time, thereby improving the accuracy and reliability of system timing control.

[0136] In one embodiment, the clock calibration method further comprises the following steps:

[0137] Step 1, when the control chip is in a non-sleep state, calculating the program execution time required for the control chip to enter a sleep state by a high-speed timer in the control chip.

[0138] Wherein, the program execution time refers to the time consumed by program running between triggering sleep and actually entering a sleep state of the control chip.

[0139] Step 2, determining a program execution clock count value according to the program execution time and the high-speed clock period of the high-speed timer.

[0140] Step 3, determining the difference between the first calibration clock count value and the program execution clock count value as a second calibration clock count value.

[0141] Step 4, calibrating the sleep timer according to the second calibration clock count value.

[0142] Exemplarily, when the control chip is in a non-sleep state, the high-speed timer is started, and the program execution time required for the control chip to enter a sleep state is calculated by the high-speed timer; the ratio of the program execution time to the high-speed clock period of the high-speed timer is determined as the program execution clock count value; further, the difference between the first calibration clock count value and the program execution clock count value is determined as the second calibration clock count value; and the sleep clock count value is updated to the second calibration clock count value, thereby realizing clock calibration of the sleep timer.

[0143] In this embodiment, the timing deviation caused by software execution delay is further compensated, and the time control accuracy of the system in the sleep state is further improved.

[0144] In one specific embodiment, taking a microchip in the CMS8S69xx series as an example (the following description is based on the actual situation of the chip, and the chip specification book can be checked): (1) In order to minimize the power consumption of the product, the STOP sleep mode of the chip needs to be used. However, in this sleep mode, all circuits except the LVD module (low voltage detection module) and the LSE module (external low-speed clock timer) are turned off, and the digital circuit does not work. Among them, the LSE module needs an external crystal oscillator to work; the UART circuit cannot work when sleeping, and the product application layer must work after being awakened from sleep to work under high-speed clock. The high-speed clock and the low-speed clock cannot work at the same time. (2) Sleep awakening can only be achieved by external edge interrupt awakening, WUT timer awakening, and LSE timer awakening; among them, the WUT awakening timer can only work when entering the STOP sleep mode, uses a low-speed clock, and the sleep time is determined by the count value set by the WUT. Moreover, the WUT has no interrupt and can only be awakened from the STOP sleep mode when the WUT counts to the set value. In addition, the WUT uses a low-speed clock, and the clock deviation of the low-speed clock is in the range of ±50% at -40°C~105°C. The LSE has an interrupt awakening function but needs an external crystal oscillator to work.

[0145] In summary, the 51 core chip has the following problems: (1) The maximum deviation of the low-speed clock can be up to 50% and -50%, which is a large deviation and has a high risk of device stability, and clock calibration is necessary; (2) The key peripherals cannot work when sleeping and must work after being awakened, so the master and slave devices will send serial communication frames at regular intervals. Therefore, the serial communication must be awakened in advance to ensure that no frames are lost. If the clock deviation is large, the count will not be accurate, and it is easy to cause the loss of serial communication frames without pre-awakening. In order to ensure that no frames are lost, a large amount of time is awakened in advance, which greatly increases the power consumption of the product. (3) The high-speed clock and the low-speed clock cannot work at the same time, and the high-speed clock cannot be used to calibrate the low-speed clock. (4) There is no timer interrupt when sleeping, and the sleep time is determined by the set value of a specific timer. Due to the large deviation of the low-speed clock, the time deviation of each count value is large, resulting in a large sleep time deviation. Because there is no available timer when sleeping, the timing task of the product can only use the sleep time as a time base for cumulative counting. For example, if the WUT is set to sleep 25ms theoretically, the application layer task can be executed once every 2000ms / 25ms=80 times. If the 25ms clock deviation is large, the application layer task execution time deviation will be large, which will affect the product function.

[0146] Although the chip has certain limitations in performance, it has a significant cost advantage compared to similar products, which can significantly reduce the overall cost of hardware. Therefore, in the application scenario limited by cost, the chip is the preferred solution. Based on the clock calibration method described in the above embodiment, the key problem of large low-speed clock deviation can be effectively solved, thereby ensuring the stable operation and long-term reliability of the product under all working conditions.

[0147] In one specific embodiment, the clock calibration method is described by taking the power-on of the control chip as an example: after the control chip is powered on, if the control chip receives the first data frame sent by the external host, the control chip enters a sleep state and triggers a sleep timer to count the clock; until the control chip receives the next data frame, the control chip exits the sleep state and reads the clock count value of the sleep timer to obtain a second actual clock count value; according to the data frame sending period corresponding to the external host and the second actual clock count value, a first actual low-speed clock period corresponding to the sleep timer is determined; according to the first actual low-speed clock period, the low-speed clock corresponding to the sleep timer is pre-calibrated to obtain a pre-calibrated low-speed clock period.

[0148] Further, when the control chip is in a non-sleep state, the control chip charges the capacitor; the charging time of the capacitor is timed by a pre-set reference clock, and when the charging time of the capacitor reaches a pre-set timing time, the charging voltage of the capacitor is sampled to obtain a to-be-calibrated initial voltage sampling value; a target theoretical voltage sampling value corresponding to the pre-set timing time is determined from a pre-set charging characteristic mapping table; and a voltage compensation parameter is determined according to the voltage sampling value deviation between the to-be-calibrated initial voltage sampling value and the target theoretical voltage sampling value.

[0149] Further, a sleep reference time is obtained; and a sleep clock count value is determined according to the pre-calibrated low-speed clock period and the sleep reference time. When the control chip is in a sleep state, the RC calibration circuit is charged by the control chip and the sleep timer is triggered to count the clock; if the first actual clock count value of the sleep timer is monitored to reach the sleep clock count value, the charging of the RC calibration circuit is stopped, and the charging voltage of the capacitor is sampled to obtain an actual voltage sampling value; the actual voltage sampling value is voltage-compensated according to the voltage compensation parameter to obtain a target voltage sampling value; according to the target voltage sampling value, a target charging time matching the target voltage sampling value is determined from the pre-set charging characteristic mapping table; and the target charging time is determined as the actual charging time of the RC calibration circuit. The sleep timer is calibrated according to the actual charging time and the sleep clock count value.

[0150] It can be understood that the pre-calibration process of the low-speed clock cycle is only performed once in the control chip power-on initialization stage to determine the sleep clock count value. The subsequent voltage compensation parameter determination process and the clock calibration process of the sleep timer can be periodically or on-demand triggered dynamic updates according to the changes of the system running environment (such as temperature fluctuation, voltage drift, etc.).

[0151] It should be understood that, although each step in the flowchart involved in each embodiment as described above is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, there is no strict order limitation for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps.

[0152] In an exemplary embodiment, a computer device, which can be a server, is provided, and an internal structure diagram thereof can be as shown in Figure 7 The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store clock calibration related data. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals through network connection. The computer program is executed by the processor to implement a clock calibration method.

[0153] Those skilled in the art can understand that Figure 7 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0154] In an embodiment, a computer device is also provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps in the above method embodiments when executing the computer program.

[0155] In an embodiment, a computer readable storage medium is provided, storing a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0156] In an embodiment, a computer program product is provided, comprising a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0157] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0158] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0159] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0160] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A clock calibration method, characterized by, The application is applied to a control chip, and the control chip comprises a sleep timer; the method comprises: obtaining a sleep clock count value of the control chip; in the case that the control chip is in a sleep state, charging an RC calibration circuit and triggering the sleep timer to perform clock counting through the control chip; if a first actual clock count value of the sleep timer reaches the sleep clock count value, stopping charging the RC calibration circuit, and determining an actual charging time of the RC calibration circuit; according to the actual charging time and the sleep clock count value, performing clock calibration on the sleep timer.

2. The method of claim 1, wherein, The method comprises: obtaining a pre-calibrated low-speed clock period and a sleep reference time; according to the pre-calibrated low-speed clock period and the sleep reference time, determining a sleep clock count value.

3. The method of claim 2, wherein, The method comprises: after each power-on of the control chip, if the control chip receives a first data frame sent by an external host, entering a sleep state and triggering the sleep timer to perform clock counting; until the control chip receives a next data frame, exiting the sleep state and reading a clock count value of the sleep timer, obtaining a second actual clock count value; according to a data frame sending period corresponding to the external host and the second actual clock count value, determining a first actual low-speed clock period corresponding to the sleep timer; according to the first actual low-speed clock period, performing clock pre-calibration on a low-speed clock corresponding to the sleep timer, obtaining a pre-calibrated low-speed clock period.

4. The method of claim 1, wherein, The RC calibration circuit comprises a capacitor and a resistor; the resistor and the capacitor are connected in series between a preset interface of the control chip and the ground; the method comprises: sampling a voltage of the capacitor, obtaining a target voltage sampling value; according to the target voltage sampling value, determining a target charging time matched with the target voltage sampling value from a preset charging characteristic mapping table; determining the target charging time as the actual charging time of the RC calibration circuit.

5. The method of claim 4, wherein, The control chip is provided with a high-speed timer; the method comprises: sampling a charging voltage of the capacitor, obtaining an actual voltage sampling value; obtaining a voltage compensation parameter corresponding to the capacitor; according to the voltage compensation parameter, performing voltage compensation on the actual voltage sampling value, obtaining a target voltage sampling value.

6. The method of claim 5, wherein, The preset charging characteristic mapping table comprises a corresponding relationship between a plurality of charging times and a plurality of theoretical voltage sampling values; the method comprises: charging the capacitor through the control chip when the control chip is in a non-sleep state; timing a charging time of the capacitor through a preset reference clock until the charging time of the capacitor reaches a preset timing time, sampling a charging voltage of the capacitor, obtaining a calibration initial voltage sampling value; The target theoretical voltage sampling value corresponding to the preset timing time is determined from the preset charging characteristic mapping table; The voltage compensation parameters are determined based on the voltage sampling value deviation between the initial voltage sampling value to be calibrated and the target theoretical voltage sampling value.

7. The method of claim 1, wherein, The step of clock calibration of the sleep timer based on the actual charging time and the sleep clock count value includes: Obtain the hibernation baseline time; The second actual low-speed clock cycle is determined based on the actual charging time and the sleep clock count value. The first calibration clock count value is determined based on the second actual low-speed clock cycle and the sleep reference time; The sleep timer is clock-calibrated based on the first calibration clock count value.

8. The method of claim 7, wherein, The method further includes: When the control chip is in a non-sleep state, the program execution time required for the control chip to enter a sleep state is calculated using a high-speed timer in the control chip. The program execution clock count value is determined based on the program execution time and the high-speed clock period of the high-speed timer; The difference between the first calibration clock count value and the program execution clock count value is determined as the second calibration clock count value; The sleep timer is clock-calibrated based on the second calibration clock count value. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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