Memory system initialization trigger

Abstract

The invention relates to a memory system initialization trigger. The memory system may receive a first command from a host device indicating that the memory system exits a sleep state, and the memory system initiates a wake-up procedure for a controller of the memory system in response to the first command, the wake-up program includes configuring an interface between the controller and one or more memory devices. The memory system may issue a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization program at the one or more memory devices prior to completing the configuration of the interface and in response to the first command, and the memory system may perform one or more access operations at the one or more memory devices based on triggering the initialization program.

Description

[0001] CROSS REFERENCE

[0002] The present application claims priority to U.S. Patent Application No. 19 / 185,033, entitled “MEMORY SYSTEM INITIALIZATION TRIGGER,” filed on April 21, 2025, by Yu, et al., and U.S. Provisional Patent Application No. 63 / 649,897, entitled “MEMORY SYSTEM INITIALIZATION TRIGGER,” filed on May 20, 2024, by Yu, et al., each of which is assigned to the assignee hereof and each of which is hereby expressly incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The technical field relates to memory system initialization triggers. BACKGROUND

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communications devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically denoted by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, “not-or” (NOR) and “and-not” (NAND) memory devices, and the like. Memory cells can be described in relation to a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time even in the absence of an external power source. Memory cells configured in a volatile configuration can lose a stored state when disconnected from an external power source. SUMMARY

[0006] A memory system is described. The memory system can include one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive, from a host device, a first command indicating the memory system to exit a sleep state, wherein the memory system comprises one or more memory devices; in response to the first command, initiate a wake-up procedure for a controller of the memory system, the wake-up procedure comprising configuring an interface between the controller and the one or more memory devices; prior to completing the configuring the interface and in response to the first command, issue a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization procedure at the one or more memory devices; and perform one or more access operations at the one or more memory devices in response to triggering the initialization procedure at the one or more memory devices.

[0007] A memory device is described. The memory device can include one or more memory arrays; a signal pin; and processing circuitry coupled with the signal pin and the one or more memory arrays and configured to cause the memory device to: receive, via the signal pin, a first signal to trigger an initialization procedure for the memory device in response to a transition of the signal pin from a first state to a second state; perform one or more access operations at the one or more memory arrays in response to the initialization procedure; and receive, via the signal pin, a second signal after completing the initialization procedure to abort access operations in response to a transition of the signal pin from the second state to the first state.

[0008] A method by a memory system is described. The method can include receiving, from a host device, a first command indicating the memory system to exit a sleep state, wherein the memory system comprises one or more memory devices; in response to the first command, initiating a wake-up procedure for a controller of the memory system, the wake-up procedure comprising configuring an interface between the controller and the one or more memory devices; prior to completing the configuring the interface and in response to the first command, issuing a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization procedure at the one or more memory devices; and performing one or more access operations at the one or more memory devices in response to triggering the initialization procedure at the one or more memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system to support triggering for an initialization procedure in accordance with examples disclosed herein is shown.

[0010] Figure 2 An example of a timing diagram that supports triggering of an initialization program is shown in accordance with the examples disclosed herein.

[0011] Figure 3 An example of a timing diagram that supports triggering of an initialization program is shown in accordance with the examples disclosed herein.

[0012] Figure 4A and Figure 4B An example of a timing diagram that supports triggering of an initialization program is shown in accordance with the examples disclosed herein.

[0013] Figure 5 A block diagram of a memory system that supports triggering of an initialization program is shown in accordance with the examples disclosed herein.

[0014] Figure 6 A flow diagram illustrating one or more methods that support triggering of a NAND initialization in accordance with the examples disclosed herein is shown. DETAILED DESCRIPTION

[0015] In some cases, a memory system, such as a managed NAND (mNAND) system, can be associated with a relatively large latency to exit a sleep state. For example, when a host device issues a command to cause the mNAND system to exit a sleep state, the mNAND system can first perform a wake-up procedure for hardware components of an integrated controller (e.g., an application-specific integrated controller (ASIC)). The wake-up procedure can include initialization for one or more interfaces (e.g., Open NAND Flash Interface (ONFI)). The interface, such as ONFI, can then trigger initialization for one or more NAND devices of the mNAND system. Thus, the initialization for the NAND devices does not begin until after the wake-up procedure for the ONFI has occurred, resulting in a long delay in read and query responses for the mNAND system. Additionally or alternatively, there can be a mismatch in ONFI configuration between the mNAND system and other systems (e.g., a Universal Flash Storage (UFS) system) that interface with the ONFI (e.g., due to a reboot that resets the ONFI configuration back to default values for another system), which can further cause issues between the mNAND system and the other system. Thus, techniques to trigger NAND initialization without relying on ONFI initialization can be desirable.

[0016] According to examples described herein, a memory system (e.g., an mNAND system) can perform an initialization procedure for one or more memory devices in parallel with a hardware wake-up procedure (e.g., for a controller). To perform the initialization procedure in parallel (e.g., at least partially in parallel) with the hardware wake-up procedure, the initialization procedure can be triggered by signaling one or more memory devices via a signal pin (e.g., an input / output (I / O) pad, a general purpose input output (GPIO) pad) of a controller of the memory system. In some examples, the memory system can include an additional signal pin dedicated to triggering the initialization procedure for the one or more memory devices. Additionally or alternatively, the memory system can repurpose one or more existing signal pins to trigger the initialization procedure. In some cases, after triggering the initialization procedure, the signal pin can be used to trigger a reset and a subsequent initialization procedure. Thus, the initialization procedure for the one or more memory devices can be performed at least partially in parallel with the hardware wake-up procedure, thereby reducing a wake-up latency of the memory system.

[0017] In addition to applicability in the memory systems described herein, the techniques for triggering an initialization procedure can also be implemented generally to improve performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications that include high-performance applications such as AI, AR, VR, and games can be associated with relatively high processing requirements to meet user expectations. Thus, improving the processing capabilities of electronic devices by shortening response times, improving power consumption, reducing complexity, increasing data throughput or access speed, shortening communication times, or increasing memory capacity or density, among other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve performance of electronic devices by reducing wake-up latency and improving read response and query response of memory systems, which can shorten response times or otherwise improve user experience, among other benefits.

[0018] Features of the disclosure are described in the context of a system, a device, and circuitry. Features of the disclosure are further illustrated and described in the context of drawings including timing diagrams and flowcharts.

[0019] Figure 1 An example of a system 100 that supports triggering for an initialization procedure in accordance with examples disclosed herein is shown. The system 100 can include a memory system 110 configured to store data received from a host system 105 and send the data to the host system 105 if requested by the host system 105 using an access command (e.g., a read command or a write command).

[0020] Memory system 110 can include one or more memory devices 140 to store data transferred between memory system 110 and host system 105 (e.g., in response to receiving access commands from host system 105). For example, memory devices 140 can include NAND memory, PCM, self-selecting memory, 3D cross-point or other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM, among other examples.

[0021] Memory system 110 can include a storage controller 130 to control the transfer of data to and from memory devices 140 (e.g., to store data, to retrieve data, to determine memory locations in which to store and retrieve data). Storage controller 130 can communicate with memory devices 140 using a memory interface 175, which can communicate with memory devices over a memory bus 178 (e.g., an ONFI bus), including using protocols specific to each type of memory device 140. In some cases, a single storage controller 130 can be used to control multiple memory devices 140 of the same or different types. In some cases, memory system 110 can include multiple storage controllers 130 (e.g., a different storage controller 130 for each type of memory device 140).

[0022] Memory system 110 can include an interface 120 to communicate with host system 105, and a buffer 125 to temporarily store data transferred between host system 105 and memory devices 140. Interface 120, buffer 125, and storage controller 130 can support the transfer of data between host system 105 and memory devices 140 (e.g., as shown by data path 150), and can be collectively referred to as data path components.

[0023] Temporarily storing data using buffer 125 during transfer can allow data to be buffered while a command is being processed, which can reduce latency between commands and can support arbitrary data sizes associated with commands. This can also allow for handling of command bursts, and buffered data can be stored or transmitted, or both (e.g., after a burst has stopped). Buffer 125 can include relatively fast memory (e.g., some types of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow data to be stored to and retrieved from buffer 125 quickly. Buffer 125 can include data path switching components for bidirectional data transfer between buffer 125 and other components.

[0024] The temporary storage of data within the buffer 125 can refer to storage of the data in the buffer 125 during execution of an access command. For example, after completion of an access command, the associated data can no longer be maintained in the buffer 125 (e.g., overwritten with data of an additional access command). In some examples, the buffer 125 can be a non-cached buffer. For example, the host system 105 can not directly read data from the buffer 125. In some examples, a read command can be added to a queue without an operation to match an address with an address already in the buffer 125 (e.g., without a cache address match or lookup operation).

[0025] The memory system 110 can also include a memory system controller 115 to execute commands received from the host system 105 (may include control of data path components for data movement). The bus 135 can be used for communication between system components.

[0026] In some cases, one or more queues (e.g., command queue 160, buffer queue 165, storage queue 170) can be used to control processing of access commands and movement of corresponding data. This can be beneficial, for example, in cases where more than one access command from the host system 105 is processed concurrently by the memory system 110. As an example of a possible implementation, the command queue 160, buffer queue 165, and storage queue 170 are depicted at the interface 120, memory system controller 115, and storage controller 130, respectively. However, the queues, if implemented, can be located anywhere within the memory system 110.

[0027] Data communicated between the host system 105 and the memory device 140 can be communicated along a different path in the memory system 110 than non-data information (e.g., commands, status information). For example, system components in the memory system 110 can communicate with each other using the bus 135, while data can be communicated using the data path 150 through data path components, rather than the bus 135. The memory system controller 115 can control how and whether data is communicated between the host system 105 and the memory device 140 by communicating with data path components via the bus 135 (e.g., using a protocol specific to the memory system 110).

[0028] If the host system 105 transmits an access command to the memory system 110, the interface 120 can receive the command (e.g., according to a protocol, such as the UFS protocol or the eMMC protocol). Thus, the interface 120 can be considered a front end of the memory system 110. After receiving each access command, the interface 120 can communicate the command to the memory system controller 115 (e.g., via the bus 135). In some cases, each command can be added to the command queue 160 by the interface 120 to communicate the command to the memory system controller 115.

[0029] The memory system controller 115 can determine that an access command has been received based on a communication from the interface 120. In some cases, the memory system controller 115 can determine that an access command has been received by retrieving the command from the command queue 160. After a command has been retrieved (e.g., by the memory system controller 115), the command can be removed from the command queue 160. In some cases, the memory system controller 115 can cause the interface 120 to remove the command from the command queue 160 (e.g., via the bus 135).

[0030] After determining that an access command has been received, the memory system controller 115 can execute the access command. For a read command, this can include obtaining data from one or more memory devices 140 and transmitting the data to the host system 105. For a write command, this can include receiving data from the host system 105 and moving the data to one or more memory devices 140. In either case, the memory system controller 115 can use the buffer 125 (among other things) for temporarily storing data received from or sent to the host system 105. The buffer 125 can be considered a mid-end of the memory system 110. In some cases, buffer address management (e.g., pointers to address locations in the buffer 125) can be performed by hardware (e.g., dedicated circuitry) in the interface 120, the buffer 125, or the memory controller 130.

[0031] To handle a write command received from the host system 105, the memory system controller 115 can determine whether the buffer 125 has sufficient available space to store data associated with the command. For example, the memory system controller 115 can determine (e.g., via firmware, via controller firmware) an amount of space within the buffer 125 that can be used to store data associated with a write command.

[0032] In some cases, a buffer queue 165 can be used to control a flow of commands associated with data stored in the buffer 125, including write commands. The buffer queue 165 can include access commands associated with data currently stored in the buffer 125. In some cases, commands in the command queue 160 can be moved to the buffer queue 165 by the memory system controller 115, and can remain in the buffer queue 165 while the associated data is stored in the buffer 125. In some cases, each command in the buffer queue 165 can be associated with an address at the buffer 125. For example, a pointer can be maintained that indicates where data associated with each command is stored in the buffer 125. Using the buffer queue 165, multiple access commands can be received sequentially from the host system 105 and at least portions of the access commands can be processed concurrently.

[0033] If the buffer 125 has sufficient space to store the write data, the memory system controller 115 can cause the interface 120 to transmit an indication of availability (e.g., a “ready to transfer” indication) to the host system 105, which can be performed in accordance with a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 120 receives data associated with a write command from the host system 105, the interface 120 can transfer the data to the buffer 125 for temporary storage using the data path 150. In some cases, the interface 120 can obtain a location within the buffer 125 for storing the data (e.g., from the buffer 125, from the buffer queue 165). The interface 120 can indicate to the memory system controller 115 (e.g., via the bus 135) whether the transfer of data to the buffer 125 has been completed.

[0034] After the write data has been stored in the buffer 125 by the interface 120, the data can be transferred out of the buffer 125 and stored in the memory devices 140, which can involve operations of the storage controller 130. For example, the memory system controller 115 can cause the storage controller 130 to retrieve the data from the buffer 125 and transfer the data to the memory devices 140 using the data path 150. The storage controller 130 can be viewed as a back end of the memory system 110. The storage controller 130 can indicate to the memory system controller 115 (e.g., via the bus 135) that the transfer of data to the one or more memory devices 140 has been completed.

[0035] In some cases, the storage queue 170 can support the transfer of write data. For example, the memory system controller 115 can push a write command from the buffer queue 165 (e.g., via the bus 135) to the storage queue 170 for processing. The storage queue 170 can include an entry for each access command. In some examples, the storage queue 170 can additionally include a buffer pointer (e.g., an address) that can indicate where in the buffer 125 the data associated with the command is stored and a storage pointer (e.g., an address) that can indicate a location in the memory devices 140 associated with the data. In some cases, the storage controller 130 can obtain a location within the buffer 125 from which to obtain the data (e.g., from the buffer 125, from the buffer queue 165, from the storage queue 170). The storage controller 130 can manage locations within the memory devices 140 for storing data (e.g., perform wear leveling, perform garbage collection, etc.). Entries can be added to the storage queue 170 (e.g., by the memory system controller 115). After the transfer of data is completed, the entries can be removed from the storage queue 170 (e.g., by the storage controller 130, by the memory system controller 115).

[0036] To handle a read command received from the host system 105, the memory system controller 115 can determine whether the buffer 125 has sufficient available space to store data associated with the command. For example, the memory system controller 115 can determine (e.g., via firmware, via controller firmware) an amount of space within the buffer 125 that is available to store data associated with a read command.

[0037] In some cases, the buffer queue 165 can support buffer storage of data associated with read commands in a manner similar to that discussed with respect to write commands. For example, if the buffer 125 has sufficient space to store read data, the memory system controller 115 can cause the storage controller 130 to retrieve data associated with a read command from the memory devices 140 and store the data in the buffer 125 for temporary storage using the data path 150. The storage controller 130 can indicate to the memory system controller 115 (e.g., via the bus 135) when the data transfer to the buffer 125 has been completed.

[0038] In some cases, the storage queue 170 can be used to assist in the transfer of read data. For example, the memory system controller 115 can push a read command to the storage queue 170 for processing. In some cases, the storage controller 130 can obtain (e.g., from the buffer 125, from the storage queue 170) a location within one or more memory devices 140 from which to retrieve data. In some cases, the storage controller 130 can obtain (e.g., from the buffer queue 165) a location within the buffer 125 for storing data. In some cases, the storage controller 130 can obtain (e.g., from the storage queue 170) a location within the buffer 125 for storing data. In some cases, the memory system controller 115 can move a command processed by the storage queue 170 back to the command queue 160.

[0039] After data has been stored in the buffer 125 by the storage controller 130, the data can be transferred out of the buffer 125 and sent to the host system 105. For example, the memory system controller 115 can cause the interface 120 to retrieve data from the buffer 125 using the data path 150 and transmit the data to the host system 105 (e.g., in accordance with a protocol, such as the UFS protocol or the eMMC protocol). For example, the interface 120 can process a command from the command queue 160 and can indicate to the memory system controller 115 (e.g., via the bus 135) that the data transfer to the host system 105 has been completed.

[0040] The memory system controller 115 can execute the received commands according to the order (e.g., a first-in, first-out order according to the order of the command queue 160). For each command, the memory system controller 115 can cause data corresponding to the command to move into and out of the buffer 125, as discussed herein. While data is moving into and stored within the buffer 125, the command can remain in the buffer queue 165. If processing of the command has been completed (e.g., if data corresponding to an access command has been transferred out of the buffer 125), the command can be removed (e.g., by the memory system controller 115) from the buffer queue 165. If a command is removed from the buffer queue 165, an address previously storing data associated with the command can be available for storing data associated with a new command.

[0041] In some examples, the memory system controller 115 can be configured for operations associated with the one or more memory devices 140. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., LBAs) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 140. For example, the host system 105 can issue a command indicating one or more LBAs, and the memory system controller 115 can identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs can correspond to non-contiguous physical block addresses. In some cases, the storage controller 130 can be configured to perform one or more of the described operations in conjunction with or in place of the memory system controller 115. In some cases, the memory system controller 115 can perform the functions of the storage controller 130, and the storage controller 130 can be omitted. The memory system controller 115, the interface 120, the buffer 125, the storage controller 130, and the bus 135 can be components of a controller integrated circuit, such as an ASIC.

[0042] In some cases, the memory system 100 can be associated with a relatively large sleep exit latency. For example, when the host system 105 issues a command to trigger the memory system 110 to exit a sleep state, the memory system 110 can first perform a wake-up procedure for hardware components of the memory system controller 115. The wake-up procedure can include initialization for one or more memory interfaces 175 (e.g., Open NAND Flash Interface (ONFI)). The initialization of the memory interface 175 can include initialization of a memory bus 178 (e.g., an ONFI bus), which can include training and parameter setting for the memory bus 178. The memory interface 175, such as ONFI, can then trigger initialization for one or more memory devices 140 of the memory system 110 (e.g., via the memory bus 178). Thus, in this example, the initialization for the memory devices 140 does not begin until after the wake-up procedure for the memory interface 175 has occurred, resulting in a long latency for read and query responses of the memory system 110. Additionally or alternatively, there can be a mismatch in ONFI configuration between the memory system 110 and other systems connected with the ONFI interface (e.g., Universal Flash Storage (UFS) systems), for example due to a reboot that resets the ONFI configuration back to a default value of another system, which can further cause issues between the memory system 110 and the other systems. Thus, techniques to trigger the initialization procedure without relying on ONFI can be desirable.

[0043] According to examples described herein, the memory system 110 can perform an initialization procedure for the memory devices 140 in parallel with a hardware wake-up procedure (e.g., for the controller IC 112). To perform the initialization procedure in parallel with the hardware wake-up procedure, the initialization procedure can be triggered by issuing a signal to the memory devices 140 via a signal pin 180 (e.g., an I / O pin) of the controller IC 112 of the memory system 110. The signal pin 180 can be separate from the memory bus 178. In some examples, the controller IC 112 can include an additional signal pin 180 dedicated to triggering the initialization procedure for the memory devices 140. Additionally or alternatively, the memory system can repurpose one or more existing signal pins 180 of the controller IC 112 to trigger the initialization procedure. In some cases, the existing signal pin can return to its original function after the initialization procedure. Additionally, the memory system 110 can override one or more trim parameters of the memory devices 140 to use the signal pin for the initialization procedure or a reset procedure.

[0044] The system 100 can include any number of non-transitory computer- readable media that support triggering of a NAND initialization. For example, the host system 105, the memory system 110, the controller IC 112, the memory system controller 115, or the memory device 140 can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 140. For example, such instructions, when executed by the host system 105, by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 140, can cause the host system 105, the memory system 110, or the memory device 140 to perform the associated functions described herein.

[0045] Figure 2 An example of a timing diagram 200 that supports triggering of an initialization procedure is shown in accordance with the examples disclosed herein. The timing diagram 200 illustrates how a memory system (e.g., with reference to the memory system 110 described herein) can initiate an initialization procedure 235 for one or more memory devices in parallel with a hardware wake-up procedure, as described herein. Figure 1

[0046] The memory system can receive a command 225 from the host system. The command 225 can trigger the memory system to exit a sleep command (e.g., explicitly, using a wake-up command; or implicitly, by issuing an access command or a query). At 205, the memory system can initiate a hardware wake-up procedure 230 (e.g., an ASIC wake-up procedure), which can begin to initialize one or more hardware components that include a controller or interface of the memory system. The memory system can also issue a signal via a signal pin of the controller (e.g., ASIC) to trigger an initialization procedure 235 for one or more memory devices prior to completing the hardware wake-up procedure 230.

[0047] In some examples, between 205 and 210, the host device can output a signal 240 that the host device is active, e.g., a user datagram protocol (UDP), such as a secure semi-reliable UDP (SSU). At 210, the hardware wake-up procedure 230 can end. The memory system can then issue a response 245 to the signal 240. After receiving the response 245, the host device can issue a message 250 indicating a query or read command. The memory system can issue a query response 255 in response to the message 250.

[0048] ​At 215, the initialization procedure 235 can end. The memory system can begin a load operation 260 to load configuration and tuning parameters for one or more memory systems. At 220, the memory system can perform a read operation 265 based on the message 250. In some examples, the read operation 265 can involve performing a scan of one or more memory systems and then performing one or more access commands. The memory system can then issue a read response 270 in response to the message 250. Thus, by performing the initialization procedure 235 in parallel with the hardware wake-up procedure 230, the memory system can reduce latency associated with the wake-up procedure, the query response 255, and the read response 270.

[0049] Figure 3 An example of a diagram 300 that supports triggering for an initialization procedure is shown in accordance with examples disclosed herein. The diagram 300 illustrates a state (e.g., electrical state) of a signal pin (e.g., pad) of a controller (e.g., ASIC) of a memory system, such as the memory system 110 described herein.

[0050] The signal pin can be a pin of a controller of the memory system and can be coupled with one or more pins of one or more memory devices to output signaling from the memory system to the one or more memory devices. For example, the signal pin can transition between a low state 305 (e.g., low voltage, zero voltage) and a high state 310 (e.g., high voltage). In some examples, the signal pin can be a dedicated signal pin for triggering an initialization procedure for one or more memory devices. Additionally or alternatively, the signal pin can have multiple functions. For example, the signal pin of one or more memory devices can be a write protect (WP) signal pin, a multi-die select (MDS) signal pin (e.g., MDS3 signal pin), or another signal pin. In some cases, the signal pin can be a GPIO pin of the controller that can drive one or more signal pins of one or more memory devices.

[0051] The signal pin can start in a low state 305. For example, the memory system can perform a power-up program in which a voltage of the memory system (e.g., a Vcc or Vccq voltage) is powered up to a respective threshold voltage. After the power-up program, the memory system (e.g., a controller of the memory system) can drive the signal pin from the low state 305 to a high state 310 (e.g., prior to completing a wake-up program for a controller or memory interface of the controller IC). The one or more memory devices can receive a signal via one or more respective pins that triggers an initialization 315-a (e.g., an initialization program) based on the signal pin transitioning from the low state 305 to the high state 310. For example, the transition from the low state 305 to the high state 310 can signal the one or more memory devices to begin the initialization 315-a. While FIG. 300 illustrates that the transition from the low state 305 to the high state 310 triggers the initialization 315-a, in other examples, a transition from the high state 310 to the low state 305 (e.g., or from any first state to a different second state) can also trigger the initialization 315-a.

[0052] In some cases, after the initialization 315-a, a transition of the signal pin between the high state 310 and the low state 305 can trigger a different operation for the one or more memory devices. In some examples, the signal pin can be used to reset the one or more memory devices. For example, the memory system can drive the signal pin from the high state 310 to the low state 305 and from the low state 305 to the high state 310 in order to trigger an initialization 315-b. In some examples, the initialization 315-b can be the same program as the initialization 315-a, and the initialization 315-b can fully reset the one or more memory devices. In some other examples, the initialization 315-b can trigger a reset for one or more components of the one or more memory devices, such as a reset for ONFI, or can trigger a reload for an ASIC ROM. Thus, the one or more memory devices can perform the initialization 315-b in response to (e.g., directly in response to) receiving the signal via the signal pin.

[0053] Additionally or alternatively, the signal pin can switch functions based on performing the initialization 315-a. For example, if the signal pin of the controller is a WP pin, the signal pin can return to a function associated with the WP after performing the initialization 315-a. For example, the signal pin can be used by the memory system to trigger one or more memory devices to abort (e.g., stop) a program operation or an erase operation, such as when the signal pin transitions from the high state 310 to the low state 305. Similarly, if the signal pin is an MDS pin, the signal pin can return to a function associated with the MDS pin after performing the initialization 315-a. For example, the signal pin can be configured to provide at least a portion of an address associated with one or more memory devices to the one or more memory devices. In some cases, for example, the MDS pin (e.g., MDS3 pin) can provide a fourth bit (e.g., most significant bit) associated with the address that can be the same for each of the one or more memory devices. In some examples, the function of the signal pin can switch such that the signal pin returns to being used for the initialization procedure, which will be described with reference to Figure 4A and 4B are described in more detail.

[0054] In some cases, if the signal pin is not to be used for the initialization 315-a, the controller can refrain from transitioning the signal pin from the low state 305 to the high state 310. This can enable the initialization 315-a to be triggered by an interface (e.g., ONFI) of the controller at a later time, such as after completion of a hardware wake-up procedure. In these cases, the signal pin can be used for the original function (e.g., WP or MDS). In some examples, the controller can update one or more trim parameters of the one or more memory devices to enable the signal pin to trigger the initialization 315-b (e.g., reset) of the one or more memory devices.

[0055] Thus, by signaling via the signal pin to trigger the initialization 315-a for the one or more memory devices, the memory system can begin the initialization procedure at an earlier time, such as in parallel with other hardware wake-up procedures, thereby reducing a latency associated with exiting a sleep state. Thus, the memory system can perform one or more access operations at the one or more memory devices with reduced latency.

[0056] Figure 4A and Figure 4B Examples of a diagram 400-a and a diagram 400-b that support triggering for an initialization procedure in accordance with examples as disclosed herein are shown. The diagram 400-a and the diagram 400-b illustrate states (e.g., electrical states) of pins (e.g., pads) of one or more memory devices driven by a controller (e.g., controller IC) of a memory system, such as the memory system 110 described herein, via a signal pin (e.g., GPIO signal pin).

[0057] Figure 400-a illustrates how a memory system can use a signal pin to trigger different operations at one or more memory devices. The memory system can receive a command from a host device indicating that the memory system exit a sleep state. In response to the command, the memory system can initiate a wake-up procedure for a controller (e.g., controller IC) of the memory system, which can involve configuring an interface (e.g., ONFI) between the controller and one or more memory devices. Prior to completing configuring the interface (e.g., at least partially in parallel), the memory system can signal via a signal pin of the controller, e.g., by transitioning the signal pin from a low state 405 to a high state 410. This can transition one or more pins of one or more memory devices coupled with the signal pin from a low state 405 to a high state 410, which can trigger initialization 415-a (e.g., an initialization procedure) of the one or more memory devices.

[0058] In some examples, after triggering initialization 415-a, the signal pin can be used for different functionality. For example, the signal pin can be a WP pin, and after initialization 415-a, the signal pin can be used by the memory system to abort a program operation, a read operation, or an erase operation, or a combination thereof, at the one or more memory devices. In some other examples, the signal pin can be a MDS pin (e.g., MDS3 pin), and the signal pin can indicate, to the one or more memory devices, at least a portion of an address associated with the one or more memory devices after triggering initialization 415-a.

[0059] The controller of the memory system can perform a trim overwrite 420 to update the functionality of the signal pin on the one or more memory devices. For example, after completing initialization 415-a, the controller can update one or more trim parameters (e.g., move trim) of the one or more memory devices. The trim overwrite 420 can change the behavior of the one or more memory devices in response to the signal signaled via the signal pin. For example, after the trim overwrite 420, the one or more memory devices can abort an operation 425, e.g., a program operation, an erase operation, a read operation, or a combination thereof, after the signal pin transitions from the high state 410 to the low state 405 (e.g., on a falling edge). Additionally or alternatively, the signal pin can perform initialization 415-b (e.g., a reset) based on transitioning from the low state 405 to the high state 410 (e.g., on a rising edge).

[0060] In some examples, it can be beneficial for the memory device to abort operation 425 prior to initialization 415-b such that all array commands are discarded prior to performing initialization 415-b. Thus, triggering abort operation 425 based on transitioning the signal pin to the low state 405 can cause abort operation 425 to precede initialization 415-b. In some cases, the memory system can wait for a reset timing 435 (e.g., 100 ns) from transitioning to the low state 405 to the transition to the high state 410 to trigger initialization 415-b. Thus, for example, the memory system can provide sufficient time for the one or more memory devices to abort operation 425 prior to performing initialization 415-b.

[0061] Additionally or alternatively, associating initialization 415-b with abort operation 425 can support resetting the one or more memory devices in the event of a power (e.g., voltage, such as Vcc) outage. For example, if a power outage occurs, the voltage of the signal pin can drop, transitioning to the low state 405. This can trigger the one or more memory devices to abort operation 425, and the one or more memory devices can stop all programming or erase programs. When the power (e.g., Vcc) returns to a threshold level, the signal pin can be driven back to the high state 410, which can trigger the one or more memory devices to reset based on initialization 415-b.

[0062] In some examples, as illustrated by diagram 400-b, the signal pin of the controller of the memory device can be configured to drive multiple pins of the one or more memory devices. For example, the signal pin (e.g., GPIO pin) can be coupled with a pin 430-a of the one or more memory devices (e.g., a dedicated reset pin) as well as a pin 430-b of the one or more memory devices (e.g., a WP pin or a MDS pin). Thus, the memory system can support signaling via multiple pins of the one or more memory devices using a single signal pin without the need for the memory system to support additional signal pins for initialization 415-a.

[0063] For example, the memory system can drive the signal pin from the low state 405 to the high state 410, which can drive both pin 430-a and pin 430-b from the low state 405 to the high state 410. The one or more memory devices can perform initialization 415-a based on detecting the pin 430-a transition to the high state 410. For example, the one or more memory devices can perform initialization 415-a based on the signal received via pin 430-a. The controller of the memory system can drive the signal pin from the high state 410 to the low state, which can drive both pin 430-a and pin 430-b from the high state 410 to the low state 405. The one or more memory system can detect the pin 430-b transition to the low state 405 and can suspend operation 425 (e.g., suspend a program operation, a read operation, an erase operation, or a combination thereof) in response. The controller can again drive the signal pin to the high state 410, which can trigger initialization 415-b at the one or more memory devices via pin 430-a.

[0064] In some examples, the controller can perform trim overwrite 420 to update one or more trim parameters and change the functionality of pin 430-a, pin 430-b, or both. For example, pin 430-a can be an MDS pin and can return to MDS functionality (e.g., indicate a portion of an address of the one or more memory devices) after initialization 415-a. After trim overwrite 420, pin 430-a can instead trigger initialization 415-b at the one or more memory devices when transitioning to the high state 410. Additionally or alternatively, the functionality of pin 430-b (which can be a WP pin) can be altered based on trim overwrite 420. For example, prior to trim overwrite 420, pin 430-b can cause suspension of program operations and erase operations at the one or more memory devices based on transitioning from the high state 410 to the low state 405. After trim overwrite 420, pin 430-b can additionally cause suspension of read operations based on transitioning from the high state 410 to the low state 405.

[0065] Thus, the controller can use one signal pin (e.g., a GPIO pin) to drive one or more pins (e.g., NAND pads) of the one or more memory devices, thereby supporting triggering of initialization 415-a in parallel with other hardware wake-up procedures (e.g., ASIC wake-up, GPIO wake-up) while preserving the functionality of existing pins at the one or more memory devices.

[0066] Figure 5 A block diagram 500 showing a memory system 520 that supports triggering for initialization procedures in accordance with examples as disclosed herein is shown. The memory system 520 can be as described with reference to Figure 1Examples of aspects of the memory system described in 4. The memory system 520, or various components thereof, can be examples of means for performing various aspects of NAND initialization as described herein. For example, the memory system 520 can include a command manager 525, a wake-up component 530, a signal component 535, an access component 540, a trim manager 545, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), can be in direct or indirect communication with one another (e.g., via one or more buses).

[0067] The command manager 525 can be configured as, or otherwise support, means for receiving, from a host device, a first command indicating that a memory system exits a sleep state, where the memory system includes one or more memory devices. The wake-up component 530 can be configured as, or otherwise support, means for, in response to the first command, initiating a wake-up procedure for a controller of the memory system, the wake-up procedure including configuring an interface between the controller and the one or more memory devices. The signal component 535 can be configured as, or otherwise support, means for, prior to completing configuring the interface and in response to the first command, issuing, via a signal pin of the controller, a first signal to the one or more memory devices to trigger an initialization procedure at the one or more memory devices. The access component 540 can be configured as, or otherwise support, means for, in response to triggering the initialization procedure at the one or more memory devices, performing one or more access operations at the one or more memory devices.

[0068] In some examples, the signal component 535 can be configured as, or otherwise support, means for, after completing the initialization procedure, issuing, via the signal pin of the controller, a second signal to the one or more memory devices to trigger a second initialization procedure for the one or more memory devices.

[0069] In some examples, the trim manager 545 can be configured as, or otherwise support, means for, after completing the initialization procedure and prior to issuing the second signal, updating one or more trim parameters of the one or more memory devices, where the second initialization procedure is triggered by the second signal in response to updating the one or more trim parameters.

[0070] In some examples, the signal component 535 can be configured as, or otherwise support, means for, issuing a third signal via a signal pin of the memory system to abort the access operations. In some examples, the third signal is configured to abort the access operations in response to the signal pin transitioning from a second state to a first state. In some examples, the signal pin includes a write protect pin or a multi-die select pin.

[0071] In some examples, the signal pin is configured to trigger an initialization procedure at the one or more memory devices in response to a transition of the signal pin from a first state to a second state.

[0072] In some examples, the signal pin is coupled with a first pin of the one or more memory devices and a second pin of the one or more memory devices. In some examples, a first signal is issued to the first pin of the one or more memory devices and the second pin of the one or more memory devices via the signal pin.

[0073] In some examples, the first pin is associated with triggering an initialization procedure for the one or more memory devices upon a transition of the signal pin from a first state to a second state, and the second pin is configured to abort an access operation for the one or more memory devices upon a transition of the signal pin from the second state to the first state. In some examples, the second pin is configured to provide at least a portion of an address associated with the one or more memory devices to the one or more memory devices.

[0074] In some examples, the functionality of the memory system 520, or various components thereof, can be supported by, or can involve, at least a portion of at least one processor, which can include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the functionality of the memory system 520, or various components thereof, can be implemented, at least in part, by instructions that can be executed by this at least one processor (e.g., stored in a memory, a non-transitory computer-readable medium).

[0075] Figure 6 A flow diagram illustrating a method 600 that supports triggering for initialization procedures in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a memory system or its components as described herein. For example, the operations of method 600 can be performed by a memory system as described with reference to Figures 1 to 5 In some examples, a memory system can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the functions described using special-purpose hardware.

[0076] At 605, the method can include receiving a first command from a host device indicating that a memory system exit a sleep state, where the memory system includes one or more memory devices. In some examples, aspects of the operation 605 can be performed by a command manager 525 as described with reference to Figure 5

[0077] ​At 610, the method can include, in response to the first command, initiating a wake-up procedure for a controller of a memory system, the wake-up procedure including configuring an interface between the controller and one or more memory devices. In some examples, aspects of operation 610 can be performed by a wake-up component 530 as described with reference to Figure 5

[0078] At 615, the method can include, prior to completing configuring the interface and in response to the first command, issuing a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization procedure at the one or more memory devices. In some examples, aspects of operation 615 can be performed by a signal component 535 as described with reference to Figure 5

[0079] At 620, the method can include, in response to triggering the initialization procedure at the one or more memory devices, performing one or more access operations at the one or more memory devices. In some examples, aspects of operation 620 can be performed by an access component 540 as described with reference to Figure 5

[0080] In some examples, an apparatus as described herein can perform one or more methods, such as method 600. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the disclosure, or any combination thereof:

[0081] Aspect 1 : A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions for, or any combination thereof: receiving, from a host device, a first command indicating that a memory system exits a sleep state, where the memory system includes one or more memory devices; in response to the first command, initiating a wake-up procedure for a controller of the memory system, the wake-up procedure including configuring an interface between the controller and the one or more memory devices; prior to completing the configuring the interface and in response to the first command, issuing a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization procedure at the one or more memory devices; and in response to triggering the initialization procedure at the one or more memory devices, performing one or more access operations at the one or more memory devices.

[0082] ​​​Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for issuing, via the signal pin of the controller, a second signal to the one or more memory devices to trigger a second initialization procedure for the one or more memory devices after completion of the initialization procedure.

[0083] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for updating one or more trim parameters of the one or more memory devices after completion of the initialization procedure and before issuing the second signal, wherein the second initialization procedure is triggered by the second signal in response to updating the one or more trim parameters.

[0084] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for issuing a third signal via the signal pin of the memory system to abort an access operation.

[0085] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of aspect 4, wherein the third signal is configured to abort the access operation in response to a transition of the signal pin from a second state to a first state.

[0086] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-5, wherein the signal pin includes a write protect pin or a multi-die select pin.

[0087] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-6, wherein the signal pin is configured to trigger the initialization procedure at the one or more memory devices in response to a transition of the signal pin from a first state to a second state.

[0088] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of aspect 7, wherein the signal pin is coupled with a first pin of the one or more memory devices and a second pin of the one or more memory devices, and the first signal is issued to the first pin of the one or more memory devices and the second pin of the one or more memory devices via the signal pin.

[0089] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, wherein the first pin is associated with triggering an initialization procedure for the one or more memory devices upon a transition of the signal pin from the first state to the second state, and the second pin is configured to abort an access operation for the one or more memory devices upon a transition of the signal pin from the second state to the first state.

[0090] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 8-9, wherein the second pin is configured to provide, to the one or more memory devices, at least a portion of an address associated with the one or more memory devices.

[0091] It should be noted that the techniques described can include possible implementations that can be practiced in various ways, and that the terminology used can be for the purpose of describing particular embodiments only and is not intended to be limiting. Further, it should be noted that the techniques described can include several no n-exclusively alternative implementations so that replacement of one implementation's parts for the parts of another can be done and still expect il to operate more or less similarly. Also, variations can be possible that would still fall under the scope of the claims.

[0092] An apparatus is described. Summaries of aspects of an apparatus as described herein are provided below:

[0093] Aspect 11 : A memory device, comprising: one or more memory arrays; a signal pin; and processing circuitry coupled with the signal pin and the one or more memory arrays and configured to cause the memory device to: receive, via the signal pin, a first signal to trigger an initialization procedure for the memory device in response to a transition of the signal pin from a first state to a second state; perform, in response to the initialization procedure, one or more access operations at the one or more memory arrays; and receive, via the signal pin, a second signal to abort an access operation after completion of the initialization procedure in response to a transition of the signal pin from the second state to the first state.

[0094] Aspect 12: The memory device of aspect 11, wherein the processing circuitry is further configured to cause the memory device to: receive, via the signal pin, a third signal to trigger a second initialization procedure for the memory device in response to a transition of the signal pin from the first state to the second state.

[0095] Aspect 13: The memory device of aspect 12, wherein the processing circuitry is further configured to cause the memory device to: update one or more trim parameters of the memory device, wherein the second initialization procedure is triggered by the signal pin in response to the update of the one or more trim parameters.

[0096] Aspect 14: The memory device of Aspect 13, wherein the signal pin indicates at least a portion of an address associated with the memory device relative to one or more additional memory devices for a duration of time after the initialization procedure and before the update of the one or more trim parameters.

[0097] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0098] The terms“electronic communication,”“electrically conductive contact,”“connected,” and“coupled” can refer to a relationship between components that supports the flow of signals between the components. Components are in electronic communication with one another (or are in electrically conductive contact with one another, or are connected to one another, or are coupled to one another) if there exists any electrically conductive path between the components that can support the flow of signals between the components at any time. The electrically conductive path between components that are in electronic communication with one another (or are in electrically conductive contact with one another, or are connected to one another, or are coupled to one another) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The electrically conductive path between connected components can be a direct electrically conductive path between the components, or the electrically conductive path between connected components can be an indirect electrically conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0099] The term“coupled” (e.g.,“electrically coupled”) can refer to a condition that moves from an open circuit relationship between components, in which signals cannot currently pass between the components through an electrically conductive path, to a closed circuit relationship between the components, in which signals can pass between the components through the electrically conductive path. If a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components through an electrically conductive path in which signals were not previously permitted to flow.

[0100] The term“isolated” refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from one another if there is an open circuit between the components. For example, components that are separated by a switch positioned between the two components are isolated from one another when the switch is open. If a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using an electrically conductive path in which signals were previously permitted to flow.

[0101] The terms “if’; “when,” “upon,” “based on” or “based at least in part on” can be used interchangeably. In some instances, the terms “if,” “when,” “upon,” “based on” or “based at least in part on” can be interchangeable if used to describe a conditional nature of how one action, condition, or process is connected to another action, condition, or process.

[0102] The term “in response to” can refer to a condition or action that occurs at least partially, if not entirely, as a result of a prior condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the prior condition or action, whether directly after the first condition or action or after one or more other intervening conditions or actions after the first condition or action.

[0103] Additionally, the term “directly in response to” or “directly responsive to” can refer to a condition or action that occurs as a direct result of a prior condition or action. In some instances, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, independent of whether other conditions or actions occur. In some instances, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed “based on,” “based at least in part on,” or “in response to” some other step, action, event, or condition can additionally or alternatively (e.g., in alternative instances) be performed “directly in response to” or “directly responsive to” such other condition or action.

[0104] Devices including memory arrays discussed herein can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The electrical conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0105] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can render the channel conductive. A transistor can be“on” or“activated” if a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be“off’ or“deactivated” if a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0106] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term“exemplary” used herein means“serving as an example, instance, or illustration,” and not “preferred” over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0107] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by following the convention, in which the first digit or digits identify the component, the second digit identifies the number of that component, and the third digit identifies a specific instance of the component. The first digit, in which “0” means “none,” means that the component so denoted can be common to any or all of the instances of a given type.

[0108] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. The functions described herein can be implemented using software, hardware, firmware, hardwiring, or a combination of any of these methods and approaches. Features described herein can be physically located in various places, including but not limited to a processing system, in different combinations of hardware and software, or in entirely different physical locations.

[0109] The illustrative blocks and modules described herein can be implemented or performed with one or more processors, such as DSPs, ASICs, FPGAs, discrete logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor can be a member of a family of microprocessors, controllers, microcontrollers, state machines, or other types of processors. A processor can also be implemented as one or more computers, specially designed to perform the functions described herein.

[0110] As used herein, including in the claims, “or” as used in a list of items (for example, the phrase “at least one of A, B, or C”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0111] As used herein, including in the claims, the article “a” preceding a noun is an open- ended article, and should be understood to refer to “at least one” or “one or more” of the noun. Thus, the terms “a,” “at least one,” “one or more,” and “at least one of each of” can be used interchangeably. For example, if a claim recites “a component” that performs one or more functions, then each individual function can be performed by a single component or by any combination of a plurality of components. Thus, the term “component” having a particular characteristic or performing a particular function can refer to “at least one of each of a plurality of components” having that characteristic or performing that function. A subsequent reference to “the component” in the claim can refer to any one of the plurality of components or to all of the plurality of components. For example, a claim that recites “the component” can be interpreted as a claim that recites “at least one of each of the plurality of components.” Similarly, a subsequent reference to “the component” that was introduced with the article “a” or “an” can refer to any one of the plurality of components or to all of the plurality of components. For example, a claim that recites “the component” can be interpreted as a claim that recites “at least one of each of the plurality of components.”

[0112] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0113] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive, from a host device, a first command instructing the memory system to exit a sleep state, wherein the memory system comprises one or more memory devices; in response to the first command, initiate a wake-up procedure for a controller of the memory system, the wake-up procedure comprising configuring an interface between the controller and the one or more memory devices; prior to completing the configuring the interface and in response to the first command, issue a first signal to the one or more memory devices via a signal pin of the controller to trigger an initialization procedure at the one or more memory devices; and in response to triggering the initialization procedure at the one or more memory devices, perform one or more access operations at the one or more memory devices.

2. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: after completing the initialization procedure, issue a second signal to the one or more memory devices via the signal pin of the controller to trigger a second initialization procedure for the one or more memory devices.

3. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: after completing the initialization procedure and prior to issuing the second signal, update one or more trim parameters of the one or more memory devices, wherein the second initialization procedure is triggered by the second signal in response to updating the one or more trim parameters.

4. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: issue a third signal via the signal pin of the memory system to abort an access operation.

5. The memory system of claim 4, wherein the third signal is configured to abort the access operation in response to a transition of the signal pin from a second state to a first state.

6. The memory system of claim 1, wherein the signal pin comprises a write protect pin or a multi-die select pin.

7. The memory system of claim 1, wherein the signal pin is configured to trigger the initialization procedure at the one or more memory devices in response to a transition of the signal pin from a first state to a second state.

8. The memory system of claim 7, wherein the signal pin is coupled with a first pin of the one or more memory devices and a second pin of the one or more memory devices, and wherein the first signal is issued to the first pin of the one or more memory devices and the second pin of the one or more memory devices via the signal pin. ​ ​ 9. The memory system of claim 8, wherein the first pin is associated with triggering an initialization procedure for the one or more memory devices upon a transition of the signal pin from the first state to the second state, and the second pin is configured to abort an access operation for the one or more memory devices upon a transition of the signal pin from the second state to the first state.

10. The memory system of claim 8, wherein the second pin is configured to provide to the one or more memory devices at least a portion of an address associated with the one or more memory devices.

11. A memory device, comprising: one or more memory arrays; a signal pin; and processing circuitry coupled with the signal pin and the one or more memory arrays and configured to cause the memory device to: receive, via the signal pin, a first signal to trigger an initialization procedure for the memory device in response to a transition of the signal pin from a first state to a second state; perform one or more access operations at the one or more memory arrays in response to the initialization procedure; and receive, via the signal pin, a second signal to abort an access operation after completion of the initialization procedure in response to a transition of the signal pin from the second state to the first state.

12. The memory device of claim 11, wherein the processing circuitry is further configured to cause the memory device to: receive, via the signal pin, a third signal to trigger a second initialization procedure for the memory device in response to a transition of the signal pin from the first state to the second state.

13. The memory device of claim 12, wherein the processing circuitry is further configured to cause the memory device to: update one or more trim parameters of the memory device, wherein the second initialization procedure is triggered by the signal pin in response to the update of the one or more trim parameters.

14. The memory device of claim 13, wherein the signal pin indicates at least a portion of an address associated with the memory device relative to one or more additional memory devices for a duration of time after the initialization procedure and before the update of the one or more trim parameters.

15. A method by a memory system, comprising: receiving, from a host device, a first command indicating the memory system to exit a sleep state, wherein the memory system comprises one or more memory devices; in response to the first command, initiating a wake-up procedure for a controller of the memory system, the wake-up procedure comprising configuring an interface between the controller and the one or more memory devices; prior to completion of the configuring the interface and in response to the first command, issuing, via a signal pin of the controller, a first signal to the one or more memory devices to trigger an initialization procedure at the one or more memory devices; and ​ ​ perform one or more access operations at the one or more memory devices in response to triggering the initialization procedure at the one or more memory devices.

16. The method of claim 15, further comprising: issuing a second signal to the one or more memory devices via the signal pin of the controller to trigger a second initialization procedure for the one or more memory devices after completion of the initialization procedure.

17. The method of claim 16, further comprising: updating one or more trim parameters of the one or more memory devices after completion of the initialization procedure and before issuing the second signal, wherein the second initialization procedure is triggered by the second signal in response to updating the one or more trim parameters.

18. The method of claim 15, further comprising: issuing a third signal via the signal pin of the memory system to abort an access operation.

19. The method of claim 18, wherein the third signal is configured to abort the access operation in response to a transition of the signal pin from a second state to a first state.

20. The method of claim 15, wherein the signal pin comprises a write protect pin or a multi-die select pin.

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