Inverter parallel system and upgrading method thereof

Abstract

The application relates to the technical field of inverters, and discloses an inverter parallel system and an upgrading method thereof. The upgrading method comprises the following steps: in the working process of the running area control inverter, when the upgrading instruction is received, the running parameters of the running area are stored in the first storage area; the upgrading firmware sent by the microcontroller is received, and the upgrading firmware is stored in the second storage area; when the upgrading firmware is written, the switching instruction sent by the microcontroller is received, and the running area is switched to the second storage area according to the switching instruction; after the switching of the running area is completed, the running parameters are obtained from the first storage area, and the inverter is controlled according to the running parameters based on the running environment of the second storage area, so that the inverter can keep power supply output. The technical scheme can keep the continuous power supply of the inverter during the upgrading of the firmware, thereby effectively avoiding the power shock and power supply interruption problems in the traditional upgrading mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inverters, in particular to an inverter parallel system and an upgrading method thereof. BACKGROUND

[0002] As the core equipment in the distributed power supply system, inverters are widely used in new energy power generation, energy storage and grid-connected power supply scenarios. In order to improve the operation performance and functional stability of the inverter, it is usually necessary to upgrade the control firmware during the product life cycle. However, the existing inverter firmware upgrading method generally has the following problems: the inverter must be stopped during the upgrading process. When the traditional inverter performs firmware update, it usually needs to stop the inverter operation and disconnect the load, so as to avoid the interruption of control logic caused by the suspension of CPU running when writing the program memory (Flash). This method inevitably causes power interruption, affecting the continuity of user power consumption and the reliability of the equipment. SUMMARY

[0003] The embodiments of the present application provide an inverter parallel system and an upgrading method thereof to solve the above technical problems.

[0004] The first aspect of the embodiments of the present application provides an upgrading method of an inverter parallel system, the inverter parallel system comprising a microcontroller, a processor and an inverter module, the microcontroller and the processor being connected to the inverter module respectively, the processor comprising a running area, a first storage area and a second storage area, the upgrading method being applied to the processor, and the upgrading method comprising:

[0005] In the case that the running area controls the working process of the inverter and an upgrading instruction is received, the running parameters of the running area are stored to the first storage area;

[0006] The upgrading firmware sent by the microcontroller is received and stored to the second storage area;

[0007] When the upgrading firmware is written, the switching instruction sent by the microcontroller is received, and the running area is switched to the second storage area according to the switching instruction;

[0008] After the running area is switched, the running parameters are obtained from the first storage area, and the inverter is controlled according to the running parameters based on the running environment of the second storage area, so that the inverter maintains power output.

[0009] Optionally, the running parameters of the inverter comprise pulse width modulation register information, interruption state information, current, voltage and control loop parameters in the running process.

[0010] Optionally, the storing the upgrade firmware to the second storage area further comprises:

[0011] Continuing to execute the original program of the running area to make the inverter in a power supply state.

[0012] Optionally, the controlling the inverter according to the running parameter comprises:

[0013] Restoring pulse width modulation register values to maintain original waveform output after switching;

[0014] Restoring interrupt state information to continue task scheduling before switching;

[0015] Restoring current, voltage and control loop parameters during running to make the inverter continue to supply power after switching.

[0016] The second aspect of the embodiment of the present application provides an upgrading method of an inverter parallel system, the inverter parallel system comprising a microcontroller, a processor and an inverter module, the microcontroller and the processor being connected to the inverter module respectively, the processor comprising a running area, a first storage area and a second storage area, the upgrading method being applied to the microcontroller, and the upgrading method comprising:

[0017] When the processor stores running parameters of the running area to the first storage area according to an upgrade instruction, receiving upgrade firmware and sending the upgrade firmware to the processor to store to the second storage area;

[0018] When the upgrade firmware is written, sending a switching instruction to the processor to make the processor switch the running area to the second storage area, to make the processor acquire the running parameters from the first storage area, and to make the processor control the inverter according to the running parameters in the second storage area, so that the inverter maintains power supply output.

[0019] Optionally, the receiving upgrade firmware comprises:

[0020] The upgrade firmware is received through MQTT, HTTP or ESP-NOW protocol.

[0021] Optionally, the storing the upgrade firmware to the second storage area comprises

[0022] Verifying a version number and check information of the upgrade firmware;

[0023] When the verification result is passed, the processor is accessed through direct memory access to write the upgrade firmware to the second storage area.

[0024] Optionally, the processor is caused to switch the running area to the second storage area comprises:

[0025] The pulse width modulation signal of the inverter module is acquired.

[0026] When the pulse width modulation signal is at a trough moment, the level signal state of the address line of the processor is adjusted by the programmable logic device to switch the running area to the second storage area.

[0027] The third aspect of the embodiment of the application provides an inverter parallel system, which comprises a microcontroller, a processor and an inverter module, the microcontroller and the processor are connected to the inverter module respectively, and the processor comprises a running area, a first storage area and a second storage area.

[0028] The processor stores the running parameter of the running area to the first storage area according to an upgrade instruction.

[0029] The microcontroller receives an upgrade firmware and stores the upgrade firmware to the second storage area.

[0030] After the upgrade firmware is written, the microcontroller sends a switching instruction to the processor to cause the processor to switch the running area to the second storage area.

[0031] After the running area is switched, the processor acquires the running parameter from the first storage area and controls the inverter according to the running parameter based on the running environment of the second storage area, so that the inverter keeps power supply output.

[0032] Optionally, the microcontroller acquires the pulse width modulation signal of the inverter, and when the pulse width modulation signal is at a trough moment, the microcontroller adjusts the level signal state of the address line of the processor by the programmable logic device to switch the running area to the second storage area.

[0033] The technical effect of the embodiment of the application is that the inverter can be upgraded without shutdown during parallel operation, compared with the prior art, not only the continuous power supply of the inverter can be kept during firmware upgrade, but also the safety of the upgrade process and the stability of the system are further improved through the saving and recovery of the running parameter, the quick switching at the PWM trough, and the firmware transmission and storage dominated by the microcontroller, so that the power shock and power interruption problems in the traditional upgrade mode are effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor under the premise of these drawings.

[0035] Figure 1 is a structural schematic diagram of an inverter parallel system provided by the embodiment one of the present application;

[0036] Figure 2 is a flow chart of an upgrading method of an inverter parallel system provided by the embodiment one of the present application;

[0037] Figure 3 is a flow chart of an upgrading method of an inverter parallel system provided by the embodiment two of the present application;

[0038] Figure 4 is a specific flow chart of step S202 in the upgrading method of an inverter parallel system provided by the embodiment two of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor under the premise of the present application, all belong to the scope of protection of the present application.

[0040] It should be understood that the present application can be implemented in different forms, and should not be interpreted as being limited to the embodiments presented here. On the contrary, these embodiments are provided to make the disclosure complete and complete, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the size and relative size of the layers and regions may be exaggerated for clarity throughout the same reference signs represent the same elements.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0044] Example 1

[0045] This embodiment provides an upgrade method for an inverter parallel system, such as... Figure 1 As shown, the inverter parallel system includes a microcontroller 101 and a processor 102. The microcontroller 101 and processor 102 are respectively connected to the inverter module 103. The processor 102 includes an operating area, a first storage area, and a second storage area. The upgrade method is applied to the processor 102, such as... Figure 2 As shown, the upgrade methods include:

[0046] Step S101. During the operation of the inverter in the operating zone, if an upgrade command is received, the operating parameters of the operating zone are stored in the first storage area;

[0047] Step S102. Receiving the upgrade firmware sent by the microcontroller, and storing the upgrade firmware to the second storage area;

[0048] Step S103. When the upgrade firmware writing is completed, receiving the switching instruction sent by the microcontroller, and switching the running area to the second storage area according to the switching instruction;

[0049] Step S104. After the running area completes the switching, obtaining the running parameters from the first storage area, and controlling the inverter according to the running parameters based on the running environment of the second storage area, so as to make the inverter keep the power supply output.

[0050] In step S101, the running state of the inverter can be completely saved before upgrading, including the pulse width modulation register value, the interrupt state, and the current, voltage and control loop parameters, so as to ensure that the running environment can be quickly restored after switching to the new firmware, and control interruption caused by state loss is avoided.

[0051] In step S102, through the process, the upgrade firmware can be written to the standby storage area in the background, and the processor continues to execute the original control logic, so as to realize the parallel running of the firmware writing and the inverter power supply control, and ensure that the inverter power supply is not interrupted during the firmware download stage.

[0052] In step S103, in this process, the storage area switching can be performed at the trough moment of the pulse width modulation signal, and the address line of the processor is controlled through the programmable logic device, so as to realize the fast switching of the first storage area and the second storage area. In this way, the firmware replacement can be completed within several microseconds, the disturbance to the power output is reduced, and the seamless switching of the running area is realized.

[0053] In step S104, after the running area completes the switching, the processor obtains the running parameters from the first storage area, and continues to control the inverter according to the running parameters based on the running environment of the second storage area, so as to ensure that the inverter keeps the power supply output. The processor can restore the running state before the switching in the new firmware environment, and keep the continuity of the control logic, so as to realize the uninterrupted power supply of the inverter during the upgrading process, and ensure the stability of the voltage and current output.

[0054] The technical effect of the embodiment is that the inverter can be upgraded without stopping during parallel operation, compared with the prior art, not only the continuous power supply of the inverter can be kept during the firmware upgrading, but also the safety and stability of the upgrading process and the system are further improved through the saving and restoration of the running parameters, the fast switching completed at the PWM trough, and the firmware transmission and storage dominated by the microcontroller, so as to effectively avoid the power shock and power interruption problems in the traditional upgrading mode.

[0055] As an implementation, the operation parameters of the inverter include: pulse width modulation register information, interrupt state information, current, voltage and control loop parameters during operation.

[0056] The pulse width modulation register information is used to represent the driving waveform output state of the inverter before switching, the interrupt state information is used to record the task scheduling of the processor before switching, and the current, voltage and control loop parameters are used to reflect the real-time working condition of the inverter before switching and the dynamic operation state of the microcontroller inside.

[0057] By saving the above operation parameters to the first storage area before upgrading, the running environment of the new firmware can be restored in time after the upgrading switching is completed, so that the processor can seamlessly continue the control logic before switching. Therefore, the inverter can not only maintain the continuity of power supply output during the upgrading process, but also avoid the output power fluctuation and control loop instability problem caused by parameter loss, thereby realizing smooth transition of system operation and high reliability of power supply.

[0058] As an implementation, the upgrading firmware is stored in the second storage area, and further comprising:

[0059] The original program of the running area is continued to be executed, so that the inverter is in a power supply state.

[0060] That is, during the process of transmitting and writing the upgrading firmware to the second storage area by the microcontroller, the processor still maintains the execution of the original program of the running area, ensuring that the power control logic and power supply output of the inverter are not disturbed.

[0061] In the above manner, the firmware writing and the inverter power supply can be performed in parallel, so that the inverter still maintains a normal running state during the firmware upgrading stage, thereby avoiding the shutdown or power interruption problem caused by upgrading writing operation in the conventional technology, and significantly improving the continuity and reliability of the system during the upgrading process.

[0062] As an implementation, the inverter is controlled according to the operation parameters, comprising:

[0063] The pulse width modulation register value is restored to maintain the original waveform output after switching;

[0064] The interrupt state information is restored to continue the task scheduling before switching;

[0065] The current, voltage and control loop parameters during operation are restored to continue the power supply of the inverter after switching.

[0066] The processor can quickly restore the control state before switching after completing the storage area switching and entering the upgrading firmware running environment, so that the output waveform of the inverter is maintained continuously, the task scheduling is not interrupted, and the electrical control loop is kept stable.

[0067] The technical effect of the technical solution is that by restoring the pulse width modulation register information, the interrupt state and the electrical operating parameters after switching is completed, the embodiment can ensure that the control logic of the inverter is seamlessly continued during the upgrading process, thereby realizing the stability and continuity of the power supply output. Compared with the shutdown or power interruption caused by upgrading in the prior art, the application not only avoids voltage and current surges, but also effectively improves the reliability of the inverter in a parallel operation environment and the user's power consumption experience.

[0068] As an embodiment, the triggering moment of the switching window is dynamically calculated by the processor according to multiple parameters. Specifically, the processor analyzes the current system state by monitoring the current zero-crossing signal, the PWM carrier synchronization signal, the temperature parameter and the bus voltage value in real time, and calculates the optimal switching phase suitable for the current working condition.

[0069] During operation, when the current is detected to be close to zero, the processor dynamically adjusts the phase delay of the PWM signal according to the transient fluctuation of the bus voltage and the temperature change of the power device, so that the power switch is turned on or turned off under the condition of minimum current or voltage difference. Through this adaptive algorithm, electromagnetic interference (EMI) and waveform distortion at the switching moment can be effectively reduced, and the overall power conversion efficiency and signal stability of the system can be improved.

[0070] Specifically, the current zero-crossing represents the instantaneous state of the load current changing from positive to negative or from negative to positive, at which time the current value is close to zero, and if the power device is turned on or turned off at this moment, the switching energy loss and electromagnetic interference can be significantly reduced. The processor monitors the current waveform in real time through the current detection module, obtains the time information when the current is close to zero, and combines the voltage change rate information provided by the bus voltage detection module and the power device junction temperature information provided by the temperature detection module to calculate the phase correction amount and adjust the output timing of the PWM signal accordingly. When the bus voltage fluctuates rapidly, the processor reduces the phase delay to avoid overlapping conduction during voltage rise; when the temperature of the power device is detected to be high, the processor appropriately increases the phase delay to compensate for the response lag caused by the change in the conduction and turn-off characteristics of the device with temperature. Through the above dynamic phase adjustment, the power device can be turned on or turned off at the moment when the current is minimum or the voltage difference is minimum, thereby effectively reducing the electromagnetic interference caused by dv / dt and di / dt, reducing waveform distortion, and improving the adaptability and energy efficiency stability of the system under different load types.

[0071] By using the adaptive PWM switching algorithm, the embodiment realizes adaptive matching of different load types (including inductive load and resistive load). For inductive load, switching can be completed near the current zero to reduce voltage spikes; for resistive load, switching can be performed at the carrier valley to reduce harmonic components. Thus, the electromagnetic compatibility and waveform quality of the system under different working conditions are effectively improved, and the stability and reliability of the equipment operation are improved.

[0072] Embodiment two

[0073] The embodiment two provides an upgrading method of an inverter parallel system, as shown in the figure, the inverter includes a microcontroller and a processor, the processor includes a running area, a first storage area and a second storage area, the upgrading method is applied to the microcontroller, as shown in the figure, the upgrading method includes: Figure 1 Figure 3

[0074] Step S201. When the processor stores the running parameters of the running area to the first storage area according to the upgrading instruction, the upgrading firmware is received, and the upgrading firmware is sent to the processor to be stored to the second storage area;

[0075] Step S202. When the upgrading firmware is written, a switching instruction is sent to the processor, the processor is switched to the second storage area, the running area is switched to the second storage area, the processor is enabled to obtain the running parameters from the first storage area, and the processor is enabled to control the inverter according to the running parameters in the second storage area, so that the inverter keeps power supply output.

[0076] ​​In step S201, on the premise that the processor has saved the running parameters of the running area to the first storage area according to the upgrade instruction, the microcontroller enters the firmware distribution process. Specifically, the microcontroller first establishes a communication connection with the cloud upgrade service, obtains the upgrade firmware and its metadata (including version number, target address area, firmware length, digest / signature information, entry address, compatibility identifier, etc.) matching the target model and target version. The microcontroller performs legality verification on the firmware, preferably including: version forward verification (prohibiting rollback to a lower version unless authorized), length and boundary alignment verification (ensuring that writing does not exceed the second storage area), digest / signature verification (such as CRC32 / SHA-256 and elliptic curve signature), and "write-before Bank free" verification (confirming that the second storage area is not occupied by the current execution). After verification, the microcontroller establishes a firmware transmission session with the processor, negotiates write parameters (page size, block size, timeout and retransmission strategy, write start offset, etc.). The transmission layer preferably uses fragmented packets with sequence numbers and an acknowledgement mechanism, with each fragment including a packet header (magic number, sequence number, length, target offset), data body, and tail verification field. The microcontroller sends firmware data to the processor in sequence according to the negotiated block granularity, and the processor maps the received data to the corresponding address of the second storage area. To reduce the impact on the real-time control load of the processor, peripheral direct memory access (DMA) or write buffering + asynchronous disk writing can be used to complete page programming, and a read sample is read after each write page to perform page-level verification; when the page-level verification or block-level cumulative verification fails, the microcontroller triggers retransmission and rewriting until the page / block verification passes or the retry limit is reached.

[0077] During the entire writing process, the processor maintains the execution of the original program in the running area, and the microcontroller does not change the current running area's instruction fetching and interrupt configuration; the processor's real-time control loop (such as current loop / voltage loop / PID integral) maintains the original frequency and duty cycle update beat unchanged. After all block writing is completed, the microcontroller issues a write completion / readiness indication to the processor and writes the Bank header information (entry address, version number, timestamp, verification digest, rollback pointer, etc.) of the second storage area, and records the upgrade session metadata in the non-volatile domain once, for subsequent switching and rollback tracking.

[0078] In step S202, after the microcontroller confirms that the firmware in the second storage area is completely written and passes the overall check, the running area switching phase is entered. The microcontroller first calculates a safe switching window according to the running state feedback of the processor (including the current PWM carrier phase / counter value, instantaneous current / voltage, loop error, etc.), and preferably selects the trough moment of the pulse width modulation signal as the switching trigger point; in the parallel machine scenario, the microcontroller can first broadcast a short-time power compensation notification to other inverters in the cluster, so that the adjacent nodes temporarily raise the output according to the preset rule, and then initiates the switching to the target inverter. When the switching is executed, the microcontroller sends a switching instruction to the processor, and atomically controls the address mapping / Bank selection signal of the processor through the programmable logic device, so that the instruction fetch area of the processor is mapped from the running area to the entry address of the second storage area. To avoid transient disturbance, the processor executes the agreed startup sequence after entering the new firmware entry: preferably, first turn off or shield non-critical interrupts for an extremely short time slice (without affecting protection interrupts), complete the stack / vector table relocation and instruction prefetch queue flushing to the new code segment, and then immediately batch restore the running parameters (including PWM register group, comparison and trigger register, timer, loop controller internal state such as integral quantity / amplitude limiting state, interrupt suspension and priority state, parallel machine power distribution weight, synchronization phase / frequency scalar, etc.) saved before the switching from the first storage area. Thereafter, the new firmware enables the shadow register / soft start strategy to smoothly take over the power path: for example, gradually change the duty cycle / phase / current limit within N PWM periods at a set slope, maintain the loop error and output ripple within the threshold; at the same time, start the online health check (bus voltage deviation, output current transient, circulating current monitoring, temperature rise rate, etc.), and if any index exceeds the limit, trigger a fast rollback, and the microcontroller will switch the running area back to the original Bank in the next safe window, and record the rollback reason and fault snapshot. When the new firmware completes the takeover and the health check passes the stable criterion (for example, the ripple / error is below the threshold for M consecutive carrier periods), the microcontroller will persist the upgrade result (mark the second storage area as the active Bank, update the version record, and clean up the temporary flag of the old Bank), and issue the compensation cancellation / resume matching instruction to the parallel machine cluster, so that the system power distribution returns to normal.

[0079] The embodiment solves the pain points of traditional upgrade, such as shutdown, control interruption and parallel machine power fluctuation, and significantly improves the maintainability and service continuity of the inverter system in the field operation.

[0080] As an implementation manner, the upgrade firmware is received, including:

[0081] The upgrade firmware is received through MQTT, HTTP or ESP-NOW protocol.

[0082] The microcontroller obtains the upgrade firmware file by establishing a communication connection with the cloud server and using a standardized network communication protocol. The MQTT protocol is suitable for lightweight message transmission scenarios and can complete firmware pushing with low power consumption and low bandwidth. The HTTP protocol is suitable for large file transmission in a regular network environment and can ensure the integrity and reliability of data transmission. The ESP-NOW protocol is suitable for local area networks or device direct connection environments and can realize point-to-point or point-to-multipoint communication without a router, thereby quickly completing firmware distribution.

[0083] The technical effect of the embodiment is that by flexibly selecting the MQTT, HTTP, or ESP-NOW protocol for receiving the upgrade firmware in different application scenarios, the transmission efficiency and network adaptability can be considered while ensuring the safety and reliability of firmware transmission. This method not only improves the flexibility and applicability of firmware upgrade, but also ensures that the inverter can successfully obtain the upgrade firmware under various network conditions, thereby improving the maintainability and reliability of the system.

[0084] As an embodiment, storing the upgrade firmware to the second storage area includes

[0085] The version number and the check information of the upgrade firmware are checked.

[0086] When the check result is passed, the upgrade firmware is written by a direct memory access processor. First, the version number and the check information of the upgrade firmware are checked to confirm that the upgrade firmware is a legal file adapted to the target inverter and has not been damaged or tampered with. When the check result is passed, the storage interface of the processor is accessed in a direct memory access (DMA) mode to write the upgrade firmware to the second storage area. In this process, the processor main core can continue to execute the original program in the running area, ensuring that the power control and power output of the inverter are not interrupted.

[0087] The technical effect of the embodiment is that by verifying the version number and the check information before writing, upgrade failure or system failure caused by firmware version mismatch or data damage can be effectively avoided, thereby improving the safety and reliability of firmware upgrade. At the same time, the firmware writing operation can be completed without occupying the processor main core resources by using the direct memory access mode, realizing the parallel operation of firmware writing and inverter power control, thereby ensuring the power continuity and running stability of the inverter during the firmware writing stage.

[0088] As an embodiment, as shown in Figure 4 The step S202 of switching the running area of the processor to the second storage area includes:

[0089] Step S301. Obtain a pulse width modulation signal of the inverter module.

[0090] Step S302. When the pulse width modulation signal is at a trough moment, adjust the level signal state of the address line of the processor through the programmable logic device to switch the running area to the second storage area.

[0091] In step S301, the pulse width modulation signal of the inverter is obtained to determine the running state of the inverter output waveform; in step S3202, when the pulse width modulation signal is at a trough moment, the level signal state of the address line of the processor is adjusted through the programmable logic device to switch the running area to the second storage area. By switching at the trough moment of the PWM signal, the transient impact of the switching action on the output voltage and current can be effectively reduced; by using the programmable logic device to control the address line of the processor, the switching of the running area can be quickly realized at the hardware level, avoiding the interruption caused by software relocation or reset.

[0092] In the above manner, the embodiment can complete the switching of the running area at the moment when the inverter power supply waveform is most stable, and maximally reduce the disturbance to the output power. At the same time, the programmable logic device is used to directly control the address line of the processor to realize the microsecond-level fast switching, so that the new firmware can immediately take over the running, ensuring the stability and reliability of the inverter power supply output during the upgrading process.

[0093] Embodiment Three

[0094] The embodiment three provides an inverter parallel system, the inverter includes a microcontroller and a processor, the processor includes a running area, a first storage area and a second storage area;

[0095] The processor stores the running parameters of the running area to the first storage area according to the upgrading instruction;

[0096] The microcontroller receives the upgrading firmware and stores the upgrading firmware to the second storage area;

[0097] After the upgrading firmware is written, the microcontroller sends a switching instruction to the processor to make the processor switch the running area to the second storage area;

[0098] After the running area is switched, the processor obtains the running parameters from the first storage area, and controls the inverter based on the running environment of the second storage area according to the running parameters, so that the inverter maintains the power supply output.

[0099] Further, the microcontroller obtains a pulse width modulation signal of the inverter; when the pulse width modulation signal is at a trough moment, the microcontroller adjusts the level signal state of the address line of the processor through the programmable logic device to switch the running area to the second storage area.

[0100] The above examples are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An upgrade method for an inverter parallel system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes a running area, a first storage area, and a second storage area. The upgrade method is applied to the processor, and the upgrade method includes: During the operation of the inverter in the operating area, if an upgrade command is received, the operating parameters of the operating area are stored in the first storage area; Receive the upgrade firmware sent by the microcontroller and store the upgrade firmware in the second storage area; After the upgrade firmware is written, a switching instruction sent by the microcontroller is received, and the running area is switched to the second storage area according to the switching instruction; After the switching of the operating area is completed, the operating parameters are obtained from the first storage area, and the inverter is controlled according to the operating parameters based on the operating environment of the second storage area, so that the inverter maintains power output; The upgrade method further includes: the triggering time of the switching window is dynamically calculated by the processor based on multiple parameters; the processor comprehensively analyzes the current system state by real-time monitoring of the current zero-crossing signal, PWM carrier synchronization signal, temperature parameters, and bus voltage value, and calculates the optimal switching phase suitable for the current operating conditions; when the current is detected to be close to the zero-crossing point, the processor dynamically adjusts the phase delay of the PWM signal based on the transient fluctuation of the bus voltage and the temperature change of the power device, so that the power switch can be turned on or off under the minimum current or voltage difference conditions; The inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation; The step of controlling the inverter according to the operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; The current, voltage, and control loop parameters during operation are restored so that the inverter can continue to supply power after switching.

2. The upgrade method as described in claim 1, characterized in that, The step of storing the upgraded firmware to the second storage area further includes: Continue executing the original program in the operating area to put the inverter into a power supply state.

3. An upgrade method for an inverter parallel system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes a running area, a first storage area, and a second storage area. The upgrade method is applied to the microcontroller, and the upgrade method includes: When the processor stores the operating parameters of the running area to the first storage area according to the upgrade instruction, it receives the upgrade firmware and sends the upgrade firmware to the processor to store it in the second storage area; After the upgrade firmware is written, a switching command is sent to the processor to switch the operating area to the second storage area, so as to drive the processor to obtain the operating parameters from the first storage area and to control the inverter in the second storage area according to the operating parameters, so as to keep the inverter supplying power. The upgrade method further includes: the triggering time of the switching window is dynamically calculated by the processor based on multiple parameters; the processor comprehensively analyzes the current system state by real-time monitoring of the current zero-crossing signal, PWM carrier synchronization signal, temperature parameters, and bus voltage value, and calculates the optimal switching phase suitable for the current operating conditions; when the current is detected to be close to the zero-crossing point, the processor dynamically adjusts the phase delay of the PWM signal based on the transient fluctuation of the bus voltage and the temperature change of the power device, so that the power switch can be turned on or off under the minimum current or voltage difference conditions; The inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation; Controlling the inverter according to the operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; The current, voltage, and control loop parameters during operation are restored so that the inverter can continue to supply power after switching.

4. The upgrade method as described in claim 3, characterized in that, The receiving of the upgraded firmware includes: The upgraded firmware is received via MQTT, HTTP, or ESP-NOW protocol.

5. The upgrade method as described in claim 4, characterized in that, Storing the upgraded firmware to the second storage area includes: The version number and verification information of the upgraded firmware are verified. If the verification result is successful, the processor is accessed via direct memory to write the upgraded firmware into the second storage area.

6. The upgrade method as described in claim 3, characterized in that, The step of switching the processor to the second storage area includes: Obtain the pulse width modulation signal of the inverter module; When the pulse width modulation signal is at a trough, the level signal state of the processor's address line is adjusted by a programmable logic device to switch the running area to the second memory area.

7. An inverter parallel operation system, characterized in that, The inverter parallel system includes a microcontroller, a processor, and an inverter module. The microcontroller and the processor are respectively connected to the inverter module. The processor includes an operating area, a first storage area, and a second storage area. The processor stores the operating parameters of the operating area into the first storage area according to the upgrade instruction; The microcontroller receives the upgrade firmware and stores the upgrade firmware in the second storage area; After the upgrade firmware is written, the microcontroller sends a switching command to the processor, causing the processor to switch the running area to the second storage area; After the switching of the operating area is completed, the processor obtains the operating parameters from the first storage area, and controls the inverter according to the operating parameters based on the operating environment of the second storage area, so that the inverter maintains power output; The triggering time of the switching window is dynamically calculated by the processor based on multiple parameters. The processor comprehensively analyzes the current system state by real-time monitoring of the current zero-crossing signal, PWM carrier synchronization signal, temperature parameters, and bus voltage value, and calculates the optimal switching phase suitable for the current operating conditions. When the current is detected to be close to the zero-crossing point, the processor dynamically adjusts the phase delay of the PWM signal based on the transient fluctuation of the bus voltage and the temperature change of the power device, so that the power switch can be turned on or off under the minimum current or voltage difference conditions. The inverter's operating parameters include: pulse width modulation register information, interrupt status information, current, voltage, and control loop parameters during operation; The step of controlling the inverter according to the operating parameters includes: Restore the pulse width modulation register value to maintain the original waveform output after switching; Restore interrupt status information to continue task scheduling from the previous switchover; The current, voltage, and control loop parameters during operation are restored so that the inverter can continue to supply power after switching.

8. The inverter parallel operation system as described in claim 7, characterized in that, The microcontroller acquires the pulse width modulation signal of the inverter; when the pulse width modulation signal is at a trough, the microcontroller adjusts the level signal state of the address line of the processor through a programmable logic device to switch the operating area to the second memory area.

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