Vector segment memory access instruction processing method and device

Abstract

The invention relates to a vector segment memory access instruction processing method and device. Comprising the following steps: decoding a vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in an instruction operation code of the vector segment memory access instruction and configuration information of a vector control state register; splitting the macro operation capable of being dispatched into a plurality of micro operations according to the size of each vector element and the effective vector length; calculating the memory access byte number and the memory access address of each micro-operation; and executing each micro-operation according to the memory access byte number and the memory access address of each micro-operation. According to the embodiment of the invention, the address and the size of the memory access data of each register are calculated through a standardized calculation formula by taking the elementary as the granularity, so that the dependence among the registers is reduced, and logic resources required by data processing are reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to the technical field of computer technology, and particularly relate to a vector segment memory access instruction processing method and device. BACKGROUND

[0002] RISC-V is an open-source reduced instruction set, which is composed of a basic instruction set and a plurality of extension instruction sets. The vector extension provides more flexible memory access operations, but also increases the complexity of implementation.

[0003] The RISC-V vector memory (vector load / store) instruction can be mainly divided into three memory access modes: unit stride, fixed stride and index. The number of bytes of the memory access instruction operation elements is determined by the default bit width (Selected element width, SEW) of each element in the vector register or the actual bit width (Effective element width, EEW) of each element actually operated during instruction execution. The number of registers of the instruction operation is determined by the vector register group multiplier (Vector register group multiplier, LMUL) or the actual register group multiplier (Effective vector register group multiplier, EMUL) during instruction execution and the number of fields (number of fields, nf) contained in each vector element in the segment load / store. The number of vector elements actually operated during current instruction execution (i.e. the effective vector length) (Vector length, VL) specifies the number of elements operated at a time. For a vector memory instruction, when the nf domain value of opcode is not 0, the instruction memory access is of the segment type. Compared with non-segment operation memory access, segment type memory access is more complex, and the address is difficult to calculate.

[0004] Take the vector length VLEN = 128 as an example, in the memory next to the A, B, C, D four 64 bits of data, to load data A, C to the register Vn, data B, D load to Vn+1, at this time can be set LMUL = 1, VL = 2, through the vlseg2e64.v, (rs1), vm instruction implementation. According to the hardware access mode of scalar processor directly decode the segment load instruction into two macro operations mop0 and mop1, each macro operation (mop) from the memory to retrieve 16 Bytes of data, wherein mop0 loads data A, C into the register Vn, mop1 B, D to Vn+1, such a way is not possible. Because A, C is not continuous address, mop0 base address for data A address, at this time mop0 retrieve data for A, B, the mop1 retrieve data for C, D, at this time must need additional data processing module to process the retrieved data so that Vn loads data A, C, Vn+1 loads data B, D.

[0005] When nf is large, such as vlseg8e8.v instruction, vl = 16, at this time the element size of the element is 8 bits, need to load 128 bytes of continuous memory to Vn, Vn+1, … Vn+7 total 8 registers. Although the above-mentioned way to decode 8 mop, each mop from the memory load 16 Bytes, and then through the data processing module to let 8 registers get the correct data. But at this time there will be a dependency between each mop, must wait for 8 mop to execute to get the final data, reduce the processor out of order ability.

[0006] If the additional data module is used to process segment instruction, need to determine which register should go to the register to retrieve, such as vlsge3e64.v, VL = 2, at this time need to load back to the Vn, Vn+1, Vn+2 register 2 64 bits of data, according to the above method decode 3 macro operation: mop0, mop1, mop2, each mop retrieve 64 bits of data for A and B, C and D, E and F. At this time the register Vn finally get the data should be A and D, the data of register Vn+1 is B and E, Vn+2 data should be C and F. At this time the data processing module needs to determine which mop each destination register should get the data to process to get the correct result, the register Vn need to get data A and D from mop0 and mop1, similarly Vn+1 data in mop0 and mop2, Vn+2 data in mop1 and mop2, obviously increase the logic complexity of the processing module.

[0007] How to reduce the logical complexity of RISC-V segment access instructions and improve execution efficiency is a technical problem to be solved at present. SUMMARY

[0008] To solve the problems in the prior art, the embodiments of the present specification provide a vector segment access instruction processing method and device, which can realize the processing of RISC-V vector segment access (Vector segment load / store) instructions with less hardware resources, effectively improve the execution efficiency of RISC-V Vector segment load / store instructions, and improve the out-of-order ability of the processor.

[0009] The specific technical solutions of the embodiments of the present specification are as follows:

[0010] In one aspect, the embodiments of the present specification provide a vector segment access instruction processing method, which comprises:

[0011] Decoding the vector segment access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment access instruction and the configuration information of the vector control state register;

[0012] Splitting the dispatchable macro operation into a plurality of micro operations according to the size of each vector element and the effective vector length;

[0013] Calculating the access byte number and access address of each micro operation;

[0014] Executing each micro operation according to the access byte number and access address of each micro operation.

[0015] Further, decoding the vector segment access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment access instruction and the configuration information of the vector control state register comprises:

[0016] Calculating the product of the number of vector registers contained in the vector register group and the number of fields to obtain the number of macro operations, and decoding the vector segment access instruction into a plurality of macro operations according to the number of macro operations;

[0017] Assigning a macro operation ID to each macro operation.

[0018] Further, the method further comprises:

[0019] Determining the number of vector registers contained in the vector register group according to the access mode of the vector segment access instruction.

[0020] Further, determining the number of vector registers contained in the vector register group according to the access mode of the vector segment access instruction comprises:

[0021] If the access mode is the index mode, the number of vector registers contained in the vector register group is the vector register grouping multiplier in the configuration information;

[0022] If the access mode is the unit stride mode or the fixed stride mode, the number of vector registers contained in the vector register group is the actual register grouping multiplier when the vector segment access instruction is executed.

[0023] Further, assigning a macro operation ID to each macro operation comprises:

[0024] The macro operations are sequentially assigned from zero.

[0025] Further, splitting the dispatchable macro operation into a plurality of micro operations according to the size of each vector element and the effective vector length comprises:

[0026] calculating the number of vector elements processed by each dispatchable macro operation, taking the number of vector elements processed by each dispatchable macro operation as the number of micro operations split from each dispatchable macro operation respectively, and splitting each macro operation into a plurality of micro operations according to the number of micro operations;

[0027] Assigning a micro operation ID to each micro operation.

[0028] Further, assigning a micro operation ID to each micro operation comprises:

[0029] The micro operations are sequentially assigned from zero.

[0030] Further, the method further comprises:

[0031] When the number of vector registers contained in the vector register group is less than 1, marking a field ID for each micro operation, the field ID is sequentially assigned from 0 to (1 / vec_group-1), wherein vec_group represents the number of vector registers contained in the vector register group.

[0032] Further, calculating the number of access bytes of each micro operation comprises:

[0033] If the access mode of the vector segment access instruction is the index mode, the number of access bytes of the micro operation is equal to the default bit width of each element in the vector register;

[0034] If the access mode of the vector segment access instruction is the unit stride mode or the fixed stride mode, the number of access bytes of the micro operation is equal to the actual bit width of each element actually operated when the instruction is executed.

[0035] Further, the memory access address of each micro-operation is calculated as follows:

[0036] If the memory access mode of the vector segment memory access instruction is the index mode, the memory access address of the micro-operation is calculated as follows:

[0037] where virt_addr1 represents the memory access address of the micro-operation corresponding to the index mode, rs1 represents the base address, vs2_offset represents the address offset, access_size represents the memory access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group1 represents the number of vector registers contained in the vector register group corresponding to the index mode, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0038] If the memory access mode of the vector segment memory access instruction is the unit stride mode, the memory access address of the micro-operation is calculated as follows:

[0039]

[0040] where virt_addr2 represents the memory access address of the micro-operation corresponding to the unit stride mode, rs1 represents the base address, VLEN represents the size of the vector register, nf represents the number of fields contained in each vector element in the segment load / store, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group2 represents the number of vector registers contained in the vector register group corresponding to the unit stride mode, uop_id represents the micro-operation ID of the micro-operation, and access_size represents the memory access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0041] If the memory access mode of the vector segment memory access instruction is the fixed stride mode, the memory access address of the micro-operation is calculated as follows:

[0042] Wherein virt_addr3 represents the access address of the micro-operation corresponding to the fixed step mode, rs1 represents the base address, VLEN represents the vector length, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group3 represents the number of vector registers contained in the vector register group corresponding to the fixed step mode, rs2 represents the step, and access_size represents the access byte number of the micro-operation. represents rounding down the division result, and field_id represents the field ID of the micro-operation.

[0043] Further, if the number of vector registers contained in the vector register group is greater than or equal to 1, the field ID of the micro-operation is 0.

[0044] On the other hand, the embodiments of the present specification also provide a vector mask calculation device, the device comprising:

[0045] a macro-operation splitting unit, configured to decode the vector segment access instruction into a plurality of macro-operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment access instruction and the configuration information of the vector control state register;

[0046] a micro-operation splitting unit, configured to split the dispatchable macro-operations into a plurality of micro-operations according to the size of each vector element and the effective vector length;

[0047] a calculation unit, configured to calculate the access byte number and the access address of each micro-operation;

[0048] an execution unit, configured to execute each micro-operation according to the access byte number and the access address of each micro-operation.

[0049] On the other hand, the embodiments of the present specification also provide a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the above method.

[0050] In the prior art, for the RISC-V segment access instruction, the data loaded or stored by one register is often discontinuous in the memory, at which time the implementation mode of the scalar access instruction cannot be reused. Taking the access instruction (load instruction) as an example, if all the data is first retrieved and then the retrieved data is processed into the correct format of the data required by the register, the data dependency between the registers will inevitably be increased. In addition, the RISC-V access instruction is in units of elements, and the segment access instruction is limited by conditions such as nf, LMUL / EMUL, SEW / EEW, and VL, which will inevitably increase the logic complexity and consume a large amount of logic resources when processing data.

[0051] Therefore, the embodiment of the present specification calculates the address and size of the data accessed by each register by a standardized calculation formula, thereby reducing the dependence between registers and reducing the logic resources required for data processing. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present specification, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0053] Figure 1 The structure of the processor in the embodiment of the present specification is shown;

[0054] Figure 2 The flowchart of the vector segment access instruction processing method in the embodiment of the present specification is shown;

[0055] Figure 3 The flowchart of decoding the vector segment access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment access instruction and the configuration information of the vector control state register in the embodiment of the present specification is shown;

[0056] Figure 4 The flowchart of determining the number of registers contained in the vector register group according to the access mode of the vector segment access instruction in the embodiment of the present specification is shown;

[0057] Figure 5 The flowchart of splitting the dispatchable macro operation into a plurality of micro operations according to the size of each vector element and the effective vector length in the embodiment of the present specification is shown;

[0058] Figure 6 The flowchart of calculating the number of access bytes of each micro operation in the embodiment of the present specification is shown;

[0059] Figure 7 The mop calculation, uop splitting and address calculation of the segment unit stride load instruction in the embodiment 1 of the present specification are shown;

[0060] Figure 8 The mop calculation, uop splitting and address calculation of the segment stride load instruction in the embodiment 2 of the present specification are shown;

[0061] Figure 9Fig. 3 shows a schematic diagram of segment index load instruction mop computation, uop split and address computation in embodiment 3 of the present specification;

[0062] Figure 10 Fig. 4 shows a schematic diagram of segment unit stride load instruction mop computation, uop split and address computation in embodiment 4 of the present specification with EMUL = 2;

[0063] Figure 11 Fig. 5 shows a schematic diagram of segment unit stride load instruction mop computation, uop split and address computation in embodiment 4 of the present specification with EMUL = 1 / 2;

[0064] Figure 12 Fig. 6 shows a schematic diagram of segment unit stride load instruction mop computation, uop split and address computation in embodiment 4 of the present specification with EMUL = 1, VL = 3, EEW = SEW = 32;

[0065] Figure 13 Fig. 7 shows a schematic diagram of a vector segment memory access instruction processing apparatus in an embodiment of the present specification;

[0066] Figure 14 Fig. 8 shows a schematic diagram of a computer device in an embodiment of the present specification.

[0067]

BRIEF DESCRIPTION OF THE DRAWINGS

[0068] 1301, macro operation split unit;

[0069] 1302, micro operation split unit;

[0070] 1303, computation unit;

[0071] 1304, execution unit;

[0072] 1402, computer device;

[0073] 1404, processing device;

[0074] 1406, storage resource;

[0075] 1408, driving mechanism;

[0076] 1410, input / output module;

[0077] 1412, input device;

[0078] 1414, output device;

[0079] 1416, presentation device;

[0080] 1418, graphical user interface;

[0081] 1420, network interface;

[0082] 1422, communication link;

[0083] 1424, communication bus. DETAILED DESCRIPTION

[0084] The technical solutions in the embodiments of the present specification will be described clearly and completely below in combination with the drawings in the embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, rather than all the embodiments. Based on the embodiments in the embodiments of the present specification, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the embodiments of the present specification.

[0085] It should be noted that the terms “first”, “second” and the like in the description and claims of the embodiments of the present specification and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the embodiments of the present specification described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or apparatus including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or apparatuses.

[0086] It should be noted that the acquisition, storage, use, processing and the like of data in the technical solutions of the embodiments of the present specification comply with the relevant provisions of national laws and regulations.

[0087] It should be noted that in the embodiments of the present specification, some industry existing solutions of software, components, models and the like may be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility of the technical solution implementation of the present application, but does not mean that the applicant has or will necessarily use the solution.

[0088] The RISC-V vector segment memory access instruction implementation method provided by the embodiments of the present specification can be applied in a processor, and a structural schematic diagram of the processor is as shown in Figure 1 The processor includes a decoding module, a dispatching module, an instruction splitting module, an execution module and a data processing module.

[0089] In the embodiment of the present specification, the decoding module is configured to decode a vector segment memory access instruction into a plurality of MOPs and send them to the dispatch module; the dispatch module is configured to dispatch the received MOPs to the execution module; the instruction splitting module is configured to split the MOPs that can be finally dispatched into a plurality of UOPs according to the element size and the VL size, calculate the memory access address and the memory access byte number of each UOP; the execution module is configured to execute the memory access operation of the UOP; and the data processing module is configured to process the accessed data to ensure the correct execution of the program.

[0090] To solve the problem of high logical complexity of the RISC-V segment memory access instruction in the prior art, the embodiment of the present specification provides a vector segment memory access instruction processing method, which can process the RISC-V Vector segment load / store instruction by using less hardware resources, effectively improve the execution efficiency of the RISC-V Vector segment load / store instruction, and improve the out-of-order capability of the processor. Figure 2 The flowchart of the vector segment memory access instruction processing method of the embodiment of the present specification is shown. In the figure, the processing process of the RISC-V Vector segment load / store instruction in the processor is described. The order of the steps listed in the embodiment is only one of the many execution orders, and does not represent the only execution order. In actual system or device product execution, the method order shown in the embodiment or the drawing can be executed in sequence or in parallel. Specifically, as shown in the figure, the method can include the following steps. Figure 2 The method can include the following steps.

[0091] Step 201: decoding the vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment memory access instruction and the configuration information of the vector control state register;

[0092] Step 202: splitting the macro operations that can be dispatched into a plurality of micro operations according to the size of each vector element and the effective vector length;

[0093] Step 203: calculating the memory access byte number and the memory access address of each micro operation;

[0094] Step 204: executing each micro operation according to the memory access byte number and the memory access address of each micro operation.

[0095] In the prior art, for the RISC-V segment access instruction, the data loaded or stored by one register is often discontinuous in the memory, and in this case, the implementation mode of the scalar access instruction cannot be reused. Taking the access instruction (load instruction) as an example, if all the data is first retrieved and then the retrieved data is processed into the correct format of the data required by the register, the data dependency between registers will inevitably be increased. In addition, the RISC-V access instruction is in units of elements, and the segment access instruction is subject to the conditions of nf, LMUL / EMUL, SEW / EEW, and VL, and when the data is processed, the logic complexity will inevitably be increased, and a large amount of logic resources will be consumed.

[0096] Therefore, in the embodiments of the present specification, the address and size of the data accessed by each register are calculated by a standardized calculation formula based on the element as the granularity, so as to reduce the dependency between registers and reduce the logic resources required for data processing.

[0097] In the embodiments of the present specification, the instruction opcode of the vector segment access instruction includes a plurality of fields for describing the behavior and operands of the instruction, which can specifically include:

[0098] The mop field is used to distinguish the access mode, and in the embodiments of the present specification, the access mode can include the index mode, the unit stride mode, or the fixed stride mode.

[0099] The width field specifies the actual bit width (EEW) of each element actually operated when the instruction is executed, and is used to determine the size of each element when accessing the memory.

[0100] The nf field is used for segment access (segment load / store) and specifies the number of segments to be transmitted, which can also be referred to as the number of fields included in each vector element in the segment load / store.

[0101] The number of fields of each vector element depends on the specific access mode and instruction type. For example:

[0102] The unit stride mode includes the mop, width, and nf fields in the opcode, and each element usually corresponds to one memory address and one data value.

[0103] The index mode includes the mop, width, and nf fields in the opcode, and also needs an additional index register field (vs2) to specify the address offset of each element.

[0104] In the embodiments of the present specification, as Figure 3As shown, the vector segment memory access instruction is decoded into multiple macro operations based on the number of fields contained in each vector element of the instruction opcode and the configuration information of the vector control status register, including:

[0105] Step 301: Calculate the product of the number of registers in the vector register group and the number of fields to obtain the number of macro operations, and decode the vector segment memory access instruction into multiple macro operations according to the number of macro operations;

[0106] Step 302: Assign a macro operation ID to each macro operation.

[0107] In the embodiments of this specification, the number of registers contained in the vector register group refers to the number of physical vector registers that the hardware logically binds into a wider virtual register. The number of registers contained in the vector register group can be represented by vec_group, and nf*vec_group represents the number of macro operations, thereby decoding the vector segment memory access instruction into multiple macro operations (mop) according to this number.

[0108] Then assign a macro operation ID (mop_id) to each macro operation.

[0109] In the embodiments of this specification, the values ​​of mop_id are assigned consecutively from zero according to the register numbering order. For example, if the starting register is V4, EMUL=2, nf=3, then the mop_id of registers V4 to V9 corresponding to mop are 0 to 5 respectively.

[0110] In embodiments of this specification, the number of registers contained in the vector register group is determined according to the memory access mode of the vector segment memory access instruction.

[0111] Specifically, such as Figure 4 As shown, determining the number of registers included in the vector register group based on the memory access mode of the vector segment memory access instruction includes:

[0112] Step 401: If the memory access mode is indexed mode, then the number of registers contained in the vector register group is the same as the number of vector register groups in the configuration information;

[0113] Step 402: If the memory access mode is a unit step mode or a fixed step mode, then the number of registers contained in the vector register group is the actual register grouping multiplier when the vector segment memory access instruction is executed.

[0114] In the embodiments of the present specification, when the instruction is decoded by the decoding module, the type of the instruction is obtained by decoding, if it is an index type, the corresponding mop is generated by using the values of LMUL and nf; if it is a unit stride or stride type, the corresponding mop is generated according to the values of EMUL and nf, and each mop is assigned a mop_id.

[0115] Then sent to the dispatch module, when the mop can be dispatched, sent to the instruction splitting module.

[0116] In the embodiments of the present specification, judging whether the macro operation can be successfully dispatched is a complex process involving hardware architecture, micro instruction set, processor state and resource availability. It occurs inside the processor, usually by the scheduler or dispatch unit. The following is a detailed description of the key factors and steps required to determine whether the MOP can be dispatched:

[0117] Core principle: the dispatch unit must ensure that the macro operation has all the resources required for execution, and its execution will not violate the correctness constraints of the processor (such as data dependency, resource conflict, state exception).

[0118] Key factors of the judgment process:

[0119] Legality and validity of the mop itself:

[0120] Format correctness: the encoding format of the mop must conform to the instruction set architecture (ISA) and microarchitecture specifications. The dispatch unit will perform preliminary decoding and format checking.

[0121] Opcode validity: the opcode of the mop must be mapped to a valid micro-operation or micro-instruction sequence supported by the processor.

[0122] Operand availability and validity:

[0123] Source operand: the source register (physical or logical) required by the mop must exist and contain valid data (not in an uninitialized state). For memory operations, the base / index registers required for address calculation must also be valid.

[0124] Target operand: the target register must be writable (for example, not a read-only register or in an exception state). For stores, the target address must be writable.

[0125] Immediate: the immediate needs to be correctly extracted and expanded.

[0126] Data dependency and correlation:

[0127] RAW (Read After Write): This is the most common dependency. The dispatch unit checks if the source operand of the mop depends on any previous dispatched or executing MOP that has not completed the write (i.e. the result has not been written back to the register file or memory). If there is an outstanding RAW dependency, the current mop is usually stalled until the dependency is resolved (through register renaming or waiting).

[0128] WAR (Write After Read): The dispatch unit needs to ensure that the target register written by the current mop does not overwrite the value read by a mop that has been dispatched but not executed (in program order) yet. Register renaming technique is the main means to resolve WAR. If there is no free renaming register available, the dispatch can be stalled.

[0129] WAW (Write After Write): The dispatch unit needs to ensure that the target register written by the current mop does not overwrite the result of a write to the same logical register by a mop that has not completed yet, but is earlier in program order. Register renaming again solves this problem. No free renaming register stalls the dispatch.

[0130] Memory dependency: For mops involving memory access (Load / Store):

[0131] Load: Needs to ensure that the address it reads has not been written by any Store operation that has not completed yet, but is earlier in program order (i.e. Store-Load Forwarding is available or needs to wait for the Store to complete).

[0132] Store: Needs to ensure that the address it writes has not been accessed by any Load or Store operation that has not completed yet, but is earlier in program order (avoid memory order violation). This is usually tracked by a Memory Order Buffer (MOB) or similar structure.

[0133] Resource availability:

[0134] Execution unit / function unit: The mop needs a specific type of execution unit (e.g. ALU, FPU, AGU, Load / Store Unit, Branch Unit). The dispatch unit needs to check if there is a free function unit of that type available to handle the mop.

[0135] Reservation station / issue queue: The dispatch unit places the mop into a Reservation Station or Issue Queue, waiting for an execution unit to become free and execute. There must be a free slot to accommodate the mop.

[0136] Reorder Buffer (ROB): In an out-of-order processor, the ROB tracks the status and results of all non-retired instructions. There must be a free ROB entry allocated to the mop.

[0137] Register Renaming Resource: There must be a free physical register allocated to the mop's write target logical register (to resolve WAW / WAR dependencies).

[0138] Load / Store Queue: For memory operations, there must be a free entry in the Load Queue or Store Queue.

[0139] Bus / Port Bandwidth: For mops that need to access cache, memory or I / O, there must be available data bus, address bus or port bandwidth.

[0140] Processor State and Events:

[0141] Interrupt and Exception Suspension: If there is a higher priority interrupt request or an unhandled exception, the processor can suspend dispatch of new instructions to handle these events first.

[0142] Branch Prediction and Speculation Status: In out-of-order execution, a mop can be in a speculative execution path (based on branch prediction). The dispatch unit can need to flush mops on the subsequent incorrect path (including those not yet dispatched) upon detecting a branch misprediction. Some architectures can restrict dispatch of certain types of mops on a speculative path.

[0143] Mode and Status Registers: Execution of a mop can depend on certain processor mode bits or status register bits (such as floating point status word, condition code register). The dispatch unit needs to ensure that the current state satisfies the mop's requirements, or the mop itself will update these states (ensuring the update order).

[0144] Serialization Operations: Certain special instructions (such as modifying control registers, memory barriers, serialization instructions) can require flushing the pipeline or blocking subsequent instruction dispatch until it completes to ensure atomicity and visibility of the operation. Dispatching such a mop will block dispatch of all subsequent mops.

[0145] Microcode Sequences (if applicable):

[0146] If the macro-operation needs to be implemented by a sequence of microcode (such as complex CISC instructions or handling exceptions), the dispatch unit can need to check if the microcode ROM access path or microcode sequencer is ready, and if there are resources to accommodate the multiple micro-operations generated by the microcode sequence.

[0147] Dispatch Decision Process:

[0148] Receive and Queue: The dispatch unit receives decoded MOPs from the front end (fetch / decode stage) and places them in the dispatch queue or directly into the dispatch decision process.

[0149] Parallel Checks: For the MOPs waiting in the dispatch queue (usually the first few in program order), the dispatch unit performs the following checks in parallel:

[0150] Check for operand dependencies (mainly to see if the source operands are produced by outstanding instructions - determined by the rename map and status bits).

[0151] Check for target resource availability (ROB, reservation station, rename register, LSQ entry).

[0152] Check for functional unit availability (whether there is a free unit of the corresponding type).

[0153] Check for privilege, status, event to allow dispatch.

[0154] Check for memory dependencies (via MOB status).

[0155] Select and Dispatch: In a given clock cycle, the dispatch unit attempts to select one or more MOPs (depending on the processor's issue width) that are the oldest, all dependencies are satisfied, and all required resources are available for dispatch.

[0156] Resource Allocation: Once a MOP is selected for dispatch:

[0157] Allocate a ROB entry (records instruction status, PC, architectural target, etc.).

[0158] Allocate a reservation station entry (holds opcode, operand values or tags, target tag).

[0159] Allocate a rename register (maps logical target register to physical register).

[0160] For Load / Store, allocate a LSQ entry.

[0161] Send MOP information (opcode, operand tags / values, target tag) to the corresponding reservation station.

[0162] Stall: If any of the checks for a mop fails (e.g. source operand not ready, no free ROB, functional unit busy, unresolved memory dependency, interrupt pending, etc.), the dispatch of that mop is stalled. It stays in the dispatch queue and is rechecked in the next cycle. Stalling a mop usually stalls the dispatch of all the subsequent (in program order) mops as well (unless the architecture supports limited out-of-order dispatch).

[0163] According to one embodiment of the present specification, as shown in Figure 5 The dispatchable macro-operations are split into micro-operations according to the size of each vector element and the effective vector length, including:

[0164] Step 501: Calculate the number of vector elements processed by each dispatchable macro-operation, and take the number of vector elements processed by each dispatchable macro-operation as the number of micro-operations split from each dispatchable macro-operation, respectively, and split each macro-operation into a plurality of micro-operations according to the number of micro-operations.

[0165] Step 502: Assign a micro-operation ID to each micro-operation.

[0166] In the embodiment of the present specification, the number of split uops is related to VL, and the number of elements processed by each mop can be obtained according to VL and vec_group, that is, the number of split uops, and a uop_id is marked on each split uop.

[0167] In the embodiment of the present specification, assigning a uop_id to each uop includes:

[0168] The uop_id is assigned to each uop from zero in sequence.

[0169] It should be noted that when the number of registers contained in the vector register group is less than 1 (for example, 1 / 2, 1 / 4 or 1 / 8), that is, the vector register group occupies one register or less, the uop_id assigned to each uop includes: the micro-operations (uops) in each vector register group are assigned from zero in sequence, respectively.

[0170] In addition, when the number of registers contained in the vector register group is less than 1, the uops in each vector register group also need to be marked with a field ID, the field IDs of the uops in the same vector register group are the same, and the field IDs corresponding to each vector register group are sequentially allocated from 0 to (1 / vec_group-1) in order, where vec_group represents the number of registers contained in the vector register group. If the number of registers contained in the vector register group is greater than or equal to 1, the field ID of the uop in the vector register group is 0.

[0171] Specifically, the method of calculating the number of uops needs to calculate the number of elements contained in a register theoretically to be processed num, wherein num=VLEN / EEW (for unit stride and stride access mode), or num=VELN / SEW (for index access mode), for example, for unit stride access mode, VLEN=128, SEW=32, a vector register group contains 128 / 32=4 elements in total;

[0172] Then calculate how many elements a vector register group can theoretically process at most, num1=VLEN / EEW*EMUL, for example, VLEN=128, SEW=32, EMUL=2, a vector register group contains 128 / 32*2=8 elements in total.

[0173] For segment, VL represents the number of elements processed by each vector register group, so the actual number of elements processed by a vector register group is VL (VL<=num1).

[0174] (1) When LMUL / EMUL is equal to 1, the number of uops is equal to VL;

[0175] (2) When LMUL / EMUL is greater than 1, prefer to start processing from the register with smaller register number, at this time, there can be some mop actually processing the number of elements less than num, at this time, decode nf*EMUL mops (select EMUL calculation for unit stride and stride access mode), decode nf*LMUL mops for index access mode, mop_id is 0, 1, …, EMUL-1, …, EMUL+1, …, nf*EMUL-1 respectively, at this time, nf vector register groups (the number of vector register groups is equal to nf) are included, each vector register group corresponds to (0, …, EMUL*1-1), (EMUL*1, …, EMUL*2-1), …, (EMUL*(nf-1), …, EMUL*nf-1) mop_id. At this time, each vector register group processes up to the i-1th mop, the number of elements processed by the mop_id greater than i-1 is 0, at this time, no actual memory access is involved, the number of elements processed by the mop_id less than i-1 is num, for the mop whose mop_id is equal to i-1, at this time, (VL-num*(mop_id%EMUL)) elements are processed, the number of uops split at last is equal to the number of elements num in the mop. It should be particularly noted that 0 uops are split for the mop, at this time, the access size is marked as 0. Wherein, i=(VL+num-1) / num*j, j represents the jth vector register group, for example, EMUL=4, nf=2, EEW=32, VLEN=128, VL=9, at this time, there are two vector register groups (the number of vector register groups is equal to nf), j is 1 and 2 respectively, the vector register group 1 corresponds to the mop_id 0, 1, 2, 3 respectively, the vector register group 2 corresponds to the mop_id 4, 5, 6, 7 respectively, for the vector register group 1 (mop_id=0, 1, 2, 3), i=(9+4-1) / 4*1=3, then the number of elements processed by the mop whose mop_id is greater than 3-1=2 is 0, when the mop_id is less than 3-1, that is, the mop_id is 0 or 1, 4 elements are processed, at this time, 4 uops are split, for the mop whose mop_id is 2, at this time, (9-4*(2%4)=1) elements are processed, at this time, 1 uop is split. Wherein, % is the modulo operation.

[0176] (3) When LMUL / EMUL is less than 1, there are nf vector register groups, and ceil(EMUL*nf) mops are decoded, and field_id needs to be allocated, the number of field_id allocated by each mop is related to nf and EMUL (or LMUL), 1 / EMUL field_id is allocated to the mop whose mop_id is less than ceil(EMUL*nf)-1, and VL uops are split for each field_id, nf-EMUL*nf*mop_id field_id is allocated to the mop whose mop_id is equal to ceil(EMUL*nf)-1, and VL uops are split for each field_id.

[0177] Then the access size and the access address of each uop are calculated.

[0178] In the embodiment of the present specification, as shown in Figure 6 The calculation of the access size of each micro-operation includes:

[0179] Step 601: If the access mode of the vector segment access instruction is the index mode, the access size of the micro-operation is equal to the default bit width of each element in the vector register;

[0180] Step 602: If the access mode of the vector segment access instruction is the unit stride mode or the fixed stride mode, the access size of the micro-operation is equal to the actual bit width of each element actually operated during the execution of the instruction in the instruction opcode.

[0181] In the embodiment of the present specification, for the index instruction, the access size of each uop is obtained according to SEW, and for the unit stride and stride instructions, the uop access size is obtained according to EEW.

[0182] Then the access address of the split uop is calculated according to the base address, mop_id, nf, uop_id, EMUL / LMUL, access_size, field_id and instruction type.

[0183] Specifically, the calculation of the access address of each micro-operation includes:

[0184] If the access mode of the vector segment access instruction is the index mode, the calculation formula of the access address of the micro-operation is:

[0185] wherein virt_addr1 represents the access address of the micro-operation corresponding to the index mode, rs1 represents the base address, vs2_offset represents the address offset, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group1 represents the number of registers contained in the vector register group corresponding to the index mode, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0186] If the access mode of the vector segment access instruction is the unit stride mode, the calculation formula of the access address of the micro-operation is:

[0187]

[0188] wherein virt_addr2 represents the access address of the micro-operation corresponding to the unit stride mode, rs1 represents the base address, VLEN represents the size of the vector register, nf represents the number of fields contained in each vector element in the segment load / store, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group2 represents the number of registers contained in the vector register group corresponding to the unit stride mode, uop_id represents the micro-operation ID of the micro-operation, and access_size represents the access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0189] If the access mode of the vector segment access instruction is the fixed stride mode, the calculation formula of the access address of the micro-operation is:

[0190] wherein virt_addr3 represents the access address of the micro-operation corresponding to the fixed stride mode, rs1 represents the base address, VLEN represents the vector length, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group3 represents the number of vector registers contained in the vector register group corresponding to the fixed stride mode, rs2 represents the stride, and access_size represents the access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation.

[0191] In the embodiments of the present specification, the base address rs1, the address offset vs2_offset and the stride rs2 can all be obtained from the corresponding instruction opcode in the vector segment memory access instruction, and the embodiments of the present specification will not be described herein.

[0192] Finally, the split uops are issued to the execution unit, and the execution unit executes each uop according to the memory access size and the memory access address of each uop. For example, if it is a segment store instruction, data needs to be written into the memory, at which time the data in the correct position is written according to the uop_id, mop_id and access_size, and if it is a segment load instruction, the retrieved data is written into the correct position of the vector register according to the uop_id, mop_id and access_size. Finally, when the mop split uops are all executed, it represents that the data reading of the corresponding vector register is completed.

[0193] Embodiment 1:

[0194] At the specific implementation level, the present embodiment describes the segment unit stride load instruction, as shown in Figure 7 There are 6 64-bit data of A0, B0, C0, A1, B1 and C1 arranged continuously in the memory, and the address of each data is as shown in Figure 7 The base address is 0x8000, and now the data of A0 and A1 needs to be loaded into the vector register V3, the data of B0 and B1 needs to be loaded into the vector register V4, and the data of C0 and C1 needs to be loaded into the vector register V5. At this time, VLEN=128, SEW=64, LMUL=1 and VL=2 can be configured, and the instruction vlseg3e64.v, v3, rs1 is used to achieve this, and the address saved in the vector register rs1 is 0x8000.

[0195] At the time of decoding, EMUL=1, EEW=64 and nf=3 are obtained, and 3 mops are decoded, each of which loads data back to the vector registers V3, V4 and V5, and the mop_id is 0, 1 and 2 respectively.

[0196] When the mop is issued to the instruction splitting module, according to the VL and EEW, it is concluded that each uop needs to be split into 2 uops, uop_id is 0 and 1 respectively, and the access_size of each uop is 8 bytes. Since EMUL = 1, the field_id of the uop is 0, and the address of each uop can be obtained according to the address calculation formula of the segment unit stride uop mentioned above. Further taking the write V5 vector register as an example, at this time, the load C0 and C1 two 64 bits of data, the decoded mop_id = 2, and two uops are split out:

[0197] uop 0load C0 data, uop address is

[0198] uop 1load C1 data, uop address should be

[0199] Embodiment 2:

[0200] At the specific implementation level, the embodiment describes the segment stride load type, as shown in Figure 8 , the memory has 6 64-bit data A0, B0, C0, A1, B1, C1, and the address of each data is given in Figure 8 , wherein the address difference between A0 and A1, B0 and B1, C0 and C1 is 0x100.

[0201] Load A0, A1 data into vector register V3, B0, B1 data into V4, C0, C1 data into V5, at this time, VLEN = 128, SEW = 64, LMUL = 1, VL = 2 can be configured, and vlsseg3e64.v, v3, rs1, rs2 instruction is used to realize, rs1 vector register saves the address 0x8000, and rs2 saves the address 0x100.

[0202] When decoding, EMUL = 1, EEW = 64, nf = 3 are obtained, and three mops are decoded, each of which loads data back to V3, V4, V5 vector register, mop_id is 0, 1, 2 respectively.

[0203] When the mop is issued to the instruction splitting module, according to the VL and EEW, it is concluded that each uop needs to be split into 2 uops, uop_id is 0 and 1 respectively, and the access_size of each uop is 8 bytes. According to the address calculation formula of the segment stride uop mentioned in the foregoing, the address of each uop can be obtained.

[0204] Further taking the write V5 vector register as an example, at this time, the load C0 and C1 two 64 bits of data, the decoded mop_id=2, and two uops are split out:

[0205] uop 0 load C0 data, uop address is

[0206] uop 1 load C1 data, uop address should be

[0207] Embodiment 3:

[0208] At the specific implementation level, the embodiment describes the segment index load type, VLEN=128, A0, B0, A1, B1, A2, B2, a total of 6 32 bits of data in the memory, and the addresses of each data are as shown in Figure 9 At this time, A0, A1, A2 need to be loaded into the vector register V4, and B0, B1, B2 need to be loaded into the vector register V5, at this time, the data load can be realized through the vector segment instruction.

[0209] More specifically, set LMUL=1, SEW=32, VL=3, and realize it through the vluxseg2ei32.v, v4, rs1, vs2 instruction, wherein rs1 saves the base address as 0x8000, vs2 saves the address offset, vs2 has 4 32 bits of elements, and each element is expressed as vs2[i], wherein vs2[0]=0, vs2[1]=0x100, and vs2[2]=0x300.

[0210] At the time of decoding, EMUL=1, EEW=32, nf=2, and two mops are decoded, each of which loads data back to the V4 and V5 vector registers, and mop_id is 0 and 1 respectively.

[0211] When the mop is issued to the instruction splitting module, according to the VL and SEW, it is concluded that each uop needs to be split into 3 uops, the uop_id is 0, 1, 2 respectively, and the access_size of each uop is 4 bytes. According to the segment index address calculation formula mentioned in the foregoing, the address of each uop can be obtained.

[0212] Further taking the write V5 vector register as an example, at this time, the load B0, B1, B2 loads 3 32-bit data, the decoded mop_id is 1, and 3 uops are split out:

[0213] The uop 0 loads B0 data, and the uop address is

[0214] The uop 1 loads B1 data, and the uop address should be

[0215] The uop 2 loads B2 data, and the uop address should be

[0216] Embodiment 4:

[0217] At the specific implementation level, the embodiment illustrates the segment unit stride load instruction with LMUL / EMUL greater than 1, taking the vlseg2e64.v, v4, rs1 instruction as an example, setting VLEN = 128, LMUL = 2, SEW = 64, VL = 3. At this time, EEW = 64, EMUL = 2, nf = 2, and the starting vector register vd of the target vector register group is equal to V4. Therefore, data needs to be loaded into 4 vector registers V4, V5, V6 and V7, wherein V4 and V5 are a vector register group, and V6 and V7 are a vector register group. The distribution of data in the memory and the data that each vector register should load are as shown in the following table. Figure 10

[0218] In the decoding stage, nf*EMUL = 2*2 = 4 mops need to be decoded, which are the same as the consecutive vector register numbers. At this time, the mop_id corresponding to v4-v7 is 0, 1, 2, 3 respectively. At this time, nf = 2 vector register groups are included, and the mop_id corresponding to each vector register group is (0, 1), (2, 3).

[0219] When the mop is issued to the instruction splitting module, the number of split uops is calculated according to the VL, VLEN, EEW and EMUL. VL = 3 indicates that each vector register group processes 3 elements. At this time, a vector register contains the number of elements to be processed in theory num = VLEN / EEW = 128 / 64 = 2. ​

[0220] For the first vector register group (containing vector registers V4 and V5, mop_id is 0, 1), j = 1, at this time i = (3 + 2 - 1) / 2 * 1 = 2, at this time the maximum number of mop processed in each vector register group is i - 1 = 2 - 1 = 1, the number of elements processed by mop_id greater than 1 is 0, at this time it does not involve actual memory access, the number of elements processed by mop_id less than 1 is num = 2, for the mop whose mop_id is equal to 1, at this time VL - num * (mop_id % EMUL) = 3 - 2 * (1 % 2) = 1 elements are processed, so V4 loads 2 elements and V5 loads 1 element, so mop 0 splits out 2 uops, which are uop 0 and uop 1 respectively, and mop 1 only needs to generate a uop, which is uop 0.

[0221] For the second vector register group (containing vector registers V6 and V7, mop_id is 2, 3), j = 2, at this time i = (3 + 2 - 1) / 2 * 2 = 4, at this time the maximum number of mop processed in each vector register group is i - 1 = 4 - 1 = 3, the number of elements processed by mop_id greater than 3 is 0, at this time it does not involve actual memory access, the number of elements processed by mop whose mop_id is less than 3 is num = 2, for the mop whose mop_id is equal to 3, at this time VL - num * (mop_id % EMUL) = 3 - 2 * (3 % 2) = 1 elements are processed, so V6 loads 2 elements and V7 loads 1 element, so mop 2 splits out 2 uops, which are uop 0 and uop 1 respectively, and mop 3 only needs to generate a uop, which is uop 0.

[0222] Further, taking the writing of the V5 vector register as an example, a uop is split out, the access_size of which is 8 bytes, and the uop address is Similarly, for the uop address split for V7:

[0223] Embodiment 5:

[0224] At the specific implementation level, the embodiment illustrates the segment unit stride load instruction whose EMUL is less than 1, taking the vlseg4e32.v, v4, rs1 instruction as an example, setting VLEN = 128, LMUL = 1 / 2, SEW = 32, VL = 2. At this time, EEW = 32, EMUL = 1 / 2, nf = 4, the starting vector register vd of the target vector register group is equal to v4, nf * EMUL = 2, at this time data needs to be loaded into V4 and V5, a total of 2 vector registers, the distribution of data in the memory and the data that should be loaded into each vector register are as followsFigure 11 As shown.

[0225] In the decoding stage, ceil(EMUL*nf) = 2 mops need to be decoded, and the consecutive vector register numbers are the same, at this time the mop_id corresponding to V4 and V5 is 0 and 1 respectively. When the mop is issued to the instruction splitting module, the number of split uops is calculated according to VL, VLEN, EEW and EMUL, at this time field_id needs to be allocated, the number of field_id allocated by each mop is related to nf and EMUL (or LMUL), when mop_id is less than ceil(EMUL*nf)-1 = 1, 1 / EMUL = 2 field_id is allocated for each mop, and each field_id splits VL = 2 uops, for the mop_id equal to ceil(EMUL*nf)-1, nf-EMUL*nf*mop_id = 4-1 / 2*4*1 = 2 filed_id is allocated, and each field_id splits VL = 2 uops.

[0226] VL = 2 indicates that each vector register group processes 2 elements, and since EMUL = 1 / 2, each vector register group only occupies half of the vector register. A vector register is divided into two parts, filed_id is marked as 0 and 1 respectively, and the whole mop needs to be split into 4 uops, and each vector register group only corresponds to 2 uops, and the uop_id of each uop is as shown in Figure 11 As shown, the uop splitting of V5 is the same.

[0227] Further taking writing V4 vector register as an example, 4 uops are split, access_size = 4 bytes, uop_id = 1, and the address of the uop of filed_id = 1 is 0x8000 + 128 / 8 x 2 x [0%(1 / 2)] + 1 x 4 x 4 + 4 x [0 / (1 / 2)] + 4 x 1 = 0x8014. Similarly, the address of the uop of mop_id = 1, uop_id = 1, field_id = 1 is

[0228] Embodiment 6:

[0229] In a specific implementation level, the segment unit stride store instruction is explained, taking VLEN = 128, LMUL = 1, SEW = 32, VL = 3, vsseg2e32.v vs2, rs1 as an example. Vector registers V2 and V3 have 4 32-bit data respectively, and the data arrangement is as shown in Figure 12As shown, because nf = 2, EMUL = 1, two mops are decoded in the same way as the decode mop of the load instruction, and mop_id is 0 and 1 respectively. For mop 1, because VL = 3, EMUL = 1, one mop needs to be split into 3 uops, uop_id is 0, 1, 2 respectively, and the number of bytes stored in each uop is EEW / 8 = 4, and the field_id of each uop is 0.

[0230] When each uop is sent to the execution unit for execution, data needs to be taken from the vector register, and the data processing module selects the correct vector register through mop_id, and selects the element through uop_id and field_id. For example, mop_id = 1, uop_id = 2, field_id = 0, at this time, the 3rd 4-byte element (i.e. B2) in the vector register V3 is taken and written into the memory, and the address calculation method of each uop is the same as the uop calculation formula of the segment unit stride load / store mentioned in the foregoing.

[0231] Based on the same inventive concept, the embodiments of the present disclosure also provide a vector segment memory access instruction processing apparatus, as shown in Figure 13 The apparatus comprises:

[0232] a macro operation splitting unit 1301 configured to decode the vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction opcode of the vector segment memory access instruction and the configuration information of the vector control state register;

[0233] a micro operation splitting unit 1302 configured to split the dispatchable macro operations into a plurality of micro operations according to the size of each vector element and the effective vector length;

[0234] a calculation unit 1303 configured to calculate the memory access byte number and the memory access address of each micro operation;

[0235] an execution unit 1304 configured to execute each micro operation according to the memory access byte number and the memory access address of each micro operation.

[0236] Further, the decoding of the vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction opcode of the vector segment memory access instruction and the configuration information of the vector control state register comprises:

[0237] calculating the product of the number of vector registers contained in the vector register group and the number of fields to obtain the number of macro operations, and decoding the vector segment memory access instruction into a plurality of macro operations according to the number of macro operations;

[0238] assigning a macro-operation ID to each macro-operation.

[0239] Further, the apparatus is further configured to:

[0240] determining the number of vector registers contained in the vector register group according to the access mode of the vector segment access instruction.

[0241] Further, determining the number of vector registers contained in the vector register group according to the access mode of the vector segment access instruction comprises:

[0242] if the access mode is the index mode, the number of vector registers contained in the vector register group is the vector register grouping multiplier in the configuration information;

[0243] if the access mode is the unit stride mode or the fixed stride mode, the number of vector registers contained in the vector register group is the actual register grouping multiplier when the vector segment access instruction is executed.

[0244] Further, assigning a macro-operation ID to each macro-operation comprises:

[0245] assigning the macro-operation IDs consecutively from zero.

[0246] Further, splitting the dispatchable macro-operation into a plurality of micro-operations according to the size of each vector element and the effective vector length comprises:

[0247] calculating the number of vector elements processed by each dispatchable macro-operation, taking the number of vector elements processed by each dispatchable macro-operation as the number of micro-operations split from each dispatchable macro-operation respectively, and splitting each macro-operation into a plurality of micro-operations according to the number of micro-operations;

[0248] assigning a micro-operation ID to each micro-operation.

[0249] Further, assigning a micro-operation ID to each micro-operation comprises:

[0250] assigning the micro-operation IDs consecutively from zero.

[0251] Further, the apparatus is further configured to:

[0252] when the number of vector registers contained in the vector register group is less than 1, marking a field ID to each micro-operation, the field ID being sequentially assigned from 0 to (1 / vec_group-1), wherein vec_group represents the number of vector registers contained in the vector register group.

[0253] Further, calculating the number of access bytes of each micro-operation comprises:

[0254] If the access mode of the vector segment access instruction is the index mode, the access byte number of the micro-operation is equal to the default bit width of each element in the vector register;

[0255] If the access mode of the vector segment access instruction is the unit stride mode or the fixed stride mode, the access byte number of the micro-operation is equal to the actual bit width of each element actually operated when the instruction is executed.

[0256] Further, the access address of each micro-operation is calculated as follows:

[0257] If the access mode of the vector segment access instruction is the index mode, the access address of the micro-operation is calculated as follows:

[0258] wherein virt_addr1 represents the access address of the micro-operation corresponding to the index mode, rs1 represents the base address, vs2_offset represents the address offset, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group1 represents the number of vector registers contained in the vector register group corresponding to the index mode, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0259] If the access mode of the vector segment access instruction is the unit stride mode, the access address of the micro-operation is calculated as follows:

[0260]

[0261] wherein virt_addr2 represents the access address of the micro-operation corresponding to the unit stride mode, rs1 represents the base address, VLEN represents the size of the vector register, nf represents the number of fields contained in each vector element in the segment load / store, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group2 represents the number of vector registers contained in the vector register group corresponding to the unit stride mode, uop_id represents the micro-operation ID of the micro-operation, access_size represents the access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation;

[0262] If the access mode of the vector segment access instruction is the fixed stride mode, the access address of the micro-operation is calculated as follows:

[0263] Wherein, virt_addr3 represents the access address of the micro-operation corresponding to the fixed step mode, rs1 represents the base address, VLEN represents the vector length, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group3 represents the number of vector registers contained in the vector register group corresponding to the fixed step mode, rs2 represents the step, and access_size represents the access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation.

[0264] Further, if the number of vector registers contained in the vector register group is greater than or equal to 1, the field ID of the micro-operation is 0.

[0265] The beneficial effects achieved by the above-mentioned apparatus are consistent with the beneficial effects achieved by the above-mentioned method, and the embodiments of the present specification will not be described here.

[0266] As shown in Figure 14 is a structural schematic diagram of a computer device in an embodiment of the present specification. The apparatus in the embodiment of the present specification can be the computer device in the embodiment, which executes the method of the above embodiment of the present specification. The computer device 1402 can include one or more processing devices 1404, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 1402 can also include any storage resource 1406 for storing any kind of information such as code, settings, data, etc. Without limitation, for example, the storage resource 1406 can include any one or a combination of more than one of the following: any type of RAM, any type of ROM, a flash memory device, a hard disk, an optical disk, etc. More generally, any storage resource can store information using any technology. Further, any storage resource can provide volatile or non-volatile retention of information. Further, any storage resource can represent a fixed or removable component of the computer device 1402. In one case, the computer device 1402 can perform any operation of the associated instructions when the processing device 1404 executes the associated instructions stored in any storage resource or combination of storage resources. The computer device 1402 also includes one or more drive mechanisms 1408 for interacting with any storage resource, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0267] The computer device 1402 can also include an input / output module 1410 (I / O) for receiving input (via input device 1412) and for providing output (via output device 1414). One specific output mechanism can include a presentation device 1416 and associated graphical user interface (GUI) 1418. In other embodiments, the input / output module 1414 (I / O), the input device 1412, and the output device 1414 can not be included, e.g., as merely a computer device in a networked environment. The computer device 1402 can also include one or more network interfaces 1420 for exchanging data with other devices via one or more communication links 1422. The one or more communication buses 1424 couple the various components in the computer device 1402.

[0268] The communication links 1422 can be implemented in any manner, such as through a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication links 1422 can include any combination of hardwired links, wireless links, routers, gateway functionality, name servers, etc., governed by any protocol or combination of protocols.

[0269] The embodiments of the present specification also provide a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by a processor to implement the above method.

[0270] The embodiments of the present specification also provide a computer readable instruction, wherein when the processor executes the instruction, the program in the instruction makes the processor execute the above method.

[0271] It should be understood that, in various embodiments of the embodiments of the present specification, the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present specification.

[0272] It should also be understood that, in the embodiments of the present specification, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships. For example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the embodiments of the present specification generally represents an "or" relationship between the associated objects before and after it.

[0273] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0274] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0275] In several embodiments provided by the embodiments of the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can also be electrical, mechanical or other forms of connection.

[0276] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present specification.

[0277] In addition, each functional unit in each embodiment of the embodiments of the present specification can be integrated in one processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0278] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present specification or the entire or part of the technical solutions that contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present specification. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0279] The principles and implementation manners of the embodiments of the present specification are described in the embodiments of the present specification. The above embodiment description is only used to help understand the method and core idea of the embodiments of the present specification. Meanwhile, for those skilled in the art, according to the idea of the embodiments of the present specification, the specific implementation manners and application ranges will be changed. In summary, the content of the present specification should not be understood as a limitation of the embodiments of the present specification.

Claims

1. A method for processing vector segment memory access instructions, characterized in that, The method comprises: decoding the vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment memory access instruction and configuration information of a vector control state register; splitting each dispatchable macro operation into a plurality of micro operations according to the size of each vector element and the effective vector length; calculating the memory byte number and the memory address of each micro operation; executing each micro operation according to the memory byte number and the memory address of each micro operation.

2. The method of claim 1, wherein, The decoding of the vector segment memory access instruction into a plurality of macro operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment memory access instruction and configuration information of a vector control state register comprises: calculating the product of the number of vector registers contained in a vector register group and the number of fields to obtain the number of macro operations, and decoding the vector segment memory access instruction into a plurality of macro operations according to the number of macro operations; assigning a macro operation ID to each macro operation.

3. The method of claim 1, wherein, The method further comprises: determining the number of vector registers contained in the vector register group according to the memory access mode of the vector segment memory access instruction.

4. The method of claim 3, wherein, The determination of the number of vector registers contained in the vector register group according to the memory access mode of the vector segment memory access instruction comprises: if the memory access mode is an index mode, the number of vector registers contained in the vector register group is a vector register grouping multiplier in the configuration information; if the memory access mode is a unit stride mode or a fixed stride mode, the number of vector registers contained in the vector register group is an actual register grouping multiplier when the vector segment memory access instruction is executed.

5. The method of claim 2, wherein, The assigning of a macro operation ID to each macro operation comprises: continuously assigning from zero to each macro operation.

6. The method of claim 1, wherein, The splitting of each dispatchable macro operation into a plurality of micro operations according to the size of each vector element and the effective vector length comprises: calculating the number of vector elements processed by each dispatchable macro operation, taking the number of vector elements processed by each dispatchable macro operation as the number of micro operations split from each dispatchable macro operation respectively, and splitting each macro operation into a plurality of micro operations according to the number of micro operations; assigning a micro operation ID to each micro operation.

7. The method of claim 6, wherein, The assigning of a micro operation ID to each micro operation comprises: continuously assigning from zero to each micro operation.

8. The method of claim 6, wherein, The method further comprises: when the number of vector registers contained in a vector register group is less than 1, marking a field ID to each micro operation, and the field ID is sequentially assigned from 0 to (1 / vec_group-1), wherein vec_group represents the number of vector registers contained in the vector register group.

9. The method of claim 1, wherein, The calculation of the memory byte number of each micro operation comprises: if the memory access mode of the vector segment memory access instruction is an index mode, the memory byte number of the micro operation is equal to the default bit width of each element in the vector register; if the memory access mode of the vector segment memory access instruction is a unit stride mode or a fixed stride mode, the memory byte number of the micro operation is equal to the actual bit width of each element actually operated when the instruction is executed.

10. The method of claim 6, wherein, The calculation of the memory address of each micro operation comprises: if the memory access mode of the vector segment memory access instruction is an index mode, the calculation formula of the memory address of the micro operation is: wherein virt_addr1 represents a memory access address of the micro-operation corresponding to the index mode, rs1 represents a base address, vs2_offset represents an address offset, access_size represents a memory access byte number of the micro-operation, mop_id represents a macro-operation ID of a macro-operation corresponding to the micro-operation, vec_group1 represents a number of vector registers contained in a vector register group corresponding to the index mode, represents rounding down the division result, and field_id represents a field ID of the micro-operation; If the access mode of the vector segment access instruction is the unit stride mode, the calculation formula of the access address of the micro-operation is: wherein virt_addr2 represents the memory address of the micro-operation corresponding to the unit stride mode, rs1 represents the base address, VLEN represents the size of the vector register, nf represents the number of fields contained in each vector element in the segmented load / store, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group2 represents the number of vector registers contained in the vector register group corresponding to the unit stride mode, uop_id represents the micro-operation ID of the micro-operation, access_size represents the memory access size of the micro-operation, represents rounding down the result of the division, and field_id represents the field ID of the micro-operation; If the access mode of the vector segment access instruction is the fixed stride mode, the calculation formula of the access address of the micro-operation is: wherein virt_addr3 represents the access address of the micro-operation corresponding to the fixed stride mode, rs1 represents the base address, VLEN represents the vector length, access_size represents the access byte number of the micro-operation, mop_id represents the macro-operation ID of the macro-operation corresponding to the micro-operation, vec_group3 represents the number of vector registers contained in the vector register group corresponding to the fixed stride mode, rs2 represents the stride, access_size represents the access byte number of the micro-operation, represents rounding down the division result, and field_id represents the field ID of the micro-operation.

11. The method of claim 10, wherein, If the number of vector registers contained in the vector register group is greater than or equal to 1, the field ID of the micro-operation is 0.

12. A vector segment memory access instruction processing device, characterized in that, The device comprises: a macro-operation splitting unit, configured to decode the vector segment access instruction into a plurality of macro-operations according to the number of fields contained in each vector element in the instruction operation code of the vector segment access instruction and configuration information of a vector control state register; a micro-operation splitting unit, configured to split the dispatchable macro-operations into a plurality of micro-operations according to the size of each vector element and the effective vector length; a calculation unit, configured to calculate the access byte number and the access address of each micro-operation; an execution unit, configured to execute each micro-operation according to the access byte number and the access address of each micro-operation.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method in any one of claims 1 to 11.

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