Test machine engineering verification method, device and equipment

Abstract

The invention relates to a test machine engineering verification method, device and equipment. The method comprises the following steps: obtaining the sequence of all levels in a test machine project based on a verification request; according to the sequence of all the hierarchies and the parts, in the editing state, of the state machines in all the hierarchies, the target part, in the editing state, of the state machine in the lowest hierarchies is determined; verifying each part in the lowest level to obtain a verification result; and updating the state of the state machine of the target part in the lowest level based on the verification result, and sequentially updating the states of the state machines of the corresponding parts in the rest levels according to the sequence of the levels and the state of the state machine of the target part in the lowest level. By adopting the method, the test efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a test machine engineering verification method, device and equipment. BACKGROUND

[0002] The test engineering of a product (test program of a chip to be tested) generally consists of two parts, including a text file and a user-defined program (UserCode), wherein the text file is divided into multiple modules, such as PinMap, ChannelMap, Power, Level, etc. In order to ensure the accuracy of the test results, it is necessary to verify the test engineering edited by the user to ensure that the settings meet the requirements of the test system. During the development of the test program of the chip to be tested, the user will frequently modify the setting parameters and the user code of the UserCode according to the debugging requirements. Therefore, as the modifications are made, it is necessary to re-verify, and the consequent requirement for the verification speed of the increment of the dynamic modification is particularly high for the debugging efficiency.

[0003] In the traditional technology, the dynamic modification verification of the test engineering is full-amount verification, that is, full-amount verification is triggered each time.

[0004] However, the full-amount verification efficiency is very low, and any modification of the user needs to be re-verified, which greatly affects the debugging efficiency of the user. SUMMARY

[0005] Therefore, it is necessary to provide a test machine engineering verification method, device and equipment capable of improving the test efficiency in view of the above technical problems.

[0006] In a first aspect, the present application provides a test machine engineering verification method, which comprises:

[0007] obtaining the order between each level in the test machine engineering based on a verification request;

[0008] determining a target part in which the state machine in the lowest level is in an editing state according to the order between each level and the part in which the state machine in each level is in the editing state;

[0009] verifying each part in the lowest level to obtain a verification result;

[0010] updating the state of the state machine of the target part in the lowest level based on the verification result, and sequentially updating the state of the state machine of the corresponding part in the remaining levels according to the order between each level and the state of the state machine of the target part in the lowest level.

[0011] In one of the embodiments, the method further comprises:

[0012] A state machine is added to each part in each level of the test machine project, and states of the state machine include a first state determined based on a configuration and a second state determined based on a check, the first state includes at least one of a nonexistence state and an editing state, the nonexistence state is a state after a part is deleted, and the editing state is a state after a part is at least partially modified, and the second state includes at least one of a check success state, a check failure state and a check warning state.

[0013] In one embodiment, the test machine project includes a plurality of levels, and each level includes at least one part, and a state of a state machine of each part in a high level is determined based on a state of a state machine of a corresponding part in a low level.

[0014] In one embodiment, before the step of determining a target part in a lowest level whose state machine is in the editing state according to an order between the levels and the part in each level whose state machine is in the editing state, the method further includes:

[0015] In a case where there is a part in the lowest level whose state machine is in the first state, updating a state machine of a corresponding part in a high level to be in the editing state based on the part in the lowest level whose state machine is in the first state.

[0016] In a case where there is a part in an intermediate level whose state machine is in the editing state, updating a state machine of a corresponding part in a high level to be in the editing state based on the part in the intermediate level whose state machine is in the editing state, until the state of the state machine of the corresponding part in each level of the test machine project is updated.

[0017] In one embodiment, there is an association relationship between the parts in the lowest level, and the part in the lowest level whose association relationship exists belongs to a different part in a high level, and the method further includes:

[0018] In a case where there is a part in the lowest level whose state machine is in the first state, obtaining an association relationship corresponding to the part whose state machine is in the first state.

[0019] Based on the association relationship, updating a state machine of an associated part of the part whose state machine is in the first state to be in the editing state.

[0020] In one embodiment, the method further includes:

[0021] Receiving an adjustment instruction for the association relationship.

[0022] Based on the adjustment instruction, dynamically adjusting the association relationship.

[0023] The obtaining of the association relationship corresponding to the part whose state machine is in the first state includes:

[0024] acquire the latest association relationship of the part in the first state.

[0025] In one embodiment, the checking the parts in the lowest level to obtain a checking result comprises:

[0026] checking the target part in the lowest level whose state machine is in the editing state for legality;

[0027] in the case where the legality checking passes, checking the parts in the lowest level for characteristics;

[0028] in the case where the characteristics checking passes, obtaining a checking result that passes the checking;

[0029] in the case where the legality checking fails or the characteristics checking fails, obtaining a checking result that fails the checking.

[0030] In one embodiment, the checking the target part in the lowest level whose state machine is in the editing state for legality comprises:

[0031] determining the target parts in the lowest level whose state machine is in the editing state and has no association relationship based on the association relationship, and checking the target parts having no association relationship in parallel for legality.

[0032] In one embodiment, the hierarchy of the test machine project comprises elements, modules and projects.

[0033] In one embodiment, the updating the state of the state machine of the corresponding part in the remaining hierarchy in sequence according to the order between the hierarchies and the state of the state machine of the target part in the lowest level comprises:

[0034] updating the second state of the state machine of the module based on the second state of the state machine of each element included in the module;

[0035] updating the second state of the state machine of the project based on the second state of the state machine of each module included in the project.

[0036] In one embodiment, before the acquiring the order between the hierarchies in the test machine project based on the checking request, the method further comprises:

[0037] in the case where there is a part in the test machine project whose state machine is in the editing state, triggering the checking request.

[0038] In a second aspect, the application further provides a test machine project checking device, which comprises:

[0039] a hierarchical order obtaining module, configured to obtain an order between hierarchies in the test machine project based on the verification request;

[0040] a target part determining module, configured to determine a target part in a lowest hierarchy whose state machine is in an editing state according to the order between the hierarchies and states of state machines of parts in the hierarchies;

[0041] a verifying module, configured to verify the parts in the lowest hierarchy to obtain a verification result;

[0042] a state updating module, configured to update a state of the state machine of the target part in the lowest hierarchy based on the verification result, and sequentially modify states of state machines of corresponding parts in the remaining hierarchies according to the order between the hierarchies and the state of the state machine of the target part in the lowest hierarchy.

[0043] In a third aspect, a computer device is provided, which includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps of the method in any one of the above embodiments are implemented.

[0044] The test machine project verification method, device and equipment described above obtain an order between hierarchies in the test machine project based on a verification request, determine a target part in a lowest hierarchy whose state machine is in an editing state according to the order between the hierarchies and parts whose state machines are in the editing state, verify the parts in the lowest hierarchy to obtain a verification result, update a state of the state machine of the target part in the lowest hierarchy based on the verification result, and sequentially update states of state machines of corresponding parts in the remaining hierarchies according to the order between the hierarchies and the state of the state machine of the target part in the lowest hierarchy. In this way, the states of the parts in the hierarchies in the test machine project are determined by the state machines, only the parts whose state machines are in the editing state are verified, the effect of incremental verification is achieved, and the states of the corresponding hierarchies can be determined based on the verification result, thereby improving the test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application or the related art. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor based on these drawings.

[0046] Figure 1 a flowchart of a test machine project verification method in an embodiment;

[0047] Figure 2 a schematic diagram of a test machine project in an embodiment;

[0048] Figure 3 a schematic diagram of a test machine engineering for another embodiment;

[0049] Figure 4 a flowchart of a test machine engineering verification method for another embodiment;

[0050] Figure 5 a structural block diagram of a test machine engineering verification device for an embodiment;

[0051] Figure 6 an internal structure diagram of a computer device for an embodiment. DETAILED DESCRIPTION

[0052] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0053] It should be noted that the terms "first", "second", etc. used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" used in the present application and any variants thereof are intended to cover non-exclusive inclusion. The term "multiple" used in the present application refers to two and more than two. The term "and / or" used in the present application refers to one of the solutions, or any combination of multiple solutions.

[0054] In an embodiment, as shown in Figure 1 a test machine engineering verification method is provided, and the embodiment takes the method applied to a host computer or an industrial computer as an example. It should be understood that the method can also be applied to a server or a terminal. In the embodiment, the method includes the following steps:

[0055] S102: obtaining the order between each level in the test machine engineering based on the verification request.

[0056] The test machine engineering includes multiple levels, the levels are arranged in order from bottom to top, and each level can include multiple parts. The parts in each lower level can belong to the same parts in the adjacent upper level, or different parts, which is not specifically limited here.

[0057] In some optional embodiments, the levels of the test machine engineering include elements, modules and engineering in order from bottom to top. The module can include at least one element, and at least one element included in each module is different. The same element can belong to different modules. The engineering can include at least one module.

[0058] S104: determining a target part in the lowest level whose state machine is in the editing state according to the order between the levels and the part in each level whose state machine is in the editing state.

[0059] In some embodiments, a state machine is added to each part in each level, and the state of the state machine indicates the state of the corresponding part. In some optional embodiments, a state machine is added to each part in each level in the test machine project in advance, and the state of the state machine includes a first state determined based on a configuration and a second state determined based on a verification. The first state includes at least one of a non-existent state and an editing state. The second state includes at least one of a verification success state, a verification failure state, and a verification warning state. The non-existent state is a state of a part after being deleted, and the editing state is a state of a part after being at least partially modified.

[0060] In some embodiments, the state machine and the part are in one-to-one correspondence, that is, one part in one level corresponds to one state machine. For example, each element corresponds to one state machine, each module corresponds to one state machine, and each project corresponds to one state machine.

[0061] In some embodiments, the first state of the state machine is determined based on a user configuration. For example, the user can edit or delete the part, and the editing includes modifying the attribute of the part and adding a new part. The deletion means deleting the corresponding part. Therefore, the first state of the state machine can be determined based on the configuration of the part. If the configuration is to modify the attribute of the part and add a new part, the first state is the editing state. If the configuration is to delete the corresponding part, the first state is the non-existent state.

[0062] The second state of the state machine is obtained based on the verification result, and the second state includes at least one of a verification success state, a verification failure state, and a verification warning state. In other embodiments, if the verification state further includes other states, the second state can also include other states, which are not limited here.

[0063] In some embodiments, the user can edit or delete any part in any level and determine the first state of the corresponding state machine. Editing or deleting a part in a high level can cause editing or deleting a part in a low level. Therefore, editing or deleting any part in any level will eventually cause editing or deleting a part in the lowest level.

[0064] In some optional embodiments, before obtaining the order between the levels in the test machine project based on the verification request, the method further includes: triggering the verification request in the case that there is a part in the test machine project whose state machine is in the editing state.

[0065] In the embodiment, when the user triggers the verification, i.e., the user edits or deletes a part in a certain level, a verification request is triggered. Before triggering the verification request, the test machine project is traversed based on the user editing or deleting a part in a certain level to modify the first state of the state machine of the part in each level of the test machine project.

[0066] In addition, since the state is not present, the part does not need to be verified, and in the application, only the part with the first state being the edit state needs to be obtained. Since the verification of the high level depends on the result of the verification of the low level, when verifying, the target part with the state machine in the edit state in the lowest level is obtained.

[0067] Specifically, the application can first determine whether the state of the state machine of each part in the highest level is in the edit state. If so, it continues to determine whether the state of the state machine of the part in the next level is in the edit state, until the target part with the state machine in the edit state in the lowest level is obtained. In the process of traversal, each part in the lowest level can be verified until the traversal of the entire test machine project is completed.

[0068] S106: verifying each part in the lowest level to obtain a verification result.

[0069] S108: updating the state of the state machine of the target part in the lowest level based on the verification result, and sequentially updating the state of the state machine of the corresponding part in the remaining levels according to the order between the levels and the state of the state machine of the target part in the lowest level.

[0070] In some optional embodiments, sequentially updating the state of the state machine of the corresponding part in the remaining levels according to the order between the levels and the state of the state machine of the target part in the lowest level includes: updating the second state of the state machine of the module based on the second state of the state machine of each element included in the module; and updating the second state of the state machine of the project based on the second state of the state machine of each module included in the project.

[0071] Then, the second state of the state machine of the part in the high level is sequentially updated based on the second state of the state machine of the part in the lowest level until the modification is completed.

[0072] In some optional embodiments, sequentially updating the state of the state machine of the corresponding part in the remaining levels according to the order between the levels and the state of the state machine of the target part in the lowest level includes: updating the second state of the state machine of the module based on the second state of the state machine of each element included in the module; and updating the second state of the state machine of the project based on the second state of the state machine of each module included in the project.

[0073] Specifically, the embodiment takes elements, modules and projects as examples, and first verifies the elements to obtain second states of the elements. If an element verification succeeds, the second state of the state machine of the element is marked as a verification success state. If the element verification fails, the second state of the state machine of the element is marked as a verification failure state. If the element verification is an alarm, the second state of the state machine of the element is marked as a verification alarm state. Then, based on the second states of the state machines of the elements, the second states of the state machines of the modules are updated. For example, a module includes a plurality of elements, and the second states of the state machines of the plurality of elements included in the module are used to update the second state of the state machine of the module. Specifically, if the second states of the state machines of the elements included in the module are all verification success states, the second state of the state machine of the module is a verification success state. If the second state of the state machine of at least one element included in the module is a verification failure state, the second state of the state machine of the module is a verification failure state. If the second state of the state machine of at least one element included in the module is a verification alarm state and there is no verification failure state, the second state of the state machine of the module is a verification alarm state.

[0074] For a project, if the second states of the state machines of all modules in the project are verification successes, the second state of the state machine of the project is a verification success. If the second state of the state machine of at least one module in the project is a verification failure, the second state of the state machine of the project is a verification failure. If the second state of the state machine of at least one module in the project is a verification alarm and there is no verification failure, the second state of the state machine of the project is a verification alarm.

[0075] In some optional embodiments, after the second state of the state machine of the corresponding part is updated, the first state of the state machine of the part is reset, for example, to a default state.

[0076] The above test machine project verification method obtains the order between the levels in the test machine project based on the verification request; determines a target part in which the state machine in the lowest level is in an editing state according to the order between the levels and the parts in the editing state in the state machine in each level; performs verification on each part in the lowest level to obtain a verification result; updates the state of the state machine of the target part in the lowest level based on the verification result, and sequentially updates the states of the state machines of the corresponding parts in the remaining levels according to the order between the levels and the state of the state machine of the target part in the lowest level. In this way, the states of the parts in each level in the test machine project are determined through the state machines, only the parts in the editing state are verified, the effect of incremental verification is achieved, and the state of the corresponding level can be determined based on the verification result, thereby improving the test efficiency.

[0077] In one of the optional embodiments, the test machine project comprises a plurality of levels, each level comprising at least one part; wherein the state of the state machine of each part of a high level is determined based on the state of the state machine of the corresponding part in a lower level.

[0078] In one of the optional embodiments, the state machine comprises two states, a first state and a second state, and the state of the state machine of each part of a high level is determined based on the state of the state machine of the corresponding part in a lower level.

[0079] For the first state, the second state of the state machine of a part of a high level can be determined based on the inclusion relationship of the parts of different levels and the first state of the state machine of the part in a lower level; or the first state of the state machine of a part in the same level can be determined based on the association relationship of the parts in the same level.

[0080] For the second state, the second state of the state machine of a part of a high level can be determined based on the inclusion relationship of the parts of different levels and the second state of the state machine of the part in a lower level.

[0081] In one of the optional embodiments, before the step of determining the target part in the lowest level whose state machine is in the editing state according to the order between the levels and the parts in the state machine of each level being in the editing state, the method further comprises: in the case that there is a part in the lowest level whose state machine is in the first state, updating the state machine of the corresponding part in the higher level to be in the editing state based on the part in the lowest level whose state machine is in the first state; in the case that there is a part in the intermediate level whose state machine is in the editing state, updating the state machine of the corresponding part in the higher level to be in the editing state based on the part in the intermediate level whose state machine is in the editing state, until the state of the state machine of the corresponding part in each level in the test machine project is updated.

[0082] For the convenience of understanding, the elements, modules and projects are still taken as examples for illustration, combined with Figure 2 As shown in FIG. 1, it is assumed that the project comprises module A, module B and module C, module A comprises element a1, element a2 and a3, module B comprises element b1, element b2 and b3, and module C comprises element c1, element c2 and c3.

[0083] In the lowest level, the first state of the state machine of the element is changed to the editing state, and the first state of the state machine of the module and the test project where the element is located is changed to the editing state. For example, the element a1 is edited, the first state of the state machine of the element a1 is changed to the editing state, and the first state of the state machine of the corresponding module A and project is changed to the editing state. The element a1 is deleted, the first state of the state machine of the element a1 is changed to the non-existent state, and the first state of the state machine of the corresponding module A and project is changed to the editing state.

[0084] In one of the optional embodiments, there is an association relationship between the parts in the lowest level. The method further comprises: in the case where the state machine of the part in the lowest level is in the first state, obtaining the association relationship corresponding to the part whose state machine is in the first state; and based on the association relationship, updating the state machine of the associated part of the part whose state machine is in the first state to the editing state.

[0085] The association relationship is pre-established and maintained. There is an association relationship between the parts in the lowest level, and the parts in the lowest level with the association relationship belong to different parts or the same part in the higher level. In this application, in the case where the state machine of the part in the lowest level is in the first state, the association relationship corresponding to the part whose state machine is in the first state is obtained, and then the state machine of the associated part of the part whose state machine is in the first state is updated to the editing state.

[0086] For example, it is assumed that there is an association relationship between the elements a1 and b1, and there is an association relationship between the elements a1 and a3. In the case where the first state of the state machine of the element a1 is in the editing state, the elements b1 and a3 are obtained, and the first state of the state machines of the elements b1 and a3 is updated to the editing state.

[0087] In addition, the following examples are combined Figure 3 As shown, there is an element PinItem1 in the Pin module. If the element ChannelItem1 in the Channel module references the element PinItem1, and the element PowerItem1 in the Power module references the element PinItem1, the element PinItem1 establishes a relationship with the elements ChannelItem1 and PowerItem1. When the element PinItem1 is modified, the first state of the state machines of the elements ChannelItem1 and PowerItem1 is automatically changed to the editing state.

[0088] In one of the optional embodiments, the method further comprises: receiving an adjustment instruction of the association relationship; dynamically adjusting the association relationship based on the adjustment instruction; and obtaining the association relationship corresponding to the part in the first state of the state machine, comprising: obtaining the latest association relationship of the part in the first state of the state machine.

[0089] In the above embodiments, the association relationship between the elements can be established at the time of engineering establishment or after the engineering establishment, and the association relationship can be dynamically adjusted, that is, an adjustment instruction of the association relationship can be received, and the association relationship is dynamically adjusted based on the adjustment instruction. Therefore, each time the first state of the state machine is updated, the latest association relationship is obtained, and then the state of the state machine is updated based on the association relationship. Figure 3 For example, if the reference of the element PinItem1 in the Power module is deleted, the association relationship between the element PinItem1 and the Power module is unbound. The initial relationship of each element of the test project is established when the test project is read, for example, when the Channel file (module) is read, the Pin element is referenced, and the association relationship between the Item of the Channel module and the corresponding PinItem is established, and this relationship is not fixed. When the user edits the test project, the relationship is unbound and managed according to the actual situation. For example, the element PinItem1 is used in the element ChannelItem1, and the user edits and modifies it to PinItem2. Then, the ChannelItem1 is unbound from the element PinItem1 and bound to the element PinItem2.

[0090] In one of the optional embodiments, the lowest level is verified to obtain a verification result, comprising: performing legality verification on the target part in the lowest level in the editing state of the state machine; performing property verification on each part in the lowest level in the case where the legality verification passes; obtaining a verification result that passes the verification in the case where the property verification passes; and obtaining a verification result that fails to pass the verification in the case where the legality verification fails or the property verification fails.

[0091] In the above embodiments, the verification includes legality verification and property verification. The legality verification is performed on the element based on the rules of the element. The property verification is performed to check whether there is a duplicate element, and whether the settings of a parameter in the element are consistent. The property verification is performed on the module, that is, after all the elements in the module pass the legality verification, the property verification is performed on the elements in the module. For example, the Power module requires that the PowerItem1 and the PowerItem2 in the module cannot contain the same element PinItem.

[0092] In the present application, only the target part in the editing state of the state machine needs to be checked for legality. If the legality check fails, the second state of the state machine of the target element is modified to a check failure state. If the legality check succeeds, all elements in the hierarchy are checked for characteristics. If the characteristic check also passes, the second state of the state machine of the target element is modified to a check success state. If the characteristic check fails, the second state of the state machine of the target element is modified to a check failure state.

[0093] In some optional embodiments, the legality check on the target part in the editing state of the state machine in the lowest level includes: determining the target parts in the editing state of the state machine in the lowest level and without an association relationship based on the association relationship, and performing the legality check on the target parts without the association relationship in parallel.

[0094] Specifically, in the present embodiment, in order to improve the efficiency of the check, the legality check on the target parts in the editing state of the state machine in the lowest level and without the association relationship can be performed in parallel. For example, the element a1 and the element b1 have no association relationship, and the first state of the state machine of each of them is in the editing state. Therefore, the legality check on the two elements can be performed in parallel.

[0095] For the convenience of understanding, the above-mentioned embodiments are described in combination with the flowchart of the test machine engineering check method shown in FIG. 6. Figure 4 Figure 4 is a flowchart of another embodiment of the test machine engineering check method. In the embodiment, the user adds, deletes, or modifies at least one part in any level of the test engineering, thereby triggering the update of the first state of the state machine of each part in each level of the test engineering. In the case where the first state of the state machine of each part in each level of the test engineering is in the editing state, the incremental check is performed.

[0096] For the convenience of understanding, the above-mentioned embodiments are described in combination with the flowchart of the test machine engineering check method shown in FIG. 6.

[0097] Step two: determine whether the first state of the state machine of the module is in the editing state. If the first state of the state machine of the module is in the editing state, jump to step three. If the first state of the state machine of the module is not in the editing state, jump to step six.

[0098] Step three: determine whether the first state of the state machine of the element is in the editing state or the non-existent state. If the first state of the state machine of the element is in the editing state or the non-existent state, jump to step four. If the first state of the state machine of the element is not in the editing state or the non-existent state, jump to step five.

[0099] ​Step four: perform element check, according to the check result, update the second state of the state machine of the element, if the check is successful, the second state of the state machine of the element is check success; if the check fails, the second state of the state machine of the element is check failure, check alarm, the second state of the state machine of the element is check alarm, the specific check process can be referred to the above.

[0100] Step five: judge whether there are elements in the current module, if yes, jump to step three; otherwise, jump to step six.

[0101] Step six: module characteristic check: check the integration logic of all elements in the module, for example, for the Power module, it is required that PowerItem1, PowerItem2, etc. in the module cannot contain the same element PinItem.

[0102] Step seven: update the second state of the state machine of the module according to the second state of the state machine of each element and the result of the module characteristic check.

[0103] If the second state of the state machine of each element included in the module is check success state and the module characteristic check is successful, the second state of the state machine of the module is check success state, if the second state of the state machine of at least one element included in the module is check failure state or the module characteristic check fails, the second state of the state machine of the module is check failure state, if the second state of the state machine of at least one element included in the module is check warning state or the module characteristic check is warning state, and there is no check failure state and the module characteristic check is successful, the second state of the state machine of the module is check warning state.

[0104] Step eight: judge whether there are modules in the current project, if yes, jump to step two; otherwise, jump to step nine.

[0105] Step nine: update the second state of the state machine of the project according to the second state of the state machine of each module.

[0106] If the second state of the state machine of all modules in the test project is check success, the second state of the state machine of the project is check success, if at least one second state of the state machine of all modules in the test project is check failure, the second state of the state machine of the project is check failure, if at least one second state of the state machine of all modules in the test project is check alarm and there is no check failure, the second state of the state machine of the project is check alarm.

[0107] The above test machine project check method greatly improves the check efficiency and is convenient for the debugging of the test project on the basis of ensuring the accuracy of the check result.

[0108] In the test engineering debugging process, the correlation between each module and each element in the engineering is established, the change of a certain element will trigger the state change of itself and its associated elements, and the state of each module and element is checked automatically during engineering verification to achieve full-quantity verification, and the verification time is much less than the full-quantity verification time. In the product debugging process, the test machine process needs to be frequently modified, and the incremental verification can greatly improve the user debugging efficiency.

[0109] It should be understood that, although each step in the flowchart involved in the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, there is no strict order limitation for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0110] Based on the same inventive concept, the embodiments of the present application also provide a test machine engineering verification device for implementing the above-mentioned test machine engineering verification method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more test machine engineering verification device embodiments provided below can refer to the limitations of the test machine engineering verification method in the above text, which will not be repeated here.

[0111] In one exemplary embodiment, as shown in Figure 5 A test machine engineering verification device is provided, comprising: a hierarchical order acquisition module 401, a target part determination module 402, a verification module 403, and a state updating module 404, wherein:

[0112] The hierarchical order acquisition module 401 is configured to acquire the order between each level in the test machine engineering based on a verification request;

[0113] The target part determination module 402 is configured to determine a target part in the lowest level whose state machine is in an editing state according to the order between each level and the state of the state machine of each part in each level;

[0114] The verification module 403 is configured to verify each part in the lowest level to obtain a verification result;

[0115] The state updating module 404 is configured to update the state of the state machine of the target part in the lowest level based on the check result, and sequentially modify the states of the state machines of the corresponding parts in the remaining levels according to the sequence between the levels and the state of the state machine of the target part in the lowest level.

[0116] In an optional embodiment, the device further includes a state machine adding module configured to add a state machine to each part in each level in the test machine project, wherein the state of the state machine includes a first state determined based on the configuration and a second state determined based on the check, the first state includes at least one of a non-existent state and an edited state, and the second state includes at least one of a check success state, a check failure state and a check warning state, wherein the non-existent state is a state after the part is deleted, and the edited state is a state after the part is at least partially modified.

[0117] In an optional embodiment, the test machine project includes a plurality of levels, and each level includes at least one part, wherein the state of the state machine of each part in a high level is determined based on the state of the state machine of the corresponding part in a low level.

[0118] In an optional embodiment, the device further includes a first state updating module 404 configured to, in a case where there is a part in the lowest level whose state machine is in the first state, update the state machine of the corresponding part in the high level to the edited state based on the part in the lowest level whose state machine is in the first state, and in a case where there is a part in the intermediate level whose state machine is in the edited state, update the state machine of the corresponding part in the high level to the edited state based on the part in the intermediate level whose state machine is in the edited state, until the states of the state machines of the corresponding parts in the levels of the test machine project are updated.

[0119] In an optional embodiment, there is an association relationship between the parts in the lowest level, and the state updating module 404 is further configured to, in a case where there is a part in the lowest level whose state machine is in the first state, obtain the association relationship corresponding to the part whose state machine is in the first state, and update the state machine of the associated part of the part whose state machine is in the first state to the edited state based on the association relationship.

[0120] In an optional embodiment, the device further includes an adjusting module configured to receive an adjusting instruction for the association relationship, and dynamically adjust the association relationship based on the adjusting instruction, and the state updating module 404 is further configured to obtain the latest association relationship of the part whose state machine is in the first state.

[0121] In one of the optional embodiments, the verification module 403 is further specifically configured to perform legality verification on the target part in the lowest level whose state machine is in the editing state; perform property verification on each part in the lowest level if the legality verification passes; obtain a verification result of passing verification if the property verification passes; and obtain a verification result of failing verification if the legality verification fails or the property verification fails.

[0122] In one of the optional embodiments, the verification module 403 is further specifically configured to determine each target part in the lowest level whose state machine is in the editing state and has no association relationship based on the association relationship, and perform legality verification on each target part in parallel.

[0123] In one of the optional embodiments, the hierarchy of the tester project includes elements, modules, and projects.

[0124] In one of the optional embodiments, the update module is further specifically configured to update the second state of the state machine of the module based on the second state of the state machine of each element included in the module, and update the second state of the state machine of the project based on the second state of the state machine of each module included in the project.

[0125] In one of the optional embodiments, the device further includes a verification request receiving module configured to trigger a verification request if there is a part in the tester project whose state machine is in the editing state.

[0126] Each module in the tester project verification device can be realized by software, hardware, or a combination thereof, in whole or in part. Each module can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be called and executed by the processor to perform the operation corresponding to each module.

[0127] In one exemplary embodiment, a computer device is provided, which can be a host computer or an industrial computer, and its internal structure diagram can be as shown in Figure 6The computer device shown in the figure includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be realized through WIFI, mobile cellular network, near field communication (NFC) or other technologies. The computer program is executed by the processor to realize a test machine engineering verification method. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0128] Those skilled in the art can understand that, Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0129] In one embodiment, a computer device is also provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to realize the steps in each of the above method embodiments.

[0130] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to realize the steps in each of the above method embodiments.

[0131] In one embodiment, a computer program product is provided, including a computer program, and the computer program is executed by a processor to realize the steps in each of the above method embodiments.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0133] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0134] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method for engineering verification of a testing machine, characterized in that, The method includes: Obtain the order between different levels in the test machine project based on the verification request; Based on the order between the levels and the parts of the state machine in the editing state in each level, the target part of the state machine in the editing state in the lowest level is determined. Verify each part in the lowest level to obtain the verification result; Based on the verification result, the state of the state machine of the target part in the lowest level is updated, and according to the order between the levels and the state of the state machine of the target part in the lowest level, the state of the corresponding parts in the other levels is updated in turn.

2. The method according to claim 1, characterized in that, The method further includes: A state machine is added to all parts at each level of the test machine project. The state machine includes a first state determined based on configuration and a second state determined based on verification. The first state includes at least one of a non-existent state and an edit state. The second state includes at least one of a verification success state, a verification failure state, and a verification warning state. The non-existent state is the state after partial deletion, and the edit state is the state after at least partial modification.

3. The method according to claim 2, characterized in that, The test machine project comprises multiple levels, each level including at least one component; The state of each part of the state machine in the higher level is determined based on the state of the corresponding part of the state machine in the lower level.

4. The method according to claim 3, characterized in that, Before the step of determining the target part of the state machine in the lowest level that is in the edit state based on the order between the levels and the parts of the state machine in the edit state in each level, the method further includes: If there is a portion of the state machine in the lowest level that is in the first state, then based on the portion of the state machine in the lowest level that is in the first state, update the corresponding portion of the state machine in the next higher level to the edit state; If there is a part of the state machine in the intermediate level that is in the edit state, based on the part of the state machine in the intermediate level that is in the edit state, update the state machine of the corresponding part in the next higher level to the edit state, until the state update of the corresponding part of the state machine in each level of the test machine project is completed.

5. The method according to claim 2, characterized in that, There are relationships between the parts in the lowest level, and the parts in the lowest level with such relationships belong to different parts in the next higher level; the method further includes: If some state machines in the lowest level are in the first state, obtain the association relationships corresponding to the parts of the state machine that are in the first state. Based on the aforementioned association, the state machine associated with the part of the state machine that is in the first state is updated to the edit state.

6. The method according to claim 5, characterized in that, The method further includes: Receive instructions to adjust the association relationship; The association relationship is dynamically adjusted based on the adjustment instruction; The association relationships corresponding to the first state portion of the obtained state machine include: Obtain the latest associations of the first state portion of the state machine.

7. The method according to claim 5, characterized in that, The verification of each part in the lowest level to obtain the verification result includes: The legality of the target part in the lowest level state machine that is in the edit state is verified; If the legality check passes, feature checks are performed on each part of the lowest level. If the feature verification passes, a verification result indicating that the verification has passed is obtained; If the legality check fails or the feature check fails, a check result indicating that the check failed is obtained.

8. The method according to claim 7, characterized in that, The validity verification of the target portion in the lowest level state machine that is in the edit state includes: Based on the aforementioned relationships, each target part in the lowest level state machine that is in the edit state and has no relationships is identified, and the legality of each target part without such relationships is verified in parallel.

9. The method according to any one of claims 2 to 8, characterized in that, The test machine project is structured in layers including elements, modules, and projects.

10. The method according to claim 9, characterized in that, The step of updating the state of the corresponding parts of the state machines in the remaining levels sequentially according to the order between the levels and the state of the target part of the state machine in the lowest level includes: The second state of the state machine of the module is updated based on the second state of the state machine of each element included in the module. The second state of the state machine of the project is updated based on the second state of the state machine of each module included in the project.

11. The method according to any one of claims 1 to 8, characterized in that, Before obtaining the order between different levels in the test machine project based on the verification request, the following steps are included: If there is a part of the state machine in the test machine project that is in the edit state, a verification request is triggered.

12. A testing machine engineering verification device, characterized in that, The device includes: The hierarchy order acquisition module is used to obtain the order between different levels in the test machine project based on the verification request; The target part determination module is used to determine the target part whose state machine in the lowest level is in the editing state, based on the order between the levels and the state of the state machine of each part in each level. The verification module is used to verify each part in the lowest level and obtain the verification result; The state update module is used to update the state of the target part of the state machine in the lowest level based on the verification result, and to modify the state of the corresponding part of the state machine in the other levels in turn according to the order between the levels and the state of the target part of the state machine in the lowest level.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 11.

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