CPU interconnection link and detection device, detection method and control method thereof

Abstract

The invention relates to the technical field of servers, and discloses a CPU interconnection link and a detection device, a detection method and a control method thereof, the detection device comprises a control module, a first switch circuit, a second switch circuit and a pull-up circuit, and through collaborative design of the control module, the first switch circuit and the second switch circuit and the pull-up circuit, the first switch circuit and the second switch circuit are switched on and switched off. According to the invention, the adaptive detection of the two interconnection modes of the CPU-CPU and the CPU-PCIe is realized. Compared with a traditional single-mode detection scheme, the architecture can automatically identify the link type without manual intervention, the mode switching time is shortened from the minute level to the millisecond level, and the system deployment efficiency is remarkably improved. For example, in a cloud computing data center scene, topology reconstruction of server nodes can be rapidly completed, and the dynamic resource allocation requirement is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a CPU interconnection link and a detection device, detection method and control method thereof. BACKGROUND

[0002] With the continuous increase of CPU core number, single-socket servers have covered most application scenarios such as cloud computing, data center routine load and the like in terms of performance improvement, computing capability, bandwidth and capacity. In addition, the single-socket architecture server gradually becomes popular due to the demand of the industry for cost optimization and simplified design, and the market's dependence on multi-socket servers begins to decrease. However, the current traditional dual-channel server still occupies the mainstream position in the market, and some customers hope that it can be flexibly reconfigured into two single-channel servers when needed. However, the existing servers are either fixed as single-channel or fixed as dual-channel, and cannot realize dynamic switching, which is an urgent market demand to be met by new technology.

[0003] At the same time, the performance and core number of server CPU are continuously improved, and the traditional bus design defects are increasingly highlighted with the evolution of heterogeneous computing (CPU+GPU / FPGA) and single-socket architecture. The scalability of the traditional bus design is poor, and different hardware configurations are required for single-socket and multi-socket scenarios, which are difficult to dynamically adapt, and there is a problem of waste of bandwidth resources. In the multi-socket scenario, the bandwidth of PCIe peripherals is not fully utilized, and in the single-socket scenario, CPU interconnection resources are prone to be idle. SUMMARY

[0004] Therefore, the present application provides a CPU interconnection link and a detection device, detection method and control method thereof to solve the problem of how to detect the CPU interconnection link configuration.

[0005] In a first aspect, the present application provides a detection device of a CPU interconnection link. The interconnection link includes a first connector and a second connector. The first connector is connected to the second connector through a cable. A first input end of the first connector is connected to a first CPU, and an input end of the second connector is connected to a second CPU or a PCIe device. The detection device includes a control module, a first switch circuit, a second switch circuit, and a pull-up circuit. A first output end of the control module is connected to a control end of the first switch circuit. A second output end of the control module is connected to a control end of the second switch circuit. A third output end of the control module is connected to the first input end of the first connector. An input end of the control module is connected to an output end of the second connector. The input end of the control module is also connected to a first end of the pull-up circuit. A first end of the first switch circuit is connected to a control end of the first CPU, and a second end of the first switch circuit is grounded. A first end of the second switch circuit is connected to a control end of the second CPU, and a second end of the second switch circuit is grounded. A second end of the pull-up circuit is connected to a power supply voltage.

[0006] The application realizes adaptive detection of two interconnection modes of CPU-CPU and CPU-PCIe through the cooperative design of the control module, the double-switch circuit and the pull-up circuit. Compared with the traditional single mode detection scheme, the architecture can automatically identify the link type without manual intervention, shortens the mode switching time from minutes to milliseconds, and significantly improves the system deployment efficiency. For example, in the cloud computing data center scenario, the topology reconstruction of the server node can be quickly completed, meeting the dynamic resource allocation demand.

[0007] In an optional embodiment, the control module comprises an editable logic device.

[0008] In an optional embodiment, the first switch circuit comprises a first triode and a first resistor, wherein the first end of the first triode is connected with the control end of the first CPU, the first end of the first triode is also connected with the power supply voltage through the first resistor, the second end of the first triode is grounded, and the control end of the first triode is connected with the first output end of the control module.

[0009] In an optional embodiment, the second switch circuit comprises a second triode and a second resistor, wherein the first end of the second triode is connected with the control end of the second CPU, the first end of the second triode is also connected with the power supply voltage through the second resistor, the second end of the second triode is grounded, and the control end of the second triode is connected with the second output end of the control module.

[0010] In an optional embodiment, the pull-up circuit comprises a pull-up resistor.

[0011] In an optional embodiment, the control module is connected with a baseboard management controller.

[0012] In a second aspect, the present application provides a CPU interconnection link, comprising: a first connector, a second connector, and the detection device of the CPU interconnection link according to the first aspect and any one of the optional embodiments thereof, the detection device comprising: a control module, a first switch circuit, a second switch circuit, and a pull-up circuit, wherein the first connector is connected to the second connector through a cable, a first input end of the first connector is connected to a first CPU, and an input end of the second connector is connected to a second CPU or a PCIe device; a first output end of the control module is connected to a control end of the first switch circuit, a second output end of the control module is connected to a control end of the second switch circuit, a third output end of the control module is connected to the first input end of the first connector, an input end of the control module is connected to an output end of the second connector, and the input end of the control module is further connected to a first end of the pull-up circuit; a first end of the first switch circuit is connected to a control end of the first CPU, and a second end of the first switch circuit is grounded; a first end of the second switch circuit is connected to a control end of the second CPU, and a second end of the second switch circuit is grounded; and a second end of the pull-up circuit is connected to a power supply voltage.

[0013] In a third aspect, the present application provides a CPU interconnection link detection and control method, the detection method being applied to the control module of the detection device of the CPU interconnection link according to the first aspect and any one of the optional embodiments thereof, and the detection method comprising: outputting a detection signal to a first connector; judging whether the interconnection link is configured as a first interconnection mode or a second interconnection mode according to a feedback signal of a second connector and the detection signal, the first interconnection mode being a CPU and CPU interconnection mode, and the second interconnection mode being a CPU and PCIe interconnection mode; if the first interconnection mode is the CPU and CPU interconnection mode, outputting a first control signal to a first switch circuit and a second switch circuit, the first control signal being used to make a working mode of a first CPU and a second CPU be the CPU interconnection mode; and if the first interconnection mode is the CPU and PCIe interconnection mode, outputting a second control signal to the first switch circuit and the second switch circuit, the second control signal being used to make the working mode of the first CPU and the second CPU be the CPU and PCIe interconnection mode.

[0014] The present application breaks through the limitation of the traditional server connection architecture by multiprotocol multiplexing and dynamic bandwidth allocation of the MCIO connector, realizes adaptive bandwidth scheduling of single / dual-path architecture and workload perception, provides a high-performance-price-ratio and scalable hardware connection solution for data center, edge computing and other scenarios, and has significant technical innovation and commercial value.

[0015] In an optional embodiment, the first control signal is further used to control the first switch circuit and the second switch circuit to be turned on, and the second control signal is further used to control the first switch circuit to be turned off and the second switch circuit to be turned off.

[0016] In an alternative embodiment, the process of determining whether the interconnect link is configured in the first interconnect mode comprises: if the feedback signal of the second connector is the same as the detection signal, then the interconnect link is configured in the first interconnect mode.

[0017] In an alternative embodiment, the process of determining whether the interconnect link is configured in the second interconnect mode comprises: if the feedback signal of the second connector is different from the detection signal, then the interconnect link is configured in the second interconnect mode. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a block diagram of an application scenario of a CPU interconnect link used as a CPU interconnect according to an embodiment of the present application;

[0020] Figure 2 is a block diagram of an application scenario of a CPU interconnect link used as a PCIe device according to an embodiment of the present application;

[0021] Fig. 3(a), Fig. 3(b) is a composition diagram of a detection device of a CPU interconnect link according to an embodiment of the present application;

[0022] Figure 4 is a composition diagram of another detection device of a CPU interconnect link according to an embodiment of the present application;

[0023] Figure 5 is a flow chart of a CPU interconnect link detection and control method according to an embodiment of the present application;

[0024] Figure 6 is a composition diagram of another detection device of a CPU interconnect link according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0026] With the evolution of server CPU technology, the multiplexing design of PCIe ports and CPU interconnection bus becomes the key to improve hardware resource utilization and optimize cost and performance. For example, AMD Turin CPU, its PCIe and XGMI are multiplexed. Its multiplexing mechanism is as follows:

[0027] Turin (9005 series) supports PCIe 5.0 and XGMI (Zen 5 architecture multi-chip module interconnection protocol) multiplexing. Some PCIe channels can be dynamically switched to XGMI for connecting multiple CPUs (dual socket scenario).

[0028] Bandwidth allocation: for example, in Turin's 128 PCIe 5.0 channels, some can be allocated to XGMI, such as 32 channels for inter-CPU communication, and the remaining 96 channels for PCIe devices, or adjusted according to the configuration, such as using PCIe only in single socket, and multiplexing 32 channels for XGMI in dual socket.

[0029] Application scenario: in a dual socket server, CPUs communicate at high speed through XGMI multiplexed PCIe channels (bandwidth up to 128 GT / s, bidirectional over 50 GB / s), while the remaining PCIe channels are connected to GPUs, network cards, etc., balancing internal interconnection and external expansion requirements.

[0030] In ARM architecture server CPU, PCIe / CCIX module supports PCIe function and CCIX function, that is, PCIe function and CCIX function multiplexing, which can be configured as PCIe or CCIX as needed. When configured as PCIe, it can connect PCIe devices such as GPU, network card, etc. When you need to connect PCIe devices, you need to configure the multiplexed port of the CPU as PCIe, and when you need to interconnect two CPUs, you need to configure it as CCIX.

[0031] When the PCIe / CCIX multiplexed port of the CPU is used as a CCIX function, the system connection relationship is as shown in Figure 1 The PCIe / CCIX multiplexed port of the two CPUs is configured as CCIX by software, the PCIe / CCIX multiplexed port of CPU1 is connected to MCIO connector #1 through CCIX bus, then connected to the second MCIO connector #2 through MCIO cable, and then connected to the PCIe / CCIX multiplexed port of CPU2 through CCIX bus.

[0032] When the PCIe / CCIX multiplexed port of CPU1 is used as a PCIe function, the system connection relationship is as shown in Figure 2As shown, the PCIe / CCIX multiplexed port of CPU1 is configured as PCIe via software, connected to MCIO connector #1 via PCIe bus, then connected to the second MCIO connector #2 via MCIO cable, and finally connected to a PCIe device via PCIe bus.

[0033] This embodiment provides a detection device for a CPU interconnect link, the interconnect link including a first connector (i.e. Figure 1 , Figure 2 MCIO connector #1 and second connector (i.e.) Figure 1 , Figure 2 The MCIO connector #2 in the middle, the first connector is connected to the second connector via a cable (i.e., the MCIO cable), the first input terminal of the first connector is connected to the first CPU (i.e., Figure 1 , Figure 2 The CPU1 in the middle is connected, and the input end of the second connector is connected to the second CPU (i.e., Figure 1 , Figure 2 Connect to CPU2 or PCIe devices.

[0034] As shown in Figures 3(a) and 3(b), the detection device includes: a control module, a first switching circuit, a second switching circuit, and a pull-up circuit.

[0035] Specifically, the first output terminal of the control module is connected to the control terminal of the first switching circuit, the second output terminal of the control module is connected to the control terminal of the second switching circuit, the third output terminal of the control module is connected to the first input terminal of the first connector, the input terminal of the control module is connected to the output terminal of the second connector, and the input terminal of the control module is also connected to the first terminal of the pull-up circuit; the first terminal of the first switching circuit is connected to the control terminal of the first CPU, and the second terminal of the first switching circuit is grounded; the first terminal of the second switching circuit is connected to the control terminal of the second CPU, and the second terminal of the second switching circuit is grounded; the second terminal of the pull-up circuit is connected to the power supply voltage.

[0036] Specifically, the control module has the following detection functions:

[0037] Output a detection signal to the first connector; based on the feedback signal and detection signal from the second connector, determine whether the interconnection link is configured as a first interconnection mode or a second interconnection mode. The first interconnection mode is a CPU-to-CPU interconnection mode, and the second interconnection mode is a CPU-to-PCIe interconnection mode. If the first interconnection mode is a CPU-to-CPU interconnection mode, output a first control signal to the first switch circuit and the second switch circuit. The first control signal is used to enable the first CPU and the second CPU to operate in the CPU interconnection mode. If the first interconnection mode is a CPU-to-PCIe interconnection mode, output a second control signal to the first switch circuit and the second switch circuit. The second control signal is used to enable the first CPU and the second CPU to operate in the CPU-to-PCIe interconnection mode.

[0038] For example, the specific detection process is as follows:

[0039] (1) When the first CPU and the second CPU are connected Figure 1 In the aforementioned interconnect link, to detect whether the current interconnect link is configured in CPU-to-CPU interconnect mode, the control module sends a first control signal to the first and second switching circuits, and simultaneously sends a detection signal to the first connector (i.e., MCIO connector #1). Upon receiving the first control signal, the first and second switching circuits activate and output a mode selection signal to the first and second CPUs, respectively. This mode selection signal corresponds to the CPU-to-CPU interconnect mode. After the first and second CPUs switch to CPU-to-CPU interconnect mode, the detection signal is sent to the second connector (i.e., MCIO connector #2) via the MCIO cable. The second connector then feeds back the detection signal to the control module. Therefore, if the control module detects that its output detection signal is the same as the detection signal fed back by the second connector, the CPU interconnect link is configured in CPU-to-CPU interconnect mode.

[0040] (2) When the first CPU and PCIe device are connected Figure 2In the interconnection link, in order to detect whether the current interconnection link is configured as the CPU-PCIe interconnection mode, the control module sends a second control signal to the first switch circuit and the second switch circuit, and sends a detection signal to the first connector (i.e., the MCIO connector #1). At this time, the first switch circuit and the second switch circuit act after receiving the second control signal, and the first switch circuit outputs a mode selection signal to the first CPU. The mode selection signal corresponds to the CPU-PCIe interconnection mode. After the first CPU switches to the CPU-PCIe interconnection mode, the PCIe device does not feed back the detection signal to the second connector. At the same time, since the control module is pulled up to the power supply voltage by the pull-up circuit, if the control module detects that the output detection signal is different from the detection signal fed back by the second connector, i.e., the control module detects that the output detection signal is different from the signal at the input end of the control module, at this time, the CPU interconnection link is configured as the CPU-PCIe interconnection mode.

[0041] In some optional embodiments, the control module comprises an editable logic device.

[0042] In some optional embodiments, as shown in Figure 4 The first switch circuit comprises a first transistor Q1 and a first resistor R1. The first end of the first transistor Q1 is connected to the control end of the first CPU, and the first end of the first transistor Q1 is also connected to the power supply voltage through the first resistor R1. The second end of the first transistor Q1 is grounded, and the control end of the first transistor Q1 is connected to the first output end of the control module.

[0043] Specifically, when the output of the control module is high (e.g., 3.3V logic high), the current passes through the first resistor R1 and the first transistor Q1, so that the first transistor Q1 enters a saturated conduction state. At this time, the specific pin of the first CPU is connected to the ground potential. When the output of the control module is low (e.g., 3.3V logic high), the current passes through the first resistor R1 and the first transistor Q1, so that the first transistor Q1 enters an off state.

[0044] In some optional embodiments, as shown in Figure 4 The second switch circuit comprises a second transistor Q2 and a second resistor R2. The first end of the second transistor Q2 is connected to the control end of the second CPU, and the first end of the second transistor Q2 is also connected to the power supply voltage through the second resistor R2. The second end of the second transistor Q2 is grounded, and the control end of the second transistor Q2 is connected to the second output end of the control module.

[0045] Specifically, when the output of the control module is high (for example, 3.3V logic high), the current passes through the second resistor R2 and the second transistor Q2, so that the second transistor Q2 enters a saturated conduction state. At this time, the specific pin of the second CPU is connected to the ground potential. When the output of the control module is low (for example, 3.3V logic high), the current passes through the second resistor R2 and the second transistor Q2, so that the first transistor enters an off state.

[0046] In some optional embodiments, as shown in FIG. 1(a), the pull-up circuit includes a pull-up resistor R3. Figure 4

[0047] In some optional embodiments, as shown in FIG. 1(a), the pull-up circuit includes a pull-up resistor R3. Figure 4

[0048] The connection between the control module and the baseboard management controller BMC is not a simple physical line joint, but a highly integrated and intelligent communication system. The two are usually connected through a standard I2C (Inter-Integrated Circuit) bus or an SMBus (System Management Bus). This two-wire serial communication bus can achieve stable and efficient data transmission through only SCL (clock line) and SDA (data line).

[0049] In the present embodiment, a CPU interconnection link is provided, as shown in FIG. 3(a), FIG. 3(b), Figure 4 The detection device of the CPU interconnection link of the above embodiment and any optional embodiment thereof includes a control module, a first switch circuit, a second switch circuit, and a pull-up circuit.

[0050] The first connector is connected to the second connector through a cable. The first input end of the first connector is connected to the first CPU, and the input end of the second connector is connected to the second CPU or the PCIe device. The first output end of the control module is connected to the control end of the first switch circuit, the second output end of the control module is connected to the control end of the second switch circuit, the third output end of the control module is connected to the first input end of the first connector, the input end of the control module is connected to the output end of the second connector, and the input end of the control module is also connected to the first end of the pull-up circuit. The first end of the first switch circuit is connected to the control end of the first CPU, and the second end of the first switch circuit is grounded. The first end of the second switch circuit is connected to the control end of the second CPU, and the second end of the second switch circuit is grounded. The second end of the pull-up circuit is connected to the power supply voltage.

[0051] ​​In the embodiment, a CPU interconnection link detection and control method is provided. The detection method is applied to the control module of the detection device of the CPU interconnection link in the above embodiment and any optional implementation manner thereof. As shown in Figure 5 The detection method comprises the following steps:

[0052] Step S1: outputting a detection signal to the first connector.

[0053] Specifically, when the system enters the CPU interconnection mode configuration stage, the control module starts the signal output process based on the preset mode switching instruction. It outputs a first control signal to the first switch circuit and the second switch circuit respectively, which carries specific level combination and timing parameters and can accurately drive the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) array in the switch circuit to turn on and off according to the requirements of the CPU interconnection mode. Specifically, the first control signal changes the topology of the switch circuit to physically connect the communication pins of the first CPU and the second CPU, and configures the necessary bus protocol controller to enter the cooperative working state, ensuring that the two are in the CPU interconnection mode. At the same time, the control module outputs a detection signal to the first connector, which contains a periodic pulse sequence for detecting the pin state and connection impedance of the first connector, providing basic data for subsequent link state judgment.

[0054] Step S2: judging whether the interconnection link is configured as a first interconnection mode or a second interconnection mode according to the feedback signal of the second connector and the detection signal, the first interconnection mode being a CPU and CPU interconnection mode, and the second interconnection mode being a CPU and PCIe interconnection mode.

[0055] Step S3: if the first interconnection mode is the CPU and CPU interconnection mode, outputting a first control signal to the first switch circuit and the second switch circuit, the first control signal being used to make the working mode of the first CPU and the second CPU be the CPU interconnection mode; if the first interconnection mode is the CPU and PCIe interconnection mode, outputting a second control signal to the first switch circuit and the second switch circuit, the second control signal being used to make the working mode of the first CPU and the second CPU be the CPU and PCIe interconnection mode.

[0056] Optionally, the first control signal is also used to control the first switch circuit and the second switch circuit to turn on; the second control signal is also used to control the first switch circuit and the second switch circuit to turn off.

[0057] Optionally, if the feedback signal of the second connector is the same as the detection signal, the interconnection link is configured as the first interconnection mode. If the feedback signal of the second connector is different from the detection signal, the interconnection link is configured as the second interconnection mode.

[0058] Specifically, after the first control signal output and the detection signal transmission are completed, the control module starts to judge the interconnection link state. It monitors the feedback signal fed back by the second connector in real time, which contains the connection state of the connector pin, signal integrity parameters and other information. At the same time, combined with the return data of the detection signal previously sent to the first connector, the interconnection link is comprehensively evaluated through the built-in link state analysis algorithm. In the specific judgment process, the control module will compare the standard parameters of the CPU and CPU interconnection mode, including signal transmission delay, data throughput rate threshold, protocol handshake response time and other indicators. If the link parameters reflected by the detection signal and the feedback signal both meet the standard of the first interconnection mode, it is determined that the interconnection link has been successfully configured as the CPU and CPU interconnection mode; otherwise, it is determined that the link configuration fails, and the corresponding error handling mechanism is triggered.

[0059] Specifically, when the system needs to switch to the CPU and PCIe interconnection mode, the control module starts the signal output process again. This time, it outputs the second control signal to the first switch circuit and the second switch circuit, which has completely different coding format and electrical characteristics from the first control signal. The second control signal can drive the switch circuit to reconfigure the internal circuit, switch the communication path of the first CPU to the mode adapted to the PCIe bus. By changing the connection logic of the first switch circuit, the PCIe controller of the CPU can establish a communication link with the external PCIe device, and configure the corresponding clock signal, differential signal line, etc., to ensure that the working mode of the first CPU is switched to the CPU and PCIe interconnection mode. At the same time, the control module continues to output the detection signal to the first connector, which is optimized for PCIe link characteristics and contains a complete integrity detection sequence of high-speed differential signals, used to monitor the physical connection state of the PCIe link.

[0060] Specifically, after the second control signal is output and the detection signal is sent, the control module enters a new round of link state judgment process. It continuously collects the feedback signal fed back by the second connector, which contains the link width, negotiation rate, link training state and other key information of the PCIe link. Combined with the return data of the detection signal of the first connector, it judges whether the interconnection link is successfully configured as the second interconnection mode.

[0061] In an actual application scenario, the application scenario detection and configuration principle block diagram of the PCIe / CCIX multiplexing port of the CPU used as the CPU interconnection port is as follows Figure 4The detection A output signal of the CPLD (configurable programmable logic device) is connected to the A8 pin of the MCIO connector #1, the MCIO connector #1 is connected to the MCIO connector #2 through the MCIO cable, the B8 pin of the MCIO connector #2 is connected to the CPLD, and the signal name is detection B, the detection B signal is pulled up to the power supply VCC and serves as an input signal of the CPLD. The CPLD is connected to Q1 and Q2 through the PE_SEL1# signal and the PE_SEL2# signal, and is connected to the PE_SEL pin of the CPU1 and the CPU2 after being inverted through Q1 and Q2. The CPLD sends a series of signals to the detection A pin, and returns to the CPLD through the detection B signal. If the signals received by the detection B and the signals sent by the detection A are consistent, the CPLD determines that the PCIe / CCIX multiplex port of the current CPU is used as a CPU interconnection port function. At this time, the CPLD controls the PE_SEL1# and the PE_SEL2# to output high level, and the PE_SEL of the CPU1 and the CPU2 receives low level. The function of the PE_SEL is to control whether the PCIe / CCIX multiplex port of the CPU is used as PCIe or CCIX, and when the PE_SEL is low level, the PCIe / CCIX multiplex port of the CPU is used as CCIX function, and when the PE_SEL is high level, the PCIe / CCIX multiplex port of the CPU is used as PCIe function. Therefore, the PCIe / CCIX multiplex port of the CPU is automatically configured as CCIX function.

[0062] In an actual application scenario, the scheme block diagram of automatic detection and configuration when the PCIe / CCIX multiplex port of the CPU is connected to the PCIe device is as shown in Figure 6 . Figure 6 The detection A signal of the CPLD in the figure is connected to the MCIO connector #1, and Figure 4 The difference is that the B8 of the MCIO connector #2 is not connected to the detection B signal of the CPLD here. Since the detection B signal of the CPLD is pulled up to the power supply VCC through the resistance, the clock of the detection B signal received by the CPLD is high level. Therefore, the CPLD compares the received detection B signal with the sent detection A signal, and they are not the same. Therefore, the CPLD determines that the PCIe / CCIX multiplex port of the CPU is used as PCIe function. The CPLD controls the PE_SEL1# and the PE_SEL2# to output low level, and the PE_SEL of the CPU1 and the CPU2 receives high level. When the PE_SEL is high level, the PCIe / CCIX multiplex port of the CPU is used as PCIe function. Therefore, the PCIe / CCIX multiplex port of the CPU is automatically configured as PCIe function.

[0063] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A detection device for CPU interconnect links, characterized in that, The interconnection link comprises a first connector, a second connector, the first connector is connected with the second connector through a cable, a first input end of the first connector is connected with a first CPU, an input end of the second connector is connected with a second CPU or a PCIe device, and the detection device comprises a control module, a first switch circuit, a second switch circuit and a pull-up circuit. A first output end of the control module is connected with a control end of the first switch circuit, a second output end of the control module is connected with a control end of the second switch circuit, a third output end of the control module is connected with the first input end of the first connector, an input end of the control module is connected with an output end of the second connector, and the input end of the control module is also connected with a first end of the pull-up circuit. A first end of the first switch circuit is connected with a control end of the first CPU, and a second end of the first switch circuit is grounded. A first end of the second switch circuit is connected with a control end of the second CPU, and a second end of the second switch circuit is grounded. A second end of the pull-up circuit is connected with a power supply voltage.

2. The apparatus of claim 1, wherein: The control module comprises an editable logic device.

3. The apparatus of claim 1, wherein: The first switch circuit comprises a first triode and a first resistor. A first end of the first triode is connected with a control end of the first CPU, the first end of the first triode is also connected with a power supply voltage through the first resistor, a second end of the first triode is grounded, and a control end of the first triode is connected with the first output end of the control module.

4. The apparatus of claim 1, wherein: The second switch circuit comprises a second triode and a second resistor. A first end of the second triode is connected with a control end of the second CPU, the first end of the second triode is also connected with a power supply voltage through the second resistor, a second end of the second triode is grounded, and a control end of the second triode is connected with the second output end of the control module.

5. The apparatus of claim 1, wherein: The control module is connected with a baseboard management controller.

6. A CPU interconnect link, characterized by, The control module comprises an editable logic device. The first connector is connected with the second connector through a cable, a first input end of the first connector is connected with a first CPU, and an input end of the second connector is connected with a second CPU or a PCIe device. A first output end of the control module is connected with a control end of the first switch circuit, a second output end of the control module is connected with a control end of the second switch circuit, a third output end of the control module is connected with the first input end of the first connector, an input end of the control module is connected with an output end of the second connector, and the input end of the control module is also connected with a first end of the pull-up circuit. A first end of the first switch circuit is connected with a control end of the first CPU, and a second end of the first switch circuit is grounded. A first end of the second switch circuit is connected with a control end of the second CPU, and a second end of the second switch circuit is grounded. The first end of the second switch circuit is connected with the control end of the second CPU, and the second end of the second switch circuit is grounded. The second end of the pull-up circuit is connected with a power supply voltage.

7. A method for detecting and controlling a CPU interconnect link, the method comprising: The method is applied to the control module of the detection device of the CPU interconnection link according to any one of claims 1-5 or the control module of the CPU interconnection link according to claim 6, and the method comprises: outputting a detection signal to the first connector; judging whether the interconnection link is configured as a first interconnection mode or a second interconnection mode according to the feedback signal of the second connector and the detection signal, the first interconnection mode being a CPU-CPU interconnection mode, and the second interconnection mode being a CPU-PCIe interconnection mode; if the first interconnection mode is the CPU-CPU interconnection mode, outputting a first control signal to the first switch circuit and the second switch circuit, the first control signal being used for making the working mode of the first CPU and the second CPU be the CPU interconnection mode; if the first interconnection mode is the CPU-PCIe interconnection mode, outputting a second control signal to the first switch circuit and the second switch circuit, the second control signal being used for making the working mode of the first CPU and the second CPU be the CPU-PCIe interconnection mode.

8. The CPU interconnection link detection and control method according to claim 7, wherein the first control signal is used for controlling the first switch circuit and the second switch circuit to be turned on; the second control signal is used for controlling the first switch circuit and the second switch circuit to be turned off.

9. The CPU interlink detection and control method of claim 7, wherein, the process of judging whether the interconnection link is configured as the first interconnection mode comprises: if the feedback signal of the second connector is the same as the detection signal, the interconnection link is configured as the first interconnection mode.

10. The CPU interlink detection and control method of claim 7, wherein, the process of judging whether the interconnection link is configured as the second interconnection mode comprises: if the feedback signal of the second connector is different from the detection signal, the interconnection link is configured as the second interconnection mode.

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