Artificial intelligence-based memory testing method

Abstract

The application relates to an artificial intelligence-based memory test method, which comprises the following steps: according to the type, module, working environment information and historical fault information of a memory to be tested, a target algorithm primitive is selected from an algorithm primitive library through a preset artificial intelligence model, wherein the algorithm primitive library comprises a plurality of algorithm primitives, and the algorithm primitive is used for indicating the data mode, address sequence, timing parameter and verification mode of an algorithm used during testing; and the memory is tested according to the target algorithm primitive. The embodiments of the application can not only reduce redundant testing and testing time consumption, improve memory test efficiency, but also facilitate the discovery of new faults and improve memory test quality.

Description

Technical Field

[0001] This application relates to the field of memory testing technology, and in particular to a memory testing method based on artificial intelligence. Background Technology

[0002] Memory, also known as internal memory or main memory, is used to temporarily store data processed by the CPU, as well as data exchanged with external storage devices such as hard drives. As a core hardware component of a computer system, the stability of memory directly affects the reliability of system operation. Memory failure can lead to data loss, system crashes, or even hardware damage.

[0003] In related technologies, memory testing methods mainly rely on preset testing algorithms (such as walk tests, address line tests, etc.) to perform tests by traversing the memory address space. The testing algorithms used in this method are fixed, making it difficult to discover new faults. Moreover, it usually performs a large number of redundant tests, resulting in long memory testing times and low efficiency, especially in large-scale memory scenarios such as servers and data centers, where memory testing efficiency is even lower. Summary of the Invention

[0004] In view of this, an artificial intelligence-based memory testing method is proposed.

[0005] In a first aspect, embodiments of this application provide an artificial intelligence-based memory testing method, comprising:

[0006] Based on the type, module, operating environment information, and historical fault information of the memory to be tested, a target algorithm primitive is selected from the algorithm primitive library using a preset artificial intelligence model. The algorithm primitive library includes multiple algorithm primitives, which are used to indicate the data mode, address sequence, timing parameters, and verification method of the algorithm used during testing. The memory is then tested based on the target algorithm primitive.

[0007] In some possible implementations, the method further includes: for any algorithm primitive in the algorithm primitive library, determining the score of the algorithm primitive based on the computational complexity of the first test algorithm corresponding to the algorithm primitive and the number of fault types covered by the algorithm primitive.

[0008] In some possible implementations, testing the memory according to the target algorithm primitive includes: determining the execution order of the first test algorithm corresponding to the target algorithm primitive based on the score of the target algorithm primitive; and testing the memory using the first test algorithm corresponding to the target algorithm primitive according to the execution order.

[0009] In some possible implementations, the memory includes multiple memory regions; the step of selecting target algorithm primitives from the algorithm primitive library based on the type, module, working environment information, and historical fault information of the memory to be tested, through a preset artificial intelligence model, includes: for any memory region, selecting the target algorithm primitive corresponding to the memory region from the algorithm primitive library based on the type, module, historical fault information, and working environment information of the memory region, through a preset artificial intelligence model.

[0010] In some possible implementations, the method further includes: performing a pre-test on the memory using multiple second test algorithms, and recording test data during the execution of each second test algorithm, the test data including test parameters and test results; and establishing a fault database based on the test data from the multiple second test algorithms.

[0011] In some possible implementations, the method further includes: extracting algorithm primitives from the fault database to obtain multiple algorithm primitives; determining the fault type corresponding to each algorithm primitive based on the fault database; and storing each algorithm primitive and its corresponding fault type in an algorithm primitive library according to their function.

[0012] In some possible implementations, the method further includes: acquiring training data, the training data including at least one type of memory, module, working environment information, and historical fault information; determining label data of the training data according to the algorithm primitive library; adding the training data and its label data to the training set; and training the artificial intelligence model according to the training set.

[0013] In some possible implementations, the method further includes: during the testing of the memory, recording test data when executing the first test algorithm corresponding to each target algorithm primitive; if the first test algorithm corresponding to the target algorithm primitive detects a new fault, determining the fault information of the first test algorithm corresponding to the target algorithm primitive based on the test data of the first test algorithm corresponding to the target algorithm primitive, the fault information including fault type, fault severity, fault occurrence conditions, and the steps in the first test algorithm that trigger the fault; adding the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to the fault database to obtain an updated fault database.

[0014] In some possible implementations, the method further includes: when a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, extracting the algorithm primitive from the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to obtain the algorithm primitive to be added; determining the fault type of the algorithm primitive to be added; and adding the algorithm primitive to be added and its fault type to the algorithm primitive library after classifying them by function to obtain an updated algorithm primitive library.

[0015] In some possible implementations, the method further includes: updating the training set according to the updated algorithm primitive library; and training the artificial intelligence model according to the updated training set.

[0016] Secondly, embodiments of this application provide an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute any of the artificial intelligence-based memory testing methods described in the first aspect.

[0017] The AI-based memory testing method of this application can select target algorithm primitives suitable for the memory under test from the algorithm primitive library through an AI model, based on the type, module, working environment information and historical fault information of the memory under test. That is, the optimal combination of algorithm primitives suitable for the memory under test (which can also be regarded as a test scheme for the memory under test), and then test the memory according to the optimal combination of algorithm primitives.

[0018] The embodiments of this application can select different target algorithm primitives for different types of memory based on memory type, module, working environment information and historical fault information through artificial intelligence. Then, based on the target algorithm primitives, the memory can be tested in a targeted manner. This not only reduces redundant testing and testing time and improves memory testing efficiency, but also facilitates the discovery of new faults and improves memory testing quality. Attached Figure Description

[0019] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0020] Figure 1 This diagram illustrates an application scenario of an AI-based memory testing method according to an embodiment of this application.

[0021] Figure 2 A schematic diagram illustrating the process of establishing a fault database according to an embodiment of this application is shown.

[0022] Figure 3This diagram illustrates the process of establishing an algorithm primitive library according to an embodiment of the present application.

[0023] Figure 4 A flowchart illustrating an AI-based memory testing method according to an embodiment of this application is shown.

[0024] Figure 5 A schematic diagram of an AI-based memory testing method according to an embodiment of this application is shown. Detailed Implementation

[0025] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0026] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0027] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0028] Memory faults include bit flips, address line short circuits, refresh anomalies, faults caused by manufacturing defects, and faults caused by hardware aging. Among them, bit flips refer to the phenomenon that the binary bits (0 or 1) in a storage cell are unexpectedly changed (0 becomes 1 or 1 becomes 0) due to physical or environmental factors.

[0029] Traditional memory testing methods (such as MemTest86) primarily rely on pre-defined testing algorithms (such as walk-through tests and address line tests) to perform tests by traversing the memory address space. Walk-through tests are mainly used to detect continuity faults in memory address lines, such as short circuits, open circuits, or poor connections. Their core logic involves sequentially traversing the memory address space, writing fixed data and verifying it by reading it back to check the accuracy of each address access. Address line tests, by verifying the consistency of address signals, can accurately locate hardware problems such as short circuits and open circuits in address lines.

[0030] When using traditional memory testing methods, a large number of redundant tests are usually performed in order to improve coverage, resulting in long memory testing time and low efficiency. Moreover, the testing algorithms used in traditional memory testing methods are fixed, making it difficult to discover new faults.

[0031] To address the aforementioned technical problems, embodiments of this application provide an artificial intelligence-based memory testing method. The method includes: selecting a target algorithm primitive from an algorithm primitive library using a preset artificial intelligence model, based on the type, module, operating environment information, and historical fault information of the memory to be tested. The algorithm primitive library includes multiple algorithm primitives, which are used to indicate the data mode, address sequence, timing parameters, and verification method of the algorithm used during testing; and testing the memory based on the target algorithm primitive.

[0032] The AI-based memory testing method of this application can select target algorithm primitives suitable for the memory under test from the algorithm primitive library through an AI model, based on the type, module, working environment information and historical fault information of the memory under test. That is, the optimal combination of algorithm primitives suitable for the memory under test (which can also be regarded as a test scheme for the memory under test), and then test the memory according to the optimal combination of algorithm primitives.

[0033] The embodiments of this application can select different target algorithm primitives for different types of memory based on memory type, module, working environment information and historical fault information through artificial intelligence. Then, based on the target algorithm primitives, the memory can be tested in a targeted manner. This not only reduces redundant testing and testing time and improves memory testing efficiency, but also facilitates the discovery of new faults and improves memory testing quality.

[0034] The AI-based memory testing method described in this application can be applied to electronic devices such as personal computers, laptops, and servers. It can be used to test memory of various types (e.g., DDR4, DDR5, LPDDR, etc.), various modules (e.g., UDIMM, RDIMM, etc.), various platforms (e.g., servers, personal computers, embedded electronic devices, etc.), and various operating environments (e.g., different temperatures, voltage fluctuations, etc.). It should be noted that this application does not limit the specific application scenarios or the specific types of electronic devices for the AI-based memory testing method.

[0035] Figure 1 This diagram illustrates an application scenario of an artificial intelligence-based memory testing method according to an embodiment of this application. Figure 1 As shown, the AI-based memory testing method of this application embodiment can be applied to electronic device 110 to test the memory 120 connected to electronic device 110. Figure 1 In this embodiment, the memory 120 to be tested is located outside the electronic device 110. In some embodiments, the memory 120 to be tested may also be located inside the electronic device 110. This application does not limit this.

[0036] The electronic device 110 can be a personal computer, laptop, server, etc., or a test platform built according to the actual test environment; the type of memory 120 to be tested can be DDR4, DDR5, LPDDR, etc., and the module of the memory 120 to be tested can be UDIMM (Unbuffered Dual In-Line Memory Module), RDIMM (Registered DIMM), etc. This application does not limit the type of electronic device 110, the type of memory 120 to be tested, or the module.

[0037] During the testing process, in order to monitor the test environment, multiple sensors can be placed on the memory 120 under test to collect data such as temperature (accuracy ±0.5℃) and voltage (accuracy ±0.01V) in real time. It should be noted that the specific placement of each sensor can be set by those skilled in the art according to actual conditions, and this application does not impose any restrictions on this.

[0038] In some possible implementations, before testing the memory using the AI-based memory testing method of this application embodiment, it is also necessary to establish a fault database and an algorithm primitive library. Based on this, the AI-based memory testing method of this application embodiment further includes: performing a pre-test on the memory using multiple second testing algorithms, and recording test data during the pre-test process when executing each second testing algorithm, the test data including test parameters and test results; and establishing a fault database based on the test data from the multiple second testing algorithms.

[0039] The second testing algorithm is a traditional memory testing algorithm. Multiple second testing algorithms include those for basic function testing, address line testing, time-sensitive testing, and other parameter testing. Basic function testing includes verifying data consistency by writing / reading data in all-1, all-0, or checkerboard patterns (alternating 0xAA / 0x55). Address line testing includes detecting hardware faults such as short circuits / open circuits on address lines through skip-address access. Time-sensitive testing includes adjusting timing parameters such as tRCD (RAS to CAS Delay, where RAS is the Row Address Strobe and CAS is the Column Address Strobe) and tWR (Write Recovery Time or write latency) to verify the memory's tolerance to timing variations. Other parameter testing includes tests related to temperature and voltage, such as testing at 85°C and 1.05V.

[0040] The memory to be tested may be, for example, 128 DDR5-RDIMM-4800 memory modules manufactured in the same batch. The memory to be tested can be connected to a test platform. The test platform includes: a server motherboard supporting DDR5-RDIMM-4800 memory modules (e.g., the Super Fusion 2288H V7), test tools supporting in-depth DDR5 memory testing (including multiple secondary test algorithms), and sensors for monitoring information such as temperature and voltage. It should be noted that this is only an illustrative description of the test platform; in actual application scenarios, the test platform can be built by those skilled in the art according to the actual situation, and this application does not limit the specific construction method of the test platform.

[0041] After the memory module to be tested is connected to the test platform, it can be pre-tested using multiple secondary test algorithms. During the pre-testing process, for each memory module, the test data of each secondary test algorithm for that memory module can be recorded. Each piece of test data may include the test parameters of the secondary test algorithm (including test address range, timing configuration parameters, data mode, voltage, temperature, etc.) and the test results (whether a fault was triggered, the location of the fault, etc.). The recorded test data is structured data.

[0042] A fault database can then be established based on test data from multiple second-order test algorithms. Specifically, test data that detects faults can be labeled. The labeling includes the fault type (e.g., bit flip, address line short circuit), fault severity (e.g., single-bit error, multi-bit error, entire row / column failure), fault occurrence conditions (e.g., environmental information such as temperature, voltage, and runtime), the step in the test algorithm where the fault occurred, and the test duration. The labeled test data is then stored in the fault database.

[0043] Figure 2 A schematic diagram illustrating the process of establishing a fault database according to an embodiment of this application is shown. Figure 2 As shown, when establishing the fault database, multiple second test algorithms can be used to perform pre-tests on the memory. During the pre-test process, the test parameters and results of each second test algorithm are recorded to obtain test data. Then, the test data (including test parameters and test results) is labeled with faults, including the fault type, severity, conditions under which the fault occurred, the step in the test algorithm where the fault occurred, and the test time. Finally, the labeled test data is stored in the fault database.

[0044] In the embodiments of this application, before testing the memory, the memory can be pre-tested using multiple second testing algorithms. During the pre-testing process, test data (including test parameters and test results) is recorded when each second testing algorithm is executed. Then, a fault database is established based on the test data of multiple second testing algorithms, thereby providing data support for the establishment of the algorithm primitive library and the optimization of algorithm primitives.

[0045] In some possible implementations, the AI-based memory testing method of this application embodiment further includes: extracting algorithm primitives from the fault database to obtain multiple algorithm primitives; determining the fault type corresponding to each algorithm primitive based on the fault database; and storing each algorithm primitive and its corresponding fault type in an algorithm primitive library according to their function.

[0046] After establishing the fault database, algorithm primitives can be extracted from it to obtain multiple algorithm primitives. Algorithm primitives can be used to indicate the data pattern, address sequence, timing parameters, and verification method of the algorithm used during memory testing. Each algorithm primitive corresponds to a test algorithm. Algorithm primitives can be considered as the basic test unit (or the smallest test unit) for memory testing.

[0047] The data pattern (also known as the test data pattern) refers to the pattern used when writing test data. Data patterns can include all-1 pattern, all-0 pattern, checkerboard pattern, etc. The address sequence refers to the arrangement of memory addresses accessed when reading / writing test data. Address sequences can include continuous address sequences (addresses from low to high or high to low), skip address sequences, graph-like address sequences, etc. Timing parameters are indicators reflecting memory response speed. Timing parameters can include tRCD, tWR, CL (CAS latency, column address access latency), tRP (Row Precharge Time), etc. Verification methods refer to the methods used to verify the correctness of the test data written to memory. Verification methods include parity checking, encryption verification, ECC (Error Checking and Correcting) verification, etc.

[0048] Based on the above example, an algorithm primitive consists of four parts: data pattern, address sequence, timing parameters, and data verification method. For example, an algorithm primitive can be "all-1 pattern + skip address sequence + first specific timing + parity check", "chessboard pattern + continuous address scan + second specific timing + ECC check", etc.

[0049] It should be noted that the above descriptions of data modes, address sequences, timing parameters, and verification methods are merely illustrative. Those skilled in the art can set them according to actual circumstances, and this application does not impose any restrictions on them.

[0050] After obtaining multiple algorithm primitives, on the one hand, the fault type corresponding to each algorithm primitive can be determined based on the test data in the fault database; on the other hand, the multiple algorithm primitives can be classified according to their functions. These functions include address testing, data verification, timing optimization, and environmental adaptation. Then, each algorithm primitive and its corresponding fault type can be stored in the algorithm primitive library according to their function.

[0051] Figure 3 This diagram illustrates the process of establishing an algorithm primitive library according to an embodiment of this application. Figure 3 As shown, multiple algorithm primitives can be extracted from the fault database using feature extraction technology, and the fault type corresponding to each algorithm primitive can be determined. Then, the multiple algorithm primitives are classified according to their functions, and each algorithm primitive and its corresponding fault type are stored in the algorithm primitive library according to their functions.

[0052] In the embodiments of this application, multiple algorithm primitives are obtained by extracting algorithm primitives from the fault database. Based on the fault database, the fault type corresponding to each algorithm primitive is determined. Then, each algorithm primitive and its corresponding fault type are stored in the algorithm primitive library according to their functions. This enables the establishment of an algorithm primitive library based on the fault database, so as to provide algorithm primitive support for memory testing.

[0053] In some possible implementations, a pre-defined artificial intelligence model can be used to select appropriate algorithmic primitives from an algorithmic primitive library based on the memory type, module, operating environment information, and historical fault information, in order to test the memory. The pre-defined artificial intelligence model can be implemented based on decision trees, neural networks, reinforcement learning algorithms, etc. This application does not limit the specific implementation method of the artificial intelligence model.

[0054] In some possible implementations, the artificial intelligence model can be trained before use. The method further includes: acquiring training data, which includes at least one type of memory, module, operating environment information, and historical fault information; determining label data for the training data based on the algorithm primitive library; adding the training data and its label data to a training set; and training the artificial intelligence model based on the training set.

[0055] First, training data can be acquired. This training data includes at least one type of memory, module, operating environment information, and historical fault information. Multiple training data sets are available. After acquiring the training data, for any given training data set, an algorithm primitive applicable to the memory described in that training data can be selected from the algorithm primitive library, and the selected algorithm primitive is used as the label data for that training data. For example, the training data and its label data could be: test data for "memory under high temperature conditions," with the label data being "all-1 mode + skip address sequence + third specific timing (applicable to high temperature environments) + ECC check"; test data for "stable areas of memory," with the label data being "all-0 mode + continuous address sequence + fourth specific timing (applicable to normal temperature environments) + ECC check". Then, the above training data and its label data are added to the training set. High-temperature environments and normal temperature environments can be distinguished using a preset temperature threshold.

[0056] Then, based on the training set, the artificial intelligence model is trained iteratively multiple times. Training ends when the training termination condition is met, resulting in the trained artificial intelligence model. The training termination condition can be that the number of iterations reaches a preset threshold (e.g., 1000 times), the loss function converges within a preset interval, or the artificial model passes validation on a validation set. It should be noted that the training termination condition can be set by those skilled in the art according to actual circumstances, and this application does not impose any restrictions on it.

[0057] In some possible implementations, where the AI ​​model is based on a reinforcement learning algorithm (such as Proximal Policy Optimization, PPO), a reward function can be set during the AI ​​model training process. The reward function can be used to guide the AI ​​model to learn and make decisions towards a desired goal. Positive rewards can be set for detecting new faults or covering high-risk areas (e.g., high-temperature areas). Negative rewards can be set for redundant testing (e.g., repeatedly scanning stable address regions) or execution time exceeding a threshold. By setting a reward function, the training efficiency of the AI ​​model can be improved.

[0058] Figure 4 A flowchart illustrating an artificial intelligence-based memory testing method according to an embodiment of this application is shown. Figure 4 As shown, the method includes:

[0059] Step S410: Based on the type, module, working environment information and historical fault information of the memory to be tested, select the target algorithm primitive from the algorithm primitive library through the preset artificial intelligence model.

[0060] The term "memory type" refers to memory based on different technical standards. The main differences between different memory types lie in data transfer rates, power consumption, and compatibility. Memory types can include DDR3, DDR4, DDR5, etc. "Memory module" refers to the number of standard memory slots supported by the chipset. Its configuration is determined by the chipset's support for the data depth and width of the memory banks, directly affecting the maximum memory capacity. Memory modules can include UDIMM, RDIMM, etc. "Memory operating environment information" includes environmentally relevant information such as temperature and voltage during memory operation. "Memory historical fault information" refers to information such as the fault type, severity, and conditions under which historical faults occurred within a predetermined time period (e.g., one month, six months, etc.) prior to the current moment.

[0061] When testing memory, the type, module, operating environment information, and historical fault information of the memory to be tested can be input into a trained artificial intelligence model. The artificial intelligence model processes the input information and selects target algorithm primitives that match the memory from the algorithm primitive library.

[0062] Step S420: Test the memory according to the target algorithm primitive.

[0063] After obtaining the target algorithm primitive, the first test algorithm corresponding to the target algorithm primitive can be determined based on the data mode, address sequence, timing parameters, and verification method of the algorithm used in memory testing as indicated by the target algorithm primitive. Then, the memory is tested by executing the first test algorithm corresponding to the target algorithm primitive.

[0064] The AI-based memory testing method of this application can select target algorithm primitives suitable for the memory under test from the algorithm primitive library through an AI model, based on the type, module, working environment information and historical fault information of the memory under test. That is, the optimal combination of algorithm primitives suitable for the memory under test (which can also be regarded as a test scheme for the memory under test), and then test the memory according to the optimal combination of algorithm primitives.

[0065] The embodiments of this application can select different target algorithm primitives for different types of memory based on memory type, module, working environment information and historical fault information through artificial intelligence. Then, based on the target algorithm primitives, the memory can be tested in a targeted manner. This not only reduces redundant testing and testing time and improves memory testing efficiency, but also facilitates the discovery of new faults and improves memory testing quality.

[0066] In some possible implementations, the memory to be tested can be divided into multiple memory regions based on different operating environment information (temperature, voltage, etc.). Based on this, step S410 may include: for any memory region, based on the memory type, module, historical fault information, and operating environment information of the memory region, selecting a target algorithm primitive corresponding to the memory region from an algorithm primitive library using a preset artificial intelligence model.

[0067] After dividing the memory to be tested into multiple memory regions, each region has different operating environment information. For any given memory region, based on the type, module, historical fault information, and operating environment information of the memory under test, a trained artificial intelligence model can select the target algorithm primitive corresponding to that memory region from the algorithm primitive library. This allows for the testing of that memory region using the target algorithm primitive. This method enables targeted testing of different regions of the memory under test, thereby reducing testing time and improving testing efficiency.

[0068] In some possible implementations, the method further includes: for any algorithm primitive in the algorithm primitive library, determining the score of the algorithm primitive based on the computational complexity of the first test algorithm corresponding to the algorithm primitive and the number of fault types covered by the algorithm primitive.

[0069] For any algorithmic primitive in the primitive library, its score can be determined. This score indicates the primitive's cost or benefit. A lower score indicates a higher cost and lower benefit, while a higher score indicates a lower cost and higher benefit.

[0070] When determining the score of an algorithm primitive, first determine the computational complexity of the first test algorithm corresponding to that primitive. Computational complexity can be determined based on the execution time, memory access volume, etc., of the first test algorithm. Then, determine the number of fault types covered by the primitive. Finally, determine the primitive's score based on both the computational complexity and the number of fault types covered. Lower computational complexity results in a higher score. A higher number of fault types covered results in a higher score.

[0071] In one example, computational complexity can be quantified to determine the score corresponding to each computational complexity. Then, the score of the complexity of the first test algorithm corresponding to the algorithm primitive is the sum of the number of fault types covered by the algorithm primitive, which is determined as the score of the algorithm primitive.

[0072] In the embodiments of this application, the score of the algorithm primitive can be determined based on the computational complexity of the first test algorithm corresponding to the algorithm primitive and the number of fault types covered by the algorithm primitive. This is simple, fast, and can improve processing efficiency.

[0073] In some possible implementations, the fault detection rate of an algorithm primitive can be considered when determining its score. A higher fault detection rate results in a higher score. For example, the fault detection rate can be calculated separately for each data mode, address sequence, timing parameter, and verification method. For any given algorithm primitive, its fault detection rate is determined based on the fault detection rates of its data mode, address sequence, timing parameter, and verification method (e.g., the fault detection rate of the algorithm primitive is the sum of the fault detection rates of the data mode, address sequence, timing parameter, and verification method), thus determining its fault detection score. Then, the sum of the complexity score of the first test algorithm corresponding to the algorithm primitive, the number of fault types covered by the algorithm primitive, and the fault detection score of the algorithm primitive is used to determine its score. This method combines the algorithm primitive's score with its fault detection rate, making the score more accurate and thus improving the efficiency of fault detection during memory testing.

[0074] In some possible implementations, step S420 may include: determining the execution order of the first test algorithm corresponding to the target algorithm primitive based on the score of the target algorithm primitive; and testing the memory using the first test algorithm corresponding to the target algorithm primitive according to the execution order.

[0075] The target algorithm primitives can be sorted from highest to lowest score to obtain the first order of the target algorithm primitives. Then, based on the first order, the corresponding first test algorithms can be sorted to obtain the execution order of the first test algorithms. Afterwards, the first test algorithms corresponding to the target algorithm primitives can be executed sequentially according to this execution order to test memory usage.

[0076] In this way, when testing memory, the first test algorithm corresponding to the target algorithm primitive with the highest score is executed first. This allows the first test algorithm, which has low cost and high benefit (i.e., high score), to be executed first during testing, thereby improving testing efficiency.

[0077] In some possible implementations, the method further includes: during the testing of the memory, recording test data when executing the first test algorithm corresponding to each target algorithm primitive, the test data including test parameters and test results; if the first test algorithm corresponding to the target algorithm primitive detects a new fault, determining the fault information of the first test algorithm corresponding to the target algorithm primitive based on the test data of the first test algorithm corresponding to the target algorithm primitive, the fault information including fault type, fault severity, fault occurrence conditions, and the steps in the first test algorithm that trigger the fault; adding the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to the fault database to obtain an updated fault database.

[0078] During memory testing, test data (including test parameters and test results) of the first test algorithm corresponding to each target algorithm primitive can be recorded. Based on the test results, it can be determined whether the first test algorithm corresponding to each target algorithm primitive has detected any new faults.

[0079] If a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, the fault information of the first test algorithm corresponding to the target algorithm primitive is determined based on the test data. This fault information includes the fault type, fault severity, fault occurrence conditions, and the steps in the first test algorithm that triggered the fault. The test data and fault information of the first test algorithm corresponding to the target algorithm primitive are then added to the fault database to obtain an updated fault database.

[0080] In this way, fault data from memory testing can be continuously accumulated, enabling dynamic updates to the fault database.

[0081] In some possible implementations, the method further includes: when a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, extracting the algorithm primitive from the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to obtain the algorithm primitive to be added; determining the fault type of the algorithm primitive to be added; and adding the algorithm primitive to be added and its fault type to the algorithm primitive library after classifying them by function to obtain an updated algorithm primitive library.

[0082] When a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, the algorithm primitive can be extracted from the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to obtain the algorithm primitive to be added. The algorithm primitive to be added here can be considered as an algorithm primitive specifically designed for the new fault. Then, the fault type of the algorithm primitive to be added is determined (it can be a new fault type or an existing fault type), and the algorithm primitive to be added and its fault type are categorized by function and added to the algorithm primitive library to obtain the updated algorithm primitive library.

[0083] In this way, corresponding algorithm primitives can be added for newly detected faults, enabling the algorithm primitive library to be continuously updated.

[0084] In some possible implementations, the method further includes: updating the training set according to the updated algorithm primitive library; and training the artificial intelligence model according to the updated training set.

[0085] After obtaining the updated algorithm primitive library, the label data of the training data in the training set can be updated based on this library, thus obtaining an updated training set. The artificial intelligence model can then be trained using the updated training set to obtain an iterative (or optimized) artificial intelligence model.

[0086] For example, assuming the algorithm primitive library is not updated, the rules for the AI ​​model to select target algorithm primitives are as follows:

[0087] "IF memory temperature > 80℃ OR voltage < 1.1V THEN"

[0088] Prioritize the combination of [environmental adaptation + time series optimization];

[0089] ELSE IF Recent Class A failure rate > 20% THEN

[0090] Select the "Address Test (Jump Address + Checkerboard Pattern)" combination;

[0091] ELSE Select the combination of "Data Validation + Time Series Optimization".

[0092] The DDR5-RDIMM-4800 memory module was tested using the AI-based memory testing method described in this application. After a second preset time period (e.g., 1 month), test data from 80 new DDR5-RDIMM-4800 memory modules were collected. Among these, 15 test data entries detected a new type of fault: intermittent multi-bit errors, classified as Class E faults.

[0093] Feature extraction was performed on the 15 test data that detected Class E faults. It was found that they all occurred in high temperature (>85℃) and continuous address scanning scenarios. The corresponding algorithm primitive "all-1 mode + high temperature zone continuous address scanning + third specific timing + enhanced parity check" was obtained. This algorithm primitive was selected as the algorithm primitive to be added. Then, the algorithm primitives to be added and their corresponding fault types (Class E faults) were classified by function and added to the algorithm primitive library to obtain the updated algorithm primitive library.

[0094] The training set can be updated based on the updated algorithm primitive library, and the AI ​​model can be trained using the updated training set to obtain an optimized AI model. The rules for selecting target algorithm primitives for the iterative AI model can be exemplified as follows:

[0095] "IF memory temperature > 85℃ AND test scenario is continuous address scan THEN"

[0096] Force the use of the combination of [continuous address scanning in high-temperature areas + enhanced parity check];

[0097] ELSE IF Class E faults: More than 5 new cases in the last 7 days. THEN

[0098] Increase the execution priority of the "Address Test Class (Jump Address + Checkerboard Pattern)".

[0099] In this way, the artificial intelligence model can iterate continuously as the algorithm primitive library is updated, thereby enabling the target algorithm primitives selected by the artificial intelligence model to be continuously updated, and thus discovering more new and complex faults after the memory testing process.

[0100] Figure 5 A schematic diagram of an artificial intelligence-based memory testing method according to an embodiment of this application is shown. Figure 5 As shown, the AI-based memory testing method includes:

[0101] Step S510: Based on the type, module, working environment information, and historical fault information of the memory to be tested, select the target algorithm primitive from the algorithm primitive library through a preset artificial intelligence model;

[0102] Step S520: Test the memory according to the target algorithm primitive;

[0103] Step S530: During the memory test, record the test data when executing the first test algorithm corresponding to each target algorithm primitive;

[0104] Step S540: Determine whether the first test algorithm corresponding to the target algorithm primitive has detected a new fault;

[0105] If the first test algorithm corresponding to the target algorithm primitive detects a new fault, perform the following steps:

[0106] Step S550: Based on the test data of the first test algorithm corresponding to the target algorithm primitive, determine the fault information of the first test algorithm corresponding to the target algorithm primitive; add the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to the fault database to obtain the updated fault database.

[0107] Step S560: Extract the algorithm primitive from the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to obtain the algorithm primitive to be added; determine the fault type of the algorithm primitive to be added;

[0108] Step S570: The algorithm primitives to be added and their fault types are classified by function and added to the algorithm primitive library to obtain the updated algorithm primitive library;

[0109] Step S580: Update the training set according to the updated algorithm primitive library;

[0110] Step S590: Train the artificial intelligence model using the updated training set to obtain the iterative artificial intelligence model. During subsequent memory testing, the iterative artificial intelligence model is used to execute step S510.

[0111] Compared with related technologies, the AI-based memory testing method of this application has achieved significant improvements in testing accuracy (e.g., covering E-type intermittent multi-bit errors that are difficult to detect by traditional methods, with a false negative rate of <3%), detection efficiency (e.g., the average detection time is reduced by 29% (from 12 hours / module to 8.5 hours / module)), and adaptability (e.g., by expanding the algorithm primitive library and iterating the AI ​​model, it successfully adapts to high temperatures, new types of faults, and other scenarios of DDR5 memory).

[0112] Furthermore, the AI-based memory testing method of this application has wide applicability. For example, it can be used to test memory with different speeds such as DDR5-RDIMM-4800 / 5600 / 6400, and its application scenarios can also be extended to multiple platforms such as PCs and workstations.

[0113] Embodiments of this application also provide an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute any of the artificial intelligence-based memory testing methods described in the first aspect.

[0114] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0115] It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented using hardware (such as circuits or ASICs (Application Specific Integrated Circuits)) that performs the corresponding function or action, or using a combination of hardware and software, such as firmware.

[0116] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0117] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory testing method based on artificial intelligence, characterized in that, include: Based on the type, module, working environment information, and historical fault information of the memory to be tested, a target algorithm primitive is selected from the algorithm primitive library through a preset artificial intelligence model. The algorithm primitive library includes multiple algorithm primitives, which are used to indicate the data mode, address sequence, timing parameters, and verification method of the algorithm used during testing. The memory is tested according to the target algorithm primitives; The method further includes: The memory is pre-tested using multiple second test algorithms, and test data is recorded during the pre-testing process for each second test algorithm. The test data includes test parameters and test results. A fault database is established based on the test data from the multiple second test algorithms; Algorithm primitives were extracted from the fault database to obtain multiple algorithm primitives; Based on the fault database, determine the fault type corresponding to each algorithm primitive; Each algorithm primitive and its corresponding fault type are stored in the algorithm primitive library according to their function.

2. The method according to claim 1, characterized in that, The method further includes: For any algorithm primitive in the algorithm primitive library, the score of the algorithm primitive is determined based on the computational complexity of the first test algorithm corresponding to the algorithm primitive and the number of fault types covered by the algorithm primitive.

3. The method according to claim 2, characterized in that, The step of testing the memory according to the target algorithm primitive includes: Based on the scores of the target algorithm primitives, the execution order of the first test algorithm corresponding to the target algorithm primitives is determined; According to the execution order, the memory is tested using the first test algorithm corresponding to the target algorithm primitive.

4. The method according to claim 1, characterized in that, The memory includes multiple memory regions; Based on the type, module, operating environment information, and historical fault information of the memory to be tested, the method selects target algorithm primitives from the algorithm primitive library using a preset artificial intelligence model, including: For any memory region, based on the memory type, module, historical fault information, and working environment information of the memory region, a target algorithm primitive corresponding to the memory region is selected from the algorithm primitive library through a preset artificial intelligence model.

5. The method according to claim 1, characterized in that, The method further includes: Acquire training data, which includes at least one type of memory, module, working environment information, and historical fault information; The label data of the training data is determined based on the algorithm primitive library; Add the training data and its label data to the training set; The artificial intelligence model is trained based on the training set.

6. The method according to claim 1, characterized in that, The method further includes: During the testing of the memory, test data is recorded when the first test algorithm corresponding to each target algorithm primitive is executed; If a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, the fault information of the first test algorithm corresponding to the target algorithm primitive is determined based on the test data of the first test algorithm corresponding to the target algorithm primitive. The fault information includes the fault type, fault severity, fault occurrence conditions, and the steps in the first test algorithm that trigger the fault. The test data and fault information of the first test algorithm corresponding to the target algorithm primitive are added to the fault database to obtain the updated fault database.

7. The method according to claim 6, characterized in that, The method further includes: If a new fault is detected by the first test algorithm corresponding to the target algorithm primitive, the algorithm primitive is extracted from the test data and fault information of the first test algorithm corresponding to the target algorithm primitive to obtain the algorithm primitive to be added. Determine the fault type of the algorithm primitive to be added; The algorithm primitives to be added and their fault types are categorized by function and then added to the algorithm primitive library to obtain the updated algorithm primitive library.

8. The method according to claim 7, characterized in that, The method further includes: Update the training set based on the updated algorithm primitives library; The artificial intelligence model is trained based on the updated training set.

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