Memory margin testing method, system, equipment and medium

Abstract

The memory margin test method, system and device and the medium provided by the embodiment of the invention comprise the steps that a main control module generates a test script in response to a received memory time sequence parameter set by a target object and a selected test option; in response to the received test request sent by the system-level test equipment, the main control module sends a test script to the system-level test equipment; the system-level test equipment receives the test script sent by the main control module and executes the test script so as to test a target memory bank set by the system-level test equipment through the test script; and the main control module captures the Bios log in the process of testing the target memory bank by the system-level test equipment, and determines a memory margin test result of the target memory bank set by the system-level test equipment according to the Bios log. Full-process automation of RMT testing is achieved, manual intervention is reduced, and the testing efficiency and the accuracy of memory stability evaluation are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory bar and related technical field, in particular, to a memory margin test method, system, device and medium. BACKGROUND

[0002] In modern computer systems, memory is a key component for data storage and processing, and its performance and stability directly affect the running efficiency and reliability of the entire system. Memory margin test (RMT) is an important means to evaluate memory performance, which can effectively find potential faults of memory by detecting the margin of memory design part, and ensure the stable and reliable operation of memory.

[0003] The traditional RMT test needs to be run independently of the SLT (System Level Test, system level test) device, and needs to manually configure parameters and restart the device multiple times, which is low in efficiency. When testing RMT, the Bios log is collected by manual grabbing, which cannot realize automatic collection and automatic extraction of RMT test results. Due to the large amount of data extracted, human error is difficult to avoid in the process of manual comparison, and the existing SLT test only verifies the memory function and does not quantify the timing margin, which is difficult to find potential stability problems. SUMMARY

[0004] The embodiments described herein provide a memory margin test method, system, device and medium to solve the problems existing in the prior art.

[0005] In a first aspect, according to the content of the present disclosure, a memory margin test method is provided, applied to a memory margin test system, the memory margin test system comprising a master module, a system level test device and a serial port server in communication connection with the system level test device, the system level test device being in communication connection with the master module through a network port, and the system level test device being in communication connection with the serial port server through a configuration interface, and the serial port server being in communication connection with the master module, comprising: The master module generates a test script in response to receiving memory timing parameters set by a target object and selected test options; In response to receiving a test request sent by the system level test device, the master module sends the test script to the system level test device; The system level test device receives the test script sent by the master module, and executes the test script to test the target memory bar set by the system level test device through the test script; The main control module captures BIOS logs during the testing of the target memory module by the system-level test equipment, and determines the memory margin test results of the target memory module set by the system-level test equipment based on the BIOS logs.

[0006] In some embodiments of this disclosure, the system-level testing device receives a test script sent by the main control module and executes the test script to test the target memory module set by the system-level testing device, including: The system-level test equipment receives the test script sent by the main control module, and enables the RMT test function through BIOS commands when executing the test script; The system-level test equipment continues to execute the test script and restarts the system-level test equipment via a restart command. After restarting, the system-level test device executes the RMT test function to test the target memory module set on the system-level test device.

[0007] In some embodiments of this disclosure, determining the memory slack test result of the target memory module set by the system-level test device based on the BIOS log includes: Extract the numerical information of the target field based on the BIOS log; Based on the numerical information of the target field and the preset numerical information, the memory margin test result of the target memory module set by the system-level test equipment is determined.

[0008] In some embodiments of this disclosure, determining the memory margin test result of the target memory module set by the system-level testing device based on the numerical information of the target field and preset numerical information includes: Based on the relationship between the numerical information of the target field and the preset numerical information, the range of the preset numerical information in which the numerical information of the target field is located is determined. Based on the range of preset numerical information where the numerical information of the target field is located, the sub-memory margin test result of the target memory module set by the system-level test equipment is determined. Based on the test results of each sub-memory margin of the target memory module set by the system-level test equipment, the memory margin test results of the target memory module set by the system-level test equipment are determined.

[0009] In some embodiments of this disclosure, before determining the memory margin test result of the target memory module set by the system-level test device based on the BIOS log, the method further includes: Obtain the type information of the target memory module set in the system-level test equipment; The step of determining the memory margin test results of the target memory module set by the system-level test device based on the BIOS log includes: Based on the BIOS logs and the type information of the target memory module set by the system-level test device, determine the memory margin test results of the target memory module set by the system-level test device.

[0010] In some embodiments of this disclosure, the memory margin testing system includes multiple system-level testing devices and multiple serial port servers that are communicatively connected to the system-level testing devices, and each of the serial port servers is communicatively connected to the main control module. The main control module, in response to receiving the memory timing parameters set by the target object and the selected test options, generates a test script, including: The main control module generates a test script in response to receiving the memory timing parameters set by the target object, the selected test options, and the selected target system-level test device identification information. In response to receiving a test request from a system-level test device, the main control module sends the test script to the system-level test device, including: In response to receiving test requests from various system-level test devices, the main control module determines the target system-level test device based on the target system-level test device identification information included in the test script; The main control module sends the test script to the target system-level test device.

[0011] In some embodiments of this disclosure, the method further includes: The main control module compares the previously captured BIOS logs with the subsequently captured BIOS logs. If the subsequently captured BIOS logs are the same as the previously captured BIOS logs, the main control module generates an early warning message.

[0012] Secondly, according to the present disclosure, a memory adequacy testing system is provided. The memory adequacy testing system includes a main control module, a system-level testing device, and a serial port server communicatively connected to the system-level testing device. The system-level testing device is communicatively connected to the main control module via a network port. The system-level testing device is also communicatively connected to the serial port server via a configuration interface. The serial port server is communicatively connected to the main control module, including: The main control module is configured to generate a test script in response to receiving the memory timing parameters set by the target object and the selected test options, and to send the test script to the system-level test device in response to receiving a test request from the system-level test device. The system-level testing device is configured to receive test scripts sent by the main control module and execute the test scripts to test the target memory module set by the system-level testing device through the test scripts. The main control module is also configured to capture BIOS logs during the testing of the target memory module by the system-level test device, and determine the memory margin test result of the target memory module set by the system-level test device based on the BIOS logs.

[0013] Thirdly, according to the present disclosure, a computer device is provided, comprising: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any of the first aspects.

[0014] Fourthly, according to the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in any of the first aspects.

[0015] The memory leeway testing method, system, device, and medium provided in this disclosure firstly involve a main control module generating a test script upon receiving memory timing parameters and selected test options set by the target object. Then, in response to a test request from a system-level testing device, the main control module sends the test script to the system-level testing device. The system-level testing device receives the test script from the main control module and executes it to test the target memory module set by the system-level testing device. Finally, during the testing process of the target memory module by the system-level testing device, the main control module captures BIOS logs and determines the memory leeway test results of the target memory module set by the system-level testing device based on the BIOS logs. Firstly, RMT testing is integrated into the system-level testing device. Through script generation, BIOS interface calls, automatic log capture, and intelligent log analysis, the entire RMT testing process is automated, reducing manual intervention and improving testing efficiency and the accuracy of memory stability assessment.

[0016] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a flowchart illustrating a memory margin testing method provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a memory margin testing system provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure.

[0018] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0021] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] Furthermore, in all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0024] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0026] To address the problems existing in the prior art, this disclosure provides a memory adequacy testing method. This method is applied to a memory adequacy testing system, which includes a main control module, a system-level testing device, and a serial port server communicatively connected to the system-level testing device. The system-level testing device communicates with the main control module via a network port and also communicates with the serial port server via a configuration interface. The serial port server communicates with the main control module. Figure 1 This is a flowchart illustrating a memory margin testing method provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of the structure of a memory margin testing system provided in an embodiment of this disclosure, combined with... Figure 1 and Figure 2 The specific process of the memory margin test method includes: S110: The main control module generates a test script in response to receiving the memory timing parameters set by the target object and the selected test options.

[0027] RMT (Rank Margin Test) is a testing technique used to evaluate the signal integrity and stability of the memory subsystem. Its core objective is to quantify the critical fault tolerance capability of memory timing. Its core principle is to dynamically adjust memory timing parameters (such as tCL, tRCD, etc.) to simulate signal degradation scenarios, find the maximum timing offset (i.e., "margin") that allows the system to operate stably, and thus discover potential memory faults, ensuring stable and reliable memory operation.

[0028] In the existing technology, the memory margin test of memory modules is a traditional test method, which requires manual capture and comparison of test data, and there is a certain degree of error.

[0029] To address the problems existing in the prior art, this disclosure provides a memory leeway testing method. This method is applied to a memory leeway testing system, which uses system-level testing equipment to test the memory leeway of memory modules. The main control module analyzes the memory leeway test results from the system-level testing equipment, thereby automating the entire memory leeway testing process, reducing manual intervention, and improving testing efficiency and the accuracy of memory stability assessment.

[0030] In the specific implementation process, firstly combine Figure 2 The memory leeway testing system includes a main control module, a system-level testing device, and a serial port server that communicates with the system-level testing device. The system-level testing device communicates with the main control module via a network port and also communicates with the serial port server via a configuration interface. The serial port server communicates with the main control module. One system-level testing device can perform memory leeway testing on one type of memory module. During the memory leeway testing process, the system-level testing device obtains the test script generated by the main control module via the network port. The main control module retrieves the BIOS logs generated during the memory module testing process from the system-level testing device via the configuration interface and the serial port server.

[0031] Specifically, the target object can configure memory timing parameters in the main control module. Memory timing parameters include tRCD, tRAS, ..., tCL, etc. After configuring the memory timing parameters, the target object selects "Yes" in the test options (such as whether to enable RMT). At this time, the main control module responds to the target object's selection operation and generates a test script.

[0032] As a specific implementation method, when there is only one system-level test device communicating with the main control module, the target object does not need to select the target system-level test device identification information. When there are multiple system-level test devices communicating with the main control module, if the generated test script is sent to all system-level test devices, the target object does not need to select the target system-level test device identification information in the main control module. When there are multiple system-level test devices communicating with the main control module, if only one of the system-level test devices is sent to the generated test script, the target object needs to select the target system-level test device identification information in the main control module.

[0033] S120. In response to receiving a test request from the system-level test device, the main control module sends a test script to the system-level test device.

[0034] The system-level test equipment continuously sends test requests to the main control module. After the main control module generates the test script, it sends the test script to the system-level test equipment when it receives the test request.

[0035] It should be noted that when the system-level test equipment connected to the main control module consists of only one system-level test equipment, the main control module will send the generated test script to that system-level test equipment after receiving the test request. When there are multiple system-level test equipment connected to the main control module, the specific process of the main control module sending the test script to the system-level test equipment is as follows.

[0036] Specifically, the memory margin testing system includes multiple system-level testing devices and multiple serial port servers that communicate with the system-level testing devices. Each serial port server communicates with the main control module.

[0037] In response to receiving the memory timing parameters set by the target object, the selected test options, and the identification information of the selected target system-level test device, the main control module generates a test script; in response to receiving test requests sent by each system-level test device, the main control module determines the target system-level test device based on the target system-level test device identification information included in the test script; the main control module sends the test script to the target system-level test device.

[0038] In other words, after the main control module generates the test script, in response to the test requests sent by each system-level test device, the main control module sends the generated test script to the target system-level test device corresponding to the target system-level test device identification information selected by the target object.

[0039] In this implementation, it should be noted that if the target system-level test device does not send a test request, even if other system-level test devices send test requests, the main control module will not send the generated test script to other system-level test devices until the target system-level test device sends a test request. Only then will the main control module send the generated test script to the target system-level test device.

[0040] As another implementation, the main control module generates a test script in response to receiving the memory timing parameters set by the target object and the selected test options; in response to receiving test requests from each system-level test device, the main control module sends the test script to each system-level test device.

[0041] In other words, in this implementation, if the memory margin test system includes multiple system-level test devices, and the target object does not select the target system-level test device identifier information in the main control module, the main control module will send the generated test script to all system-level test devices after receiving the test requests sent by each system-level test device.

[0042] S130: The system-level test device receives the test script sent by the main control module and executes the test script to test the target memory module set by the system-level test device.

[0043] In the specific implementation, the system-level test device receives and executes the test script sent by the main control module to test the target memory module set by the system-level test device. This includes: the system-level test device receiving the test script sent by the main control module and enabling the RMT test function via BIOS commands during the execution of the test script; the system-level test device continuing to execute the test script and restarting the system-level test device via a restart command; and the system-level test device executing the RMT test function after restarting to test the target memory module set by the system-level test device.

[0044] It should be noted that the test script includes the interface command to enable the RMT test function through the BIOS interface, as well as the restart command after enabling the RMT test.

[0045] Specifically, firstly, after receiving the test script sent by the main control module, the system-level test device executes the test script. During the execution of the test script, it calls BIOS commands (such as RMT_Enable, mrvmt -fuc 22 -par_rmt 1) through the UEFI Shell script to dynamically enable the RMT test function of the system-level test device. After the RMT test function of the system-level test device is enabled, the system-level test device continues to execute the test script and restarts the system-level test device according to the restart command in the test script. Then, after restarting, the system-level test device executes the RMT test function to test the target memory module set by the system-level test device.

[0046] S140. During the testing of the target memory module by the system-level test equipment, the main control module captures the BIOS log and determines the memory margin test result of the target memory module set by the system-level test equipment based on the BIOS log.

[0047] During the testing of the target memory module by the system-level test equipment, the main control module captures BIOS logs from the system-level test equipment through a serial port server and configuration interface.

[0048] After capturing the BIOS logs, the main control module analyzes the BIOS logs to obtain the memory margin test results of the target memory module.

[0049] In the specific implementation, the memory margin test result of the target memory module set by the system-level test device is determined according to the BIOS log, including: extracting the numerical information of the target field according to the BIOS log; and determining the memory margin test result of the target memory module set by the system-level test device according to the numerical information of the target field and the numerical information of the preset target field.

[0050] Specifically, determining the memory margin test result of the target memory module set by the system-level test equipment based on the numerical information of the target field and the numerical information of the preset target field includes: determining the range of the preset numerical information in which the numerical information of the target field is located based on the relationship between the numerical information of the target field and the numerical information of the preset target field; determining the sub-memory margin test result of the target memory module set by the system-level test equipment based on the range of the preset numerical information in which the numerical information of the target field is located; and determining the memory margin test result of the target memory module set by the system-level test equipment based on the sub-memory margin test results of the target memory module set by the system-level test equipment.

[0051] That is, the first step is to extract the numerical information of the target field from the BIOS log, and then compare the extracted numerical information of the target field with the preset numerical information to determine the memory margin test result of the memory module.

[0052] In the specific implementation, the preset numerical information corresponding to different target fields are different. By comparing the numerical information of different target fields with the preset numerical information corresponding to the target field, the range of the numerical information of different target fields in the preset numerical information corresponding to the target field is determined. Then, based on the range of the numerical information of different target fields in the preset numerical information corresponding to the target field, the test results of multiple sub-memory margins of the target memory module are determined. Finally, the test results of multiple sub-memory margins are averaged to obtain the memory margin test results of the target memory module set by the system-level test equipment.

[0053] As a preferred implementation method, before determining the memory margin test results of the target memory module set on the system-level test device based on the BIOS logs, the following steps are also included: Obtain the type information of the target memory module set in the system-level test equipment.

[0054] At this point, based on the BIOS log, the memory margin test results of the target memory module set by the system-level test device are determined, including: based on the BIOS log and the type information of the target memory module set by the system-level test device, the memory margin test results of the target memory module set by the system-level test device are determined.

[0055] Since different types of memory modules correspond to different preset value information, in this embodiment of the disclosure, before determining the memory margin test results of the target memory modules set by each system-level test device, the main control module first obtains the type information of the target memory modules set by each system-level test device. Then, based on the type information of the target memory modules set by each system-level test device, it filters out the preset value information corresponding to the target fields that are different from the type information of the target memory modules set by each system-level test device. Then, based on the value information of the target fields of each system-level test device and the preset value information, it determines the memory margin test results of the target memory modules set by each system-level test device, ensuring the accuracy of the determined memory margin test results of the target memory modules set by each system-level test device.

[0056] The memory leeway testing method provided in this disclosure first involves the main control module generating a test script upon receiving the memory timing parameters and selected test options set by the target object. Then, in response to a test request from a system-level testing device, the main control module sends the test script to the system-level testing device. The system-level testing device receives the test script from the main control module and executes it to test the target memory module set by the system-level testing device. Finally, during the testing process of the target memory module by the system-level testing device, the main control module captures BIOS logs and determines the memory leeway test result of the target memory module set by the system-level testing device based on the BIOS logs. Firstly, RMT testing is integrated into the system-level testing device. Through script generation, BIOS interface calls, automatic log capture, and intelligent log analysis, the entire RMT testing process is automated, reducing manual intervention and improving testing efficiency and the accuracy of memory stability assessment.

[0057] Based on the above embodiments, the method provided in this disclosure further includes: the main control module compares the previously captured BIOS log with the subsequently captured BIOS log, and when the subsequently captured BIOS log is the same as the previously captured BIOS log, the main control module generates an early warning message.

[0058] It should be noted that if the BIOS log captured in the previous capture is the same as the BIOS log captured in the next capture, it indicates that the target memory module has not been replaced on the system-level test device. In this case, by generating an early warning message, we can suggest replacing the internal standard memory module set on the system-level test device, thereby improving the efficiency of the target memory module's memory margin test.

[0059] In other words, when the main control module detects that the BIOS log has not been updated within a preset time, it generates an early warning message and attempts to capture the BIOS log again, thereby testing the memory sufficiency of different target memory modules set on the system-level test device.

[0060] Based on the above embodiments, continue Figure 2 The memory margin testing system includes a main control module, a system-level testing device, and a serial port server that communicates with the system-level testing device. The system-level testing device communicates with the main control module via a network port, and the system-level testing device also communicates with the serial port server via a configuration interface. The serial port server communicates with the main control module. The system is characterized by comprising: The main control module is configured to generate a test script in response to receiving the memory timing parameters set by the target object and the selected test options, and to send the test script to the system-level test device in response to receiving a test request from the system-level test device. The system-level testing device is configured to receive test scripts sent by the main control module and execute the test scripts to test the target memory module set by the system-level testing device through the test scripts. The main control module is also configured to capture BIOS logs during the testing of the target memory module by the system-level test device, and determine the memory margin test result of the target memory module set by the system-level test device based on the BIOS logs.

[0061] The memory margin testing system provided in this embodiment first generates a test script upon receiving the memory timing parameters and selected test options set by the target object. Then, in response to a test request from a system-level testing device, the main control module sends the test script to the system-level testing device. The system-level testing device receives the test script from the main control module and executes it to test the target memory module set by the system-level testing device. Finally, the main control module captures BIOS logs during the testing process of the target memory module by the system-level testing device and determines the memory margin test result of the target memory module set by the system-level testing device based on the BIOS logs. Firstly, RMT testing is integrated into the system-level testing device. Through script generation, BIOS interface calls, automatic log capture, and intelligent log analysis, the entire RMT testing process is automated, reducing manual intervention and improving testing efficiency and the accuracy of memory stability assessment.

[0062] In a specific implementation, the system-level testing device receives a test script sent by the main control module and executes the test script to test the target memory module set by the system-level testing device, including: The system-level test equipment receives the test script sent by the main control module, and enables the RMT test function through BIOS commands when executing the test script; The system-level test equipment continues to execute the test script and restarts the system-level test equipment via a restart command. After restarting, the system-level test device executes the RMT test function to test the target memory module set on the system-level test device.

[0063] In a specific implementation, determining the memory margin test result of the target memory module set by the system-level test device based on the BIOS log includes: Extract the numerical information of the target field based on the BIOS log; Based on the numerical information of the target field and the preset numerical information, the memory margin test result of the target memory module set by the system-level test equipment is determined.

[0064] In a specific implementation, determining the memory margin test result of the target memory module set by the system-level testing device based on the numerical information of the target field and the preset numerical information includes: Based on the relationship between the numerical information of the target field and the preset numerical information, the range of the preset numerical information in which the numerical information of the target field is located is determined. Based on the range of preset numerical information where the numerical information of the target field is located, the sub-memory margin test result of the target memory module set by the system-level test equipment is determined. Based on the test results of each sub-memory margin of the target memory module set by the system-level test equipment, the memory margin test results of the target memory module set by the system-level test equipment are determined.

[0065] In a specific implementation, before determining the memory margin test result of the target memory module set by the system-level test device based on the BIOS log, the method further includes: Obtain the type information of the target memory module set in the system-level test equipment; The step of determining the memory margin test results of the target memory module set by the system-level test device based on the BIOS log includes: Based on the BIOS logs and the type information of the target memory module set by the system-level test device, determine the memory margin test results of the target memory module set by the system-level test device.

[0066] In a specific implementation, the memory margin test system includes multiple system-level test devices and multiple serial port servers that are communicatively connected to the system-level test devices, and each of the serial port servers is communicatively connected to the main control module. The main control module, in response to receiving the memory timing parameters set by the target object and the selected test options, generates a test script, including: The main control module generates a test script in response to receiving the memory timing parameters set by the target object, the selected test options, and the selected target system-level test device identification information. In response to receiving a test request from a system-level test device, the main control module sends the test script to the system-level test device, including: In response to receiving test requests from various system-level test devices, the main control module determines the target system-level test device based on the target system-level test device identification information included in the test script; The main control module sends the test script to the target system-level test device.

[0067] In a specific implementation, the method further includes: The main control module compares the previously captured BIOS logs with the subsequently captured BIOS logs. If the subsequently captured BIOS logs are the same as the previously captured BIOS logs, the main control module generates an early warning message.

[0068] This application also provides a computer device, please refer to the following for details. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0069] The computer device includes a memory 510 and a processor 520 that are interconnected via a system bus. It should be noted that only a computer device with components 510-520 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented alternatively. Those skilled in the art will understand that the computer device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0070] Computer devices can include desktop computers, laptops, handheld computers, and cloud servers. These devices allow for human-computer interaction with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0071] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the computer device. Of course, the memory 510 may include both internal storage units and external storage devices of the computer device. In this embodiment, the memory 510 is typically used to store the operating system and various application software installed on the computer device, such as the program code of the method described above. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or will be output.

[0072] The processor 520 is typically used to perform the overall operation of a computer device. In this embodiment, the memory 510 is used to store program code or instructions, including computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or to process data, such as program code that runs the methods described above.

[0073] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0074] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0075] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0076] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0077] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0078] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0079] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0081] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0082] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A memory adequacy testing method, applied to a memory adequacy testing system, the memory adequacy testing system comprising a main control module, a system-level testing device, and a serial port server communicatively connected to the system-level testing device, the system-level testing device being communicatively connected to the main control module via a network port, the system-level testing device also being communicatively connected to the serial port server via a configuration interface, the serial port server being communicatively connected to the main control module, characterized in that, include: The main control module generates a test script in response to receiving the memory timing parameters set by the target object and the selected test options. In response to receiving a test request from a system-level test device, the main control module sends the test script to the system-level test device; The system-level test equipment receives the test script sent by the main control module and executes the test script to test the target memory module set by the system-level test equipment. The main control module captures BIOS logs during the testing of the target memory module by the system-level test equipment, and determines the memory margin test results of the target memory module set by the system-level test equipment based on the BIOS logs.

2. The method according to claim 1, characterized in that, The system-level testing equipment receives the test script sent by the main control module and executes the test script to test the target memory module set by the system-level testing equipment, including: The system-level test equipment receives the test script sent by the main control module, and enables the RMT test function through BIOS commands when executing the test script; The system-level test equipment continues to execute the test script and restarts the system-level test equipment via a restart command. After restarting, the system-level test device executes the RMT test function to test the target memory module set on the system-level test device.

3. The method according to claim 1, characterized in that, The step of determining the memory margin test results of the target memory module set by the system-level test device based on the BIOS log includes: Extract the numerical information of the target field based on the BIOS log; Based on the numerical information of the target field and the preset numerical information, the memory margin test result of the target memory module set by the system-level test equipment is determined.

4. The method according to claim 3, characterized in that, The step of determining the memory margin test result of the target memory module set by the system-level testing equipment based on the numerical information of the target field and the preset numerical information includes: Based on the relationship between the numerical information of the target field and the preset numerical information, the range of the preset numerical information in which the numerical information of the target field is located is determined. Based on the range of preset numerical information where the numerical information of the target field is located, the sub-memory margin test result of the target memory module set by the system-level test equipment is determined. Based on the test results of each sub-memory margin of the target memory module set by the system-level test equipment, the memory margin test results of the target memory module set by the system-level test equipment are determined.

5. The method according to claim 1, characterized in that, Before determining the memory margin test result of the target memory module set by the system-level test device based on the BIOS log, the method further includes: Obtain the type information of the target memory module set in the system-level test equipment; The step of determining the memory margin test results of the target memory module set by the system-level test device based on the BIOS log includes: Based on the BIOS logs and the type information of the target memory module set by the system-level test device, determine the memory margin test results of the target memory module set by the system-level test device.

6. The method according to claim 1, characterized in that, The memory margin testing system includes multiple system-level testing devices and multiple serial port servers that are communicatively connected to the system-level testing devices. Each of the serial port servers is communicatively connected to the main control module. The main control module, in response to receiving the memory timing parameters set by the target object and the selected test options, generates a test script, including: The main control module generates a test script in response to receiving the memory timing parameters set by the target object, the selected test options, and the selected target system-level test device identification information. In response to receiving a test request from a system-level test device, the main control module sends the test script to the system-level test device, including: In response to receiving test requests from various system-level test devices, the main control module determines the target system-level test device based on the target system-level test device identification information included in the test script; The main control module sends the test script to the target system-level test device.

7. The method according to claim 1, characterized in that, The method further includes: The main control module compares the previously captured BIOS logs with the subsequently captured BIOS logs. If the subsequently captured BIOS logs are the same as the previously captured BIOS logs, the main control module generates an early warning message.

8. A memory adequacy testing system, comprising a main control module, a system-level testing device, and a serial port server communicatively connected to the system-level testing device, wherein the system-level testing device is communicatively connected to the main control module via a network port, and the system-level testing device is also communicatively connected to the serial port server via a configuration interface, and the serial port server is communicatively connected to the main control module, characterized in that... include: The main control module is configured to generate a test script in response to receiving the memory timing parameters set by the target object and the selected test options, and to send the test script to the system-level test device in response to receiving a test request from the system-level test device. The system-level testing device is configured to receive test scripts sent by the main control module and execute the test scripts to test the target memory module set by the system-level testing device through the test scripts. The main control module is also configured to capture BIOS logs during the testing of the target memory module by the system-level test device, and determine the memory margin test result of the target memory module set by the system-level test device based on the BIOS logs.

9. A computer device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 7.

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