Link training state alignment method and data transmission system
By modifying the training bitstream using a Retimer chip, the end devices maintain a consistent training state throughout the training process, resolving the issues of state misalignment and transition in existing technologies and improving the stability and reliability of the system.
Patent Information
- Application Number
- CN202511202473.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-26
- Publication Date
- 2025-11-21
AI Technical Summary
Existing Retimer chips suffer from misalignment or state transition issues during link training, affecting the stability and reliability of the system.
The training bitstream is obtained through the control module in the Retimer chip, modified based on the current training state, and the modified bitstream is sent to the peer device to ensure that the peer device remains in the current state until both devices are in the current training state or the set time threshold is reached, at which point the modification stops.
This achieves alignment of the training states of the links on both ends of the system, improving the stability and reliability of the system and avoiding problems such as infinite loops and reduced link width.
Smart Images
Figure CN120994587A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal processing technology, and more specifically, to a link training state alignment method and a data transmission system. Background Technology
[0002] In high-speed data transmission systems, the retimer chip is a critical device. Its main function is to reshape and time received signals to ensure signal quality and reliability. In semiconductor integrated circuit design, retimer chips are typically integrated into various high-speed interfaces, such as PCIe, USB, and SATA, to achieve high-speed data transmission. In communication equipment manufacturing, retimer chips are widely used in various communication devices, such as switches, routers, and servers, to improve the communication performance and stability of these devices.
[0003] In existing technologies, retimer chips need to perform a resistance detection operation before retiming signals to verify the presence and validity of the signal. Then, channel alignment is required to ensure that the signals in each channel are time-aligned. This operation typically requires a specific operating system, such as selecting SKPOS in Gen1.
[0004] However, existing retimer chips have some problems in practical applications. First, because the alignment operation takes time, the timing of the bitstream transmission from both ends may interrupt the bitstream reception by both ends, thus affecting data transmission efficiency. Second, because the state machine transitions very quickly, problems may occur during state transitions, such as getting stuck in a certain state or training failures. These problems will affect the stability and reliability of the system.
[0005] In summary, existing technologies suffer from issues such as misalignment of training states or problems during state transitions during the training process of end devices, which affect the stability and reliability of the system. Summary of the Invention
[0006] The purpose of this application is to provide a link training state alignment method and a data transmission system to improve the stability and reliability of the system.
[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:
[0008] On one hand, embodiments of this application provide a link training state alignment method applied to a Retimer chip in a data transmission system. The data transmission system further includes a first-end device and a second-end device, both of which are communicatively connected to the Retimer chip. The method includes:
[0009] Obtain the training bitstream sent by the sending end; wherein, the sending end is either the first end device or the second end device;
[0010] The current training state is determined based on the training bitstream;
[0011] The training stream is modified based on the current training state, and the modified stream is sent to the peer device so that the peer device remains in the current state; wherein, the peer device is the other one of the first device and the second device;
[0012] When both the first end device and the second end device are in the current training state or have reached the set time threshold, the modification of the training bitstream is stopped.
[0013] Optionally, the step of modifying the training bitstream based on the current training state includes:
[0014] The training bitstream can be modified to the training bitstream of the previous training state, or the training bitstream can be modified to an invalid bitstream.
[0015] Optionally, before modifying the training bitstream based on the current training state, the method further includes:
[0016] Acquire the data processing capabilities of the peer device;
[0017] The steps for modifying the training bitstream based on the current training state include:
[0018] The method of modifying the bitstream is determined based on the data processing capability of the peer device. The method of modifying the bitstream includes modifying the training bitstream to the training bitstream of the previous training state, or modifying the training bitstream to an invalid bitstream.
[0019] Optionally, if the current training state is polling, the step of modifying the training bitstream based on the current training state includes:
[0020] Modify the received PAD-PAD TS2 training bitstream to PAD-PAD TS1 training bitstream.
[0021] Optionally, if the current training state is polling, the step of modifying the training bitstream based on the current training state includes:
[0022] After receiving fewer than N PAD-PAD TS2 training bitstreams, the critical domain is modified to an invalid value; where N represents the number of PAD-PAD TS2 training bitstreams required to jump from the polling state to the next training state.
[0023] Optionally, when N=8, the step of modifying the training bitstream based on the current training state includes:
[0024] Every 7 received PAD-PAD TS2 training bitstreams, the critical domain segments are modified to invalid values.
[0025] Optionally, if the current training state is cfg state, the step of modifying the training bitstream based on the current training state includes:
[0026] Modify the received None-PAD-PAD TS1 training bitstream to PAD-PAD TS2 training bitstream.
[0027] Optionally, if the current training state is cfg state, the step of modifying the training bitstream based on the current training state includes:
[0028] After every one received None-PAD-PAD TS1 training bitstream, the key domain segment is modified to an invalid value.
[0029] On the other hand, this application embodiment also provides a data transmission system, which further includes a first end device, a second end device, and a Retimer chip. The first end device and the second end device are both communicatively connected to the Retimer chip, and the Retimer chip is used to execute the above-described link training state alignment method.
[0030] Optionally, the Retimer chip includes a control module, a first processing module, and a second processing module. The control module is connected to both the first and second processing modules. The signal receiving end of the first processing module is connected to the first terminal device, and the signal output end of the first processing module is connected to the second terminal device. The signal receiving end of the second processing module is connected to the second terminal device, and the signal output end of the second processing module is connected to the first terminal device.
[0031] The first processing module is used to receive the training code stream sent by the first terminal device, and modify the training code stream based on the first control signal of the control module before sending it to the second terminal device;
[0032] The second processing module is used to receive the training code stream sent by the second terminal device, and modify the training code stream based on the second control signal of the control module before sending it to the first terminal device.
[0033] Compared with the prior art, this application has the following advantages:
[0034] This application provides a link training state alignment method and a data transmission system. The data transmission system uses a Retimer chip and includes a first-end device and a second-end device, both communicatively connected to the Retimer chip. First, the system acquires the training bitstream sent by the sending end (either the first or second device). Then, it determines the current training state based on the training bitstream. Next, it modifies the training bitstream based on the current training state and sends the modified bitstream to the peer device, ensuring the peer device remains in the current state. Finally, when both the first and second devices are in the current training state or a set time threshold is reached, the modification of the training bitstream stops. Because this application modifies the training bitstream after it is sent by the sending end during link training, ensuring the peer device remains in the current state, and stops modifying the training bitstream only when both ends are in the current training state, it guarantees consistency between the two devices in the training state, improving the system's stability and reliability.
[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram illustrating the unequal selection and training states of the two end devices in the prior art.
[0038] Figure 2 This is a schematic diagram illustrating how the link training width of devices at both ends in the existing technology cannot reach the theoretical maximum value.
[0039] Figure 3 This is a schematic diagram of the data transmission system provided in the embodiments of this application.
[0040] Figure 4 This is an exemplary flowchart of the link training state alignment method provided in the embodiments of this application.
[0041] Figure 5 This is a schematic diagram illustrating the modification of the training bitstream for the Polling state provided in the embodiments of this application.
[0042] Figure 6 This is a schematic diagram illustrating the modification of the training bitstream in the cfg state provided in the embodiments of this application.
[0043] In the picture:
[0044] 110 - Retimer chip; 111 - Control module; 112 - First processing module; 113 - Second processing module; 120 - First end device; 130 - Second end device. Detailed Implementation
[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0047] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0048] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0049] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0050] As described in the background section, currently, during end-device training, issues may arise such as misalignment of training states or problems during state transitions, affecting the stability and reliability of the system.
[0051] Specifically, during link training, the process sequentially goes through the Detect state, Polling state, and Configuration state (cfg state). The Polling state includes the Polling.active sub-state and the Polling.cfg sub-state. The condition for transitioning to the polling.cfg sub-state is receiving 8 consecutive TS2 streams and sending 16 TS2 streams. If the Retimer chip is still consuming streams for alignment operations when the later-entering device 1 sends TS2 streams, it may cause the earlier-entering device 2 to not receive enough 8 TS2 streams. This would cause device 1 to enter the next state machine, while device 2 would be stuck in this state. Since the timeout of the next state machine is half that of the current state, there is a significant time window for device 1 to re-enter this scenario after a timeout, repeating this process many times, ultimately leading to link training failure.
[0052] For example, such as Figure 1 As shown, terminal device 1 and terminal device 2 are connected via a Retimer chip. Terminal device 2 sends the bitstream to terminal device 1 via the uplink path, and terminal device 1 sends the bitstream to terminal device 2 via the downlink path. During link training, due to performance differences between terminal device 1 and terminal device 2 or other reasons, the time they spend in different training states may be unequal. Figure 1 As mentioned above, when terminal device 1 has ended the Polling.active sub-state, the alignment path of terminal device 2 is not yet complete, that is, the Polling.active sub-state is not completed. Therefore, terminal device 1 will time out and retrain. Since the time terminal device 2 spends in the Polling.active sub-state is half the time terminal device 1 spends in the Polling.active sub-state, terminal device 1 is very likely to fail to align with the state of terminal device 2 during retraining, leading to repeated training and a state machine dead loop.
[0053] In another possible scenario, when the physical link width of the RC (Root Complex) and EP (Endpoint) is 8 or 16, the initial bitstream transmission may not start with all links. This could cause the Retimer chip to align only a portion of the lanes first. When all links are up and running, the link interaction will quickly end once the cfg phase begins, typically completing with a dozen or so bitstreams. If the conditions for the Retimer chip to realign and add newly started links are not met at this point, the training width of the links may not reach its theoretical maximum.
[0054] like Figure 2As shown, if the newly added channel of end device 1 arrives just before the polling.active sub-state times out, and the polling.cfg sub-state lasts for tens of seconds, it may result in insufficient time to add the new channel. Furthermore, if end device 1's active transmitting channel reaches its maximum value just before end device 2 times out, end device 1 will enter the polling.cfg sub-state if its transmission and reception satisfy the transmission and reception rules for all channels, and the EP channel will time out and enter the polling.cfg stage. In these situations, the link training width may not reach its theoretical maximum; for example, the theoretical link training width is 16 channels, but only 8 channels are trained.
[0055] In view of this, in order to solve the above problems, this application provides a link training state alignment method and a method for extending the initial state machine window of the Retimer chip to achieve state alignment of the link training state machines on both sides.
[0056] The link training state alignment method provided in this application is illustrated below. It should be noted that the link training state alignment method provided in this application is applied to the Retimer chip of a data transmission system. Please refer to [link to relevant documentation]. Figure 3 The data transmission system further includes a first end device 120 and a second end device 130, both of which are communicatively connected to the Retimer chip 110.
[0057] Furthermore, the Retimer chip 110 includes a control module 111, a first processing module 112, and a second processing module 113. The control module 111 is connected to the first processing module 112 and the second processing module 113 respectively. The signal receiving end of the first processing module 112 is connected to the first end device 120, the signal output end of the first processing module 112 is connected to the second end device 130, the signal receiving end of the second processing module 113 is connected to the second end device 130, and the signal output end of the second processing module 113 is connected to the first end device 120.
[0058] The control module 111 can notify the first processing module 112 and the second processing module 113 to start and stop modifying the training bitstream based on the received training bitstream information. When it is necessary to extend the initial state machine window of both end devices, the first processing module 112 and the second processing module 113 are enabled to start modifying the training bitstream. When it is found that the extension of the initial state machine window time is sufficient, the modification function of the first processing module 112 and the second processing module 113 is turned off. The first processing module 112 is used to receive the training bitstream sent by the first end device 120, and modify the training bitstream based on the first control signal of the control module 111 before sending it to the second end device 130; the second processing module 113 is used to receive the training bitstream sent by the second end device 130, and modify the training bitstream based on the second control signal of the control module 111 before sending it to the first end device 120.
[0059] As one implementation method, please refer to Figure 4 The link training state alignment method provided in this application includes:
[0060] S102, obtain the training bitstream sent by the sending end; wherein the sending end is either the first end device 120 or the second end device 130.
[0061] S104, determine the current training status based on the training bitstream.
[0062] S106, Modify the training bitstream based on the current training state, and send the modified bitstream to the peer device so that the peer device remains in the current state; wherein, the peer device is the other one of the first end device 120 and the second end device 130.
[0063] S108, when both the first-end device 120 and the second-end device 130 are in the current training state or have reached the set time threshold, stop modifying the training bitstream.
[0064] Understandably, in the method provided in this application, the training bitstream is modified by the Retimer chip 110. This ensures that the state of the link training state machine of the two devices on both sides of the Retimer chip 110 remains consistent, thus enabling normal interaction. It also prevents one side from getting stuck in a certain state due to the Retimer chip 110. Furthermore, it overcomes the problem that some chips may not reach their maximum link width at startup due to some physical channels not being ready, and the Retimer chip 110 may not be able to process these physical channels in time when they are ready, resulting in a reduction in link width. This improves the overall stability and reliability of the system.
[0065] In this application, the peer device is the receiving end of the training code stream. For example, when the first end device 120 sends the training code stream to the second end device 130, the first end device 120 acts as the sending end and the second end device 130 acts as the peer device; and when the second end device 130 sends the training code stream to the first end device 120, the second end device 130 acts as the sending end and the first end device 120 acts as the peer device.
[0066] After the first-end device 120 or the second-end device 130 sends the training bitstream, the Retimer chip 110 receives the training bitstream through the first processing module 112 or the second processing module 113, and determines the current training state based on the training bitstream. Specifically, for each training state, there is specific bitstream information. For example, when a TS2 training bitstream with both the link number and lane number being the character "PAD" is received (i.e., PAD-PAD TS2), the current training state is determined to be the Polling.cfg sub-state; while when a TS1 training bitstream with a non-PAD character link number and a PAD character lane number is received (i.e., None-PAD-PADTS1), the current training state is determined to be the cfg state. Of course, the other training states also correspond to their respective specific bitstreams, which will not be elaborated upon here.
[0067] It should be noted that the training bitstream described in this application can be a binary string, such as 01010101, while the specific bitstream described in this application represents a specific string, such as 11110000, 00001111, etc.
[0068] It should also be noted that, due to the performance differences between the first-end device 120 and the second-end device 130, when the control module 111 modifies the training bitstream, it needs to determine the sending end of the training bitstream and its corresponding peer device. Since the first-end device 120 and the second-end device 130 will send the training bitstream through different processing modules before reaching the peer device, the control module 111 can determine which end device sent the training bitstream based on the received training bitstream processing module. For example, when the first processing module 112 receives the training bitstream, the control module 111 can determine that the sending end of the training bitstream is the first-end device 120 and the peer device is the second-end device 130; while when the second processing module 113 receives the training bitstream, the control module 111 can determine that the sending end of the training bitstream is the second-end device 130 and the peer device is the first-end device 120.
[0069] After determining the current training state and the sending end of the training bitstream, the control module 111 controls the processing module to modify the training bitstream based on the current training state. In this application, there are two ways to modify the training bitstream: one is to modify the training bitstream to the training bitstream of the previous training state, and the other is to modify the training bitstream to an invalid bitstream. When modifying the training bitstream to the training bitstream of the previous training state, after the end device receives the training bitstream, since this training bitstream is not the current training bitstream, the end device's state machine cannot jump to the next state, thus extending the state machine window. Similarly, when modifying the training bitstream to an invalid bitstream, after the end device receives the training bitstream, the end device's state machine also cannot jump to the next state, thus extending the state machine window.
[0070] Furthermore, modifying the training bitstream to match the previous training state's bitstream does not damage the training bitstream, but the implementation cost is relatively high; while modifying the training bitstream to an invalid bitstream, although the bitstream is damaged, the implementation cost is relatively low. Therefore, in order to flexibly and effectively extend the state machine window, it is necessary to select an appropriate training bitstream modification method based on the actual operating conditions.
[0071] In this application, the data processing capability of the peer device is obtained, and the method of modifying the bitstream is determined based on the peer device's data processing capability. For example, when the first device 120 sends out a training bitstream, the control module 111 can obtain the data processing capability of the peer device, i.e., the second device 130. If the peer device has good data processing capability, it can choose to modify the training bitstream to an invalid bitstream; if the peer device has poor data processing capability, it can choose to modify the training bitstream to the training bitstream of the previous training state.
[0072] Furthermore, the control module 111 can determine the method of modifying the bitstream by setting the register. For example, when the value of the register is 0, the training bitstream is modified to the training bitstream of the previous training state; when the value of the register is 1, the training bitstream is modified to an invalid bitstream.
[0073] The specific modifications to the training bitstream can also be adjusted based on different training states. For example, if the current training state is polling, the specific method for modifying the training bitstream is as follows:
[0074] Modify the received PAD-PAD TS2 training bitstream to PAD-PAD TS1 training bitstream.
[0075] In this implementation, the PAD-PAD TS2 training stream is the training stream of the Polling.cfg sub-state, and the PAD-PAD TS1 training stream is the training stream of the Polling.active sub-state. Taking the first-end device 120 sending the training stream as an example, based on this implementation, the training stream sent by the first-end device 120 is the PAD-PAD TS2 training stream. When the first processing module 112 receives the PAD-PAD TS2 training stream, it modifies the PAD-PAD TS2 training stream to the PAD-PAD TS1 training stream and sends the PAD-PAD TS1 training stream to the second-end device 130. After receiving the PAD-PAD TS1 training stream, the second-end device 130 will remain in the polling state because the state machine does not meet the rule of jumping to the next training state (i.e., the cfg state), thus lengthening the state machine window.
[0076] As another implementation, the key domain segment can be modified to an invalid value every N times after receiving the PAD-PAD TS2 training bitstream; where N represents the number of PAD-PAD TS2 training bitstreams required to jump from the polling state to the next training state.
[0077] The state machine transitions from the polling state to the cfg state only after receiving eight consecutive PAD-PADTS2 training streams. Therefore, if the peer device fails to receive eight consecutive PAD-PAD TS2 training streams, it will remain in the polling state and unable to transition to the cfg state. This application does not limit the interval for modifying key fields; for example, it can modify key fields to invalid values after 5, 6, or 7 training streams. To maintain the state machine's maximum normal operation, this application modifies key fields to invalid values every 7 received PAD-PAD TS2 training streams.
[0078] For example, when the first device 120 sends the training bitstream, the first processing module 112, after receiving the training bitstream, modifies the key segment in the 8th PAD-PAD TS2 training bitstream within every 8 consecutive PAD-PAD TS2 training bitstreams. Specifically, the modification can be done by changing a key character in the string, such as changing "1" to "0". This ensures that when the second device 130 receives the training bitstream, the first 7 PAD-PAD TS2 training bitstreams can be recognized normally, but the 8th training bitstream cannot be recognized because it has been modified. Furthermore, since the condition for the state machine to jump to the next training state is receiving 8 consecutive PAD-PAD TS2 training bitstreams, the state machine of the second device 130 cannot jump to the next training state after the training bitstream is modified.
[0079] Furthermore, the control module 111 continuously monitors the training states of the first device 120 and the second device 130. When both devices are in the current training state, the control module 111 stops modifying the training bitstream, allowing both devices to simultaneously enter the first training state, thus achieving training state synchronization. Conversely, if the modification time of the training bitstream reaches a set threshold, it indicates a potential system malfunction, and the control module 111 will also stop modifying the training bitstream.
[0080] Therefore, please refer to Figure 5 When in polling state, the link training state alignment steps may include the following:
[0081] Step 1: Control module 111 continuously captures training bitstream information from both end devices and determines whether the end device has entered the Polling.cfg stage (i.e., PAD-PAD TS2) based on the current bitstream. If the currently received training bitstream is PAD-PAD TS2, then proceed to step 2; otherwise, continue capturing the training bitstream.
[0082] Step 2: Control module 111 determines whether the currently captured PAD-PAD TS2 training bitstream was sent by the first end device 120. If yes, proceed to step 3; otherwise, proceed to step 4.
[0083] Step 3: Control module 111 determines the method of modifying the bitstream (register value 0 or 1). If it is method 1, proceed to step 5; otherwise, proceed to step 6.
[0084] Step 4: Control module 111 determines the method of modifying the bitstream. If it is method 1, proceed to step 7; otherwise, proceed to step 8.
[0085] Step 5: According to the instruction to modify the training bitstream transmitted from the control module 111, the first processing module 112 adopts the bitstream modification method 1 to change the received PAD-PAD TS2 training bitstream from the first end device 120 to the PAD-PAD TS1 training bitstream and sends it to the second end device 130.
[0086] Step 6: According to the instruction to modify the training bitstream from the control module 111, the first processing module 112 modifies the key field of the received PAD-PAD TS2 training bitstream from the first end device 120 to an invalid value after every 7 bits, and sends it to the second end device 130. In this way, the state machine of the second end device 130 cannot meet the condition for jumping to the next state.
[0087] Step 7: The second processing module 113, according to the instruction to modify the training bitstream transmitted from the control module 111, adopts the bitstream modification method 1 to change the received PAD-PAD TS2 training bitstream from the second end device 130 to the PAD-PAD TS1 training bitstream, and sends it to the first end device 120.
[0088] Step 8: According to the instruction to modify the training bitstream from the control module 111, the second processing module 113 modifies the key field of the received PAD-PAD TS2 training bitstream from the second end device 130 to an invalid value after every 7 bits, and sends it to the first end device 120. In this way, the state machine of the first end device 120 cannot meet the condition for jumping to the next state.
[0089] Step 9: After the control module 111 issues the modification code stream for a certain period of time (register operation) or after the control module 111 makes both end devices in polling.cfg, the state machines of both end devices are aligned, and the conditions for stopping the modification of the training code stream are met. The control module 111 simultaneously notifies the first processing module 112 and the second processing module 113 to stop modifying the training code stream.
[0090] If the current training state is cfg, the specific method to modify the training bitstream is as follows:
[0091] Modify the received None-PAD-PAD TS1 training bitstream to PAD-PAD TS2 training bitstream.
[0092] In this implementation, the None-PAD-PAD TS1 training stream is in the cfg state, and the PAD-PAD TS2 training stream is in the Polling.cfg sub-state. Taking the first device 120 sending the training stream as an example, based on this implementation, the training stream sent by the first device 120 is the None-PAD-PAD TS1 training stream. When the first processing module 112 receives the None-PAD-PAD TS1 training stream, it modifies the None-PAD-PAD TS1 training stream to the PAD-PAD TS2 training stream and sends the PAD-PAD TS2 training stream to the second device 130. After receiving the PAD-PAD TS2 training stream, the second device 130 will remain in the cfg state because the state machine does not meet the rule for jumping to the next training state, thus lengthening the state machine window.
[0093] As an alternative implementation, the key domain segment can be modified to an invalid value every single one of the received None-PAD-PAD TS1 training bitstreams.
[0094] The requirement for the state machine to transition from the cfg state to the next training state is to receive two consecutive None-PAD-PAD TS1 training streams. Therefore, if the peer device cannot receive two consecutive PAD-PAD TS2 training streams, it will remain in the cfg state and will not be able to transition to the next state.
[0095] Therefore, please refer to Figure 6 When in cfg state, the link training state alignment steps may include the following:
[0096] Step 1: Control module 111 continuously captures training bitstream information from both end devices and determines whether the end device has entered the cfg stage (i.e., received None-PAD-PAD TS1) based on the current training bitstream. If the currently received training bitstream is None-PAD-PAD TS1, then proceed to step 2; otherwise, continue capturing the training bitstream.
[0097] Step 2: Control module 111 determines whether the currently captured None-PAD-PAD TS1 training bitstream was sent by the first end device 120. If yes, proceed to step 3; otherwise, proceed to step 4.
[0098] Step 3: Control module 111 determines the method of modifying the bitstream. If it is method 1, proceed to step 5; otherwise, proceed to step 6.
[0099] Step 4: Control module 111 determines the method of modifying the bitstream. If it is method 1, proceed to step 7; otherwise, proceed to step 8.
[0100] Step 5: According to the instruction to modify the training bitstream transmitted from the control module 111, the first processing module 112 adopts the bitstream modification method 1 to change the None-PAD-PAD TS1 training bitstream received from the first end device 120 to the PAD-PAD TS2 training bitstream, and sends it to the second end device 130.
[0101] Step 6: According to the instruction to modify the training bitstream from the control module 111, the first processing module 112 modifies the key field of the received None-PAD-PAD TS1 training bitstream from the first end device 120 to an invalid value after every 1, and sends it to the second end device 130. In this way, the state machine of the second end device 130 can no longer meet the conditions for jumping to the next state.
[0102] Step 7: The second processing module 113, according to the instruction to modify the training bitstream transmitted from the control module 111, adopts the bitstream modification method 1 to change the received None-PAD-PAD TS1 training bitstream from the second end device 130 to the PAD-PAD TS2 training bitstream, and sends it to the first end device 120.
[0103] Step 8: According to the instruction to modify the training bitstream from the control module 111, the second processing module 113 modifies the key field of the received None-PAD-PAD TS1 training bitstream from the second end device 130 to an invalid value after every 1, and sends it to the first end device 120. In this way, the state machine of the first end device 120 can no longer meet the conditions for jumping to the next state.
[0104] Step 9: After the control module 111 issues the modification code stream for a certain period of time, or after the control module 111 makes both end devices on both sides enter the cfg stage, the state machines of both end devices are aligned, and the conditions for stopping the modification of the training code stream are met. The control module 111 simultaneously notifies the first processing module 112 and the second processing module 113 to stop modifying the training code stream.
[0105] Understandably, the method of modifying the training bitstream using the Retimer chip in this application can effectively extend the initial state machine window of both end devices, enabling the initial state machines of both end devices to align and avoiding infinite loops caused by state machine misalignment due to the Retimer chip. Simultaneously, modifying the training bitstream using the Retimer chip can accommodate the reduced link width introduced by significant differences in the initialization completion times of different channels on some end devices, ensuring that each PCIe training session reaches the maximum supported channel width.
[0106] In addition, this application adopts two methods to modify the training bitstream, which can flexibly and effectively delay the corresponding initial state machine window, align the state machines on both sides and update the link state, while not causing errors in the link establishment process of the first end device 120 and the second end device 130, ensuring that the link with the Retimer chip can be trained smoothly and achieve the expected rate and width.
[0107] Based on the above implementation, this application embodiment also provides a data transmission system, which further includes a first end device 120, a second end device 130, and a Retimer chip. Both the first end device 120 and the second end device are communicatively connected to the Retimer chip, which is used to execute the above-mentioned link training state alignment method.
[0108] In summary, this application provides a link training state alignment method and a data transmission system. The data transmission system uses a Retimer chip and includes a first-end device 120 and a second-end device 130, both of which are communicatively connected to the Retimer chip. First, the system acquires the training bitstream sent by the sending end (either the first-end device 120 or the second-end device 130). Then, it determines the current training state based on the training bitstream. Next, it modifies the training bitstream based on the current training state and sends the modified bitstream to the peer device to ensure the peer device remains in the current state (the other of the first-end device 120 and the second-end device 130). Finally, when both the first-end device 120 and the second-end device 130 are in the current training state or a set time threshold is reached, the modification of the training bitstream is stopped. Because this application modifies the training bitstream after the sending end sends it during the link training process, the peer device remains in the current state. Furthermore, the modification of the training bitstream will only stop when both ends of the device are in the current training state. Therefore, the consistency of the two ends of the device in the training state is guaranteed, and the stability and reliability of the system are improved.
[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0110] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A link training state alignment method, characterized in that, A Retimer chip is used in a data transmission system, the data transmission system further including a first end device and a second end device, both of which are communicatively connected to the Retimer chip. The method includes: Obtain the training bitstream sent by the sending end; wherein, the sending end is either the first end device or the second end device; The current training state is determined based on the training bitstream; The training stream is modified based on the current training state, and the modified stream is sent to the peer device so that the peer device remains in the current state; wherein, the peer device is the other one of the first device and the second device; When both the first end device and the second end device are in the current training state or have reached the set time threshold, the modification of the training bitstream is stopped.
2. The link training state alignment method as described in claim 1, characterized in that, The step of modifying the training bitstream based on the current training state includes: The training bitstream can be modified to the training bitstream of the previous training state, or the training bitstream can be modified to an invalid bitstream.
3. The link training state alignment method as described in claim 2, characterized in that, Before the step of modifying the training bitstream based on the current training state, the method further includes: Acquire the data processing capabilities of the peer device; The steps for modifying the training bitstream based on the current training state include: The method of modifying the bitstream is determined based on the data processing capability of the peer device. The method of modifying the bitstream includes modifying the training bitstream to the training bitstream of the previous training state, or modifying the training bitstream to an invalid bitstream.
4. The link training state alignment method as described in claim 1, characterized in that, If the current training state is polling, the steps for modifying the training bitstream based on the current training state include: Modify the received PAD-PAD TS2 training bitstream to PAD-PAD TS1 training bitstream.
5. The link training state alignment method as described in claim 1, characterized in that, If the current training state is polling, the steps for modifying the training bitstream based on the current training state include: After receiving fewer than N PAD-PAD TS2 training bitstreams, the critical domain is modified to an invalid value; where N represents the number of PAD-PAD TS2 training bitstreams required to jump from the polling state to the next training state.
6. The link training state alignment method as described in claim 5, characterized in that, When N=8, the steps for modifying the training bitstream based on the current training state include: Every 7 received PAD-PAD TS2 training bitstreams, the critical domain segments are modified to invalid values.
7. The link training state alignment method as described in claim 1, characterized in that, If the current training state is cfg state, the steps for modifying the training bitstream based on the current training state include: Modify the received None-PAD-PAD TS1 training bitstream to PAD-PAD TS2 training bitstream.
8. The link training state alignment method as described in claim 1, characterized in that, If the current training state is cfg state, the steps for modifying the training bitstream based on the current training state include: After every one received None-PAD-PAD TS1 training bitstream, the key domain segment is modified to an invalid value.
9. A data transmission system, characterized in that, The data transmission system further includes a first end device, a second end device, and a Retimer chip. Both the first end device and the second end device are communicatively connected to the Retimer chip, which is used to execute the link training state alignment method as described in any one of claims 1 to 8.
10. The data transmission system as described in claim 9, characterized in that, The Retimer chip includes a control module, a first processing module, and a second processing module. The control module is connected to both the first and second processing modules. The signal receiving end of the first processing module is connected to a first terminal device, and its signal output end is connected to the second terminal device. The signal receiving end of the second processing module is connected to the second terminal device, and its signal output end is connected to the first terminal device. The first processing module is used to receive the training code stream sent by the first terminal device, and modify the training code stream based on the first control signal of the control module before sending it to the second terminal device; The second processing module is used to receive the training code stream sent by the second terminal device, and modify the training code stream based on the second control signal of the control module before sending it to the first terminal device.