DDR model system for soc chip verification and method of using the same

Abstract

This invention discloses a DDR model system and its usage method for SoC chip verification, relating to the field of chip design verification technology. The system includes: multiple protocol interface modules capable of connecting to the circuit modules being verified on the SoC chip, used to receive command sequences from different bus interface protocols; an initialization data module for storing key timing information required for DDR controller initialization, converting command sequences from different bus interface protocols into command sequences conforming to the JEDEC DDR specification, supporting direct loading of key timing information via a backdoor, and automatically loading key timing information into registers after reset; and an address mapping module for mapping logical addresses in the command sequences to physical addresses recognizable by the storage module, and writing the data corresponding to the logical addresses to the corresponding locations in the storage module. This invention can significantly shorten the DDR controller initialization time and accelerate the simulation verification process of the SoC chip.

Description

Technical Field

[0001] This invention relates to the field of chip design verification technology, and in particular to a DDR model system for SoC chip verification and its usage method. Background Technology

[0002] With the rapid development of integrated circuit technology, the design scale of System-on-Chip (SoC) chips has grown exponentially. The number of logic gates integrated within large SoC chips has reached tens of billions, and the functional modules are becoming increasingly complex. This complexity makes simulation verification of SoC chips before tape-out a key bottleneck in the entire design process. Simulation verification is difficult, time-consuming, and costly. Therefore, developing efficient SoC chip verification acceleration technologies is crucial.

[0003] In the simulation and verification process of SoC chips, the initialization process of high-speed peripheral interface circuits, such as the double data rate synchronous dynamic random access memory (DDR) controller, is an indispensable step. The DDR controller initialization process typically requires the processor core (CPU Core) to complete register configuration by sending a series of commands under the management of the operating system. Taking the fifth-generation DDR (DDR5) controller as an example, it requires configuring tens of thousands of registers, making the DDR controller initialization process extremely time-consuming. Furthermore, if the DDR controller initialization process includes training operations, it requires extensive circuit algorithm iterations to adjust signal timing. This results in the DDR controller initialization time accounting for over 99% of the total SoC chip simulation time, while the actual time for other functional modules of the SoC chip to access DDR for functional verification accounts for less than 1%.

[0004] In the existing simulation verification process of SoC chips, it is necessary to wait for the DDR controller to be initialized before other circuit modules can be effectively simulated and verified. The initialization process of the DDR controller is extremely time-consuming, which greatly affects the efficiency of SoC chip simulation verification and thus limits the convergence time of SoC chip simulation verification.

[0005] Therefore, a DDR model system and its usage method for SoC chip verification are proposed, which can significantly shorten the DDR controller initialization time, significantly accelerate the simulation verification process of SoC chips, shorten the SoC chip verification cycle, and reduce the time and cost of SoC chip R&D. Summary of the Invention

[0006] To address some or all of the technical problems existing in the prior art, this invention provides a DDR model system and its usage method for SoC chip verification, which can significantly shorten the DDR controller initialization time, significantly accelerate the simulation verification process of SoC chips, shorten the SoC chip verification cycle, and reduce the time and cost of SoC chip development.

[0007] The technical solution of the present invention is as follows:

[0008] Firstly, a DDR model system for SoC chip verification is provided, including:

[0009] Multiple protocol interface modules can connect to verified circuit modules on the SoC chip to receive command sequences of different bus interface protocols;

[0010] The initialization data module is connected to multiple protocol interface modules and is configured with registers and backdoor operation interfaces. It is used to store key timing information required for DDR controller initialization, convert command sequences of different bus interface protocols into command sequences that conform to the JEDEC DDR specification, support the direct loading of key timing information required for DDR controller initialization through a backdoor, and can automatically load key timing information into registers after reset.

[0011] The address mapping module is connected to the initialization data module and the storage module respectively. It is used to map the logical address in the command sequence to the physical address that the storage module can recognize, and write the data corresponding to the logical address into the corresponding position of the storage module.

[0012] The storage module is used for storing data.

[0013] Furthermore, in some embodiments, the plurality of the protocol interface modules include multiple of the following: CHI protocol interface module, AXI4 protocol interface module, AXI4-Lite protocol interface module, AXI4-Stream protocol interface module, APB protocol interface module, and AHB protocol interface module.

[0014] Furthermore, in some embodiments, the APB protocol interface module can write data to and read data from the initialization data module to verify whether the APB function of other circuit modules on the SoC chip is correct.

[0015] Furthermore, in some embodiments, the AHB protocol interface module can write data to and read data from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

[0016] Furthermore, in some implementations, the DDR model system is configured via a multi-bit-wide mode selection parameter and compiler macro definitions to select and enable different protocol interface modules;

[0017] The highest bit of the mode selection parameter is used to select whether to use a DDR model system or a real DDR controller, and the lowest bit of the mode selection parameter is used to further select the enabled protocol interface module when selecting a DDR model system.

[0018] Secondly, a method for using the DDR model system for SoC chip verification, as described above, is also provided, including:

[0019] During the simulation compilation phase, the working mode of the DDR model system and the required protocol interface modules are selected by setting multi-bit width mode selection parameters and configuring macro definitions;

[0020] At the start of the simulation, the key timing information required for DDR controller initialization is directly loaded into the initialization data module through a backdoor, thereby skipping the actual DDR controller initialization process.

[0021] The DDR model system interacts with the verified circuit modules in the SoC chip through the selected protocol interface module to complete the functional verification of the circuit modules.

[0022] Furthermore, in some embodiments, selecting the operating mode of the DDR model system and the required protocol interface module by setting multi-bit width mode selection parameters and configuring macro definitions includes the following steps:

[0023] Determine the value of ddr_model[3];

[0024] If the value of ddr_model[3] is 1'b0, then the working mode of the DDR model system is selected as disabled, and the macro definition of the real DDR controller is used to verify the function of the circuit module in the SoC chip using the real DDR controller, and the DDR controller is initialized normally.

[0025] If the value of ddr_model[3] is 1'b1, then the working mode of the DDR model system is selected as enabled, and the value of ddr_model[2] is further determined;

[0026] If the value of ddr_model[2] is 1'b0, then the macro definition of the APB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the APB protocol interface module.

[0027] If the value of ddr_model[2] is 1'b1, then the macro definition of the AHB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AHB protocol interface module;

[0028] Wherein, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1'b0 represents a 1-bit wide binary number with a value of 0; 1'b1 represents a 1-bit wide binary number with a value of 1.

[0029] Furthermore, in some embodiments, the step of selecting the operating mode of the DDR model system and the required protocol interface module by setting multi-bit width mode selection parameters and configuring macro definitions further includes the following steps:

[0030] When the value of ddr_model[3] is 1'b1, further determine the value of ddr_model[1:0];

[0031] If the value of ddr_model[1:0] is 2'b00, then the macro definition of the CHI protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the CHI protocol interface module.

[0032] If the value of ddr_model[1:0] is 2'b01, then the macro definition of the AXI4 protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4 protocol interface module.

[0033] If the value of ddr_model[1:0] is 2'b10, then the macro definition of the AXI4-Lite protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4-Lite protocol interface module.

[0034] If the value of ddr_model[1:0] is 2'b11, then the macro definition of the AXI4-Stream protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4-Stream protocol interface module.

[0035] Wherein, ddr_model[1:0] indicates that the mode selection parameter includes a bit field of two binary bits from the 1st bit to the 0th bit; 2'b00 represents a 2-bit wide binary number with a value of 00; 2'b01 represents a 2-bit wide binary number with a value of 01; 2'b10 represents a 2-bit wide binary number with a value of 10; 2'b11 represents a 2-bit wide binary number with a value of 11.

[0036] The main advantages of the technical solution of this invention are as follows:

[0037] The DDR model system for SoC chip verification of this invention can replace the real DDR controller, DDR physical interface, and SDRAM module in a simulation verification environment. By setting up various different protocol interface modules to receive and process command sequences of different types of bus interface protocols, it can quickly adapt to different SoC chip architectures and verification requirements, and is suitable for various verification scenarios such as module level, subsystem level, and system level. By setting up an initialization data module that supports directly loading the key timing information required for DDR controller initialization through a backdoor, and automatically loading the key timing information into registers after reset, it can completely avoid the time-consuming and lengthy DDR controller initialization process, significantly accelerate the simulation verification process of SoC chips, shorten the SoC chip verification cycle, and reduce the time cost of SoC chip development. Furthermore, the initialization data module supports dynamic reconfiguration, which facilitates boundary condition testing, fault injection, and debugging by verification engineers, and helps to more comprehensively cover test points and improve the completeness of verification. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0039] Figure 1 A schematic diagram of the structure of an existing SoC chip is provided as an example;

[0040] Figure 2 This is a schematic diagram of the structure of a DDR model system for SoC chip verification provided in an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of another DDR model system for SoC chip verification provided in an embodiment of the present invention;

[0042] Figure 4 This is a flowchart illustrating a method for using a DDR model system for SoC chip verification, as provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0044] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] refer to Figure 1The SoC chip mainly includes a core module, a Level 3 cache module, a PCIe (Peripheral Component Interconnect Express) module, a UCIE (Universal Chip Interconnect Express) module, a DDR module, and an SDRAM (Synchronous Dynamic Random-Access Memory) module; the DDR module includes a DDR controller and a DDR physical interface. The SoC chip's core module is primarily responsible for sending configuration register commands to set the DDR controller's registers and for interacting with the SDRAM module via read / write commands. The L3 cache module handles data caching to improve access efficiency. The PCIe module is a high-speed serial computer expansion bus module, primarily responsible for connecting to computer peripherals and providing high-speed data transmission. The UCIE module is a standard for chip-to-chip interconnection, primarily responsible for enabling high-speed, low-latency communication between chips. The DDR controller connects to and interacts with the L3 cache module. The DDR controller can convert the logical addresses of memory access commands sent by the L3 cache module (such as AXI (Advanced eXtensible Interface), CHI (Coherent Hub Interface), APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), etc.) into corresponding physical addresses, and convert these memory access commands into read / write commands conforming to the JEDEC (Joint Electron Device Engineering Council) DDR specification. The DDR physical interface primarily converts the logic signals sent by the DDR controller into electrical signals and sends them to the SDRAM module. It is also used for ZQ calibration, Write Leveling, Read Leveling, and VREF Leveling to ensure signal accuracy and stability. The SDRAM module is the core of data storage, responsible for storing data and providing data according to read commands from the DDR physical interface, and writing data according to write commands from the DDR physical interface.

[0046] refer to Figure 2In a first aspect, embodiments of the present invention provide a DDR model system for SoC chip verification. This DDR model system is used to replace the actual DDR controller, DDR physical interface, and SDRAM module in a simulation verification environment, including:

[0047] Multiple protocol interface modules can connect to verified circuit modules on the SoC chip to receive command sequences of different bus interface protocols;

[0048] The initialization data module is connected to multiple protocol interface modules and is configured with registers and backdoor operation interfaces. It is used to store the key timing information required for DDR controller initialization, convert the command sequence of different bus interface protocols into a command sequence that conforms to the JEDEC DDR specification, support the direct loading of key timing information required for DDR controller initialization through the backdoor, and can automatically load key timing information into registers after reset.

[0049] The address mapping module is connected to the initialization data module and the storage module respectively. It is used to map the logical addresses in the command sequence to physical addresses that the storage module can recognize, and write the data corresponding to the logical addresses into the corresponding positions in the storage module.

[0050] The storage module is used to store data.

[0051] In this embodiment of the invention, one protocol interface module corresponds to one type of bus interface protocol. Each protocol interface module is responsible for receiving the command sequence of its corresponding bus interface protocol and sending it to the initialization data module, so that the initialization data module converts the received command sequence of the bus interface protocol into a command sequence conforming to the JEDEC DDR specification. By designing multiple protocol interface modules and making each of the multiple protocol interface modules correspond to a variety of different bus interface protocols, the DDR model system can have extremely high flexibility and scalability, and can be seamlessly integrated into SoC chip verification environments based on different bus architectures.

[0052] In this embodiment of the invention, the initialization data module is internally configured with registers and a backdoor operation interface, enabling connection to devices in the SoC chip verification environment. The initialization data module stores critical timing information required for DDR controller initialization. This critical timing information is essential for ensuring the system operates normally under different protocols. The initialization data module can convert command sequences from different bus interface modules into command sequences conforming to the JEDEC DDR specification based on the critical timing information. This conversion process enables the DDR model system to support various complex AMBA (Advanced Microcontroller Bus Architecture) bus interface protocols, ensuring normal and efficient operation in different verification environments. The initialization data module supports directly loading the critical timing information required for DDR controller initialization via a backdoor. After reset, it automatically loads the critical timing information into registers. In other words, the verification environment can directly write the critical timing information into the internal registers of the initialization data module via the backdoor operation interface, thereby quickly completing the initialization process and avoiding the time-consuming initialization process of a real DDR controller.

[0053] In this embodiment of the invention, the backdoor method can be implemented using the force and deposit commands of SystemVerilog, or the uvm_hdl_deposit() function of UVM (Universal Verification Methodology).

[0054] In this embodiment of the invention, the address mapping module receives the converted command sequence sent by the initialization data module, converts the logical address corresponding to the command sequence into a physical address that the storage module can recognize according to the predefined address mapping rules, and writes the data corresponding to the command sequence into the corresponding location of the storage module.

[0055] In this embodiment of the invention, the storage module performs data read and write operations according to the address provided by the address mapping module to store the data, thereby simulating the function of the SDRAM module in the SoC chip.

[0056] The DDR model system for SoC chip verification provided in this invention can replace the real DDR controller, DDR physical interface, and SDRAM module in a simulation verification environment. By setting up various protocol interface modules to receive and process command sequences of different types of bus interface protocols, it can quickly adapt to different SoC chip architectures and verification requirements, and is suitable for various verification scenarios such as module level, subsystem level, and system level. By setting up an initialization data module that supports directly loading the key timing information required for DDR controller initialization through a backdoor, and automatically loading the key timing information into registers after reset, the time-consuming and lengthy DDR controller initialization process can be completely avoided, significantly accelerating the simulation verification process of SoC chips, shortening the SoC chip verification cycle, and reducing the time cost of SoC chip development. Furthermore, the initialization data module supports dynamic reconfiguration, which facilitates boundary condition testing, fault injection, and debugging by verification engineers, helping to more comprehensively cover test points and improve the completeness of verification.

[0057] refer to Figure 3 Furthermore, in this embodiment of the invention, the plurality of protocol interface modules include: multiple of the following: CHI (CoherentHub Interface) protocol interface module, AXI4 (Advanced eXtensible Interface 4) protocol interface module, AXI4-Lite (Advanced eXtensible Interface 4-Lite) protocol interface module, AXI4-Stream (Advanced eXtensible Interface 4-Stream) protocol interface module, APB (Advanced PeripheralBus) protocol interface module, and AHB (Advanced High-performance Bus) protocol interface module.

[0058] The CHI protocol interface module is used to connect to external devices compliant with the CHI protocol and receive command sequences of the CHI protocol; the AXI4 protocol interface module is used to connect to external devices compliant with the AXI4 protocol and receive command sequences of the AXI4 protocol; the AXI4-Lite protocol interface module is used to connect to external devices compliant with the AXI4-Lite protocol and receive command sequences of the AXI4-Lite protocol; the AXI4-Stream protocol interface module is used to connect to external devices compliant with the AXI4-Stream protocol and receive command sequences of the AXI4-Stream protocol; the APB protocol interface module is used to connect to external devices compliant with the APB protocol and receive command sequences of the APB protocol; and the AHB protocol interface module is used to connect to external devices compliant with the AHB protocol and receive command sequences of the AHB protocol.

[0059] In this embodiment of the invention, by setting up a CHI protocol interface module, an AXI4 protocol interface module, an AXI4-Lite protocol interface module, an AXI4-Stream protocol interface module, an APB protocol interface module, and an AHB protocol interface module, the DDR model system can be adapted to multiple bus interface protocols, including CHI, AXI, APB, and AHB protocols, to meet different usage scenarios and verification requirements.

[0060] Furthermore, in this embodiment of the invention, the APB protocol interface module can write data to and read data from the initialization data module to verify whether the APB function of other circuit modules on the SoC chip is correct; the AHB protocol interface module can write data to and read data from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

[0061] Furthermore, in this embodiment of the invention, the DDR model system is configured through a multi-bit-wide mode selection parameter and compiler macro definition to select and enable different protocol interface modules.

[0062] Specifically, in this embodiment of the invention, a multi-bit wide mode selection parameter is set to determine the protocol interface module to be enabled in the DDR model system; wherein, the highest bit of the mode selection parameter is used to select whether to use the DDR model system or the actual DDR controller, and the lowest bit of the mode selection parameter is used to further select the enabled protocol interface module when selecting the DDR model system.

[0063] In this embodiment of the invention, a 4-bit mode selection parameter is set to determine the protocol interface module enabled by the DDR model system.

[0064] refer to Figure 4 Secondly, embodiments of the present invention also provide a method for using the DDR model system for SoC chip verification as described above, the method comprising the following steps:

[0065] Step 1: During the simulation compilation phase, select the working mode of the DDR model system and the required protocol interface modules by setting the multi-bit width mode selection parameters and configuring macro definitions;

[0066] Step 2: At the start of the simulation, the key timing information required for DDR controller initialization is directly loaded into the initialization data module through a backdoor, thereby skipping the actual DDR controller initialization process.

[0067] Step 3: Enable the DDR model system to interact with the verified circuit module in the SoC chip through the selected protocol interface module to complete the functional verification of the circuit module.

[0068] Specifically, in this embodiment of the invention, when selecting the operating mode of the DDR model system through the set multi-bit width mode selection parameters and configuration macro definitions, the operating mode of the DDR model system includes enabled and disabled. When the operating mode of the DDR model system is enabled, the DDR model system is used to perform functional verification of the circuit modules in the SoC chip. When the operating mode of the DDR model system is disabled, the actual DDR controller is used to perform functional verification of the circuit modules in the SoC chip. Specifically, when using the DDR model system to perform functional verification of the circuit modules in the SoC chip, the key timing information required for DDR controller initialization is directly loaded into the initialization data module via a backdoor, thereby skipping the actual DDR controller initialization process. When using the actual DDR controller to perform functional verification of the circuit modules in the SoC chip, the DDR controller is initialized normally.

[0069] Furthermore, based on the aforementioned specific configuration of multiple protocol interface modules, in this embodiment of the invention, the operating mode of the DDR model system and the required protocol interface modules are selected through the configured multi-bit width mode selection parameters and configuration macro definitions, including the following steps:

[0070] Determine the value of ddr_model[3];

[0071] If the value of ddr_model[3] is 1'b0, then the working mode of the DDR model system is selected as disabled, and the macro definition of the real DDR controller is used to verify the function of the circuit module in the SoC chip using the real DDR controller, and the DDR controller is initialized normally.

[0072] If the value of ddr_model[3] is 1'b1, then the working mode of the DDR model system is selected as enabled, and the value of ddr_model[2] is further determined;

[0073] If the value of ddr_model[2] is 1'b0, then the macro definition of the APB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the APB protocol interface module.

[0074] If the value of ddr_model[2] is 1'b1, then the macro definition of the AHB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AHB protocol interface module.

[0075] In this embodiment of the invention, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1'b0 represents a 1-bit wide binary number with a value of 0; 1'b1 represents a 1-bit wide binary number with a value of 1.

[0076] Furthermore, based on the aforementioned specific configuration of multiple protocol interface modules, in this embodiment of the invention, the operating mode of the DDR model system and the required protocol interface modules are selected through the configured multi-bit width mode selection parameters and configuration macro definitions, and the following steps are also included:

[0077] When the value of ddr_model[3] is 1'b1, further determine the value of ddr_model[1:0];

[0078] If the value of ddr_model[1:0] is 2'b00, then the macro definition of the CHI protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the CHI protocol interface module.

[0079] If the value of ddr_model[1:0] is 2'b01, then the macro definition of the AXI4 protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4 protocol interface module.

[0080] If the value of ddr_model[1:0] is 2'b10, then the macro definition of the AXI4-Lite protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4-Lite protocol interface module.

[0081] If the value of ddr_model[1:0] is 2'b11, then the macro definition of the AXI4-Stream protocol interface module is used to enable the DDR model system to connect to the verified circuit module in the SoC chip through the AXI4-Stream protocol interface module.

[0082] In this embodiment of the invention, ddr_model[1:0] indicates that the mode selection parameter includes a bit field of two binary bits from the 1st bit to the 0th bit; 2'b00 represents a 2-bit wide binary number with a value of binary 00; 2'b01 represents a 2-bit wide binary number with a value of binary 01; 2'b10 represents a 2-bit wide binary number with a value of binary 10; 2'b11 represents a 2-bit wide binary number with a value of binary 11.

[0083] In this embodiment of the invention, by selecting the working mode and required protocol interface modules of the DDR model system in the above manner, interfaces of different bus protocols can be freely configured, thereby improving the flexibility and scalability of the DDR model system to be suitable for different SoC chip functional verification test scenarios; by directly loading the key timing information required for DDR controller initialization through a backdoor, the initialization time of the DDR controller can be reduced, thereby accelerating the verification speed of other circuit modules on the SoC chip, thus shortening the SoC chip simulation verification convergence cycle and reducing chip R&D design costs.

[0084] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, the terms "front," "back," "left," "right," "upper," and "lower" in this document refer to the placement shown in the accompanying drawings.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DDR model system for SoC chip verification, characterized in that, The DDR model system is used to replace the real DDR controller, DDR physical interface, and SDRAM module in a simulation verification environment, skipping the real DDR controller initialization process, including: Multiple protocol interface modules are available to connect to verified circuit modules on the SoC chip and are used to receive command sequences of different bus interface protocols. Each protocol interface module corresponds to a type of bus interface protocol, and each protocol interface module is responsible for receiving the command sequence of its corresponding bus interface protocol. The initialization data module is connected to multiple protocol interface modules and is configured with registers and backdoor operation interfaces. It is used to store key timing information required for DDR controller initialization, convert command sequences of different bus interface protocols into command sequences that conform to the JEDEC DDR specification, support the direct loading of key timing information required for DDR controller initialization through a backdoor, and can automatically load key timing information into registers after reset. The address mapping module is connected to the initialization data module and the storage module respectively. It is used to map the logical address in the command sequence to the physical address that the storage module can recognize, and write the data corresponding to the logical address into the corresponding position of the storage module. The storage module is used for storing data; The DDR model system is configured through a multi-bit-wide mode selection parameter and compiler macro definitions to select and enable different protocol interface modules; The highest bit of the mode selection parameter is used to select whether to use a DDR model system or a real DDR controller, and the lowest bit of the mode selection parameter is used to further select the enabled protocol interface module when selecting a DDR model system. The DDR model system is configured through a multi-bit-wide mode selection parameter and compiler macro definitions to select and enable different protocol interface modules, including: Determine the value of ddr_model[3]; If the value of ddr_model[3] is 1'b0, then the working mode of the DDR model system is selected as disabled, and the macro definition of the real DDR controller is used to verify the function of the circuit module in the SoC chip using the real DDR controller, and the DDR controller is initialized normally. If the value of ddr_model[3] is 1'b1, then the working mode of the DDR model system is selected as enabled, and the value of ddr_model[2] is further determined; If the value of ddr_model[2] is 1'b0, then the macro definition of the APB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the APB protocol interface module. If the value of ddr_model[2] is 1'b1, then the macro definition of the AHB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AHB protocol interface module; Wherein, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1'b0 represents a 1-bit wide binary number with a value of 0; 1'b1 represents a 1-bit wide binary number with a value of 1.

2. The DDR model system for SoC chip verification according to claim 1, characterized in that, The plurality of protocol interface modules include multiple of the following: CHI protocol interface module, AXI4 protocol interface module, AXI4-Lite protocol interface module, AXI4-Stream protocol interface module, APB protocol interface module, and AHB protocol interface module.

3. The DDR model system for SoC chip verification according to claim 2, characterized in that, The APB protocol interface module can write data to and read data from the initialization data module to verify whether the APB functions of other circuit modules on the SoC chip are correct.

4. The DDR model system for SoC chip verification according to claim 2, characterized in that, The AHB protocol interface module can write data to and read data from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

5. A method of using a DDR model system for SoC chip verification as described in any one of claims 1-4, characterized in that, include: During the simulation compilation phase, the working mode of the DDR model system and the required protocol interface modules are selected by setting multi-bit width mode selection parameters and configuring macro definitions; At the start of the simulation, the key timing information required for DDR controller initialization is directly loaded into the initialization data module through a backdoor, thereby skipping the actual DDR controller initialization process. The DDR model system interacts with the verified circuit module in the SoC chip through the selected protocol interface module to complete the functional verification of the circuit module. The process of selecting the operating mode and required protocol interface module of the DDR model system by setting multi-bit width mode selection parameters and configuring macro definitions includes the following steps: Determine the value of ddr_model[3]; If the value of ddr_model[3] is 1'b0, then the working mode of the DDR model system is selected as disabled, and the macro definition of the real DDR controller is used to verify the function of the circuit module in the SoC chip using the real DDR controller, and the DDR controller is initialized normally. If the value of ddr_model[3] is 1'b1, then the working mode of the DDR model system is selected as enabled, and the value of ddr_model[2] is further determined; If the value of ddr_model[2] is 1'b0, then the macro definition of the APB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the APB protocol interface module. If the value of ddr_model[2] is 1'b1, then the macro definition of the AHB protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AHB protocol interface module; Wherein, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1'b0 represents a 1-bit wide binary number with a value of 0; 1'b1 represents a 1-bit wide binary number with a value of 1.

6. The method of using the DDR model system for SoC chip verification according to claim 5, characterized in that, The process of selecting the operating mode and required protocol interface modules of the DDR model system through the set multi-bit width mode selection parameters and configuration macro definitions also includes the following steps: When the value of ddr_model[3] is 1'b1, further determine the value of ddr_model[1:0]; If the value of ddr_model[1:0] is 2'b00, then the macro definition of the CHI protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the CHI protocol interface module. If the value of ddr_model[1:0] is 2'b01, then the macro definition of the AXI4 protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4 protocol interface module. If the value of ddr_model[1:0] is 2'b10, then the macro definition of the AXI4-Lite protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4-Lite protocol interface module. If the value of ddr_model[1:0] is 2'b11, then the macro definition of the AXI4-Stream protocol interface module is used so that the DDR model system can connect to the verified circuit module in the SoC chip through the AXI4-Stream protocol interface module. Wherein, ddr_model[1:0] indicates that the mode selection parameter includes a bit field of two binary bits from the 1st bit to the 0th bit; 2'b00 represents a 2-bit wide binary number with a value of 00; 2'b01 represents a 2-bit wide binary number with a value of 01; 2'b10 represents a 2-bit wide binary number with a value of 10; 2'b11 represents a 2-bit wide binary number with a value of 11.

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