AXI master device and CHI request node read transfer bridging device and method

Abstract

This invention relates to a read transfer bridging device and method for AXI master devices and CHI request nodes. It enables master devices that do not support cache consistency to interconnect with the CHI bus for read transfers without design modifications, maintaining cache consistency and address allocation throughout the system. The device exhibits excellent compatibility, conforming to the standard AXI4 and CHI protocols. Furthermore, it maintains cache consistency within the system, ensuring data consistency when master devices access shared data and preventing errors caused by outdated or conflicting caches. This read transfer bridging device connects the AXI master device to the CHI bus request node, the central processing unit (CPU) is connected to the CHI bus request node, and external devices and memory are connected to the CHI bus completion node.

Description

Technical Field

[0001] This invention relates to the technical field of chip design, and more particularly to a read transfer bridging device for an AXI master device and a CHI request node, as well as a method for operating such a read transfer bridging device for an AXI master device and a CHI request node. Background Technology

[0002] AMBA (Advanced Microcontroller Bus Architecture) is ARM's bus architecture standard, widely used for communication between ARM processors and other chips. AMBA CHI (Coherent Hub Interface) is part of the AMBA architecture, primarily used to support cache coherency and data sharing in multi-core systems. It is a key interface for efficient data transfer between ARM processors and other components. With the development of multi-core processors, chip design has become more complex, especially when multiple processor cores share data. Maintaining cache coherency has become a critical issue. The CHI protocol was developed for this purpose, providing an efficient way to ensure data consistency between processors in multi-core systems. While the AMBA CHI bus is used in multi-core processor systems, the interface for master and slave devices that do not support cache coherency is still the AMBA AXI4 bus. Connecting these master and slave devices to the CHI bus becomes a key issue in chip design within the system. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a read transmission bridge device for AXI master devices and CHI request nodes, which enables master devices that do not support cache consistency to interconnect with the CHI bus for read transmission without modifying the design, maintains the cache consistency and address allocation of the entire system, has good compatibility, conforms to the standard AXI4 protocol and CHI protocol, and maintains the cache consistency in the system, ensuring data consistency when the master device accesses shared data, and avoiding errors caused by outdated or conflicting caches.

[0004] The technical solution of the present invention is: a read transmission bridge device for an AXI master device and a CHI request node, which connects the AXI master device to the request node of the CHI bus, the central processing unit (CPU) is connected to the request node of the CHI bus, and external devices and memory are connected to the completion node of the CHI bus.

[0005] The read transmission bridging device receives read commands from the AXI master device and converts them into different types of read requests using the CHI protocol. The CHI read requests are sent to the CHI request node in the form of command packets. Each command packet contains a source identifier, destination identifier, transmission identifier, command identifier, weight, transmission size, address, cache attributes, and response attributes. The source identifier is a unique identifier for this device, ensuring its uniqueness throughout the system. The device compares the read address sent by the AXI master device with addresses in the cache status table. If a match is successful, the destination identifier corresponding to the cache line containing that address is obtained. If the match fails, it indicates that the address does not exist in the system, and the AXI read response channel returns an error. The transmission identifier is added sequentially to the transmission command. When the device receives a read command from the AXI master device, the command identifier... A code of 4 indicates a read request that does not require listening and does not change the cache line state. The weight and address are the corresponding weights and addresses in the read command sent by the AXI master device. In the AXI protocol, the total amount of data transmitted is equal to the size of the transmitted data multiplied by the length of the transmitted data. When the total amount of data transmitted is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of data transmitted. When it is greater than 64 bytes, the total amount of data transmitted is divided by 64. If there is a remainder, the quotient is incremented by 1, indicating how many commands are divided into. The transmission size of the last command is the remainder, and the rest are transmitted in 64-byte increments. If there is no remainder, the quotient is the number of commands divided into, and the transmission size of each command is 64 bytes. When the AXI command is a read command, the cache attribute is determined according to the cache state in the cache state table. The command sent by the AXI master device is an AXI protocol request with a response attribute of 0, indicating a request that does not require listening.

[0006] The beneficial technical effects of the present invention are as follows:

[0007] 1. This device complies with the AXI and CHI protocols;

[0008] 2. The device is compatible and can be adapted to the CHI bus without the need for additional functions in existing AXI master devices;

[0009] 3. This device can interconnect and communicate with AXI interface master devices without the need for additional CHI bus functionality;

[0010] 4. This device maintains cache consistency in multi-core processor systems and shares the cache state table in the system, eliminating the need for additional cache states.

[0011] A read transfer bridging method for an AXI master device and a CHI request node is also provided, which includes the following steps:

[0012] (1) Receive a read command initiated by AXI master device 0, which includes the read address, read data size, read transmission length, and read command weight;

[0013] (2) Multiply the read data size and read transmission length in the read command to calculate the total data transmission volume of this read command;

[0014] (3) Based on the read address sent by the AXI master device, traverse and query the address in the address mapping table to determine whether a certain address in the cache status table is hit. If yes, execute step (4); otherwise, execute step (11).

[0015] (4) Obtain the identifier, size and cache status of the cache line where the address is located in the cache status table. The identifier is the destination identifier in the CHI read request, and the transmission identifier is incremented by 1.

[0016] (5) Determine the total data volume of the AXI read command and the size of the corresponding cache line. If the cache status is unique and clean or unique and dirty, then execute step (6); if the cache status is shared and clean, then execute step (7); if the cache status is shared and dirty, or the cache status is invalid, then execute step (9).

[0017] (6) Obtain the cache identifier from the list corresponding to the cache line, and replace the destination identifier in the read request with the cache identifier;

[0018] (7) Replace the destination identifier in the read request with the cache identifier, and combine the source identifier, destination identifier, transmission identifier, command identifier, weight, size, address, cache attribute and response attribute into a read request command packet;

[0019] (8) Send a read request command packet according to the CHI protocol; jump to step (13);

[0020] (9) Read the cache status in the list corresponding to the cache line in a loop, and increment the timeout counter by 1;

[0021] (10) Determine whether the timeout counter value is greater than the set timeout value. If yes, execute step (11); otherwise, execute step (5).

[0022] (11) Read the response channel through AXI, return the error value, and decrement the number of read commands by 1; jump to step (13);

[0023] (12) Calculate the address and the amount of data to be transmitted; jump to step (3);

[0024] (13) Determine if splitting is enabled. If it is 0, execute step (14); if it is 1, execute step (12); convert the size to the number of bytes, add the address and the number of bytes to get the next address, and then traverse and compare the address with the address in the cache status table.

[0025] (14) Transmission ends. Attached Figure Description

[0026] Figure 1 This is a CHI bus system architecture diagram of the read transfer bridging device for the AXI master device and the CHI request node according to the present invention.

[0027] Figure 2 It is a request command packet of the AXI master device and CHI request node read transmission bridging device according to the present invention.

[0028] Figure 3 This is a cached state table of the read transfer bridging device for the AXI master device and the CHI request node according to the present invention.

[0029] Figure 4 This is a flowchart of the read transfer bridging method for the AXI master device and the CHI request node according to the present invention. Detailed Implementation

[0030] AXI (Advanced eXtensible Interface) is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 4.0 protocol proposed by ARM. It is a high-performance, high-bandwidth, low-latency on-chip bus. The AXI protocol separates address / control and data channels, supports unaligned data transmission, and in burst transmissions, only the starting address is needed, with a maximum transmission length of 4KB. The AXI protocol supports separate read / write data channels and supports outstanding and out-of-order access. The AXI high-performance bus system mainly consists of three parts: the master device, the controlled devices, and the infrastructure.

[0031] AMBA CHI (Coherent Hub Interface) is a bus protocol introduced by ARM specifically designed for multi-core processors to ensure data consistency between multiple processor cores. CHI supports cache coherency protocols, guaranteeing data synchronization in the caches of different processor cores and avoiding data conflicts and errors. The CHI bus supports MESI (Modify, Exclusive, Shared, Invalidate) cache coherency protocols, point-to-point and broadcast data transfer modes, and coordinates memory and cache access in complex multi-core systems. The CHI protocol uses a message-passing mechanism, supporting efficient data transfer with low latency and high bandwidth. Its main advantages include efficient data consistency management, optimized memory access paths, and good scalability, making it widely used in high-performance computing, embedded systems, servers, and other fields requiring multi-processor collaboration.

[0032] In multi-core processor systems, when the master device and CHI bus interconnection do not require cache coherency support, a read transfer bridge device for the AXI master device and CHI request node needs to be added. This device has good compatibility, conforms to the standard AXI4 protocol and CHI protocol, and maintains cache coherency in the system, ensuring data consistency when the master device accesses shared data, and avoiding errors caused by outdated or conflicting caches.

[0033] like Figure 1 As shown, this read transfer bridge device for AXI master devices and CHI request nodes connects the AXI master device to the request node of the CHI bus, the central processing unit (CPU) is connected to the request node of the CHI bus, and external devices and memory are connected to the completion node of the CHI bus.

[0034] The read transmission bridge receives read commands from the AXI master device, converts the read commands into different types of read requests in the CHI protocol, and sends the CHI read requests to the CHI request node in the form of command packets, such as... Figure 2As shown, the command packet includes source identifier, destination identifier, transmission identifier, command identifier, weight, transmission size, address, cache attributes, and response attributes. The source identifier is a unique identifier for this device, and this identifier is unique throughout the entire system. The read address sent by the AXI master device is compared one by one with the addresses in the cache status table. When the comparison is successful, the destination identifier corresponding to the cache line where the address in the cache status table is located is obtained. If the comparison fails, it means that the address does not exist in the entire system, and the AXI read response channel replies with an error. The transmission identifier is incremented by the device in the transmission command. When the device receives a read command sent by the AXI master device, the command identifier is 4, indicating that it is a read request that does not need to be monitored and does not change the cache line status. The weight, destination identifier, transmission size, address, cache attributes, and response attributes are all unique identifiers for this device. The address corresponds to the weight and address in the read command sent by the AXI master device. In the AXI protocol, the total amount of data transmitted equals the size of the transmitted data multiplied by the length of the transmitted data. When the total amount of data transmitted is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of data transmitted. When it is greater than 64 bytes, the total amount of data transmitted is divided by 64. If there is a remainder, the quotient is incremented by 1, indicating how many commands are divided into. The transmission amount of the last command is the remainder, and the rest are transmitted in 64-byte increments. If there is no remainder, the quotient is the number of commands divided into, and the transmission amount of each command is 64 bytes. When the AXI command is a read command, the cache attribute is determined according to the cache status in the cache status table. The command sent by the AXI master device is in the AXI protocol, and the response attribute is 0, indicating that no listening is required for the request.

[0035] The beneficial technical effects of the present invention are as follows:

[0036] 1. This device complies with the AXI and CHI protocols;

[0037] 2. The device is compatible and can be adapted to the CHI bus without the need for additional functions in existing AXI master devices;

[0038] 3. This device can interconnect and communicate with AXI interface master devices without the need for additional CHI bus functionality;

[0039] 4. This device maintains cache consistency in multi-core processor systems and shares the cache state table in the system, eliminating the need for additional cache states.

[0040] Preferably, there are two AXI master devices, two read transfer bridge devices, two CPUs, two external devices, and two memory.

[0041] Preferably, the read command issued by the AXI master device includes the read address, read transmission length, read transmission mode, and read command characteristics.

[0042] Preferably, such as Figure 3As shown, the cache status table contains the address, identifier, size, cache status, and cache identifier corresponding to the cache line. This cache status table is a combination of the cache status list and the address mapping table. The identifier represents the identifier corresponding to the address. The size represents the size of the cache in bytes. The cache status is divided into invalid, unique and clean, unique and dirty, shared and clean, and shared and dirty. When the cache status is unique, the cache identifier is the identifier that uniquely stores the cache line. When the cache status is shared, the cache identifier is one of the identifiers that stores the cache line. In the group request command packet, the destination identifier is the identifier corresponding to the address.

[0043] like Figure 4 As shown, a read transfer bridging method between an AXI master device and a CHI request node is also provided, which includes the following steps:

[0044] (1) Receive a read command initiated by AXI master device 0, which includes the read address, read data size, read transmission length, and read command weight;

[0045] (2) Multiply the read data size and read transmission length in the read command to calculate the total data transmission volume of this read command;

[0046] (3) Based on the read address sent by the AXI master device, traverse and query the address in the address mapping table to determine whether a certain address in the cache status table is hit. If yes, execute step (4); otherwise, execute step (11).

[0047] (4) Obtain the identifier, size and cache status of the cache line where the address is located in the cache status table. The identifier is the destination identifier in the CHI read request, and the transmission identifier is incremented by 1.

[0048] (5) Determine the total data volume of the AXI read command and the size of the corresponding cache line. If the cache status is unique and clean or unique and dirty, then execute step (6); if the cache status is shared and clean, then execute step (7); if the cache status is shared and dirty, or the cache status is invalid, then execute step (9).

[0049] (6) Obtain the cache identifier from the list corresponding to the cache line, and replace the destination identifier in the read request with the cache identifier;

[0050] (7) Replace the destination identifier in the read request with the cache identifier, and combine the source identifier, destination identifier, transmission identifier, command identifier, weight, size, address, cache attribute and response attribute into a read request command packet;

[0051] (8) Send a read request command packet according to the CHI protocol; jump to step (13);

[0052] (9) Read the cache status in the list corresponding to the cache line in a loop, and increment the timeout counter by 1;

[0053] (10) Determine whether the timeout counter value is greater than the set timeout value. If yes, execute step (11); otherwise, execute step (5).

[0054] (11) Read the response channel through AXI, return the error value, and decrement the number of read commands by 1; jump to step (13);

[0055] (12) Calculate the address and the amount of data to be transmitted; jump to step (3);

[0056] (13) Determine if splitting is enabled. If it is 0, execute step (14); if it is 1, execute step (12); convert the size to the number of bytes, add the address and the number of bytes to get the next address, and then traverse and compare the address with the address in the cache status table.

[0057] (14) Transmission ends.

[0058] Preferably, between steps (4) and (5), the total data volume of the AXI read command and the size of the corresponding cache line are determined. If the total data volume is greater than the size of the corresponding cache line, it means that the command needs to be split, the split enable is set to 1, and the transmission size is changed to the size of the corresponding cache line, and the transmission data volume is changed to the total data volume minus the size of the corresponding cache line. If the total data volume is less than the cache line, it means that the command does not need to be split, the split enable is set to 0, and the transmission size is the total data volume.

[0059] The present invention will be described in more detail below.

[0060] This invention is a read transfer bridge device for an AXI master device and a CHI request node. The location where this device is interconnected with the CHI bus is as follows: Figure 1 As shown. This device receives read commands from the AXI master device, including the read address, read transfer length, read transfer mode, and read command characteristics, and converts the read commands into different types of read requests in the CHI protocol. CHI read requests are sent to the CHI request node in packet format, as shown in the image. Figure 2As shown, the command packet contains a source identifier, destination identifier, transport identifier, command identifier, weight, transport size, address, cache attributes, and response attributes. The source identifier is a unique identifier for this device, and this identifier is unique throughout the entire system. The read address sent by the AXI master device is compared one by one with the addresses in the cache state table. If a match is successful, the destination identifier corresponding to the cache line containing that address in the cache state table is obtained. If the match fails, it indicates that the address does not exist in the entire system, and the AXI read response channel replies with an error. The transport identifier is added sequentially by the device in the transport command. Since the AXI master device does not have the ability to trigger a system-wide cache consistency intervention request, this device only needs to maintain the cache consistency of the entire system. When this device receives a read command from the AXI master device, the command identifier is 4, indicating that it is a read request that does not need to be monitored, and the cache line state is not changed. The weight and address are the weights and addresses corresponding to the read command sent by the AXI master device. In the AXI protocol, the total amount of data transmitted (in bytes) equals the size of the transmitted data (in bytes) multiplied by the length of the transmitted data. When the total amount of data transmitted is less than or equal to 64 bytes, the size of the request command packet is the actual total amount of data transmitted. When it is greater than 64 bytes, the total amount of data transmitted is divided by 64. If there is a remainder, the quotient is incremented by 1, which indicates how many commands are divided into. The last command's transmission size is the remainder, and the rest are transmitted in 64-byte increments. If there is no remainder, the quotient is the number of commands divided into, and the transmission size for each command is 64 bytes. When the AXI command is a read command, the cache attribute needs to be determined based on the cache status in the cache status table. Since the commands sent by the AXI master device are in the AXI protocol and do not have the ability to modify the listening attribute, the response attribute is 0, indicating that it is a request that does not require listening.

[0061] The cache state table in the entire system, such as Figure 3 As shown, the cache state table contains the address, identifier, size, cache state, and cache identifier corresponding to each cache line. This cache state table is a combination of the cache state list and the address mapping table in the system. The identifier represents the identifier corresponding to the address. The size represents the size of the cache, in bytes. The cache state is divided into invalid, unique and clean, unique and dirty, shared and clean, and shared and dirty. When the cache state is unique, the cache identifier is the identifier unique to the cache line. When the cache state is shared, the cache identifier is one of the identifiers of the cache line. In the group request command packet, the destination identifier can be the identifier corresponding to the address.

[0062] The process by which the device receives a read command from the AXI master device and converts it into a CHI read request is as follows: Figure 4As shown. The device receives a read command initiated by AXI master device 0, which includes the read address, read data size, read transmission length, and read command weight. The read data size and read transmission length in the read command are multiplied to calculate the total data transmission volume of this read command. Based on the read address sent by the AXI master device, the address mapping table is traversed and queried. If the address matches, it indicates a hit; if the entire table does not contain a match, it indicates a miss, meaning that the address does not exist in the entire system. An error is returned through the reply signal in the AXI read reply channel, indicating that the read command is erroneous. When the read address matches an address in the address mapping table, the corresponding identifier, size, and cache status are obtained. The identifier is the destination identifier in the CHI read request, and the transmission identifier is incremented by 1. The total data volume of the AXI read command is compared with the size corresponding to the cache line. If the total data volume is greater than the size corresponding to the cache line, it means that the command needs to be split. The split enable is set to 1, and the transmission size is changed to the size corresponding to the cache line. The transmission data volume is changed to the total data volume minus the size corresponding to the cache line. If the total data volume is less than the cache line, no split command is needed, and the split enable is 0. The transmission size is the total data volume. The cache status is checked. If the cache status is shared and dirty or invalid, the cache status of the corresponding cache line is read in a loop. Each loop increments the timeout counter. When the cache status changes, the process jumps to the corresponding status flow. If the timeout counter value exceeds the system-set timeout value, an error value is returned through the AXI read response channel, and the number of read commands is decremented. If the cache status is unique and clean or unique and dirty, the cache identifier is retrieved from the corresponding cache line list, and the destination identifier in the read request is replaced with the cache identifier. The source identifier, destination identifier, transmission identifier, command identifier, weight, size, address, cache attributes, and response attributes are combined into a read request packet and sent according to the CHI protocol. The split enable is checked. If it is 0, the transmission ends. If it is 1, the size is converted to bytes, the address and the number of bytes are added to obtain the next address, and this address is then compared with the addresses in the cache status table.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A read transmission bridging device for an AXI master device and a CHI request node, characterized in that: It connects the AXI master device to the request node of the CHI bus, the central processing unit (CPU) is connected to the request node of the CHI bus, and external devices and memory are connected to the completion node of the CHI bus. The read transmission bridging device receives read commands from the AXI master device and converts them into different types of read requests using the CHI protocol. The CHI read requests are sent to the CHI request node in the form of command packets. Each command packet contains a source identifier, destination identifier, transmission identifier, command identifier, weight, transmission size, address, cache attributes, and response attributes. The source identifier is a unique identifier for this device, ensuring its uniqueness throughout the system. The device compares the read address sent by the AXI master device with addresses in the cache status table. If a match is successful, the destination identifier corresponding to the cache line containing that address is obtained. If the match fails, it indicates that the address does not exist in the system, and the AXI read response channel returns an error. The transmission identifier is added sequentially to the transmission command. When the device receives a read command from the AXI master device, the command identifier... A code of 4 indicates a read request that does not require listening and does not change the cache line state. The weight and address are the corresponding weights and addresses in the read command sent by the AXI master device. In the AXI protocol, the total amount of data transmitted is equal to the size of the transmitted data multiplied by the length of the transmitted data. When the total amount of data transmitted is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of data transmitted. When it is greater than 64 bytes, the total amount of data transmitted is divided by 64. If there is a remainder, the quotient is incremented by 1, indicating how many commands are divided into. The transmission size of the last command is the remainder, and the rest are transmitted in 64-byte increments. If there is no remainder, the quotient is the number of commands divided into, and the transmission size of each command is 64 bytes. When the AXI command is a read command, the cache attribute is determined according to the cache state in the cache state table. The command sent by the AXI master device is an AXI protocol request with a response attribute of 0, indicating a request that does not require listening.

2. The read transmission bridging device for the AXI master device and the CHI request node according to claim 1, characterized in that: The AXI master device, read transfer bridge, CPU, external devices, and memory are all in pairs.

3. The read transmission bridging device for the AXI master device and the CHI request node according to claim 2, characterized in that: The read command issued by the AXI master device includes the read address, read transmission length, read transmission mode, and read command characteristics.

4. The read transmission bridging device for the AXI master device and the CHI request node according to claim 3, characterized in that: The cache status table contains the address, identifier, size, cache status, and cache identifier corresponding to the cache line. This cache status table is a combination of the cache status list and the address mapping table. The identifier represents the identifier corresponding to the address. The size represents the size of the cache in bytes. The cache status is divided into invalid, unique and clean, unique and dirty, shared and clean, and shared and dirty. When the cache status is unique, the cache identifier is the identifier that uniquely stores the cache line. When the cache status is shared, the cache identifier is one of the identifiers that stores the cache line. In the group request command packet, the destination identifier is the identifier corresponding to the address.

5. A read transfer bridging method between the AXI master device and the CHI request node, characterized in that: It includes the following steps: (1) Receive a read command initiated by AXI master device 0, which includes the read address, read data size, read transmission length, and read command weight; (2) Multiply the read data size and read transmission length in the read command to calculate the total data transmission volume of this read command; (3) Based on the read address sent by the AXI master device, traverse and query the address in the address mapping table to determine whether a certain address in the cache status table is hit. If yes, execute step (4); otherwise, execute step (11). (4) Obtain the identifier, size and cache status of the cache line where the address is located in the cache status table. The identifier is the destination identifier in the CHI read request, and the transmission identifier is incremented by 1. (5) Determine the total data volume of the AXI read command and the size of the corresponding cache line. If the cache status is unique and clean or unique and dirty, then execute step (6); if the cache status is shared and clean, then execute step (7); if the cache status is shared and dirty, or the cache status is invalid, then execute step (9). (6) Obtain the cache identifier from the list corresponding to the cache line, and replace the destination identifier in the read request with the cache identifier; (7) Replace the destination identifier in the read request with the cache identifier, and combine the source identifier, destination identifier, transmission identifier, command identifier, weight, size, address, cache attribute and response attribute into a read request command packet; (8) Send a read request command packet according to the CHI protocol; jump to step (13); (9) Read the cache status in the list corresponding to the cache line in a loop, and increment the timeout counter by 1; (10) Determine whether the timeout counter value is greater than the set timeout value. If yes, execute step (11); otherwise, execute step (5). (11) Read the response channel through AXI, return the error value, and decrement the number of read commands by 1; jump to step (13); (12) Calculate the address and the amount of data to be transmitted; jump to step (3); (13) Determine if splitting is enabled. If it is 0, execute step (14); if it is 1, execute step (12); convert the size to the number of bytes, add the address and the number of bytes to get the next address, and then traverse and compare the address with the address in the cache status table. (14) Transmission ends.

6. The read transmission bridging method for the AXI master device and the CHI request node according to claim 5, characterized in that: Between steps (4) and (5), the total data volume of the AXI read command and the size of the corresponding cache line are determined. If the total data volume is greater than the size of the corresponding cache line, it means that the command needs to be split, the split enable is set to 1, and the transmission size is changed to the size of the corresponding cache line. The transmission data volume is changed to the total data volume minus the size of the corresponding cache line. If the total data volume is less than the cache line, it means that the command does not need to be split, the split enable is set to 0, and the transmission size is the total data volume.

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