Server, signal transmission method, electronic device, and storage medium

Abstract

The embodiment of the present disclosure provides a kind of server, signal transmission method, electronic equipment and storage medium, it is related to server technical field, the system includes: first chip, the first end of first chip includes first chip select pin, first clock pin, first master-slave input / output pin and first master-slave output / input pin;Second chip, second chip includes second chip select pin, second clock pin, second master-slave output / input pin and second master-slave input / output pin, first chip select pin is electrically connected with second chip select pin, first clock pin is electrically connected with second clock pin, first master-slave input / output pin is electrically connected with second master-slave output / input pin, first master-slave output / input pin is electrically connected with second master-slave input / output pin;Universal substrate UBB, UBB is electrically connected with the second end of first chip.Such, the fast communication connection of second chip and UBB is realized, and then the out-of-band management function of component in UBB by second chip can be conveniently realized.

Description

Technical Field

[0001] This disclosure relates to the field of server technology, and in particular to a server, a signal transmission method, an electronic device, and a storage medium. Background Technology

[0002] Currently, Universal Baseboards (UBBs) typically use the Universal Serial Bus (USB) protocol as one of their out-of-band management communication standards. However, because some dedicated chips are not designed with an integrated USB controller that can act as a master device, these chips cannot establish a fast communication connection with the UBB board, thus preventing them from monitoring and managing the components on the UBB board. Summary of the Invention

[0003] This disclosure provides a server, a signal transmission method, an electronic device, and a storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0004] In a first aspect, embodiments of this disclosure provide a server, the server comprising:

[0005] The first chip, the first terminal of the first chip includes a first chip select pin, a first clock pin, a first master input-slave output pin and a first master output-slave input pin;

[0006] The second chip includes a second chip select pin, a second clock pin, a second master output slave input pin, and a second master input slave output pin. The first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master input slave output pin is electrically connected to the second master output slave input pin, and the first master output slave input pin is electrically connected to the second master input slave output pin.

[0007] A universal substrate UBB is electrically connected to the second terminal of the first chip; the first terminal and the second terminal of the first chip are different types of ports.

[0008] The first chip receives a first type signal transmitted by the first object through one end of the first chip, converts the first type signal into a second type signal, and transmits the second type signal to the second object through the other end of the first chip;

[0009] Wherein, if the first object includes the second chip and the second object includes UBB, one end of the first chip is the first end and the other end of the first chip is the second end; or, if the first object includes UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end.

[0010] Secondly, embodiments of this disclosure provide a signal transmission method applied to a server, the method comprising:

[0011] The first type of signal transmitted by the first object is obtained through one end of the first chip;

[0012] The first type of signal is converted into the second type of signal using the first chip;

[0013] The second type of signal is transmitted to the second object through the other end of the first chip;

[0014] The server includes a first object and a second object; when the first object includes a second chip and the second object includes a universal substrate UBB, one end of the first chip is the first end and the other end of the first chip is the second end; or, when the first object includes a UBB and the second object includes a second chip, one end of the first chip is the second end and the other end of the first chip is the first end.

[0015] The first chip has a first chip select pin, a first clock pin, a first master input / slave output pin, and a first master output / slave input pin. The second chip has a second chip select pin, a second clock pin, a second master output / slave input pin, and a second master input / slave output pin. The first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master input / slave output pin is electrically connected to the second master output / slave input pin, and the first master output / slave input pin is electrically connected to the second master input / slave output pin. UBB is electrically connected to the second terminal of the first chip. The first terminal and the second terminal of the first chip are terminals of different types.

[0016] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the signal transmission methods.

[0017] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the signal transmission methods.

[0018] Based on the server provided in this disclosure, a first chip, a second chip, and a UBB can be configured in the server. The first chip may include a first chip select pin, a first clock pin, a first master-in-slave-out pin, and a first master-out-slave-in pin at its first terminal. The second chip may include a second chip select pin, a second clock pin, a second master-out-slave-in pin, and a second master-in-slave-out pin. The first chip select pin and the second chip select pin are electrically connected, the first clock pin and the second clock pin are electrically connected, the first master-in-slave-out pin and the second master-out-slave-in pin are electrically connected, and the first master-out-slave-in pin and the second master-in-slave-out pin are electrically connected. The UBB is electrically connected to the second terminal of the first chip. Thus, the first chip can convert a first type of signal supported by the first object into a second type of signal supported by the second object, thereby achieving a communication connection between the first object and the second object. This also enables a fast communication connection between the second chip and the UBB, avoiding the situation in the prior art where the chip cannot establish a fast communication connection with the UBB because it does not integrate a USB controller that can act as a master device. This allows the second chip to conveniently perform out-of-band management of the components in the UBB.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a server in a related art provided by an embodiment of this disclosure;

[0021] Figure 2 This is one of the structural schematic diagrams of a server provided in the embodiments of this disclosure;

[0022] Figure 3 This is a second schematic diagram of the structure of a server provided in this embodiment of the disclosure;

[0023] Figure 4 This is the third schematic diagram of a server structure provided in this embodiment of the disclosure;

[0024] Figure 5 This is a schematic flowchart of a signal transmission method provided in an embodiment of this disclosure;

[0025] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0030] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0031] As described in the background section, general-purpose boards typically use the USB protocol as one of their out-of-band management communication standards. However, because some dedicated chips are not designed to integrate a USB controller that can act as a host device, these dedicated chips cannot establish a communication connection with UBB.

[0032] Based on this, in order to solve the problem that some dedicated chips cannot establish a communication connection with UBB, such as Figure 1 As shown, chip 11 may include an Inter-Integrated Circuit (I2C) interface, and the Baseboard Management Controller (BMC) 121 in UBB 12 may also include an I2C interface. Thus, chip 11 can communicate with BMC 121 in UBB 12 via I2C to achieve out-of-band management functions for the UBB. It should be noted that, based on... Figure 1 As shown in the structure, BMC121 can be used as a slave device. BMC121 first communicates with modules such as Retimer, OAM, FRU, and I2C EXP IO in UBB12 via I2C. Chip 11 then communicates with BMC121 in UBB12 via I2C to obtain device information such as temperature and manufacturer / device ID from the Retimer and OAM devices in UBB12. However, since I2C is a high-speed communication mode, the communication speed is generally 100kHz. Therefore, obtaining OAM and Retimer card information and upgrading the UBB board BMC FW from BMC121 in UBB12 via I2C is relatively slow, preventing the chip from establishing a fast communication connection with the UBB board.

[0033] To address the shortcomings of existing technologies where chips cannot establish rapid communication connections with UBB boards, this disclosure provides a server, signal transmission method, electronic device, and storage medium that can solve the aforementioned problems. Specifically, the server can be configured with a first chip, a second chip, and a UBB. The first chip may include a first chip select pin, a first clock pin, a first master-in-slave-out pin, and a first master-out-slave-in pin at its first terminal. The second chip may include a second chip select pin, a second clock pin, a second master-out-slave-in pin, and a second master-in-slave-out pin. The first chip select pin and the second chip select pin are electrically connected, the first clock pin and the second clock pin are electrically connected, the first master-in-slave-out pin and the second master-out-slave-in pin are electrically connected, and the first master-out-slave-in pin and the second master-in-slave-out pin are electrically connected. The UBB is electrically connected to the second terminal of the first chip. In this way, the first chip can realize the communication connection between the first object and the second object by converting the first type of signal supported by the first object into the second type of signal supported by the second object. That is, it realizes the fast communication connection between the second chip and UBB, avoiding the situation in the prior art where the chip cannot establish a fast communication connection with UBB because the chip does not integrate a USB controller that can be used as a host device. Thus, it can conveniently realize the out-of-band management function of the second chip for the components in UBB.

[0034] The server provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and specific examples.

[0035] Figure 2 This is one of the structural diagrams of a server provided in the embodiments of this disclosure.

[0036] like Figure 2 As shown in the embodiments of this disclosure, a server is provided, which may include the following parts:

[0037] The first chip 21 has a first terminal including a first chip select pin SCS, a first clock pin SCK, a first master input-slave output pin SDI, and a first master output-slave input pin SDO.

[0038] The second chip 22 includes a second chip select pin CS, a second clock pin CLK, a second master-output-slave-in pin MOSI, and a second master-output-slave-out pin MISO. Specifically, the first chip select pin SCS is electrically connected to the second chip select pin CS; the first clock pin SCK is electrically connected to the second clock pin CLK; the first master-output-slave-out pin SDI is electrically connected to the second master-output-slave-in pin MOSI; and the first master-output-slave-in pin SDO is electrically connected to the second master-output-slave-out pin MISO.

[0039] The universal substrate UBB23 is electrically connected to the second terminal of the first chip 21; the first terminal and the second terminal of the first chip 21 are different types of ports.

[0040] Here, since the first end and the second end of the first chip 21 can be different types of ports, the first end and the second end of the first chip 21 can be used to transmit different types of signals, without any specific limitation.

[0041] Additionally, in some embodiments, the second chip 22 described above does not integrate a Universal Serial Bus (USB) host controller.

[0042] Based on the structure of the server described above, the first chip 21 receives a first type signal transmitted by the first object through one end of the first chip 21, converts the first type signal into a second type signal, and transmits the second type signal to the second object through the other end of the first chip 21.

[0043] In some embodiments, when the first object includes the second chip 22 and the second object includes UBB23, one end of the first chip 21 is the first end and the other end of the first chip 21 is the second end; or, when the first object includes UBB23 and the second object includes the second chip 22, one end of the first chip 21 is the second end and the other end of the first chip 21 is the first end, without specific limitations here.

[0044] It should also be noted that the first type of signal and the second type of signal mentioned above can be different types of signals. The specific type of the first type of signal and the second type of signal can be determined according to the specific transmission object, and no further restrictions are imposed here.

[0045] It is conceivable that during the process of the second chip 22 transmitting signals to the UBB23 through the first chip 21, the first chip 21 can receive the first type of signal transmitted by the second chip 22 through the first end of the first chip 21, the first chip 21 can convert the first type of signal into a second type of signal, and can transmit the second type of signal to the UBB23 through the second end of the first chip 21.

[0046] Similarly, during the process of UBB23 transmitting signals to the second chip 22 through the first chip 21, the first chip 21 can receive the first type signal transmitted by UBB23 through the second terminal of the first chip 21, convert the first type signal into a second type signal, and transmit the second type signal to the second chip 22 through the second terminal of the first chip 21.

[0047] Based on the server provided in this disclosure, a first chip, a second chip, and a UBB can be configured in the server. The first chip may include a first chip select pin, a first clock pin, a first master-in-slave-out pin, and a first master-out-slave-in pin at its first terminal. The second chip may include a second chip select pin, a second clock pin, a second master-out-slave-in pin, and a second master-in-slave-out pin. The first chip select pin and the second chip select pin are electrically connected, the first clock pin and the second clock pin are electrically connected, the first master-in-slave-out pin and the second master-out-slave-in pin are electrically connected, and the first master-out-slave-in pin and the second master-in-slave-out pin are electrically connected. The UBB is electrically connected to the second terminal of the first chip. Thus, the first chip can convert a first type of signal supported by the first object into a second type of signal supported by the second object, thereby achieving a communication connection between the first object and the second object. This also enables a fast communication connection between the second chip and the UBB, avoiding the situation in the prior art where the chip cannot establish a fast communication connection with the UBB because it does not integrate a USB controller that can act as a master device. This allows the second chip to conveniently perform out-of-band management of the components in the UBB.

[0048] Since the first type signal and the second type signal are different types of signals in the embodiments of this disclosure, in order to describe the server provided in the embodiments of this disclosure in more detail, in some embodiments, when the first object includes the second chip 22 and the second object includes UBB23, the first type signal may include a Serial Peripheral Interface (SPI) signal and the second type signal may include a Universal Serial Bus (USB) signal.

[0049] When the first object includes UBB23 and the second object includes the second chip 22, the first type of signal may include a USB signal and the second type of signal may include an SPI signal.

[0050] For example, assuming the second chip involved in this embodiment is a ZX1000 chip and the first chip is a CH374F chip, if the first object is a ZX1000 chip and the second object is a UBB, then the first type of signal transmitted between the first object and the first chip can be a Serial Peripheral Interface (SPI) signal, and the second type of signal transmitted between the first chip and the second object is a Universal Serial Bus (USB) signal. If the first object is a UBB and the second object is a ZX1000 chip, then the first type of signal transmitted between the first object and the first chip can be a USB signal, and the second type of signal transmitted between the first chip and the second object can be an SPI signal.

[0051] In this embodiment, communication between the second chip and UBB can be achieved by converting between SPI signals and USB signals. Compared with the existing technology that uses I2C for communication, this improves the communication speed between the second chip and UBB and enables a fast communication connection between the second chip and UBB.

[0052] To better achieve a fast communication connection between the second chip and UBB, and to ensure the stability and integrity of signal transmission between them, in some embodiments, such as... Figure 3 As shown, the server may also include multiple first resistors 31.

[0053] Based on this, the first chip select pin SCS and the second chip select pin CS are electrically connected through the first resistor 31; the first clock pin SCK and the second clock pin CLK are electrically connected through the first resistor 31; the first master input slave output pin SDI and the second master output slave input pin MOSI are electrically connected through the first resistor 31; and the first master output slave input pin SDO and the second master input slave output pin MISO are electrically connected through the first resistor 31.

[0054] Each of the first resistors 31 mentioned above can be a resistor with a resistance of 33 ohms, and no specific limitation is made here.

[0055] It can be imagined that since the first chip 21 has a first chip select pin SCS, a first clock pin SCK, a first master input slave output pin SDI and a first master output slave input pin SDO, the second chip 22 has a second chip select pin CS, a second clock pin CLK, a second master output slave input pin MOSI and a second master input slave output pin MISO. Thus, the first chip select pin SCS and the second chip select pin CS are electrically connected through the first resistor 31, which is used for impedance matching of the line formed by the first chip select pin SCS and the second chip select pin CS; the first clock pin SCK and the second clock pin CLK are electrically connected through the first resistor 31, which is used for impedance matching of the line formed by the first clock pin SCK and the second clock pin CLK; the first master input slave output pin SDI and the second master output slave input pin MOSI are electrically connected through the first resistor 31, which is used for impedance matching of the line formed by the first master input slave output pin SDI and the second master output slave input pin MOSI; the first master output slave input pin SDO and the second master input slave output pin MISO are electrically connected through the first resistor 31, which is used for impedance matching of the line formed by the first master output slave input pin SDO and the second master input slave output pin MISO.

[0056] In this way, impedance matching can be achieved by setting a resistor in series between a pin on the first end of the first chip and a pin on the second chip, thereby ensuring that the energy of the transmitted signal can be absorbed to the maximum extent during the transmission process from the source end to the load end, avoiding the transmission signal being reflected, and thus ensuring the integrity and stability of the transmitted signal during the transmission process.

[0057] Additionally, in some embodiments, such as Figure 3 As shown, the server provided in this embodiment may further include a power network P3V3_STBY and a plurality of second resistors 32.

[0058] Thus, the first chip select pin SCS is electrically connected to the power network P3V3_STBY through the second resistor 32, and the second chip select pin CS is electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0059] The first clock pin SCK is electrically connected to the power network P3V3_STBY through the second resistor 32, and the second clock pin CLK is electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0060] The first master input / slave output pin SDI is electrically connected to the power network P3V3_STBY through the second resistor 32, and the second master output / slave input pin MOSI is electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0061] The first master input / output pin SDO is electrically connected to the power network P3V3_STBY through the second resistor 32, and the second master input / output pin MISO is electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0062] Here, the second resistor 32 mentioned above can be a resistor with a resistance of 2.2kΩ, and no specific limitation is made here.

[0063] It is conceivable that, based on the first chip 21 having a first chip select pin SCS, a first clock pin SCK, a first master-in-slave-out pin SDI, and a first master-out-slave-in pin SDO, and the second chip 22 having a second chip select pin CS, a second clock pin CLK, a second master-out-slave-in pin MOSI, and a second master-in-slave-out pin MISO, it is possible to configure the first chip select pin SCS to be electrically connected to the power network P3V3_STBY through the second resistor 32, and the second chip select pin CS to be electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32; then, the first clock pin SCK to be electrically connected to the power network P3V3_STBY through the first resistor 31 and the second resistor 32; TBY is electrically connected via the second resistor 32, and the second clock pin CLK is electrically connected to the power network P3V3_STBY via the first resistor 31 and the second resistor 32; the first master-in-slave-out pin SDI is electrically connected to the power network P3V3_STBY via the second resistor 32, and the second master-out-slave-in pin MOSI is electrically connected to the power network P3V3_STBY via the first resistor 31 and the second resistor 32; alternatively, the first master-out-slave-in pin SDO can be electrically connected to the power network P3V3_STBY via the second resistor 32, and the second master-in-slave-out pin MISO can be electrically connected to the power network P3V3_STBY via the first resistor 31 and the second resistor 32.

[0064] In this embodiment, by setting a second resistor on each line connected to the first terminal of the first chip and the second chip, the corresponding line can be pulled up to the power network, ensuring that each line is in a certain and stable high-level state when idle or initialized. This can prevent miscommunication caused by uncertain pin states and realize accurate and fast communication between the second chip and the first chip.

[0065] In order to provide a comprehensive and detailed description of the server provided in the embodiments of this disclosure, in some embodiments, such as Figure 3 As shown, the server provided in this embodiment may further include:

[0066] Choke 33, the first end of choke 33 is electrically connected to the second end of the first chip 21, and the second end of choke 33 is electrically connected to UBB23;

[0067] The choke 33 is used to filter common-mode noise in the transmitted signal between the first chip 21 and UBB23.

[0068] It is conceivable that by setting a choke coil 33 in the server, and electrically connecting the first end of the choke coil 33 to the second end of the first chip 21, and electrically connecting the second end of the choke coil 33 to UBB23, the choke coil 33 can acquire the transmission signal between the first chip 21 and UBB23, and filter the common-mode noise in the transmission signal.

[0069] In this embodiment, by setting a choke in the server and electrically connecting the first end of the choke to the second end of the first chip, and electrically connecting the second end of the choke to a general-purpose substrate, the common-mode noise of the transmitted signal between the first chip and the general-purpose substrate can be filtered by the choke, thereby effectively reducing common-mode interference.

[0070] In addition, in some embodiments, the following continues... Figure 3 As shown, the first chip 21 may further include an interrupt pin INT, and the second chip 22 may further include a general-purpose input / output pin GPIO. Here, the interrupt pin INT of the first chip 21 is electrically connected to the general-purpose input / output pin GPIO of the second chip 22.

[0071] Based on this, when the first chip 21 detects an interrupt event, it transmits an interrupt request signal to the general purpose input / output pin GPIO of the second chip 22 through the interrupt pin INT of the first chip 21.

[0072] Interruption events can be related events that require pausing the current task and switching to handling specific events in response to external or internal signals.

[0073] In addition, since the interrupt pin INT of the first chip 21 and the general-purpose input / output pin GPIO of the second chip 22 are active low in this embodiment, the interrupt request signal can include a low-level signal, which is not specifically limited here.

[0074] It is conceivable that when the first chip 21 detects an interrupt event, it can transmit an interrupt request signal to the general-purpose input / output pin GPIO set in the second chip 22 through the interrupt pin INT set in the first chip 21, so as to request the second chip 22 to suspend the current service and prioritize the interrupt event.

[0075] Additionally, it should be noted that, as Figure 3 As shown, the server provided in this embodiment may also include a third resistor 34 and a power network P3V3_STBY. Here, the third resistor 34 can be a resistor with a resistance of 33 ohms, and is not specifically limited to this.

[0076] Thus, the third resistor 34 can be connected in series between the power network P3V3_STBY and the interrupt pin INT of the first chip 21, and in series between the power network P3V3_STBY and the general purpose input / output pin GPIO of the second chip 22.

[0077] It should also be noted that the interrupt pin INT of the first chip 21 can be left unconnected, but the read operation needs to be performed by polling the interrupt flag register, which is a slower method.

[0078] In this embodiment, by setting an interrupt pin in the first chip and a general-purpose input / output pin in the second chip, and setting the interrupt pin to be electrically connected to the general-purpose input / output pin, when the first chip detects a relatively urgent interrupt event such as a device failure, a low-level signal can be transmitted through the interrupt pin of the first chip and the general-purpose input / output of the second chip, so that the interrupt event can be processed in a timely manner, effectively reducing the idle waiting time of the interrupt event.

[0079] In order to accurately and comprehensively describe the server provided in the embodiments of this disclosure, in some embodiments, such as Figure 3 As shown, the first chip 21 may also include a status indicator pin ACT; the status indicator pin ACT of the first chip is electrically connected to the light-emitting element 35.

[0080] Here, the status indicator pin ACT of the first chip 21 can determine the operating status of the first chip 21 through the status of the external light-emitting element 35. The light-emitting element 35 can be a light-emitting diode, and no specific limitation is made here.

[0081] Based on this, when the first chip 21 outputs the first activity signal through the control state indicator pin ACT, the light-emitting element 35 is turned on and illuminates.

[0082] The first activity signal mentioned above can be a low-level signal, and no specific limitation is made here.

[0083] It can be imagined that when the control state indicator pin ACT of the first chip 21 outputs a low-level signal, the light-emitting element 35 can be turned on and illuminated, and at this time the working state of the first chip 21 is the normal working state.

[0084] In addition, in some embodiments, the light-emitting element 35 is turned off when the first chip 21 controls the state indication pin ACT to output a second activity signal.

[0085] The second activity signal mentioned above can be a high-level signal, and no specific limitation is made here.

[0086] It can be imagined that when the control state indicator pin ACT of the first chip 21 outputs a high-level signal, the light-emitting element 35 can be turned off and extinguished. At this time, the working state of the first chip 21 is an abnormal working state.

[0087] In this embodiment, a light-emitting element can be connected to the status indicator pin of the first chip, and the working status of the first chip can be directly determined by the light-emitting or off state of the light-emitting element, so as to facilitate timely detection of abnormalities of the first chip.

[0088] In some embodiments, the first chip 21 may integrate a first hub, which may include multiple ports that together constitute a second terminal of the first chip 21. Thus, when the first chip 21 is used as a USB controller for a host device, multiple USB devices can be connected.

[0089] In this embodiment, by setting a hub in the content of the first chip, the first chip can connect to multiple devices, thereby significantly improving the device access capability of the first chip.

[0090] In order to provide a complete and detailed description of the server provided in the embodiments of this disclosure, in some embodiments, such as Figure 4 As shown, the above-mentioned UBB23 may include:

[0091] The second hub 41 has its first end electrically connected to the second end of the first chip 21;

[0092] The baseboard management controller BMC42 is electrically connected to the second terminal of the second hub 41.

[0093] Based on this, when the first object includes UBB23 and the second object includes the second chip 22, the device information is obtained through BMC42 and transmitted to the first chip 21 via the second hub 41 through BMC42 in the form of a first type signal.

[0094] The aforementioned device information may include UBB-related information, such as sensor information including temperature information, without being specifically limited here.

[0095] It is conceivable that by setting a second hub 41 and a BMC 42 in UBB23, and by setting the first end of the second hub 41 to be electrically connected to the second end of the first chip 21, and the BMC 42 to be electrically connected to the second end of the second hub 41, device information can be obtained through the BMC 42 during the data transmission from UBB23 to the second chip 22, and the device information can be transmitted to the first chip 21 through the second hub 41 via the BMC 42 in the form of a first type signal.

[0096] In this embodiment, by setting a second hub and a BMC in the UBB, and setting the first end of the second hub to be electrically connected to the second end of the first chip, and the first end of the second hub of the BMC to be connected to the first chip, the UBB can transmit device information obtained by the BMC through the first chip, which facilitates the monitoring and management of components on the UBB board by the second chip.

[0097] It should be noted that, in this embodiment of the disclosure, UBB can not only transmit device information from the first chip to the second chip, but also transmit fault monitoring information from the first chip to the first device. Based on this, in order to comprehensively and thoroughly describe the signal transmission method provided in this embodiment of the disclosure, in one embodiment of the disclosure, the following continues... Figure 4 As shown, the UBB23 involved in this embodiment may further include:

[0098] Multiplexer 43, the first terminal of multiplexer 43 is electrically connected to the second terminal of second hub 41;

[0099] Conversion component 44, the first terminal of conversion component 44 is electrically connected to the second terminal of multiplexer 43;

[0100] Based on this, when the first object includes UBB23 and the second object includes the second chip 22, fault monitoring information is obtained through the conversion component 44 and transmitted to the first chip 21 in the form of a first type signal via the conversion component 44, multiplexer 43, and second hub 41.

[0101] It is conceivable that by setting a multiplexer 43 and a conversion component 44 in UBB23, and electrically connecting the first terminal of the multiplexer 43 to the second terminal of the second hub 41, and electrically connecting the first terminal of the conversion component 44 to the second terminal of the multiplexer 43, fault monitoring information can be obtained through the conversion component 44 during the transmission of signals from the first chip 21 to the second chip 22 by UBB23. This fault monitoring information can then be transmitted to the first chip 21 in the form of a first type signal via the multiplexer 43 and the second hub 41 through the conversion component 44.

[0102] It should be noted that the aforementioned fault monitoring information can be obtained by the conversion component 44 from the OAM component connected to it; for details, please refer to [link to relevant documentation]. Figure 4 Each conversion component 44 is connected to an OAM component, which will not be described in detail here.

[0103] In this embodiment, the UBB provided by this disclosure may include a multiplexer and a conversion component, with the first terminal of the multiplexer electrically connected to the second terminal of the second hub, and the first terminal of the conversion component electrically connected to the second terminal of the multiplexer. Thus, the circuitry constructed between the first chip, the second hub, the multiplexer, and the conversion component enables the second chip to monitor the UBB for faults, facilitating timely management of the UBB by the second chip.

[0104] Based on any of the foregoing servers, embodiments of this disclosure also provide a signal transmission method, which can be specifically as follows: Figure 5 As shown, the execution subject of this method can be any of the aforementioned servers, and the method may specifically include the following steps:

[0105] S510 acquires a first type of signal transmitted by a first object through one end of the first chip.

[0106] The S520 converts a first-type signal into a second-type signal using a first chip.

[0107] S530 transmits a second type of signal to a second object through the other end of the first chip.

[0108] The server may include the first object, the second object, and the first chip.

[0109] In some embodiments, if the first object is a second chip, and the second object may include a UBB, then one end of the first chip may be a first end, and correspondingly, the other end of the first chip may be a second end. If the first object may include a UBB and the second object may include a second chip, then one end of the first chip is a second end, and correspondingly, the other end of the first chip is a first end.

[0110] It should be noted here that the first terminal of the first chip may include a first chip select pin, a first clock pin, a first master-slave input pin, and a first master-slave output pin. The second chip includes a second chip select pin, a second clock pin, a second master-slave output pin, and a second master-slave input pin. The first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master-slave input pin is electrically connected to the second master-slave output pin, and the first master-slave output pin is electrically connected to the second master-slave input pin. UBB is electrically connected to the second terminal of the first chip. The first terminal and the second terminal of the first chip are ports of different types.

[0111] Furthermore, the aforementioned first-type signal and second-type signal can be signals of different types. For example, assuming the second chip involved in this embodiment is a ZX1000 chip and the first chip is a CH374F chip, if the first object includes the second chip and the second object includes a UBB, the first-type signal can be an SPI signal and the second-type signal can be a USB signal. Correspondingly, if the first object includes a UBB and the second object includes the second chip, the first-type signal can be a USB signal and the second-type signal can be an SPI signal.

[0112] Specifically, during the process of the second chip transmitting signals to UBB through the first chip, the first chip can receive the first type of signal transmitted by the second chip through the first terminal of the first chip, convert the first type of signal into a second type of signal, and transmit the second type of signal to UBB through the second terminal of the first chip.

[0113] Similarly, during the process of UBB transmitting signals from the first chip to the second chip, the first chip can receive the first type of signal transmitted by UBB through the second terminal of the first chip. The first chip can convert the first type of signal into a second type of signal and transmit the second type of signal to the second chip through the second terminal of the first chip.

[0114] Based on the signal transmission method provided in this disclosure, whether the second chip transmits signals to the UBB through the first chip or the UBB transmits signals to the second chip through the first chip, the first chip can convert different types of signals to achieve a fast communication connection between the second chip and the UBB. This avoids the situation in the prior art where the chip cannot establish a fast communication connection with the UBB because it does not integrate a USB controller that can act as a host device. In this way, the out-of-band management function of the second chip on the components in the UBB can be conveniently realized.

[0115] In order to describe the signal transmission method provided by the embodiments of this disclosure in detail, in one embodiment of the embodiments of this disclosure, the signal transmission method provided by the embodiments of this disclosure may further include the following steps:

[0116] The second chip sends the address code and command code to the first chip.

[0117] The address code can be used to indicate the starting address of the operation performed by the second chip, and the command code can be used to indicate the operation performed by the second chip. The operation performed by the second chip can include a read operation or a write operation.

[0118] It is conceivable that, whether the second chip transmits signals to the UBB through the first chip, or the UBB transmits signals to the second chip through the first chip, it is necessary for the second chip to send address codes and command codes to the first chip to instruct the first chip on the execution operation of the second chip and the starting address of the execution operation of the second chip, thereby realizing a fast communication connection between the second chip and the UBB.

[0119] Therefore, if the operation performed by the second chip includes a write operation, the first object may include the second chip. Specifically, S410 may include the following steps:

[0120] The data to be written is transmitted from the second chip to the first chip.

[0121] The first chip receives the data to be written transmitted by the second chip and stores the data to be written to the first storage address.

[0122] The first type of signal mentioned above may include data to be written, and the first storage address may be determined based on the starting address of the operation performed by the second chip.

[0123] Specifically, if the second chip performs a write operation, it indicates that the transmission direction is for the second chip to transmit data to the general-purpose substrate via the first chip, and the first object is the second chip. Based on this, it is possible to transmit data to be written to the first chip via the second chip, receive the data to be written transmitted by the second chip via the first chip, and store the data to be written to the first memory address via the first chip.

[0124] Accordingly, if the operation performed by the second chip is a read operation, the second object may include the second chip. Specifically, S430 may include the following steps:

[0125] The data to be read is read from the second storage address using the first chip;

[0126] The data to be read is transmitted from the first chip to the second chip.

[0127] The second type of signal may include the data to be read.

[0128] Specifically, if the second chip performs a read operation, the transmission direction is from UBB through the first chip to the second chip; that is, the second object can include the second chip. Thus, the general-purpose server can read data from the second storage address through the first chip and transmit that data to the second chip through the first chip.

[0129] In one example, the second chip can issue a one-byte address code according to a preset method to specify the starting address of the read / write operation of the second chip. This preset method is associated with the signal type output by the second chip. If the transmission signal output by the second chip is an SPI signal, then the preset method can be SPI output mode, which will not be elaborated further here. Next, the second chip can issue a one-byte command code to indicate the operation to be performed. If the operation is a read operation, the corresponding command code can be COH; if the first operation is a write operation, the corresponding command code can be 80H.

[0130] Therefore, if the second chip performs a write operation, it can send out one byte of data to be written. The first chip can receive this data and save it to a specified address (determined based on the starting address of the second chip's read / write operation). Subsequent addresses can be automatically incremented by 1. When the second chip continues to send out several bytes of data to be written, the first chip can process them sequentially until the second chip disables chip select, thus ending the current write operation.

[0131] If the second chip performs a read operation, the first chip can read one byte of data from a specified address and output it to the second chip, after which the address can be automatically incremented by 1. The second chip can then receive and save this data. The first chip can then continue reading data from the next address and outputting it to the second chip until the second chip disables chip select, thus ending the current read operation.

[0132] In this embodiment, the second chip can send an address code and a command code to the first chip to instruct the first chip on the execution operation of the second chip and the starting address of the execution operation of the second chip. In this way, the communication connection between the second chip and the first chip can be effectively realized according to the execution operation of the second chip indicated by the command code and the starting address of the execution operation of the second chip indicated by the address code, thereby effectively realizing a fast communication connection between the second chip and UBB.

[0133] In order to describe the signal transmission method provided by the embodiments of this disclosure in detail, in one embodiment of this disclosure, the signal transmission method provided by the embodiments of this disclosure may specifically include the following steps:

[0134] When the first chip detects an interrupt event, it transmits an interrupt request signal to the general-purpose input / output pin of the second chip through the interrupt pin of the first chip.

[0135] Interrupt events can be related events that require pausing the current task and switching to processing a specific event in response to external or internal signals. Additionally, an interrupt request signal can be a low-level signal used to request a second chip to prioritize processing the interrupt event.

[0136] Thus, when the first chip detects an interrupt event, the server can transmit an interrupt request signal to the general-purpose input / output pin of the second chip through the interrupt pin of the first chip, in order to request the second chip to suspend the current service and prioritize the interrupt event.

[0137] In this embodiment, when the first chip in the server detects a relatively urgent interruption event, such as a device failure, it can transmit a low-level signal through the interrupt pin of the first chip to the general-purpose input / output of the second chip, so as to process the interruption event in a timely manner and effectively reduce the idle waiting time of the interruption event.

[0138] In addition, in one embodiment of this disclosure, the signal transmission method provided by this embodiment may further include the following steps:

[0139] When the first chip control status indicator pin outputs the first activity signal, the light-emitting element connected to the status indicator pin is turned on and illuminates.

[0140] The first activity signal mentioned above can be a low-level signal, and there is no specific limitation here. In addition, the first chip mentioned above may include the status indicator pin mentioned above.

[0141] Thus, when the first chip's control status indicator pin outputs a low-level signal, the light-emitting element can be turned on and illuminated, at which point the first chip is in normal working condition.

[0142] Based on this, the signal transmission method provided in this disclosure embodiment may further include the following steps:

[0143] When the first chip control status indicator pin outputs the second activity signal, the light-emitting element connected to the status indicator pin is turned off.

[0144] The second activity signal mentioned above can be a high-level signal, and no specific limitation is made here.

[0145] Thus, when the first chip's control status indicator pin outputs a high-level signal, the light-emitting element can be turned off, and at this time, the first chip's operating state is an abnormal operating state.

[0146] In this embodiment, the operating state of the first chip can be directly determined by the light-emitting state or the off state of an external light-emitting element connected to the status indicator pin in the first chip, which facilitates timely detection of any abnormalities in the first chip.

[0147] To fully and thoroughly describe the signal transmission method provided in the embodiments of this disclosure, in one embodiment of this disclosure, where the first object includes a UBB and the second object includes a second chip, the UBB includes a second hub and a baseline management controller (BMC).

[0148] Thus, before acquiring the first type of signal transmitted by the first object through the first chip, the method further includes:

[0149] Obtain device information through BMC;

[0150] Device information is transmitted to the first chip via the BMC and the second hub in the form of a first type of signal.

[0151] Thus, during the process of UBB transmitting data to the second chip, device information can be obtained through BMC, and the device information can be transmitted to the first chip through the second hub via BMC in the form of a first type of signal.

[0152] In this embodiment, based on the communication line in the server consisting of a first chip, a second hub, and a UBB, the UBB can transmit device information obtained by the BMC through the first chip, which facilitates the monitoring and management of components on the UBB board by the second chip.

[0153] In one embodiment of this disclosure, where the first object includes a UBB and the second object includes a second chip, the UBB may include a second hub, a multiplexer, and a conversion component.

[0154] Thus, before acquiring the first type of signal transmitted from the first object to the first chip, the signal transmission method provided in this disclosure embodiment further includes:

[0155] Obtain fault monitoring information through conversion components;

[0156] In the form of a first type of signal, fault monitoring information is transmitted to the first chip via a conversion component, a multiplexer, and a second hub.

[0157] Specifically, during the process of UBB transmitting signals from the first chip to the second chip, fault monitoring information can be obtained through the conversion component, and the fault monitoring information is transmitted to the first chip in the form of a first type of signal through the conversion component, multiplexer, and second hub.

[0158] In this embodiment, the second chip can monitor the UBB for faults through the lines constructed between the first chip, the second hub, the multiplexer, and the conversion components, which facilitates the timely management of the UBB by the second chip.

[0159] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a signal transmission method.

[0160] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and when executed by a processor, they will cause the processor to execute the signal transmission method provided in this application.

[0161] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0162] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0163] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0164] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0165] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 6 As shown, the electronic device 60 includes: a processor 601, and a memory 602 communicatively connected to the processor 601; the memory 602 stores instructions executable by the processor 601. The instructions are executed by the processor 601 to enable the processor 601 to perform:

[0166] The first type of signal transmitted by the first object is obtained through one end of the first chip;

[0167] The first type of signal is converted into a second type of signal by the first chip;

[0168] The second type of signal is transmitted to the second object through the other end of the first chip;

[0169] The server includes the first object and the second object; where the first object includes the second chip and the second object includes the universal substrate UBB, one end of the first chip is the first end and the other end of the first chip is the second end; or, where the first object includes the UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end.

[0170] The first chip includes a first chip select pin, a first clock pin, a first master input / slave output pin, and a first master output / slave input pin. The second chip includes a second chip select pin, a second clock pin, a second master output / slave input pin, and a second master input / slave output pin. The first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master input / slave output pin is electrically connected to the second master output / slave input pin, and the first master output / slave input pin is electrically connected to the second master input / slave output pin. The UBB is electrically connected to the second terminal of the first chip. The first terminal and the second terminal of the first chip are ports of different types.

[0171] The electronic devices and corresponding signal transmission methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0172] In practical applications, the electronic device 60 may further include at least one network interface 603. The various components of the electronic device 60 are coupled together via a bus system 604. It is understood that the bus system 604 is used to implement communication between these components. In addition to a data bus, the bus system 604 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 6 All buses are labeled as bus system 604. The number of processors 601 and the number of memories 602 can be at least one. The network interface 603 is used for wired or wireless communication between the electronic device 60 and other devices.

[0173] The memory 602 in this embodiment is used to store various types of data to support the operation of the electronic device 60.

[0174] The methods disclosed in the above embodiments of this disclosure can be applied to or implemented by processor 601. Processor 601 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 601 or by instructions in software form. The processor 601 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 601 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 602. Processor 601 reads the information in memory 602 and, in conjunction with its hardware, completes the steps of the aforementioned signal transmission method.

[0175] In some embodiments, the electronic device 60 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0176] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0177] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0178] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0179] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0180] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0181] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A server, characterized in that, The server includes: The first chip, the first terminal of the first chip includes a first chip select pin, a first clock pin, a first master input-slave output pin and a first master output-slave input pin; The second chip includes a second chip select pin, a second clock pin, a second master output slave input pin, and a second master input slave output pin. The first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master input slave output pin is electrically connected to the second master output slave input pin, and the first master output slave input pin is electrically connected to the second master input slave output pin. A universal substrate UBB is electrically connected to the second terminal of the first chip; the first terminal and the second terminal of the first chip are different types of ports. The first chip receives a first type signal transmitted by the first object through one end of the first chip, converts the first type signal into a second type signal, and transmits the second type signal to the second object through the other end of the first chip. Wherein, if the first object includes the second chip and the second object includes the UBB, one end of the first chip is the first end and the other end of the first chip is the second end, the first type of signal includes the Serial Peripheral Interface (SPI) signal, and the second type of signal includes the Universal Serial Bus (USB) signal; or, if the first object includes the UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end, the first type of signal includes the USB signal, and the second type of signal includes the SPI signal; The second chip does not integrate a Universal Serial Bus (USB) host controller; The first chip is used to perform signal conversion and transmission between the second chip and the UBB, so that the second chip, which does not integrate a Universal Serial Bus (USB) host controller, can perform out-of-band management of the components in the UBB.

2. The server according to claim 1, characterized in that, The server also includes a plurality of first resistors; The first chip select pin and the second chip select pin are electrically connected through the first resistor; the first clock pin and the second clock pin are electrically connected through the first resistor; the first master input / slave output pin and the second master output / slave input pin are electrically connected through the first resistor; the first master output / slave input pin and the second master input / slave output pin are electrically connected through the first resistor.

3. The server according to claim 2, characterized in that, The server also includes a power network and multiple second resistors; The first chip select pin is electrically connected to the power network through the second resistor, and the second chip select pin is electrically connected to the power network through the first resistor and the second resistor; The first clock pin is electrically connected to the power network through the second resistor, and the second clock pin is electrically connected to the power network through the first resistor and the second resistor; The first master input / slave output pin is electrically connected to the power network through the second resistor, and the second master output / slave input pin is electrically connected to the power network through the first resistor and the second resistor; The first master input / slave output pin is electrically connected to the power network through the second resistor, and the second master input / slave output pin is electrically connected to the power network through the first resistor and the second resistor.

4. The server according to claim 3, characterized in that, The server also includes: A choke is provided, with its first end electrically connected to the second end of the first chip and its second end electrically connected to the UBB; the choke is used to filter common-mode noise in the transmitted signal between the first chip and the UBB.

5. The server according to any one of claims 1 to 4, characterized in that, The first chip further includes an interrupt pin, and the second chip further includes a general-purpose input / output pin. The interrupt pin of the first chip is electrically connected to the general-purpose input / output pin of the second chip. When the first chip detects an interrupt event, it controls the interrupt pin to transmit an interrupt request signal to the general-purpose input / output pin of the second chip.

6. The server according to any one of claims 1 to 4, characterized in that, The first chip also includes a status indicator pin; the status indicator pin of the first chip is electrically connected to the light-emitting element. When the first chip controls the status indicator pin to output a first activity signal, the light-emitting element is turned on and illuminates.

7. The server according to claim 6, characterized in that, When the first chip controls the status indicator pin to output a second activity signal, the light-emitting element is turned off.

8. The server according to any one of claims 1 to 4, characterized in that, The first chip integrates a first hub, which includes multiple ports, and the multiple ports together constitute the second end of the first chip.

9. The server according to any one of claims 1 to 4, characterized in that, The UBB includes: The second hub has its first end electrically connected to the second end of the first chip; A baseboard management controller (BMC) is electrically connected to the second terminal of the second hub. When the first object includes the UBB and the second object includes the second chip, device information is obtained through the BMC and transmitted to the first chip via the second hub in the form of a first type signal through the BMC.

10. The server according to claim 9, characterized in that, The UBB also includes: A multiplexer, wherein a first terminal of the multiplexer is electrically connected to a second terminal of the second hub; A conversion component, wherein a first terminal of the conversion component is electrically connected to a second terminal of the multiplexer; The server is configured as follows: When the first object includes the UBB and the second object includes the second chip, fault monitoring information is obtained through the conversion component and transmitted to the first chip in the form of a first type signal via the conversion component, multiplexer, and second hub.

11. A signal transmission method, characterized in that, Applied to a server, the method includes: The first type of signal transmitted by the first object is obtained through one end of the first chip; The first type of signal is converted into a second type of signal by the first chip; The second type of signal is transmitted to the second object through the other end of the first chip; The server includes the first object and the second object; where the first object includes a second chip and the second object includes a Universal Serial Bus (UBB) substrate, one end of the first chip is the first end and the other end of the first chip is the second end, the first type of signal includes a Serial Peripheral Interface (SPI) signal, and the second type of signal includes a Universal Serial Bus (USB) signal; or, where the first object includes the UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end, the first type of signal includes the USB signal, and the second type of signal includes the SPI signal. The first chip has a first chip select pin, a first clock pin, a first master input / slave output pin, and a first master output / slave input pin. The second chip has a second chip select pin, a second clock pin, a second master output / slave input pin, and a second master input / slave output pin. The first chip select pin is electrically connected to the second chip select pin. The first clock pin is electrically connected to the second clock pin. The first master input / slave output pin is electrically connected to the second master output / slave input pin. The first master output / slave input pin is electrically connected to the second master input / slave output pin. The UBB is electrically connected to the second terminal of the first chip. The first terminal and the second terminal of the first chip are different types of ports. The second chip does not integrate a Universal Serial Bus (USB) host controller. The first chip is used to perform signal conversion and transmission between the second chip and the UBB, so that the second chip, which does not integrate a Universal Serial Bus (USB) host controller, can perform out-of-band management of the components in the UBB.

12. The method according to claim 11, characterized in that, The method further includes: The second chip sends an address code and a command code to the first chip. The address code is used to indicate the starting address of the operation performed by the second chip, and the command code is used to indicate the operation performed by the second chip. The operation performed by the second chip includes a read operation or a write operation. When the operation performed by the second chip is a write operation, the first object includes the second chip; the step of acquiring the first type of signal transmitted by the first object through the first chip includes: The second chip transmits the data to be written to the first chip, and the first type of signal includes the data to be written. The first chip receives the data to be written transmitted by the second chip and stores the data to be written to a first storage address, which is determined based on the starting address of the operation performed by the second chip. When the operation performed by the second chip is a read operation, the second object includes the second chip; the transmission of the second type of signal to the second object through the first chip includes: The data to be read is read from the second storage address using the first chip; The data to be read is transmitted from the first chip to the second chip, and the second type of signal includes the data to be read.

13. The method according to claim 11, characterized in that, The method further includes: When the first chip detects an interrupt event, it transmits an interrupt request signal to the general-purpose input / output pin of the second chip through the interrupt pin of the first chip.

14. The method according to claim 11, characterized in that, The method further includes: When the first chip outputs a first activity signal from the control status indicator pin, the light-emitting element connected to the status indicator pin is turned on and illuminates. The first chip includes the status indicator pin.

15. The method according to claim 11, characterized in that, The first object includes the UBB, and the second object includes the second chip; the UBB includes a second hub and a baseline management controller (BMC). Before acquiring the first type of signal transmitted by the first object via the first chip, the method further includes: Device information is obtained through the BMC; The device information is transmitted to the first chip via the second hub through the BMC in the form of the first type of signal.

16. The method according to claim 11, characterized in that, The first object includes the UBB, and the second object includes the second chip; the UBB includes a second hub, a multiplexer, and a conversion component; Before acquiring the first type of signal transmitted from the first object to the first chip, the method further includes: Fault monitoring information is obtained through the conversion component; The fault monitoring information is transmitted to the first chip via the conversion component, multiplexer, and second hub in the form of the first type of signal.

17. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the signal transmission method according to any one of claims 11 to 16.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the signal transmission method according to any one of claims 11 to 16.

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