Anti-counterfeiting FPGA chip based on PUF and FPGA chip anti-counterfeiting method
By embedding a PUF circuit within the FPGA chip and utilizing process deviations during manufacturing to generate a unique identification code, the problem of easy counterfeiting of FPGA chips is solved, achieving highly secure anti-counterfeiting identification.
Patent Information
- Application Number
- CN202510866075.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-11-21
AI Technical Summary
In existing technologies, FPGA chips are easily counterfeited and recycled, which damages the legitimate rights and interests of legitimate manufacturers and users, and there is a lack of effective anti-counterfeiting identification methods.
A Physically Unclonable Function (PUF) circuit is embedded in the FPGA chip. A unique random sequence is generated using process deviations during manufacturing as an identification code. The result of the PUF circuit calculation is used as the identity authentication code of the FPGA chip, and verification is performed in conjunction with EDA software.
This technology enables unique identification of FPGA chips, preventing counterfeiting and refurbishment, and improving chip security and the efficiency of verifying their legitimate identity.
Smart Images
Figure CN120995513A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of microelectronics and integrated circuit technology, and in particular to an anti-counterfeiting method for FPGA chips. Background Technology
[0002] FPGA stands for Field Programmable Gate Array, a type of hardware chip that can be repeatedly programmed and configured using EDA software. Users can customize its internal hardware circuitry to achieve specific functions according to their needs.
[0003] With the widespread application of FPGA chips in various engineering fields, some unscrupulous merchants have used illegal means such as imitation and recycling to put counterfeit and substandard FPGA chips into the market, which seriously damages the legitimate rights and interests of legitimate FPGA chip manufacturers and users. Therefore, it is particularly important to develop a technology that can identify counterfeit and substandard FPGA chips. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an FPGA chip with anti-counterfeiting function, and an anti-counterfeiting method for the FPGA chip.
[0005] The technical solution adopted by the present invention to solve the aforementioned technical problem is a PUF-based anti-counterfeiting FPGA chip, comprising N ID bit generation branches, where N is a preset natural number; each ID bit generation branch includes an RS latch and two lookup table links; the output of the RS latch is connected to the ID output interface; the R input of the RS latch is connected to the output of one lookup table link, and the S input is connected to the output of the other lookup table link; the inputs of all lookup table links are connected to the initial signal input interface; the lookup table links are composed of a predetermined number of lookup tables connected in series.
[0006] Furthermore, all lookup table links consist of the same number of lookup tables.
[0007] The FPGA chip anti-counterfeiting method provided by this invention includes the following steps:
[0008] (1) Input an initial signal to the anti-counterfeiting module of the FPGA chip. The anti-counterfeiting module includes N ID bit generation branches, where N is a preset natural number. Each ID bit generation branch includes an RS latch and two lookup table links. The output of the RS latch is connected to the ID output interface. The R input of the RS latch is connected to the output of one lookup table link, and the S input is connected to the output of another lookup table link. The inputs of all lookup table links are connected to the initial signal input interface. The lookup table links are composed of a predetermined number of lookup tables connected in series. (2) Read the output information of the anti-counterfeiting module and compare it with the pre-stored chip ID information. If they match, the verification is deemed successful. If they do not match, the verification is deemed unsuccessful.
[0009] A Physically Unclonable Function (PUF) is a random number generation method based on physical responses. It utilizes the randomness of a physical system to generate a unique sequence of random numbers, which can be used as an identification code. Embedding a PUF circuit module in an integrated circuit extracts and amplifies random deviations generated during the manufacturing process, producing a physical random response corresponding to the integrated circuit. This results in an unpredictable and unique identifier for that specific integrated circuit entity, possessing both uniqueness and randomness.
[0010] Based on this idea, this invention utilizes the unique logic and wiring resources within an FPGA chip to implement a PUF circuit. The result of the PUF circuit's calculations is used as the FPGA chip's identification code. Due to random deviations in the manufacturing process of FPGA chips, the result of the PUF circuit's calculations is different for each FPGA chip, possessing uniqueness. Furthermore, this result is not predictable, thus providing extremely high security. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the anti-counterfeiting module structure of the present invention.
[0012] Figure 2 A schematic diagram of the state of an RS latch constructed from NOR gates when all inputs are 1.
[0013] Figure 3 A schematic diagram of the state of an RS latch composed of NOR gates when the inputs are different.
[0014] Figure 4 A schematic diagram of an RS latch constructed from NOR gates, where the output remains in a state where all inputs are 0.
[0015] Figure 5 It is a PUF sub-circuit that generates a single ID.
[0016] Figure 6This is a schematic diagram of the initial input signal.
[0017] Figure 7 This is a schematic diagram of the operation of the sub-circuit when the delay of delay chain 1 is greater than that of delay chain 2.
[0018] Figure 8 This is a schematic diagram of the sub-circuit operation when the delay of delay chain 2 is greater than that of delay chain 1.
[0019] Figure 9 This is a schematic diagram of the layout of the PUF circuit of the present invention in an Xlinx Spartan7 series FPGA.
[0020] Figure 10 This is a screenshot of the response information obtained from the PUF circuit. Detailed Implementation
[0021] The PUF circuit of this invention consists of 2N LUT (lookup table) delay chains and N RS latches, generating a random sequence of length N, such as... Figure 1 As shown. The value of N depends on the number of FPGA chips that need to be identified, and should be guaranteed to be 2. N >>Number of FPGA chips to be identified.
[0022] As a logic resource in an FPGA chip, a LUT can be used to implement combinational logic. This invention uses a 6-input lookup table as an example, but the method of this invention is not limited to FPGA chips with 6-input lookup tables.
[0023] An RS latch is a basic digital circuit element used to store one bit of binary data. It consists of two cross-connected NOR gates and NAND gates, and has two inputs (R and S) and two outputs (Q and S). ).
[0024] like Figure 2 As shown, when both inputs S and R of the RS latch are 1, the output Q will always be 0. Figure 3 As shown, the output value is determined when the inputs S and R of the RS latch are different. However, when both inputs S and R of the RS latch are 0, the output value will remain unchanged. Figure 4 As shown.
[0025] The PUF circuit of this invention consists of N such Figure 5 The sub-circuit shown can generate a single-bit anti-counterfeiting ID. This sub-circuit consists of M "LUT delay" modules (the larger M is, the more significant the delay difference; it is recommended that M be >= 4) and an RS latch. The initial signal is as follows: Figure 6 As shown, a counter and a flip-flop can be used to generate it.
[0026] The "LUT delay" module in the sub-circuit utilizes the LUTs in the FPGA to construct a signal delay buffer. The method is as follows: configure the lookup table of the 6-input device with a lookup value of "64'haaaa_aaaa_aaaa_aaaa". For a 4-input LUT, configure the value as "16'haaaa". This ensures that the LUT's output is identical to its input logic value, delaying only the input signal. This delay time depends solely on the physical properties of the LUT device itself. Due to process variations in FPGA chip manufacturing, each LUT device will have certain physical differences, resulting in variations in signal delay time when used as a signal delay buffer. Using multiple "LUT delay" modules can amplify these signal delay differences. The RS latch consists of two NOR gates connected together.
[0027] The principle behind generating a single ID is as follows:
[0028] During the FPGA chip manufacturing process, due to process errors, each LUT device will have certain physical differences. This causes the delayed signal 1 and delayed signal 2, obtained by the initial signal passing through two delay chains, to arrive at the RS latch at different times, resulting in the following two situations:
[0029] 1. For example Figure 7 As shown, the delay of delay chain 1 is greater than that of delay chain 2. The operation of the RS latch in this case is as follows:
[0030] Process 1: Input S=1, R=1, output Q=0.
[0031] Process 2: Input S=1, R=0, output Q=0.
[0032] Process 3: Input S = 0, R = 0, output Q remains 0.
[0033] 2. For example Figure 8 As shown, the delay of delay chain 1 is less than that of delay chain 2. The operation of the RS latch in this case is as follows:
[0034] Process 1: Input S=1, R=1, output Q=0.
[0035] Process 2: Input S=0, R=1, output Q=1.
[0036] Process 3: Input S=0, R=0, output Q remains at 1.
[0037] It can be seen that the output value of the Q terminal of the RS latch reflects the signal propagation delay, which in turn reflects the random error of the LUT during the manufacturing process.
[0038] The PUF circuit for generating an N-bit anti-counterfeiting ID in this invention consists of N such... Figure 5 The sub-circuit shown is described in the following principle:
[0039] 1. The initial input signals of each delay chain are the same, such as... Figure 6 As shown.
[0040] 2. The sub-circuit generated by each ID uses two symmetrical delay chains to delay the initial input signal.
[0041] 3. After being delayed by two M-order delay chains, delayed signal 1 and delayed signal 2 are obtained and input to the R and S input terminals of the RS latch, respectively.
[0042] 4. The output value of the RS latch reflects the signal propagation delay, which in turn reflects the random error of the LUT during the manufacturing process.
[0043] 5. The output value of the RS latch in the N sub-circuits is an N-bit random sequence, which can be used as the ID information of the FPGA chip.
[0044] In summary, the PUF circuit of this invention reflects the differences in signal propagation delay in the circuit, thereby reflecting the random differences in the LUT devices in the FPGA chip during the manufacturing process, and is a physical random response of the FPGA chip.
[0045] Using the technology of this invention, each FPGA chip has a unique ID value, which can be used for anti-counterfeiting. Manufacturers store the ID data of each genuine FPGA chip in a database. When a user programs a specific model of FPGA chip from an FPGA manufacturer, while using EDA software to connect to the FPGA chip, the EDA development software will download data to the FPGA. Figure 1 The system uses the PUF circuit shown and reads its response value, comparing it with data in the database. If the ID of the PUF chip is detected as a genuine FPGA chip from the manufacturer, the system increments the connection count for that FPGA chip ID and then sends the authenticity information and connection count to the EDA software. Conversely, if it is a counterfeit chip, the EDA software immediately disconnects from the FPGA chip, preventing the use of the counterfeit chip. The number of times the FPGA chip ID has been used allows the user to confirm whether they have purchased a refurbished FPGA chip.
Claims
1. A PUF-based anti-counterfeiting FPGA chip, characterized in that, It includes N ID bit generation branches, where N is a preset natural number; each ID bit generation branch includes an RS latch and two lookup table links; the output of the RS latch is connected to the ID output interface; the R input of the RS latch is connected to the output of one lookup table link, and the S input is connected to the output of the other lookup table link; the inputs of all lookup table links are connected to the initial signal input interface; the lookup table links are composed of a predetermined number of lookup tables connected in series.
2. The PUF-based anti-counterfeiting FPGA chip as described in claim 1, characterized in that, All lookup table links consist of the same number of lookup tables.
3. An anti-counterfeiting method for FPGA chips, characterized in that, Includes the following steps: (1) An initial signal is input to the anti-counterfeiting module of the FPGA chip. The anti-counterfeiting module includes N ID bit generation branches, where N is a preset natural number. Each ID bit generation branch includes an RS latch and two lookup table links. The output of the RS latch is connected to the ID output interface. The R input of the RS latch is connected to the output of one lookup table link, and the S input is connected to the output of another lookup table link. The inputs of all lookup table links are connected to the initial signal input interface. The lookup table links are composed of a predetermined number of lookup tables connected in series. (2) Read the output information of the anti-counterfeiting module and compare it with the pre-stored chip ID information. If they match, the verification is deemed successful; otherwise, the verification is deemed unsuccessful.