Circuit board simulation test system and method and electronic equipment

Abstract

The invention relates to the field of circuit board development and test, and discloses a circuit board simulation test system and method and electronic equipment, and the system comprises a data collection module, a performance prediction module, a test task generation module, a priority scoring module, a resource scheduling module, and a test execution and feedback module. The method comprises the steps that simulation environment parameters are collected, and the performance of a circuit board is predicted; identifying a function item based on the prediction result and generating a test task; the scheduling priority is calculated, and resource matching and task scheduling are completed; testing is executed, response data are collected, and a feedback result is generated; the electronic equipment comprises a memory, a processor and a communication module, wherein the circuit board simulation test method is realized when the processor is executed. According to the method, the environmental adaptability and precision of the test are improved, intelligent task scheduling and efficient resource utilization are realized, the prediction correction capability is realized, and the fault discovery efficiency and the system adaptability are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit board development testing, in particular to a circuit board simulation testing system and method, and an electronic device. BACKGROUND

[0002] In the field of circuit board development testing, traditional testing methods usually rely on physical prototype construction and repetitive testing mechanisms with preset environmental parameters. Engineers generally verify the functionality and performance of circuit boards by setting specific input signals and working conditions. This method has certain applicability in the standardization and mass production stage, and can test whether the basic logic of the circuit board meets the design requirements in a static environment.

[0003] However, with the increasing integration of circuit boards and the diversification of application scenarios, the traditional testing system gradually exposes a series of problems of insufficient adaptability and intelligence. On the one hand, the working environment of the circuit board often fluctuates greatly in temperature, voltage, humidity and other parameters in actual application, and the test results under a single environment cannot fully evaluate the performance stability of the circuit in real working conditions; on the other hand, the traditional testing process is usually based on manual configuration and static test scripts, lacks a targeted task allocation mechanism, resulting in low resource scheduling efficiency, and problems such as redundant occupation or conflict waiting of some test resources.

[0004] Currently, the industry gradually adopts simulation-based circuit board testing methods to verify the correctness of the function and performance bottleneck in advance through model simulation means before physical prototype construction. One of the more common methods is to build a simulation platform based on a fixed test model and a preset scenario, and then compare the theoretical performance indicators with the simulation output results to determine the rationality of the circuit board design. This method improves the flexibility of testing to some extent and provides prior judgment basis in the early development stage.

[0005] However, the existing simulation testing scheme has the following problems: first, the performance evaluation process relies on static test models and fixed parameter configurations, lacks the ability to perceive and adapt to environmental changes, and is difficult to reflect the dynamic influence of complex external conditions on the running state of the circuit board, thereby affecting the credibility of the test results; second, test resources are usually allocated according to task order or static priority, which makes it difficult to accurately schedule according to task risk, complexity or urgency, resulting in a decline in testing efficiency, delay of critical tasks or unreasonable resource allocation; third, existing testing platforms are mostly one-way execution structures, lack real-time feedback and performance prediction correction mechanisms, and are difficult to perceive and analyze potential fault points in advance, thereby increasing the failure rate of products in the later development or field operation.

[0006] Therefore, the present application proposes a circuit board simulation testing system, method and electronic device to solve the deficiencies of the prior art. SUMMARY

[0007] In view of the deficiencies of the prior art, the circuit board simulation test system, method and electronic equipment provided by the present application solve the problems of test precision affected by environmental changes, low resource allocation efficiency and lack of fault prediction capability in the prior art.

[0008] To achieve the above object, the present application is implemented by the following technical solutions: a circuit board simulation test system, comprising: a data acquisition module for acquiring environmental parameters of the circuit board under a simulation test scenario; a performance prediction module for predicting and outputting the running performance result of the circuit board based on the environmental parameters; a test task generation module for generating a test task to be executed according to the running performance result; a priority scoring module for calculating the scheduling priority of each test task based on multiple influence factors; a resource scheduling module for allocating and scheduling resources for the test task based on the scheduling priority; a test execution and feedback module for executing the test task and collecting response data of the circuit board to generate a test feedback result.

[0009] The present application also provides a circuit board simulation test method, comprising the following steps: acquiring environmental parameters of the circuit board under a simulation test scenario; predicting the running performance result of the circuit board based on the environmental parameters; identifying a functional item to be tested based on the running performance result, and generating a test task to be executed according to the identification result; extracting scoring factors affecting the scheduling priority of the test task, assigning corresponding weight values to each scoring factor, and calculating the scheduling priority of the test task based on the scoring factors and weight values; allocating and scheduling resources for the test task according to the scheduling priority; executing the test task, collecting response data of the circuit board, and generating a test feedback result based on the response data.

[0010] The present application also provides an electronic device comprising a memory and a processor; the memory for storing a computer program; the processor for executing the program stored on the memory to implement the circuit board simulation test method of claim 9.

[0011] The present application provides a circuit board simulation test system, method and electronic equipment. The following beneficial effects are achieved: 1.The present application realizes the dynamic evaluation of the running state of the circuit board under different temperature and humidity, voltage conditions by introducing an environment perception-based performance prediction mechanism. Compared with the performance drift problem caused by ignoring environmental disturbance in traditional testing, the present technical solution effectively solves the test accuracy fluctuation caused by environmental changes, and improves the consistency and reliability of the overall test results.

[0012] 2.The present application adopts a task priority scoring algorithm + resource dynamic scheduling framework, and the system can automatically identify high-risk tasks and preferentially match resources. This approach breaks the problem of high idle rate of test resources in the prior art. It can allocate computing power according to the actual task value, and achieve "targeted" allocation of resources, significantly improving resource utilization.

[0013] 3.The present application combines test feedback and prediction error closed-loop mechanism, not only tests, but also "learns". Each execution result will feed back to the performance model, and the system will become more accurate with more tests. This design is different from the traditional static modeling method, which can adapt to the behavior of the circuit board in real time, and improve the forward-looking prediction ability of potential faults and performance drift, especially suitable for complex and variable development environments.

[0014] 4.The present application system supports automatic construction, dynamic scheduling, and multi-source signal parallel acquisition of test tasks, and truly realizes the transition from "manual control" to "self-driving". Most of the existing solutions rely on manual configuration of test processes, which is low in efficiency and prone to omissions. The present application can make the test process continuous like a pipeline, significantly improving the response efficiency and product reliability of the development link. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a system architecture diagram of the present application; Figure 2 is a method flowchart of the present application; Figure 3 is an electronic device structure schematic diagram of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0017] Please refer to the drawings of the present application Figure 1 The circuit board simulation test system provided by the embodiments of the present application comprises: A data acquisition module is used to acquire environmental parameters of the circuit board in a simulation test scene. The main function of the data acquisition module is to collect key operating parameters of the circuit board in the simulation test environment, to provide real and quantifiable input data for subsequent performance prediction, task construction and scheduling scoring modules. As a design idea, this module can be built as an independent subsystem coupled with the test platform, or embedded on the main controller to form a tightly coupled hardware structure.

[0018] Generally, the data acquisition module needs to ensure the continuous sampling capability of various analog and digital parameters, and has basic data buffering, preprocessing and time alignment mechanism to adapt to the subsequent data modeling process. Specifically, the data acquisition module can be designed as a modular acquisition framework with multiple sensing interfaces, and the submodules are expanded according to the functional complexity of the circuit board under test.

[0019] In this embodiment, the data acquisition module includes at least a temperature sensing module, a humidity sensing module, a power supply monitoring module and a timing signal monitoring module. The technical implementation and acquisition content of each submodule are described as follows.

[0020] In this embodiment, the temperature sensing module is used to collect the temperature parameters of the space or the inside of the shell where the circuit board is located. Specifically, a thermistor, a thermocouple or a digital temperature chip can be used for temperature sensing. In some embodiments, a digital temperature device such as DS18B20 is used, which supports 1-Wire bus protocol and can be connected in parallel in multiple on-board areas. The collected temperature data is in Celsius and is sent to the central cache module at a fixed sampling frequency. As an option, the temperature sampling period can be set to 1-3 seconds, and the sampling accuracy is better than ±0.5℃. Temperature information is of great reference value for performance prediction of heat-sensitive circuits such as voltage stabilizing modules and power amplifier chips.

[0021] In some embodiments, the humidity sensing module is used to measure the relative humidity parameter in the ambient air. The specific implementation can use an integrated capacitive humidity chip (such as SHT30) or an open-loop resistance type sensor. The humidity reading is expressed in percentage (%RH) form, and the range is usually 0% to 100%. The data collected by this module helps to determine whether there is a humidity risk that affects signal integrity or device insulation. In one possible implementation, the humidity sampling period is 5 seconds, allowing the formation of a synchronous data stream with the temperature sensing submodule.

[0022] In this embodiment, the power supply monitoring module is mainly used to collect the power supply parameters of the circuit board in the simulation state, covering voltage and current signals. Generally, this module is composed of a pre-stage circuit, a sampling resistor and a high-precision analog-to-digital conversion chip. For example, one implementation uses INA219 current / voltage sensing chip to upload real-time data to the controller through I2C interface. The sampled data can be used to estimate the instantaneous power consumption, and the calculation method is as follows: ; wherein, represents the instantaneous power consumption of the circuit board, in units of watts; represents the power supply voltage, in units of volts; represents the power supply current, in units of amperes (A).

[0023] The obtained power consumption information can be used not only to evaluate the stability of the device, but also as one of the input factors of the performance prediction model.

[0024] In this embodiment, the timing signal monitoring module is used to sample and analyze the control signals and data transmission signals that appear during the operation of the circuit board. This module supports multiple communication protocol parsing, including SPI, I2C, CAN, UART, etc. Specifically, the signal level, transition edge, period, time delay, etc. can be recorded through a digital oscilloscope, a logic analyzer module, or a self-developed high-speed signal sampler. In some embodiments, a high-speed ADC with a sampling rate higher than 100MHz is used to collect signals, capturing signal changes in nanosecond resolution.

[0025] In one possible implementation, the signal sampling data is organized as a time series structure, represented as follows: ; wherein, is a sequence of timing signal features, representing a set of signal samples collected within a time window; is the th timing feature vector, containing a combination of multi-dimensional signal features; is the number of sampling times, i.e. the total number of sample points contained in the window.

[0026] As an optional design, the data acquisition module can also integrate a primary data alignment function. In the scenario of multi-source asynchronous signal sampling, the timestamp mapping mechanism is used to align the outputs of modules with different sampling frequencies to a unified time base, ensuring the consistency of subsequent model inputs.

[0027] Overall, the data acquisition module provided in this embodiment has the characteristics of multi-channel, multi-parameter, scalability, high compatibility, etc. While providing comprehensive raw data support, it is also easy to use with subsequent prediction models, with good openness and practicality. The data obtained by the data acquisition module will be directly used as the input of the performance prediction module, and then throughout the entire simulation test process of test task construction, scheduling execution, etc.

[0028] The performance prediction module is configured to predict and output the running performance result of the circuit board based on the environmental parameters. The performance prediction module as a core functional unit aims to intelligently analyze and estimate the performance of the collected environmental parameters and operating state data. The input mainly comes from the multi-dimensional parameters output by the data acquisition module, including temperature, humidity, power state, timing signal characteristics, etc. The performance prediction module generates performance indicators and abnormal warning information of the circuit board through steps such as feature extraction, modeling training, and performance output, providing a basis for test task scheduling and evaluation.

[0029] Generally, the performance prediction module works cooperatively through three parts: preprocessing module, prediction model module, and output module, which are respectively responsible for feature extraction, performance estimation, and result output. Through modular design, not only the prediction accuracy is improved, but also the system's scalability and flexibility are enhanced. The specific implementation of each sub-module is described in detail below.

[0030] Feature processing module: In this embodiment, the feature processing sub-module is used to preprocess the environmental parameters to extract the features required for modeling.

[0031] Generally, to ensure the consistency and effectiveness of the input data, the feature processing sub-module needs to perform denoising, smoothing, and normalization operations. Specifically, temperature, humidity, power, and timing signal features can be preprocessed to construct a standardized feature vector set.

[0032] As an option, the feature processing sub-module performs sliding window smoothing on the timing signal to suppress the influence of acquisition noise. Assuming the signal sampling sequence is: ; where, is the timing signal feature sequence; is the th timing feature vector, which contains a combination of multi-dimensional signal features; is the number of sampling times, i.e., the total number of sample points contained in the window.

[0033] The sliding window length is , then the smoothed signal value is calculated as follows: ; where, represents the smoothed signal value at the th time; represents the sampling value of the original signal at the th time; represents the length of the sliding window, i.e., the number of sampling points contained; is the time index in the sliding window, the traversal range is from to ; This is the window averaging coefficient, used to calculate the mean of signal values ​​within the window.

[0034] In one possible implementation, to adapt to different testing scenarios, the feature processing submodule can automatically adjust the sliding window length based on the volatility of the input features.

[0035] In some embodiments, for power state data, the feature processing submodule extracts the instantaneous power consumption change rate through differential calculation: ; in, For the first Increment in power consumption at any given moment; For the first Power consumption at any given moment, in watts.

[0036] Predictive model module; In this embodiment, the prediction model submodule generates the circuit board's operating performance results based on the extracted feature data.

[0037] Alternatively, this submodule employs a regression prediction model, such as linear regression or a multilayer perceptron (MLP). The input feature vector is in the form of: ; in, For the first Each feature value is taken from Output of the feature processing submodule; The number of features.

[0038] Predictive models use weight parameters and bias Calculate the predicted value: ; in, To predict performance metrics; This is the weight vector; This is the bias value.

[0039] In one possible implementation, the model uses a gradient descent algorithm to optimize the weight parameters and is trained based on the mean squared error (MSE) loss function. ; in, This is the loss value; The number of samples; This is a predicted value; This is the actual value.

[0040] Output submodule: In this embodiment, the output submodule is used to output the performance results generated by the prediction model, which serve as the input basis for the subsequent task scheduling module.

[0041] Typically, the output format includes predicted values ​​and anomaly alarm indicators. Specifically, if the performance deviation exceeds a threshold, an anomaly warning is triggered. ; in, For the first The relative error of each performance indicator; This is a predicted value; For reference only.

[0042] Output module: In this embodiment, the output submodule is used to output the performance results generated by the prediction model, which serve as the input basis for the subsequent test task generation module.

[0043] Typically, the output format includes predicted values ​​and anomaly alarm indicators. Specifically, if the performance deviation exceeds a threshold, an anomaly warning is triggered. ; in, For the first The relative error of each performance indicator; This is a predicted value; For reference only.

[0044] As an option, if If the percentage exceeds a preset threshold (e.g., 5%), it will be marked as abnormal.

[0045] In one possible implementation, the performance prediction module also integrates a model update mechanism. During the actual operation of the circuit board, the model parameters are updated in real time through an online learning algorithm, so that the prediction results gradually approach the actual operating state, further improving the prediction accuracy and robustness.

[0046] In some embodiments, for multi-board parallel testing scenarios, the prediction module supports batch processing calculations, utilizing GPUs to accelerate the calculation process and improve prediction response speed.

[0047] In summary, the performance prediction module in this embodiment can accurately estimate the circuit board performance based on input environmental parameters and operating status, and promptly output anomaly warnings, providing a basis for decision-making in the scheduling and optimization of simulation test tasks. Through the rational design of feature processing and model construction methods, efficient and flexible prediction capabilities are achieved.

[0048] The test task generation module is used to generate test tasks to be executed based on the running performance results; The test task generation module is an important intermediate link between performance prediction and scheduling execution. The main function of the test task generation module is to dynamically identify the functional items that need to be tested in the current circuit board according to the running performance results output by the performance prediction module, and to construct a corresponding test task structure based on the identified functional items.

[0049] In general, the input of the test task generation module is the performance prediction data provided by the output module, which includes the predicted performance value at each time point, the number of the corresponding functional unit, the performance deviation value, and the abnormal alarm identifier, etc. The module needs to have the ability to analyze the mapping relationship between the predicted results and the functional structure, and to complete the processes of functional item screening, task body construction, and test task output, in combination with the preset performance index baseline.

[0050] As a design method, the module can be divided into three functional sub-units: a task analysis module, a task construction module, and a task output module. The functions of these sub-units will be described in detail below.

[0051] In this embodiment, the task analysis module is used to extract valid signals from the running performance data provided by the performance prediction module, and to identify the functional items corresponding to the functional units that have performance deviations.

[0052] Specifically, the module first obtains the mapping set of each functional unit and its performance index in the circuit board design. This set is static configuration information, which can be represented in the form of: ; wherein, is the functional unit-performance index mapping set; represents the i-th functional unit in the circuit board; represents the reference performance standard value corresponding to the functional unit, which is set according to the type of the performance item, such as frequency, power consumption, or delay, etc. is the total number of functional units in the system.

[0053] Then, the module compares the predicted results from the performance prediction module with the above-mentioned reference values, and calculates the performance deviation value of each functional unit. The calculation formula is as follows: ; wherein, is the predicted performance value of the functional unit, is the reference standard performance value of the functional unit; In one possible implementation, the system sets a performance deviation judgment preset threshold When the deviation value satisfies the following condition: , the system identifies the functional item corresponding to the functional unit as a "to-be-tested functional item".​ The judgment logic is used to focus on the functional area with abnormal trend or stability decline, so as to realize the focus of test resources and the optimization of coverage.

[0054] In the embodiment, the task construction module is used to construct the corresponding test task structure on the basis of identifying the to-be-tested function item.

[0055] Generally, each to-be-tested function item will be mapped to an independent test task. The test task includes but is not limited to the following field information: function item identifier; function unit number; performance deviation value; recommended test strategy number; test priority; estimated test duration, etc.

[0056] In a possible implementation, the task construction module automatically assigns the test priority according to the deviation value. For example: ; wherein, , are the performance deviation thresholds of high priority and medium priority, respectively; is the basic deviation identification threshold, which is set by the task analysis module.

[0057] As an option, the module can also match different test strategy templates according to the function unit belonging to the area or the signal type, to form a structured test task.

[0058] In the embodiment, the task output module is used to output the constructed test task structure in a standardized format, for reading and parsing by the scheduling execution module.

[0059] Generally, the task output module organizes the task set into a list form, as follows: ; wherein, represents the total test task set generated in the current period; represents the th test task structure unit, wherein ; represents the total number of to-be-tested function items identified in the current task generation period, corresponding to the number of generated test tasks.

[0060] In some embodiments, the output format can be encapsulated in JSON, ProtocolBuffer or a custom binary frame structure, to adapt to different scheduling system interface protocols.

[0061] To ensure the real-time scheduling, the task output module can also sort the task list according to the priority field and attach the task generation timestamp to ensure the timing consistency of the test process.

[0062] In addition, in some extended implementations, the module can also bind the task with its corresponding performance prediction history for output, forming a tracking data pair for closed-loop verification, for the resource scheduling module or subsequent analysis module to perform effect tracing and optimization modeling.

[0063] In summary, the test task generation module provided in the embodiment can realize dynamic identification and task construction of the to-be-tested function item through the automatic discrimination mechanism of performance deviation combined with the static structure mapping relationship. The modular design not only improves the generation efficiency of the test task, but also provides a clear structure and clear priority data support path for scheduling execution.

[0064] The priority scoring module is configured to calculate the scheduling priority of each test task based on multiple influence factors. The priority scoring module serves as an intermediate link between the test task generation and the scheduling execution, and is responsible for the extraction of scoring factors, the processing of factor weights, and the calculation of priority, etc.

[0065] Generally, due to significant differences between different test tasks in terms of task size, risk level, resource constraints, and time requirements, etc., if they are not distinguished and scheduled homogeneously, it may cause critical tasks to be delayed, thereby affecting the coverage and efficiency of the overall simulation verification. Therefore, the system needs to assign different priorities to test tasks based on multiple influence factors, so as to realize orderly and efficient test process control.

[0066] In one possible implementation, the priority scoring module includes a factor extraction module, a weight processing module, and a priority calculation module, which work together to calculate and output the priority value of each test task.

[0067] In the embodiment, the functions and structure of the priority scoring module are described as follows: The factor extraction module is configured to extract key scoring factors that affect the priority of task scheduling from the test task data structure. The module receives the task set output by the task generation module ; and parses the following field information in each test task structure one by one: The predicted risk value (Risk), denoted as , is determined according to the absolute value, duration, volatility, etc. of the aforementioned deviation ratio EEE; The resource consumption rate (Utilization), denoted as , based on the test duration required for task execution, device occupancy ratio, memory bandwidth, etc. The deadline urgency is denoted as , which is determined by the remaining interval from the current time to the deadline of the task.

[0068] The weight processing module is used to assign weight values to the above scoring factors to reflect the degree of influence of different factors on the final priority score.

[0069] In some embodiments, the module has a built-in static weight table, and can also access an external weight learning model for dynamic adjustment. Specifically, let the corresponding weight of each factor be , , , The weights satisfy the following constraint relationship: ; In another possible implementation, the weight parameters can be automatically trained based on historical scheduling data through a supervised learning mechanism. This method is suitable for system environments where task characteristics change frequently, and is beneficial to the adaptive evolution of the scoring strategy.

[0070] The priority calculation module is used to calculate the scheduling priority score of each task based on the scoring factors and their corresponding weight values , which is used as the basis for sorting by the subsequent scheduling module.

[0071] Specifically, the scheduling priority calculation formula is defined as follows: ; Wherein, is the scoring factor, represents the task complexity factor, represents the predicted risk value, represents the resource consumption rate, represents the deadline urgency, , , , is the weight parameter of each scoring factor.

[0072] In the above scoring factors, the units and dimensions of each parameter need to be uniformly processed, and if necessary, they are mapped to a uniform numerical interval (such as [0, 1]) through standardization processing to ensure the dimensional consistency and reasonableness of the formula calculation results.

[0073] In some embodiments, the task complexity factor can be further refined into a weighted combination of structural complexity and input vector complexity, such as: ; wherein, represents the number of logic gates of the function logic unit to be tested; represents the number of test vectors required for the task; , is a secondary weight parameter of the complexity internal factor.

[0074] In another possible implementation, the predicted risk value may be expressed jointly with its derivative term, for example: ; wherein, represents the performance deviation value (Deviation) at the current time; represents the performance deviation value rate of change over time, i.e., the derivative term of the deviation; , are both non-negative real numbers, and the values can be set by experience or obtained automatically by the system.

[0075] to improve the ability to judge the risk trend, especially for detecting potential fault risk points with rapidly growing deviation but small current amplitude.

[0076] Further, when outputting the priority score result , the priority score module can be accompanied by a confidence coefficient or a score source label, supporting secondary judgment or strategy rollback of the subsequent module in the case of scheduling conflict or resource shortage.

[0077] As an option, the score result may be mapped to a priority level label through a logical segmentation function, for example: is high priority; is high-medium priority; is medium priority; is low priority.

[0078] This segmentation processing mode can be used to support the multi-level resource distribution strategy of the scheduler or the batch test execution plan.

[0079] To sum up, the priority score module in the embodiment realizes scientific evaluation and quantitative calculation of the test task scheduling priority by structured extraction of score factors, dynamic configuration of weight values, and combination of a unified priority score function. The module not only improves the accuracy and response efficiency of task scheduling, but also provides a quantitative support basis for resource coordination and scheduling strategy at the system level.

[0080] ​A resource scheduling module is configured to allocate and schedule the test tasks based on the scheduling priority. After the priority scoring module calculates the scheduling priority of the test tasks, the resource scheduling module is configured to allocate and schedule the test tasks accurately to realize the orderly execution of the test tasks and the optimal utilization of the system resources. The resource scheduling module and the priority scoring module are directly connected to each other to receive the test task queue scored and sorted, and to generate a dynamic matching and scheduling instruction in combination with the real-time available state of the test resources, so that the system can still complete the test process efficiently and stably under the condition of limited resources.

[0081] Generally, the test resources available in the circuit board simulation test system include a logic simulator channel, an input vector cache, a data analysis unit and a multi-type signal excitation source, and these resources are usually limited shared resources and have a dependent or mutually exclusive relationship between different tasks. Therefore, the scheduling and screening must be performed before execution to avoid resource conflicts and scheduling blockage.

[0082] In the embodiment, the resource scheduling module includes the following functional sub-modules: a resource state monitoring module, a task matching module and a scheduling control module, and the sub-modules are coordinated to support the integrity and responsiveness of the entire scheduling process.

[0083] The resource state monitoring module is configured to collect the occupation information and the remaining capacity of various test resources in the system in real time. A resource state table is constructed In the embodiment, the resource state monitoring module is configured to collect the occupation information and the remaining capacity of various test resources in the system in real time. A resource state table is constructed The resource state table is used to record the current state of each type of test resource in the system. The state structure unit of the i-th type of test resource is used to comprehensively describe the schedulable state, allocation capability and real-time use of the resource. Each of the state structure units includes the following fields: a resource type identifier , a current occupation amount , a total capacity , an available amount , and an access flag . The resource state update period can be configured as a fixed interval or can be triggered to refresh by a task event. In a possible implementation, if the available amount of a certain type of resource is less than the total capacity , the resource is marked as an unschedulable state and is not involved in the subsequent matching process.

[0084] In a possible implementation, if the available amount of a certain type of resource is less than the total capacity , the resource is marked as an unschedulable state and is not involved in the subsequent matching process.​​If the resource is not found to be schedulable, it will be marked as unschedulable and will not participate in the subsequent matching process.

[0085] The task matching module is used to match the resource requirements of the test tasks to be scheduled with the current available resource status.

[0086] Specifically, let's say we have a test task. The corresponding resource demand vector is: ; in, Indicates the first Resource requirement vector for each test task; This indicates the total number of test resource types defined in the current system; Indicates test task For the The demand for this type of resource.

[0087] all It is a non-negative number, and the unit is set according to the resource type (such as the number of time slices, the number of channels, etc.); The matching condition is defined as: for all , must meet In other words, a task only enters the schedulable state when all the resources required for the task can be met.

[0088] In some embodiments, to improve scheduling robustness, a partial resource tolerance mechanism can be introduced, that is, when some resources are critically insufficient, the risk of congestion can be mitigated by task segmentation scheduling, resource queuing or resource sharing strategies.

[0089] The scheduling control module is used to determine the actual allocation order and specific execution time of test tasks based on the successful matching of tasks and resources, combined with the aforementioned priority scoring results.

[0090] In one possible implementation, all tasks to be scheduled are first scored according to their priority. Sort the candidates in descending order to form a candidate queue: ; in, Indicates the first One test task awaiting scheduling. , The total number of tasks to be scheduled; Indicates task The priority score is calculated by the aforementioned priority scoring module based on task characteristics (such as time sensitivity, importance, etc.). This indicates that the task queue is sorted in descending order by priority score, and the tasks... Highest priority The priority is the lowest.

[0091] The system tries to match resources in order from the head of the queue, and dispatches the task to the corresponding test unit when the conditions are met.

[0092] As an option, the module can combine a time wheel or dynamic window mechanism to implement priority promotion protection, resource reservation mechanism or back-off rearrangement logic in the high resource contention stage.

[0093] In some cases, to prevent high-priority tasks from occupying resources for a long time and causing low-priority tasks to starve for a long time, a scheduling threshold coefficient can be set, and if the task waiting time is greater than the threshold, the system will forcibly insert the task at the front of the scheduling queue.

[0094] In some embodiments, the resource scheduling module also supports a load balancing strategy, and the resource utilization matrix is used as one of the scheduling references to optimize concurrent resource allocation among different test nodes. The definition is as follows: ; wherein represents the current utilization of the type of resource in the test channel; is the total number of resource types; is the number of test execution channels; the task is preferentially scheduled to a low-utilization node to achieve resource balancing and bottleneck resolution.

[0095] In summary, the resource scheduling module in the embodiment, on the basis of comprehensive analysis of the test task scheduling priority and the current resource available state, completes the dynamic matching and execution scheduling of tasks and resources. The functional sub-modules are connected through standard interfaces, supporting efficient resource scheduling control in a multi-task concurrent environment, and ensuring the stability and continuity of the system simulation test process.

[0096] The test execution and feedback module is used to execute the test task and collect the response data of the circuit board to generate test feedback results; In order to realize the automatic execution and efficient feedback of the test task in the hardware simulation environment, after completing task scheduling and resource matching, the system enters the test execution phase. This phase is completed by the test execution and feedback module, which is a key bridging unit between the task scheduling module and the performance prediction module. Its role is to collect the scheduling execution results of the test task and form data basis that can be used for subsequent analysis. This module not only depends on the task scheduling results and resource configuration state of the front end, but also provides original data support for subsequent performance evaluation and model correction, so it plays a key role in the entire system architecture.

[0097] In the present embodiment, the test execution and feedback module comprises three functional sub-modules: task execution module, response collection module, and result feedback module. The three modules cooperatively constitute a closed-loop system for task execution and feedback. The details are as follows: Task execution module: This module is used to execute the tasks in the task priority queue generated by the scheduling module in sequence. Each task corresponds to a resource requirement vector: ; Wherein: is the demand of the test task for the resource type ; is the total number of resource types, which corresponds to the resource state set in the system; if the condition is met, where is the remaining available amount of the resource, the task enters the execution state.

[0098] Generally, the task execution module will start the signal excitation, test logic, and timing control signal bound to the test task immediately after the scheduling result is issued, thereby driving the circuit board into a controlled test state.

[0099] As an option, in the embodiment supporting multi-stage testing, the task may be divided into multiple stages, and the resource requirement of each stage is represented as: ; Wherein: represents the resource requirement vector of the test task in the th stage; represents the total number of stages into which the test task is divided; represents the total number of resource types defined in the system; represents the occupation requirement of the th resource type (such as logic simulator, vector generator, waveform analyzer, etc.) in the th stage of the task ; wherein , ; the task execution module will reset the corresponding resource state when switching between stages.

[0100] Response collection module: During the execution of the test task, this module is used to sample the response of the circuit board and extract data. Generally, the collection methods can include: State sampling of parallel data bus interface Analog waveform acquisition of ADC (analog-to-digital converter) input channel Logical pull of FPGA output register, etc.

[0101] Specifically, the module defines the target acquisition as the output response of the circuit board under the action of the excitation signal, and the acquisition result forms the original response data set .

[0102] As an option, the response acquisition module can also have built-in response format conversion logic to convert unstructured original response waveform data into standard vector or matrix form for subsequent processing module calls.

[0103] Result feedback module: After acquisition is complete, the result feedback module processes the response data to generate standardized test feedback results . The specific structure is as follows: ; Among them: the measured performance indicators of the task include delay, throughput, power consumption, stability, and other multi-dimensional data; the error information between the measured performance indicators and the predicted values in the performance prediction module , and the calculation formula is as follows: ; In one possible implementation, error calculation supports vectorization operations, so that the system can automatically evaluate test accuracy in a multi-dimensional performance space.

[0104] The result feedback module passes the results to the performance prediction module to realize the correction feedback loop of the original model prediction accuracy.

[0105] As an option, the feedback module can also mark the error cause and report it to the scheduling module when the task fails or the circuit is abnormal, thereby supporting subsequent fault-tolerant rescheduling strategies.

[0106] In some embodiments, the feedback module also supports connection with a database system to archive all test results, providing data accumulation for long-term model training and trend learning.

[0107] In summary, the test execution and feedback module, as the key intermediate layer in the system architecture of the present application, connects the task scheduling logic and performance analysis mechanism, and has three major functions of automatic execution, accurate response acquisition, and feedback loop. During task execution, combined with the task resource demand vector , the resource state set , and the priority queue and error vector to constitute a complete data path structure. The module effectively supports the system to measure and iteratively optimize the complex performance indicators of the circuit board.

[0108] Please refer to Figure 2 The application also provides a circuit board simulation test method, comprising the following steps: S1, collecting environmental parameters of the circuit board under a simulation test scenario; S2, predicting the running performance results of the circuit board based on the environmental parameters; S3, identifying the function items to be tested based on the running performance results, and generating a test task to be executed according to the identification results; S4, extracting scoring factors affecting the scheduling priority of the test task, assigning corresponding weight values to each scoring factor, and calculating the scheduling priority of the test task based on the scoring factors and weight values; S5, according to the scheduling priority, resource matching and scheduling of the test task are performed; S6, executing the test task, collecting the response data of the circuit board, and generating a test feedback result based on the response data.

[0109] For S1, in this step, the system obtains external parameter information closely related to the test through the environment perception module, such as temperature, voltage, humidity, electromagnetic interference level, etc. In some embodiments, auxiliary parameters that affect the running state of the circuit board, such as power supply mode, load configuration, or signal excitation characteristics, can also be further collected.

[0110] For S2, the system calls the performance prediction module to predict the key performance indicators of the circuit board under the current conditions based on the collected environmental parameter information. The prediction results can cover multiple dimensions such as timing characteristics, processing capacity, power consumption behavior, and temperature response.

[0111] For S3, in this step, the system automatically identifies the function modules or boundary scenarios that need to be verified in the current simulation environment by comparing with the performance standards or function specifications. According to the identified key test areas, a corresponding test task set is automatically generated, and the task content includes test type, test signal parameter, expected response characteristics, etc.

[0112] For S4, this step forms a scheduling priority score by evaluating the importance, urgency, resource consumption, dependency relationship, and other scoring factors of each test task. The weight of the scoring factor can be pre-set or dynamically adjusted according to the historical task performance.

[0113] For S5, the scheduling control module performs matching and scheduling operations of the test task according to the task priority, resource requirement of the task and available condition of the current resource pool. In some embodiments, the task can be split into multiple stages for batch scheduling, or the scheduling sequence is adjusted according to the resource conflict condition.

[0114] For S6, in this step, the system drives the target circuit board to execute the preset test task, and collects output response data. The response collection can cover multiple aspects such as logic level change, timing waveform and output state. Subsequently, the system analyzes and processes the collected data to generate a structured test feedback result, which is used for subsequent performance verification or model correction.

[0115] Please refer to Figure 3 The application further provides an electronic device including a memory and a processor. The memory is configured to store a computer program. The processor, when executing the program stored on the memory, implements the circuit board simulation test method in claim 9.

[0116] The electronic device in this embodiment can be used to execute the method embodiments described above, and has similar principles and technical effects, which will not be described here again.

[0117] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A circuit board emulation test system, characterized by, Comprise: a data acquisition module for acquiring environmental parameters of the circuit board under a simulation test scenario; a performance prediction module for predicting and outputting running performance results of the circuit board based on the environmental parameters; a test task generation module for generating test tasks to be executed according to the running performance results; a priority scoring module for calculating scheduling priorities of the test tasks based on multiple influence factors; a resource scheduling module for allocating and scheduling resources for the test tasks based on the scheduling priorities; a test execution and feedback module for executing the test tasks and acquiring response data of the circuit board to generate test feedback results.

2. The circuit board emulation test system of claim 1, wherein, The data acquisition module comprises: a temperature sensing module for acquiring temperature parameters of the environment in which the circuit board is located; a humidity sensing module for acquiring humidity parameters of the environment in which the circuit board is located; a power supply monitoring module for acquiring working voltage and current parameters of the circuit board; a timing signal monitoring module for acquiring timing signal parameters in the process of control and data transmission of the circuit board.

3. The circuit board emulation test system of claim 1, wherein, The performance prediction module comprises: a feature processing module for pre-processing the environmental parameters to extract features required for modeling; a prediction model module for generating running performance results of the circuit board based on the extracted features; an output module for outputting the running performance results as prediction results.

4. The circuit board emulation test system of claim 1, wherein, The test task generation module comprises: a task analysis module for identifying functional items to be tested based on the running performance results; a task construction module for generating corresponding test task data structures according to the functional items; a task output module for outputting the test task data structures as test tasks to be executed; The step of identifying functional items to be tested based on the running performance results comprises: obtaining a set of performance indicators corresponding to each functional unit of the circuit board; Comparing the running performance results with the performance index set, calculate the performance deviation value of each functional unit ; wherein, represents the performance deviation of the i-th functional unit, and the calculation formula is: ； wherein, is a predicted performance value of the functional unit, is a reference standard performance value of the functional unit; based on the deviation value with a preset threshold value judgment, identification ≥ The function item corresponding to the function unit is a to-be-tested function item.

5. The circuit board emulation test system of claim 1, wherein, The priority scoring module comprises: a factor extraction module for extracting scoring factors affecting the scheduling priorities of the test tasks; a weight processing module for assigning corresponding weight values to each scoring factor; a priority calculation module for calculating the scheduling priorities of the test tasks based on the scoring factors and weight values; The scoring factors include task complexity, prediction risk value, resource consumption rate, and deadline urgency, and the calculation formula of the scheduling priorities is: ； wherein, is a score factor, denotes a task complexity factor, denotes a predicted risk value, denotes a resource consumption rate, denotes a deadline urgency, , , , are weight parameters for the respective score factors.

6. The circuit board emulation test system of claim 1, wherein, The resource scheduling module comprises: a resource state monitoring module for monitoring the current occupation state and remaining availability of various test resources; a task matching module for matching available resources according to the resource requirements of the test tasks; a scheduling control module for controlling the allocation and execution order of the test tasks based on the task scheduling priorities.

7. The circuit board emulation test system of claim 1, wherein, The test execution and feedback module comprises: a task execution module for executing the test tasks and controlling the test process according to the scheduling results; a response acquisition module for acquiring response data of the circuit board during the test process; a result feedback module for processing the response data of the circuit board and generating test feedback results, and providing the test feedback results to the performance prediction module.

8. The circuit board emulation test system of claim 7, wherein, The test feedback results include measured performance data of the test tasks and error information between the measured performance data and the prediction results.

9. A method for testing a circuit board simulation, applied to a system for testing a circuit board simulation according to any one of claims 1 to 8, characterized in that, The steps comprise: acquiring environmental parameters of the circuit board under a simulation test scenario; predicting a running performance result of the circuit board based on the environment parameter; identifying a function item to be tested based on the running performance result, and generating a test task to be executed according to the identification result; extracting scoring factors affecting the scheduling priority of the test task, assigning corresponding weight values to each scoring factor, and calculating the scheduling priority of the test task based on the scoring factors and the weight values; matching and scheduling resources for the test task according to the scheduling priority; executing the test task, collecting response data of the circuit board, and generating a test feedback result based on the response data.

10. An electronic device, comprising: comprising a memory and a processor; the memory is used to store a computer program; the processor executes the program stored on the memory, and realizes the circuit board simulation test method in claim 9.

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