Chip control method and device

Abstract

Embodiments of the present disclosure provide a chip control method and device, and relate to the technical field of power consumption management. The method comprises: receiving a first control instruction sent by a measurement and control host; controlling a target controlled chip to execute a target operation corresponding to the first control instruction. A measurement and control module group comprises at least one second measurement and control module selected from a plurality of first measurement and control modules based on the number of bits of a to-be-controlled quantum bit. Each second measurement and control module comprises a control chip and a controlled chip. At least one control chip comprises a target control chip, and at least one controlled chip comprises a target controlled chip. User operation data indicates the number of bits of the to-be-controlled quantum bit. In a case where it is determined that the target controlled chip has finished executing the target operation, the state of the target controlled chip is switched to an off state. In this way, the overall power consumption of the system can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of power management technology, and in particular to a chip control method and apparatus. Background Technology

[0002] The measurement and control system, a key component of a superconducting quantum computer, consists of multiple measurement and control modules responsible for signal generation from the quantum chip and the reading and parsing of computation results. However, as the number of qubits in the quantum chip continues to increase, the demand for measurement and control modules in a superconducting quantum computer also increases linearly, and the application of a large number of measurement and control modules will significantly increase the resource consumption of the entire system. Summary of the Invention

[0003] This disclosure provides a chip control method and apparatus to at least solve the above-mentioned technical problems existing in the prior art.

[0004] In a first aspect, embodiments of this disclosure provide a chip control method applied to a target control chip, the method comprising:

[0005] The system receives a first control command sent by the monitoring and control host. The first control command is determined based on user operation data obtained by the monitoring and control host when multiple first monitoring and control modules associated with the monitoring and control host are in a sleep state.

[0006] The controlled target chip executes the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from multiple first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip. User operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0007] Once it is determined that the target controlled chip has finished performing the target operation, the state of the target controlled chip is switched to the off state.

[0008] Secondly, embodiments of this disclosure provide a chip control method applied to a measurement and control host, the device comprising:

[0009] When multiple first measurement and control modules associated with the measurement and control host are in a dormant state, user operation data is acquired, and the user operation data indicates the number of qubits to be manipulated;

[0010] Based on the number of qubits to be manipulated, a measurement and control module group is obtained by screening multiple first measurement and control modules. The measurement and control module group includes at least one second measurement and control module. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0011] Send a first control command to the target control chip so that the target control chip controls the target controlled chip to execute the target operation corresponding to the first control command, and when it is determined that the target controlled chip has finished executing the target operation, switch the state of the target controlled chip to the off state;

[0012] The first control command is determined based on user operation data; each second measurement and control module includes a control chip and a controlled chip, at least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip.

[0013] Thirdly, embodiments of this disclosure provide a chip control device applied to a target control chip, the device comprising:

[0014] The receiving module is used to receive the first control command sent by the measurement and control host. The first control command is determined based on user operation data obtained by the measurement and control host when multiple first measurement and control modules associated with the measurement and control host are in a sleep state.

[0015] The control module is used to control the target controlled chip to execute the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from multiple first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip. User operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0016] The switching module is used to switch the state of the target controlled chip to the off state when it is determined that the target controlled chip has finished performing the target operation.

[0017] Fourthly, embodiments of this disclosure provide a chip control device applied to a measurement and control host, the device comprising:

[0018] The acquisition module is used to acquire user operation data when multiple first measurement and control modules associated with the measurement and control host are in a dormant state. The user operation data indicates the number of qubits to be manipulated.

[0019] A screening module is used to select a set of measurement and control modules from multiple first measurement and control modules based on the number of qubits to be manipulated. The set of measurement and control modules includes at least one second measurement and control module. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0020] The sending module is used to send a first control command to the target control chip, so that the target control chip controls the target controlled chip to execute the target operation corresponding to the first control command, and when it is determined that the target controlled chip has finished executing the target operation, the module switches the state of the target controlled chip to the off state.

[0021] The first control command is determined based on user operation data; each second measurement and control module includes a control chip and a controlled chip, at least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip.

[0022] Fifthly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the chip control method of the first aspect or the second aspect.

[0023] In a sixth aspect, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute a chip control method according to the first or second aspect.

[0024] Based on the chip control method provided in this disclosure, the measurement and control host can acquire user operation data when multiple first measurement and control modules associated with the host are in a dormant state. Since this user operation data can indicate the number of qubits to be manipulated and other data representing the user's operational intent, the measurement and control host can select a group of measurement and control modules to be operated from the multiple dormant first measurement and control modules based on the number of qubits to be manipulated. Within this group, the host can identify the target control chip to be operated and send a first control command to it. Based on this, the target control chip can control the corresponding target controlled chip to execute the target operation corresponding to the first control command. Upon determining that the target controlled chip has finished executing the target operation, the host switches the target controlled chip to a closed state. In this way, the corresponding measurement and control module (including the aforementioned target control chip and target controlled chip) can be selected and started to execute related operations through user operation data, avoiding the problem of high system resource consumption caused by a large number of inoperable or unusable measurement and control modules being in the start-up state, thereby effectively reducing system resource consumption.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a measurement and control system provided in an embodiment of this disclosure;

[0027] Figure 2 This is one of the interactive schematic diagrams between a measurement and control host and a target control chip provided in this embodiment of the present disclosure;

[0028] Figure 3 This is a second schematic diagram illustrating the interaction between a measurement and control host and a target control chip provided in this embodiment of the present disclosure;

[0029] Figure 4 This is a schematic flowchart of a chip control method provided in an embodiment of this disclosure;

[0030] Figure 5 This is one of the structural schematic diagrams of a chip control device provided in the embodiments of this disclosure;

[0031] Figure 6 This is a second schematic diagram of the structure of a chip control device provided in an embodiment of this disclosure;

[0032] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0033] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0037] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0038] A superconducting quantum computer mainly consists of a quantum chip, a dilution refrigerator, a measurement and control system, and quantum software. Among them, the measurement and control system, as a key component of the superconducting quantum computer, is composed of multiple measurement and control modules. It is mainly responsible for generating signals to control the operation of the quantum chip and reading and analyzing the calculation results of the quantum chip.

[0039] In related technologies, measurement and control systems are mainly built separately based on traditional microwave sources, arbitrary waveform generators, data acquisition cards, and other equipment and instruments. However, this type of measurement and control system suffers from problems such as high cost, large size, inconvenience of use, and difficulty in system integration and management. Therefore, considering the abundant resources and flexible programming of Field Programmable Gate Array (FPGA) chips, measurement and control modules can be built using FPGA chips to replace those built using traditional equipment and instruments. Compared to measurement and control modules built using traditional equipment and instruments, the current method of building measurement and control modules using FPGA chips can effectively solve the aforementioned problems. However, with the continuous increase in the number of qubits in quantum chips, the demand for measurement and control modules in superconducting quantum computers also increases linearly. The use of a large number of measurement and control modules places higher demands on power supply and heat dissipation, resulting in significant overall system resource consumption. Meanwhile, industry efforts are mainly focused on improving the performance and scale of superconducting quantum chips, rather than energy saving and power consumption reduction in measurement and control modules. Therefore, how to effectively reduce the resource consumption of measurement and control modules in superconducting quantum computers is a pressing technical problem that needs to be solved.

[0040] Based on this, the present disclosure provides a chip control method to at least solve the technical problem of high overall resource consumption of the measurement and control system in superconducting quantum computers in the prior art.

[0041] Since the chip control method provided in this disclosure involves the measurement and control system in a superconducting quantum computer, for ease of understanding, before introducing the chip control method provided in this disclosure, we will first refer to the appendix. Figure 1 The measurement and control system involved in the embodiments of this disclosure will be described in detail.

[0042] Figure 1 This is a schematic diagram of the structure of a measurement and control system provided in an embodiment of this disclosure.

[0043] like Figure 1 As shown, the measurement and control system may include a measurement and control host 11 and multiple measurement and control modules 12. The measurement and control host 11 can establish communication connections with the multiple measurement and control modules 12 through network ports, which are not specifically limited here.

[0044] Continue as Figure 1 As shown, each measurement and control module 12 may include a control chip and a controlled chip. The control chip and the controlled chip can communicate according to a preset communication method. The preset communication method may include at least one of the General Purpose Input / Output (GPIO) communication method and the Serial Peripheral Interface (SPI) communication method, without being specifically limited here.

[0045] It should be noted that the aforementioned control chip can be a low-power chip, using an independent power supply separate from the power supply of the controlled chip. Each controlled chip can also be configured with a corresponding power supply circuit and clock circuit. It should also be noted that the control chip can be a microcontroller unit (MUC) management chip, and the controlled chip can be an FPGA chip; no specific limitations are made here.

[0046] Based on such Figure 1 The measurement and control system shown below, with reference to the accompanying drawings, will be described in detail with reference to the chip control method provided in the embodiments of this disclosure.

[0047] Figure 2 This is one of the interactive schematic diagrams between a measurement and control host and a target control chip provided in the embodiments of this disclosure.

[0048] like Figure 2 As shown, the chip control method provided in this embodiment may specifically include the following steps:

[0049] S201, the monitoring and control host acquires user operation data when all the first monitoring and control modules associated with the monitoring and control host are in a dormant state.

[0050] It should be noted that the association between the measurement and control host and the first measurement and control module can be determined based on their connection relationship; that is, the multiple first measurement and control modules associated with the measurement and control host here can be considered as... Figure 1 The multiple measurement and control modules connected to the measurement and control host shown are not specifically limited here. Additionally, user operation data can be data representing the user's operational intent; specifically, user operation data can indicate the number of qubits to be manipulated, which is not specifically limited here.

[0051] Specifically, the control host in the control system can be connected to multiple first control modules. When the control system is not undergoing any testing, these multiple first control modules are in a dormant state. This avoids the consumption of power and other resources caused by multiple first control modules being inactive but in normal startup mode. In this situation, the control host acquires user operation data that represents the user's operational intent, so that the corresponding control module can be selectively activated for data processing based on this user operation data, avoiding resource consumption caused by activating too many control modules.

[0052] S202, the measurement and control host selects a measurement and control module group from multiple first measurement and control modules based on the number of qubits to be manipulated.

[0053] The aforementioned measurement and control module group may include at least one second measurement and control module, which may be a measurement and control module required by the measurement and control system during relevant testing.

[0054] Since the measurement and control host can acquire user operation data that represents the user's operation intention, and the user operation data can indicate the number of bits of the qubit to be manipulated, and the number of bits of the qubit to be manipulated is related to the number of measurement and control modules required during the test (i.e. the number of at least one second measurement and control module mentioned above), the measurement and control host can select at least one second measurement and control module to be used from multiple first measurement and control modules based on the number of bits of the qubit to be manipulated, thus forming a measurement and control module group.

[0055] S203, the monitoring and control host sends the first control command to the target control chip.

[0056] like Figure 1 As shown, each measurement and control module may include a control chip and a controlled chip, and the first measurement and control module in this embodiment is... Figure 1The measurement and control module shown is selected from multiple first measurement and control modules. Therefore, each second measurement and control module can also include a control chip and a controlled chip. Thus, the measurement and control module group can include at least one control chip and at least one controlled chip. The target control chip can be one of the at least one control chips, and correspondingly, the target controlled chip can also be one of the at least one controlled chips. That is, the at least one control chip can include the aforementioned target control chip, and the at least one controlled chip can include the target controlled chip. It should also be noted that the number of target control chips in this embodiment can be at least one, and correspondingly, the number of target controlled chips can also be at least one; no specific limitation is made here.

[0057] Based on this, after obtaining the measurement and control module group, since the measurement and control module group may include at least one control chip and at least one controlled chip, the measurement and control host can select the target control chip to be used and send a first control command to the target control chip to trigger the target control chip to start the corresponding target controlled chip and perform related operations.

[0058] It should also be noted that the aforementioned first control command can be determined based on user operation data obtained by the monitoring and control host when multiple first monitoring and control modules associated with the monitoring and control host are in a dormant state.

[0059] S204, the target control chip controls the target controlled chip to execute the target operation corresponding to the first control instruction.

[0060] After the measurement and control host sends the first control command to the target control chip, the target control chip can receive the first control command and, based on the first control command, control the corresponding target controlled chip to perform the target operation corresponding to the first control command.

[0061] The aforementioned target operation may include the operation of the target controlled chip generating measurement and control waveform data based on the first control command, and may also include the operation of the target controlled chip sending the aforementioned measurement and control waveform data to the quantum chip via a microwave cable connected to the corresponding measurement and control module to control the operation of the quantum chip. It should be noted that the specific content of this target operation may vary depending on the actual situation, and is not specifically limited here.

[0062] S205, when the target control chip determines that the target controlled chip has finished performing the target operation, the target control chip switches the state of the target controlled chip to the off state.

[0063] Specifically, when the target controlled chip finishes performing the target operation, that is, when the target controlled chip enters an idle state, the state of the target controlled chip can be switched to the off state.

[0064] Based on the chip control method provided in this disclosure, the measurement and control host can acquire user operation data when multiple first measurement and control modules associated with the host are in a dormant state. Since this user operation data can indicate the number of qubits to be manipulated and other data representing the user's operational intent, the measurement and control host can select a group of measurement and control modules to be operated from the multiple dormant first measurement and control modules based on the number of qubits to be manipulated. Within this group, the host can identify the target control chip to be operated and send a first control command to it. Based on this, the target control chip can control the corresponding target controlled chip to execute the target operation corresponding to the first control command. Upon determining that the target controlled chip has finished executing the target operation, the host switches the target controlled chip to a closed state. In this way, the corresponding measurement and control module (including the aforementioned target control chip and target controlled chip) can be selected and started to execute related operations through user operation data, avoiding the problem of high system resource consumption caused by a large number of inoperable or unusable measurement and control modules being in the start-up state, thereby effectively reducing system resource consumption.

[0065] Considering that if the target controlled chip is directly switched to the off state upon completion of the target operation (i.e., the target controlled chip is shut down as soon as it enters the idle state), and if the target control chip receives relevant instructions requiring the target controlled chip to perform related actions, this could lead to frequent startups of the target controlled chip, potentially resulting in significant power and resource consumption. Therefore, to further reduce resource consumption, in one embodiment, such as... Figure 3 As shown, the chip control method provided in this embodiment may include the following steps:

[0066] S301, the target control chip sends a notification message to the telemetry and control host after determining that the target controlled chip has finished performing the target operation.

[0067] In some embodiments, the above notification message can be used to notify the monitoring and control host and the target controlled chip that the target operation has been completed.

[0068] S302, the monitoring and control host sends a second control command to the target control chip.

[0069] S303, the target control chip records the idle time of the target controlled chip based on the second control instruction.

[0070] S304, when the idle time of the target controlled chip is longer than the preset idle time, the target control chip switches the state of the target controlled chip to the off state.

[0071] The aforementioned preset idle time can be a duration pre-set based on actual experience or circumstances to determine whether the target controlled chip has been idle for too long; no specific limitation is made here.

[0072] Specifically, the target control chip can send a notification message to the monitoring and control host when it determines that the target controlled chip has finished executing the target operation, informing the monitoring and control host and the target controlled chip that the target operation has been completed, i.e., the current state of the target controlled chip is idle. Then, the monitoring and control host can send a second control command to the target control chip to instruct the next operation. Therefore, after receiving the second control command from the monitoring and control host, the target control chip can record the idle duration of the target controlled chip based on the second control command. If the idle duration of the target controlled chip is longer than a preset idle duration, i.e., the target controlled chip is idle for a relatively long time, the target controlled chip's state is switched to the off state, i.e., the target controlled chip is turned off, thereby avoiding unnecessary power consumption.

[0073] It should be noted that when the target control chip records the idle time of the target controlled chip, it can start a timer based on the second control instruction to record the idle time of the target controlled chip. No specific limitation is made here.

[0074] In this embodiment, once it is determined that the target controlled chip has completed the target operation, the idle time of the target controlled chip is recorded, and if the idle time exceeds a preset idle time, the state of the target controlled chip is switched to the off state. This effectively avoids the problem of excessive power and resource consumption caused by frequent starting and stopping of the target controlled chip in a short period, further reducing system resource consumption.

[0075] In order to effectively switch the state of the target controlled chip to reduce power consumption, in one embodiment, the step of switching the state of the target controlled chip to the off state mentioned above may specifically include the following steps:

[0076] By disabling the state switching circuit of the target controlled chip, the state of the target controlled chip is switched to the off state.

[0077] In some embodiments, the state switching circuit includes at least a power supply circuit and a clock circuit.

[0078] It should be noted here that, as Figure 1As shown, each target controlled chip is equipped with a power supply circuit and a clock circuit. In this embodiment of the disclosure, the power supply circuit and the clock circuit can be used to switch the state of the target controlled chip. Specifically, when the target controlled chip is in the start state, the state of the target controlled chip can be switched from the start state to the stop state by turning off the power supply circuit and the clock circuit of the target controlled chip. When the target controlled chip is in the stop state, the state of the target controlled chip can be switched from the stop state to the start state by enabling the power supply circuit and the clock circuit of the target controlled chip.

[0079] Specifically, the target control chip can switch the target controlled chip to the off state by directly shutting down the state switching circuit of the target controlled chip, i.e., shutting down the power supply circuit and clock circuit of the target control chip, after determining that the target controlled chip has finished performing the target operation, i.e., when the target controlled chip is in an idle state, thereby avoiding unnecessary power consumption.

[0080] Alternatively, the target control chip can, upon determining that the target controlled chip has finished performing the target operation (i.e., when the target controlled chip is in an idle state), receive a second control command from the measurement and control host, record the idle duration of the target controlled chip, and, if the idle duration of the target controlled chip is longer than a preset idle duration (i.e., when the target controlled chip is in an idle state and has been idle for a relatively long time), switch the state of the target controlled chip to the off state by turning off the state switching circuit of the target controlled chip (i.e., turning off the power supply circuit and clock circuit of the target control chip), thereby avoiding unnecessary power consumption.

[0081] In this embodiment, when the target controlled chip is in an idle state or the idle time of the target controlled chip is long, the state switching circuit, including the power supply circuit and clock circuit of the target controlled chip, can be turned off to switch the state of the target controlled chip to a shut-off state, thereby avoiding unnecessary power consumption and effectively reducing system power consumption.

[0082] In addition, to further reduce system power consumption effectively, in one embodiment, the target controlled chip may include multiple components. Based on this, the chip control method provided in this disclosure embodiment may further include the following steps:

[0083] Based on the first control instruction, identify the idle component among multiple components during the execution of the target operation by the target controlled chip;

[0084] During the execution of the target operation by the target controlled chip, the idle components are controlled to enter a low-power state.

[0085] Specifically, after receiving the first control command from the telemetry and control host, the target control chip can determine, based on the first control command, the idle components among the multiple components included in the target controlled chip during the execution of the target operation by the target controlled chip; that is, the idle resources in the target controlled chip during the execution of the target operation. Based on this, during the execution of the target operation by the target controlled chip, the idle components can be controlled to enter a low-power state to reduce power consumption.

[0086] In this embodiment, by identifying idle components during the execution of a target operation by the target controlled chip and controlling these idle components to enter a low-power state, unnecessary power consumption is avoided, and system power consumption is effectively reduced.

[0087] Based on this, in one embodiment, the step of controlling the idle component to enter a low-power state may specifically include the following steps:

[0088] Idle components are controlled to enter a low-power state according to a preset method.

[0089] In some embodiments, the aforementioned preset methods may include FPGA register control enable method, general purpose input / output (GPIO) control enable method, or FPGA input clock control enable method. It should be noted that the specific preset method used may depend on the support capabilities of different types of target controlled chips, which will not be elaborated upon here.

[0090] Specifically, after identifying the idle component of the target controlled chip during the execution of the target operation, the idle component can be controlled to enter a low-power state by means of FPGA register control enable mode, general purpose input / output port (GPIO) control enable mode, or FPGA input clock control enable mode.

[0091] In this embodiment, the target controlled chip can be accurately controlled to enter a low-power state by means of FPGA register control enable mode, GPIO control enable mode or FPGA input clock control enable mode, thereby avoiding unnecessary power consumption and effectively reducing system power consumption.

[0092] To accurately and comprehensively describe the chip control method provided in the embodiments of this disclosure, in one embodiment, the aforementioned user operation data may further include multiple test instructions. Thus, when the measurement and control module group includes at least two second measurement and control modules, before sending the first control instruction to the target control chip, such as... Figure 4 As shown, the chip control method provided in this embodiment may further include the following steps:

[0093] S410 obtains the execution order of multiple test instructions.

[0094] The execution order mentioned above can be obtained by arbitrarily arranging and combining the multiple test instructions; no specific limitation is made here. Since different test instructions involve different test items and use different measurement and control modules, and the execution of different test instructions involves the state switching of different measurement and control modules, the overall power consumption of the system may also change under different execution orders. Therefore, different execution orders of multiple test instructions correspond to different power consumption.

[0095] S420 determines the target execution order from multiple execution orders that meets the preset power consumption conditions.

[0096] The preset power consumption conditions can be set in advance based on actual conditions, and no specific restrictions are made here.

[0097] S430 selects the target measurement and control module from at least two second measurement and control modules to execute the target test command.

[0098] In some embodiments, the target measurement and control module includes a target control chip and a target controlled chip. Furthermore, the target test instructions are instructions to be executed sequentially from a plurality of test instructions according to the target execution order.

[0099] Specifically, since user operation data can include multiple test instructions, when the measurement and control module group includes at least two second measurement and control modules, the measurement and control host can obtain multiple execution sequences of the multiple test instructions and determine the target execution sequence from the multiple execution sequences that meets the preset conditions for power consumption. Then, in the process of executing the corresponding test instructions according to the target execution sequence, the host can determine the current instruction to be executed, i.e. the target test instruction, and then select the target measurement and control module to execute the target test instruction from the at least two second measurement and control modules, thereby starting the corresponding target control chip and target controlled chip.

[0100] In this embodiment, based on multiple test instructions included in the user operation data, a target execution order that meets preset power consumption conditions can be selected from multiple execution sequences of these test instructions. Furthermore, the corresponding target control chip and target controlled chip can be activated based on this target execution order. In this way, relevant chips can be activated selectively based on the user operation data, avoiding excessive chip activation and thus reducing resource consumption and effectively lowering system power consumption.

[0101] In order to accurately select the target execution order that meets the preset power consumption condition from multiple execution orders, in one embodiment, the above-mentioned S420 may specifically include the following steps:

[0102] Calculate the power consumption value corresponding to each execution sequence;

[0103] Based on the power consumption value corresponding to each execution order, the execution order that satisfies the preset power consumption condition is determined from multiple execution orders as the target execution order.

[0104] In this embodiment of the disclosure, the preset power consumption condition can be the execution order with the lowest power consumption value determined from the plurality of execution orders, and no specific limitation is made here.

[0105] Specifically, after acquiring multiple execution sequences, the monitoring and control host can calculate the power consumption value corresponding to each execution sequence, and then, based on the power consumption value corresponding to each execution sequence, determine the execution sequence whose power consumption meets the preset power consumption condition as the target execution sequence from among the multiple execution sequences.

[0106] It should be noted that in the chip control method provided in this disclosure embodiment, the power consumption value corresponding to each execution sequence can be calculated by using a power consumption calculation model trained based on historical data or by selecting a suitable power consumption algorithm; no specific limitation is made here.

[0107] In this embodiment, by calculating the power consumption value of each execution sequence, a target execution sequence whose power consumption value meets the preset power consumption conditions can be selected from the multiple execution sequences. This facilitates the targeted activation of relevant chips for subsequent operations, avoiding the problem of excessive chip activation leading to large resource consumption and effectively reducing system consumption.

[0108] In another embodiment, the above-described S420 may specifically include the following steps:

[0109] For the I-th test instruction in the first execution order, determine the third measurement and control module required for the execution of the test instruction, where I is a positive integer and the first execution order is any one of multiple execution orders;

[0110] Determine the fourth measurement and control module required for the execution of at least two first test instructions, wherein the at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of the plurality of test instructions;

[0111] For each first test instruction, calculate the module usage similarity between the third measurement and control module required for the execution of the test instruction and the fourth measurement and control module corresponding to the first test instruction, and obtain at least two module similarities;

[0112] Based on the similarity of at least two modules, the first test instruction with the highest module similarity among the first test instructions is updated to the (I+1)th test instruction in the first execution order, and I is updated to I+1. Then, the steps for executing the I-th test instruction in the first execution order to determine the third measurement and control module required for the execution of the test instruction are returned until I equals N-1, and the execution stops, thus obtaining the target execution order in which the power consumption meets the preset power consumption condition.

[0113] Specifically, an execution order can be arbitrarily selected from multiple execution orders, namely the first execution order. For the I-th test instruction in the first execution order, the third measurement and control module required for the I-th test instruction is determined, and the fourth measurement and control module required for the execution of at least two first test instructions is determined respectively. In this way, by calculating the similarity between the fourth measurement and control module and the third measurement and control module corresponding to each first test instruction, the (I+1)-th test instruction in the first execution order with the highest similarity can be selected, I+1 is updated, and the step of determining the third measurement and control module required for the execution of the I-th test instruction in the first execution order is returned, until I equals N-1 and stops. In this way, the target execution order that meets the preset power consumption condition can be obtained.

[0114] In this embodiment, for any execution sequence, the similarity between the current instruction and the measurement and control modules required for the execution of the remaining instructions can be calculated. Based on this similarity, the next instruction in the execution sequence can be determined, thereby adjusting the execution sequence and obtaining the target execution power consumption that meets preset conditions. This facilitates the targeted activation of relevant chips for subsequent operations, avoiding the problem of excessive chip activation leading to high resource consumption and effectively reducing system power consumption.

[0115] Based on the same inventive concept, this disclosure provides a chip control device that can be applied to a measurement and control host computer, as detailed in the accompanying drawings. Figure 5 A chip control device provided in the embodiments of this disclosure will be described in detail.

[0116] Figure 5 This is a schematic diagram of the structure of a chip control device provided in an embodiment of this disclosure.

[0117] like Figure 5 As shown, the chip control device 500 may include:

[0118] The receiving module 510 is used to receive a first control command sent by the measurement and control host. The first control command is determined based on user operation data obtained by the measurement and control host when multiple first measurement and control modules associated with the measurement and control host are in a sleep state.

[0119] The control module 520 is used to control the target controlled chip to execute the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from multiple first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip. User operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0120] The switching module 530 is used to switch the state of the target controlled chip to the off state when it is determined that the target controlled chip has finished performing the target operation.

[0121] In one embodiment, the chip control device provided in this disclosure may include:

[0122] The sending module is used to send a notification message to the telemetry and control host when it is determined that the target controlled chip has finished performing the target operation. The notification message is used to notify the telemetry and control host and the target controlled chip that the target operation has been completed.

[0123] The receiving module is also used to receive the second control command sent by the measurement and control host;

[0124] The recording module is used to record the idle time of the target controlled chip based on the second control command;

[0125] The switching module is specifically used to switch the state of the target controlled chip to the off state when the idle time of the target controlled chip is longer than the preset idle time.

[0126] In one embodiment, the chip control device provided in this disclosure may include:

[0127] The switching module is specifically used to switch the state of the target controlled chip to the off state by turning off the state switching circuit of the target controlled chip. The state switching circuit includes at least a power supply circuit and a clock circuit.

[0128] In one embodiment, the target controlled chip includes multiple components; based on this, the chip control device provided in this disclosure embodiment may include:

[0129] The determination module is used to determine, based on the first control instruction, the idle component among multiple components during the execution of the target operation by the target controlled chip;

[0130] The control module is also used to control idle components to enter a low-power state during the execution of target operations by the target controlled chip.

[0131] In one embodiment, the chip control device provided in this disclosure may include:

[0132] The control module is used to control idle components to enter a low-power state according to preset methods; the preset methods include FPGA register control enable mode, general purpose input / output port (GPIO) control enable mode, or FPGA input clock control enable mode.

[0133] It is understood that, when implementing the corresponding chip control method, the chip control device provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the device and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0134] Based on the same inventive concept, this disclosure provides a chip control device that can be applied to a target control chip, and can be specifically described in conjunction with the appendix. Figure 6 A chip control device provided in the embodiments of this disclosure will be described in detail.

[0135] Figure 6 This is a schematic diagram of the structure of a chip control device provided in an embodiment of this disclosure.

[0136] like Figure 6 As shown, the chip control device 600 may include:

[0137] The acquisition module 610 is used to acquire user operation data when multiple first measurement and control modules associated with the measurement and control host are in a sleep state. The user operation data indicates the number of qubits to be manipulated.

[0138] The screening module 620 is used to select a group of measurement and control modules from multiple first measurement and control modules based on the number of qubits to be manipulated. The group of measurement and control modules includes at least one second measurement and control module. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0139] The sending module 630 is used to send a first control command to the target control chip, so that the target control chip controls the target controlled chip to execute the target operation corresponding to the first control command, and when it is determined that the target controlled chip has finished executing the target operation, the state of the target controlled chip is switched to the off state;

[0140] The first control command is determined based on user operation data; each second measurement and control module includes a control chip and a controlled chip, at least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip.

[0141] In one embodiment, the chip control device provided in this disclosure may include:

[0142] The receiving module is used to receive notification messages sent by the target control chip. The notification message is sent by the target control chip to the measurement and control host after determining that the target controlled chip has finished performing the target operation. The notification message is used to notify the measurement and control host and the target controlled chip that the target operation has been completed.

[0143] The sending module is also used to send a second control command to the target control chip, so that the target control chip records the idle time of the target controlled chip based on the second control command, and switches the state of the target controlled chip to the off state when the idle time of the target controlled chip is longer than the preset idle time.

[0144] In one embodiment, the user operation data includes multiple test instructions, and the measurement and control module group includes at least two second measurement and control modules; based on this, the chip control device provided in this disclosure embodiment includes:

[0145] The acquisition module is also used to acquire the execution order of multiple test instructions; different execution orders of multiple test instructions correspond to different power consumption.

[0146] The determination module is used to determine the target execution order from multiple execution orders, which satisfies the preset power consumption conditions;

[0147] The filtering module is also used to filter the target measurement and control module for executing the target test instructions from at least two second measurement and control modules. The target measurement and control module includes a target control chip and a target controlled chip. The target test instructions are instructions to be executed sequentially from multiple test instructions according to the target execution order.

[0148] In one embodiment, the chip control device provided in this disclosure may include:

[0149] The calculation module is used to calculate the power consumption value corresponding to each execution sequence;

[0150] The determination module is specifically used to determine the target execution order from multiple execution orders based on the power consumption value corresponding to each execution order.

[0151] In one embodiment, the chip control device provided in this disclosure may include:

[0152] The determination module is specifically used to determine the third measurement and control module required for the execution of the I-th test instruction in the first execution order, where I is a positive integer and the first execution order is any one of multiple execution orders;

[0153] The determination module is specifically used to determine the fourth measurement and control module required for the execution of at least two first test instructions. The at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of multiple test instructions.

[0154] The calculation module is used to calculate the module usage similarity between the third measurement and control module required for the execution of the test instruction and the fourth measurement and control module corresponding to the first test instruction for each first test instruction, so as to obtain at least two module similarities;

[0155] The determination module is specifically used to update the first test instruction with the highest module similarity among the first test instructions in the first execution order based on the similarity of at least two modules, and update I=I+1 and return to execute the steps of the third measurement and control module required for the execution of the test instruction for the I-th test instruction in the first execution order, until I equals N-1, and then stop to obtain the target execution order in which the power consumption meets the preset power consumption condition.

[0156] It is understood that, when implementing the corresponding chip control method, the chip control device provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the device and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0157] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a chip control method.

[0158] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the chip control method provided in this application.

[0159] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0160] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0161] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0162] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0163] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 7 As shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform:

[0164] The system receives a first control command sent by the monitoring and control host. The first control command is determined based on user operation data obtained by the monitoring and control host when multiple first monitoring and control modules associated with the monitoring and control host are in a sleep state.

[0165] The controlled target chip executes the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from multiple first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes a target control chip, and at least one controlled chip includes a target controlled chip. User operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of at least one second measurement and control module.

[0166] Once it is determined that the target controlled chip has finished performing the target operation, the state of the target controlled chip is switched to the off state.

[0167] The electronic devices and corresponding chip control methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0168] In practical applications, the electronic device 70 may further include at least one network interface 703. The various components of the electronic device 70 are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 All buses are labeled as bus system 704. The number of processors 701 and the number of memories 702 can be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

[0169] The memory 702 in this embodiment is used to store various types of data to support the operation of the electronic device 70.

[0170] The methods disclosed in the above embodiments of this disclosure can be applied to processor 701, or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in the form of software. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 702. Processor 701 reads the information in memory 702 and, in conjunction with its hardware, completes the steps of the aforementioned chip control method.

[0171] In some embodiments, the electronic device 70 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0172] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0173] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0174] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0175] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0176] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0177] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip control method, characterized in that, Applied to a target control chip, the method includes: The system receives a first control command sent by the measurement and control host. The first control command is determined based on user operation data obtained by the measurement and control host when all of the multiple first measurement and control modules associated with the measurement and control host are in a sleep state. The measurement and control system of the superconducting quantum computer includes the measurement and control host and the multiple first measurement and control modules. The control target controlled chip executes the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from the plurality of first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes the target control chip, and at least one controlled chip includes the target controlled chip. The user operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of the at least one second measurement and control module. If it is determined that the target controlled chip has finished performing the target operation, the state of the target controlled chip is switched to the off state; The user operation data includes multiple test commands, and the measurement and control module group includes at least two second measurement and control modules; the measurement and control host determines the target control chip and the target controlled chip after executing the following steps: The execution order of the multiple test instructions is obtained; different execution orders of the multiple test instructions correspond to different power consumption. Determine the target execution order whose power consumption meets the preset power consumption condition from the plurality of execution orders; Select a target measurement and control module from the at least two second measurement and control modules to execute the target test instruction. The target measurement and control module includes the target control chip and the target controlled chip. The target test instruction is an instruction to be executed determined sequentially from the plurality of test instructions according to the target execution order. Determining the target execution order from the plurality of execution orders that satisfies the preset power consumption condition includes: For the I-th test instruction in the first execution order, determine the third measurement and control module required for the execution of the test instruction, where I is a positive integer, and the first execution order is any one of the plurality of execution orders; Determine the fourth measurement and control module required for the execution of at least two first test instructions, wherein the at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of the plurality of test instructions; For each of the first test instructions, the module usage similarity between the third measurement and control module required to execute the test instruction and the fourth measurement and control module corresponding to the first test instruction is calculated to obtain at least two module similarities; Based on the similarity of the at least two modules, the first test instruction with the highest module similarity among the at least two first test instructions is updated to the (I+1)th test instruction in the first execution order, and I is updated to I+1. The steps for executing the I-th test instruction in the first execution order to determine the third measurement and control module required for the execution of the test instruction are returned until I equals N-1, and the execution order that satisfies the preset power consumption condition is obtained.

2. The method according to claim 1, characterized in that, The step of switching the state of the target controlled chip to the off state when it is determined that the target controlled chip has finished performing the target operation includes: Upon determining that the target controlled chip has finished executing the target operation, a notification message is sent to the measurement and control host. The notification message is used to notify the measurement and control host and the target controlled chip that the target operation has been completed. Receive the second control command sent by the monitoring and control host; Based on the second control command, the idle time of the target controlled chip is recorded; If the idle time of the target controlled chip is longer than a preset idle time, the state of the target controlled chip is switched to the off state.

3. The method according to claim 1 or 2, characterized in that, Switching the state of the target controlled chip to the off state includes: By disabling the state switching circuit of the target controlled chip, the state of the target controlled chip is switched to the off state. The state switching circuit includes at least a power supply circuit and a clock circuit.

4. The method according to claim 1, characterized in that, The target controlled chip includes multiple components; after receiving the first control command sent by the monitoring and control host, the method further includes: Based on the first control instruction, determine the idle component among the plurality of components during the process of the target controlled chip performing the target operation; During the execution of the target operation by the target controlled chip, the idle component is controlled to enter a low-power state.

5. The method according to claim 4, characterized in that, The control of the idle component to enter a low-power state includes: The idle components are controlled to enter a low-power state according to a preset method; the preset method includes FPGA register control enable method, general purpose input / output port (GPIO) control enable method, or FPGA input clock control enable method.

6. A chip control method, characterized in that, Applied to a measurement and control host, the method includes: When all the first measurement and control modules associated with the measurement and control host are in a dormant state, user operation data is acquired. The user operation data indicates the number of qubits to be manipulated. The measurement and control system of the superconducting quantum computer includes the measurement and control host and the multiple first measurement and control modules. Based on the number of qubits to be manipulated, a measurement and control module group is obtained by screening from the plurality of first measurement and control modules. The measurement and control module group includes at least one second measurement and control module. The number of qubits to be manipulated is related to the number of the at least one second measurement and control module. A first control command is sent to the target control chip to control the target controlled chip to execute the target operation corresponding to the first control command, and when it is determined that the target controlled chip has finished executing the target operation, the state of the target controlled chip is switched to the off state; The first control command is determined based on the user operation data; each of the second measurement and control modules includes a control chip and a controlled chip, at least one control chip includes the target control chip, and at least one controlled chip includes the target controlled chip. The user operation data includes multiple test commands, and the measurement and control module group includes at least two second measurement and control modules; before sending the first control command to the target control chip, the method further includes: The execution order of the multiple test instructions is obtained; different execution orders of the multiple test instructions correspond to different power consumption. Determine the target execution order whose power consumption meets the preset power consumption condition from the plurality of execution orders; Select a target measurement and control module from the at least two second measurement and control modules to execute the target test instruction. The target measurement and control module includes the target control chip and the target controlled chip. The target test instruction is an instruction to be executed determined sequentially from the plurality of test instructions according to the target execution order. Determining the target execution order from the plurality of execution orders that satisfies the preset power consumption condition includes: For the I-th test instruction in the first execution order, determine the third measurement and control module required for the execution of the test instruction, where I is a positive integer, and the first execution order is any one of the plurality of execution orders; Determine the fourth measurement and control module required for the execution of at least two first test instructions, wherein the at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of the plurality of test instructions; For each of the first test instructions, the module usage similarity between the third measurement and control module required to execute the test instruction and the fourth measurement and control module corresponding to the first test instruction is calculated to obtain at least two module similarities; Based on the similarity of the at least two modules, the first test instruction with the highest module similarity among the at least two first test instructions is updated to the (I+1)th test instruction in the first execution order, and I is updated to I+1. The steps for executing the I-th test instruction in the first execution order to determine the third measurement and control module required for the execution of the test instruction are returned until I equals N-1, and the execution order that satisfies the preset power consumption condition is obtained.

7. The method according to claim 6, characterized in that, The method further includes: The system receives a notification message sent by the target control chip. The notification message is sent by the target control chip to the measurement and control host after determining that the target controlled chip has finished performing the target operation. The notification message is used to notify the measurement and control host and the target controlled chip that the target operation has been completed. A second control command is sent to the target control chip, so that the target control chip records the idle time of the target controlled chip based on the second control command, and switches the state of the target controlled chip to the off state if the idle time of the target controlled chip is longer than a preset idle time.

8. The method according to claim 6, characterized in that, Determining the target execution order from the plurality of execution orders that satisfies the preset power consumption condition includes: Calculate the power consumption value corresponding to each of the execution sequences; Based on the power consumption value corresponding to each execution order, the execution order that satisfies the preset power consumption condition is determined from the plurality of execution orders as the target execution order.

9. A chip control device, characterized in that, The device, applied to a target control chip, includes: A receiving module is used to receive a first control command sent by the measurement and control host. The first control command is determined based on user operation data obtained by the measurement and control host when all of the multiple first measurement and control modules associated with the measurement and control host are in a sleep state. The measurement and control system of the superconducting quantum computer includes the measurement and control host and the multiple first measurement and control modules. The control module is used to control the target controlled chip to execute the target operation corresponding to the first control instruction. The measurement and control module group includes at least one second measurement and control module selected from the plurality of first measurement and control modules based on the number of qubits to be manipulated. Each second measurement and control module includes a control chip and a controlled chip. At least one control chip includes the target control chip, and at least one controlled chip includes the target controlled chip. The user operation data indicates the number of qubits to be manipulated. The number of qubits to be manipulated is related to the number of the at least one second measurement and control module. The switching module is used to switch the state of the target controlled chip to the off state when it is determined that the target controlled chip has finished performing the target operation; The user operation data includes multiple test commands, and the measurement and control module group includes at least two second measurement and control modules; the measurement and control host determines the target control chip and the target controlled chip after executing the following steps: The execution order of the multiple test instructions is obtained; different execution orders of the multiple test instructions correspond to different power consumption. Determine the target execution order whose power consumption meets the preset power consumption condition from the plurality of execution orders; Select a target measurement and control module from the at least two second measurement and control modules to execute the target test instruction. The target measurement and control module includes the target control chip and the target controlled chip. The target test instruction is an instruction to be executed determined sequentially from the plurality of test instructions according to the target execution order. Determining the target execution order from the plurality of execution orders that satisfies the preset power consumption condition includes: For the I-th test instruction in the first execution order, determine the third measurement and control module required for the execution of the test instruction, where I is a positive integer, and the first execution order is any one of the plurality of execution orders; Determine the fourth measurement and control module required for the execution of at least two first test instructions, wherein the at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of the plurality of test instructions; For each of the first test instructions, the module usage similarity between the third measurement and control module required to execute the test instruction and the fourth measurement and control module corresponding to the first test instruction is calculated to obtain at least two module similarities; Based on the similarity of the at least two modules, the first test instruction with the highest module similarity among the at least two first test instructions is updated to the (I+1)th test instruction in the first execution order, and I is updated to I+1. The steps for executing the I-th test instruction in the first execution order to determine the third measurement and control module required for the execution of the test instruction are returned until I equals N-1, and the execution order that satisfies the preset power consumption condition is obtained.

10. The apparatus according to claim 9, characterized in that, The device includes: The sending module is used to send a notification message to the measurement and control host when it is determined that the target controlled chip has finished performing the target operation. The notification message is used to notify the measurement and control host and the target controlled chip that the target operation has been completed. The receiving module is also used to receive a second control command sent by the measurement and control host; A recording module is used to record the idle time of the target controlled chip based on the second control command; The switching module is specifically used to switch the state of the target controlled chip to the off state when the idle time of the target controlled chip is longer than a preset idle time.

11. The apparatus according to claim 9 or 10, characterized in that, The device includes: The switching module is specifically used to switch the state of the target controlled chip to the off state by turning off the state switching circuit of the target controlled chip. The state switching circuit includes at least a power supply circuit and a clock circuit.

12. The apparatus according to claim 9, characterized in that, The target controlled chip includes multiple components; the device includes: The determining module is configured to determine, based on the first control instruction, an idle component among the plurality of components during the process of the target controlled chip performing the target operation; The control module is also used to control the idle component to enter a low-power state during the process of the target controlled chip performing the target operation.

13. The apparatus according to claim 12, characterized in that, The device includes: The control module is used to control the idle component to enter a low-power state according to a preset method; the preset method includes FPGA register control enable mode, general purpose input / output port (GPIO) control enable mode, or FPGA input clock control enable mode.

14. A chip control device, characterized in that, The device, applied to a measurement and control host, includes: The acquisition module is used to acquire user operation data when the multiple first measurement and control modules associated with the measurement and control host are all in a dormant state. The user operation data indicates the number of qubits to be manipulated. The measurement and control system of the superconducting quantum computer includes the measurement and control host and the multiple first measurement and control modules. A screening module is used to select a set of measurement and control modules from the plurality of first measurement and control modules based on the number of qubits to be manipulated. The set of measurement and control modules includes at least one second measurement and control module. The number of qubits to be manipulated is related to the number of the at least one second measurement and control module. The sending module is used to send a first control command to the target control chip, so that the target control chip controls the target controlled chip to perform the target operation corresponding to the first control command, and when it is determined that the target controlled chip has finished performing the target operation, the module switches the state of the target controlled chip to the off state; The first control command is determined based on the user operation data; each of the second measurement and control modules includes a control chip and a controlled chip, at least one control chip includes the target control chip, and at least one controlled chip includes the target controlled chip. The user operation data includes multiple test commands, and the measurement and control module group includes at least two second measurement and control modules; the device includes: The acquisition module is also used to acquire multiple execution orders of the multiple test instructions; different execution orders of the multiple test instructions correspond to different power consumption. The determining module is used to determine, from the plurality of execution sequences, a target execution sequence in which the power consumption meets a preset power consumption condition; The filtering module is further configured to filter a target measurement and control module for executing target test instructions from the at least two second measurement and control modules. The target measurement and control module includes the target control chip and the target controlled chip. The target test instructions are instructions to be executed sequentially determined from the plurality of test instructions according to the target execution order. The device includes: The determining module is specifically used to determine the third measurement and control module required for the execution of the I-th test instruction in the first execution order, where I is a positive integer and the first execution order is any one of the plurality of execution orders; The determining module is specifically used to determine the fourth measurement and control module required for the execution of at least two first test instructions. The at least two first test instructions include all test instructions from the (I+1)th test instruction to the Nth test instruction, where N is the number of the plurality of test instructions. The calculation module is used to calculate, for each first test instruction, the module usage similarity between the third measurement and control module required for the execution of the test instruction and the fourth measurement and control module corresponding to the first test instruction, and to obtain at least two module similarities. The determination module is specifically used to update the first test instruction with the highest module similarity among the at least two first test instructions to the (I+1)th test instruction in the first execution order based on the similarity of the at least two modules, update I=I+1, and return to execute the step of determining the third measurement and control module required for the execution of the I-th test instruction in the first execution order, until I equals N-1, and stop to obtain the target execution order in which the power consumption meets the preset power consumption condition.

15. The apparatus according to claim 14, characterized in that, The device includes: A receiving module is used to receive a notification message sent by the target control chip. The notification message is sent by the target control chip to the measurement and control host after determining that the target controlled chip has finished performing the target operation. The notification message is used to notify the measurement and control host and the target controlled chip that the target operation has been completed. The sending module is further configured to send a second control command to the target control chip, so that the target control chip records the idle time of the target controlled chip based on the second control command, and switches the state of the target controlled chip to the off state when the idle time of the target controlled chip is longer than a preset idle time.

16. The apparatus according to claim 14, characterized in that, The device includes: The calculation module is used to calculate the power consumption value corresponding to each of the execution sequences; The determining module is specifically used to determine, based on the power consumption value corresponding to each of the execution sequences, the execution sequence whose power consumption satisfies the preset power consumption condition as the target execution sequence from the plurality of execution sequences.

Images