A graphics processor correctable error processing method and electronic device

Abstract

The application discloses a graphics processor correctable error processing method and electronic equipment, relates to the technical field of servers, and determines a flexible correctable error processing strategy for a graphics processor from the dual angles of error reporting time and error reporting frequency, greatly reduces the occupation of processor and bus resources by correctable error processing, and based on an intelligent time window and time threshold mechanism, can distinguish transient interference from hardware failure, avoids excessive interference of accidental errors on the system, and can early warn hardware degradation problems, so that sufficient time is obtained for system maintenance.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a graphics processor error correction method and electronic device. Background Technology

[0002] High-speed data transmission between the graphics processor and the host is achieved via the PCIe (Peripheral Component Interconnect Express) bus. However, due to the heavy workload and frequent data transmission of the graphics processor, its PCIe link is more prone to correctable errors. Currently, the common approach to handling correctable errors in the graphics processor's PCIe link is to respond immediately and trigger correction. This approach has the following problems: (1) Significant performance impact: The graphics processor has extremely high requirements for the real-time and continuous nature of data transmission. Frequent correctable error handling will cause the graphics processor's computing tasks to be interrupted, increase data processing latency, reduce the graphics rendering frame rate, and affect the user experience; (2) Serious resource waste: Correctable errors that recur in a short period of time are often caused by transient interference. Immediately correcting these errors will consume a lot of system resources, resulting in unnecessary waste. Summary of the Invention

[0003] This application provides a method and electronic device for correcting errors in a graphics processor, in order to at least solve the problems of affecting system performance and wasting system resources in the related art.

[0004] This application provides a method for handling correctable errors in a graphics processor. The method includes: in response to a system management interrupt being triggered by the current system, determining the faulty device that caused the interruption and the type of error; in response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, acquiring an error timestamp variable and a cumulative error count variable, determining a first error timestamp based on the current value of the error timestamp variable, and determining a first cumulative error count based on the current value of the cumulative error count variable; determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and performing the corresponding correctable error handling operation based on the second cumulative error count.

[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program and implementing at least the following steps of a graphics processor correctable error processing method: in response to a system management interrupt triggered by the current system, determining the faulty device that caused the system management interrupt to be triggered, and simultaneously determining the error type that caused the system management interrupt to be triggered; in response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, acquiring an error timestamp variable and a cumulative error count variable, and determining a first error timestamp based on the current value of the error timestamp variable, and simultaneously determining a first cumulative error count based on the current value of the cumulative error count variable; determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and performing a corresponding correctable error processing operation based on the second cumulative error count.

[0006] This application establishes a flexible error correction handling strategy for graphics processors from the dual perspectives of error time and error count, significantly reducing the impact of error correction handling on processor and bus resources. Based on an intelligent time window and time threshold mechanism, this application can distinguish between transient interference and hardware failure, avoiding excessive interference from occasional errors on the system and providing early warning of hardware degradation issues, thus gaining sufficient time for system maintenance. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a simplified flowchart of the error correction method of the graphics processor in the first embodiment;

[0009] Figure 2 This is a detailed flowchart of the error correction method of the graphics processor in the first embodiment;

[0010] Figure 3 This is a flowchart illustrating the power-on self-test steps in the first embodiment;

[0011] Figure 4 This is a structural block diagram of the error-correcting processing device of the graphics processor in the second embodiment;

[0012] Figure 5This is a diagram of the internal structure of the electronic device in the third embodiment. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] In the first embodiment, such as Figure 1 As shown, a method for handling correctable errors in a graphics processor is provided. The method includes: in response to a system management interrupt being triggered by the current system, determining the faulty device that caused the interruption and the type of error; in response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, acquiring an error timestamp variable and a cumulative error count variable, determining a first error timestamp based on the current value of the error timestamp variable, and determining a first cumulative error count based on the current value of the cumulative error count variable; determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and performing the corresponding correctable error handling operation based on the second cumulative error count.

[0017] Specifically, for graphics processors, a flexible error correction handling strategy is determined from the dual perspectives of error time and error count, which significantly reduces the occupation of processor and bus resources by error correction handling. Based on the intelligent time window and time threshold mechanism, this application can distinguish between transient interference and hardware failure, which not only avoids excessive interference of occasional errors to the system, but also provides early warning of hardware degradation problems, thus gaining sufficient time for system maintenance.

[0018] Furthermore, such as Figure 2 As shown, the method for processing correctable errors in a graphics processor further includes: in response to the first occurrence of a correctable error in the erroneous device, obtaining a cumulative error count variable, and determining an initial cumulative error count based on the current value of the cumulative error count variable, wherein the initial cumulative error count is a first preset value; obtaining a third cumulative error count based on the initial cumulative error count and a second preset value, and saving the third cumulative error count to the cumulative error count variable, wherein the third cumulative error count represents the cumulative error count corresponding to the current correctable error; determining a third error timestamp, and saving the third error timestamp to an error timestamp variable, wherein the third error timestamp represents the error timestamp corresponding to the current correctable error.

[0019] In a specific embodiment, the first preset value is 0, and the second preset value is 1. The timestamp corresponding to the correctable error is determined by reading the processor's internal clock.

[0020] Furthermore, such as Figure 3 As shown, before the current system triggers a system management interrupt, the error correction method for the graphics processor further includes: traversing multiple high-speed expansion devices in the current system to obtain multiple configuration spaces, wherein the multiple high-speed expansion devices correspond one-to-one with the multiple configuration spaces; extracting a first number and a second number from the configuration space, wherein the first number and the second number are unique for the high-speed expansion device; and determining one or more graphics processors deployed in the current system from the multiple high-speed expansion devices based on the multiple first numbers and the multiple second numbers.

[0021] Specifically, one or more graphics processors among multiple high-speed expansion devices are identified by the first number and the second number, so that corresponding processing operations can be performed on the graphics processors that have correctable errors, thereby meeting the requirements of high real-time performance and high continuity of the graphics processors.

[0022] In practice, the first number is the device identifier, and the second number is the manufacturer identifier. The device identifier and manufacturer identifier are stored in the device's configuration space; the first four bytes of the configuration space contain the device identifier and manufacturer identifier. During startup, the Basic Input / Output System (BIOS) first loads the firmware code responsible for enumerating high-speed expansion devices, ensuring the BIOS has the ability to read and write the high-speed expansion device configuration space. Secondly, it initializes the root controller on the motherboard to ensure the high-speed expansion bus can communicate. It then traverses the high-speed expansion devices from top to bottom, simultaneously reading the corresponding device's configuration space and matching the first four bytes of the configuration space with the graphics processor's device identifier and manufacturer identifier to determine which high-speed expansion devices are graphics processors. The device identifier and manufacturer identifier are defined by the manufacturer according to industry standards, thus ensuring their uniqueness.

[0023] Furthermore, before a system management interrupt is triggered in response to the current system, the error correction method of the graphics processor further includes: generating multiple third numbers and assigning the multiple third numbers to multiple high-speed expansion devices, wherein the multiple third numbers correspond one-to-one with the multiple high-speed expansion devices, and the third number is unique for each high-speed expansion device; traversing multiple configuration spaces to obtain multiple first registers and multiple second registers, wherein the multiple first registers correspond one-to-one with the multiple configuration spaces, and the multiple second registers correspond one-to-one with the multiple configuration spaces; determining that the multiple high-speed expansion devices are in a normal state in response to the absence of data in the multiple first registers and multiple second registers; and generating a signal to trigger a system management interrupt in response to the presence of data in one or more first registers and / or one or more second registers.

[0024] Specifically, based on whether data exists in the first register and / or the second register, a corresponding signal for a system management interrupt is generated, and then the corresponding correctable error handling operation is determined based on the reporting device and error type.

[0025] In practical implementation, the third number is the bus device function identifier, the first register is the correctable error status register, and the second register is the uncorrectable error status register. During the enumeration of high-speed expansion devices, a unique bus device function identifier is assigned to each high-speed expansion device encountered. Errors from all high-speed expansion devices are unified on the integrated endpoint controller, which then triggers a unified system management interrupt to traverse the configuration spaces of all high-speed expansion devices.

[0026] Further, determining the faulty device that caused the current system to trigger a system management interrupt includes: traversing multiple first registers and multiple second registers; determining the current high-speed expansion device as a faulty device in response to the presence of data in the second register and / or third register of the current high-speed expansion device; obtaining the third number of the faulty device and the third number of one or more graphics processors, and comparing the third number of the faulty device with the third number of one or more graphics processors; determining the faulty device as a graphics processor in response to the presence of the third number of the faulty device among the third numbers of one or more graphics processors; determining the faulty device as another high-speed expansion device in response to the absence of the third number of the faulty device among the third numbers of one or more graphics processors; wherein, other high-speed expansion devices refer to high-speed expansion devices other than one or more graphics processors among the multiple high-speed expansion devices.

[0027] Specifically, the third number of the erroneous device is compared with one or more graphics processors to determine the erroneous device whose device type is graphics processor. Then, based on the error type, it is determined whether to perform the corresponding correctable error handling operation on the erroneous device.

[0028] Furthermore, such as Figure 2 As shown, determining the error type that caused the current system to trigger a system management interrupt includes: determining whether there is data in the first register and the second register of the error-reporting device; in response to the presence of data in the first register of the error-reporting device and the absence of data in the second register of the error-reporting device, determining the error type as a correctable error; in response to the presence of data in both the first and second registers of the error-reporting device, determining the error type as either a correctable error or an uncorrectable error; in response to the absence of data in the first register of the error-reporting device and the presence of data in the second register of the error-reporting device, determining the error type as an uncorrectable error.

[0029] Specifically, if data exists in the first register, the error type is determined to include correctable errors. Then, based on the error time and number of errors, corresponding processing operations are performed for correctable errors of the reporting device to ensure the high real-time performance and high continuity of the graphics processor.

[0030] In practice, the uncorrectable errors corresponding to the faulty devices will be reported.

[0031] Furthermore, such as Figure 2 As shown, determining whether a correctable error has occurred for the first time in a faulty device includes: determining whether the current value of the fault timestamp variable is empty; in response to the current value of the fault timestamp variable being empty, determining that the faulty device has occurred for the first time in a correctable error; in response to the current value of the fault timestamp variable being non-empty, determining that the faulty device has not occurred for the first time in a correctable error.

[0032] Furthermore, such as Figure 2 As shown, the second cumulative error count corresponding to the correctable error is determined based on the first error timestamp, the second error timestamp, and the first cumulative error count. This includes: obtaining the error time difference based on the first and second error timestamps; obtaining an error time difference threshold and comparing the error time difference with the error time difference threshold; in response to the error time difference being less than or equal to the error time difference threshold, obtaining the second cumulative error count based on the first cumulative error count and a second preset value; and in response to the error time difference being greater than the error time difference threshold, using the first cumulative error count as the second cumulative error count.

[0033] Specifically, the second cumulative error count is determined based on the relationship between the error reporting time difference and the error reporting time difference threshold, so as to avoid the waste of system resources caused by instantaneous interference.

[0034] In a specific embodiment, the basic input / output system provides user-configurable options, such as the error time difference threshold for the graphics processor.

[0035] Furthermore, such as Figure 2 As shown, based on the second cumulative error count, the corresponding correctable error processing operation is performed, including: obtaining the cumulative error count threshold and comparing the second cumulative error count with the cumulative error count threshold; in response to the second cumulative error count being less than the cumulative error count threshold, saving the second cumulative error count to the cumulative error count variable and the second error timestamp to the error timestamp variable, while masking the correctable error that occurred this time; in response to the second cumulative error count being equal to the cumulative error count threshold, reporting the correctable error that occurred this time.

[0036] Specifically, based on the relationship between the second cumulative error count and the cumulative error count threshold, corresponding error correction operations are performed to ensure data accuracy while avoiding momentary interference.

[0037] In a specific embodiment, the basic input / output system provides user-configurable options, such as a cumulative error count threshold for the graphics processor. The reported information includes at least the third ID of the reporting device and the data in the first register. These two pieces of information specify the device itself and the specific error type under the correctable error category. Simultaneously with reporting the correctable error, the error timestamp variable and the cumulative error count variable are restored to their initial states.

[0038] In addition, reporting correctable errors includes: obtaining the error reporting policy of the reporting device, wherein the error reporting policy describes the correspondence between business scenarios and reporting parameters, and the error reporting policy includes at least a first reporting parameter, a second reporting parameter, and a third reporting parameter; determining the target business scenario and matching the target business scenario with the reporting policy of the reporting device to obtain the target reporting parameter; in response to the target reporting parameter being the first reporting parameter, obtaining the operating system address in the first reporting parameter, and reporting the correctable error to the operating system based on the operating system address; in response to the target reporting parameter being the second reporting parameter, obtaining the baseboard management controller address in the second reporting parameter, and reporting the correctable error to the baseboard management controller based on the baseboard management controller address; in response to the target reporting parameter being the third reporting parameter, obtaining the operating system address and the baseboard management controller address in the third reporting parameter, and reporting the correctable error to the operating system and the baseboard management controller based on the operating system address and the baseboard management controller address.

[0039] Specifically, reporting correctable errors to the operating system for error analysis, logging, and system reset is suitable for scenarios requiring operating system intervention. Reporting correctable errors to the baseboard management controller ensures that correctable errors can be received by a hardware management unit independent of the operating system. The baseboard management controller can independently diagnose and log errors, while triggering alarm notifications. This is suitable for situations where the operating system is unavailable or needs to maintain stable operation. Reporting correctable errors to both the operating system and the baseboard management controller demonstrates the synergy of system management. This is suitable for scenarios where the operating system and the base management controller need to work together to quickly respond to and handle correctable errors, such as critical hardware failures or system-level errors. This ensures that the system can respond to errors comprehensively and at multiple levels, improving the comprehensiveness and efficiency of error management. The selection mechanism of the above three reporting paths—reporting to the operating system, reporting to the baseboard management controller, or reporting to both simultaneously—depends on the reporting address in the reporting parameters. This mechanism not only enhances the flexibility of correctable error reporting but also ensures that correctable error information is processed correctly, avoiding processing delays or redundant reporting, and maintaining the efficient operation of the system.

[0040] It should be understood that, although Figure 1 , Figure 2 , Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 , Figure 3At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0041] In the second embodiment, as Figure 4 As shown, a graphics processor error correction processing device is provided. The device includes: a first determining module, configured to determine, in response to a system management interrupt triggered by the current system, an error-causing device that caused the interruption, and simultaneously determine the error type causing the interruption; a judging module, configured to determine whether the error-causing device is experiencing an error for the first time, given that the error-causing device is a graphics processor and the error type includes correctable errors; an acquiring module, configured to acquire an error timestamp variable and a cumulative error count variable, in response to the error-causing device experiencing an error more than once; a second determining module, configured to determine a first error timestamp based on the current value of the error timestamp variable, and simultaneously determine a first cumulative error count based on the current value of the cumulative error count variable; a third determining module, configured to determine a second error timestamp corresponding to the current correctable error, and determine a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and an execution module, configured to execute a corresponding correctable error processing operation based on the second cumulative error count.

[0042] In a third embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it performs the following steps: in response to a system management interrupt triggered by the current system, it determines the faulty device that caused the system management interrupt and the type of error that caused the system management interrupt; in response to the faulty device being a graphics processor and the error type including correctable errors, it determines whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, it obtains an error timestamp variable and a cumulative error count variable, and determines a first error timestamp based on the current value of the error timestamp variable, and determines a first cumulative error count based on the current value of the cumulative error count variable; it determines a second error timestamp corresponding to the current correctable error, and determines a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and it performs a corresponding correctable error processing operation based on the second cumulative error count.

[0043] When the program instructions are read and executed by one or more processors, they can also perform operations corresponding to the steps in the above method embodiments, as described above, and will not be repeated here. Reference Figure 5 This exemplifies the architecture of an electronic device, which may include a processor 510, a video display adapter 511, a disk drive 512, an input / output interface 513, a network interface 514, and a memory 520. The processor 510, video display adapter 511, disk drive 512, input / output interface 513, network interface 514, and memory 520 can communicate with each other via a communication bus 530.

[0044] The processor 510 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in this application.

[0045] The memory 520 can be implemented as a read-only memory (ROM), random access memory (RAM), static storage device, dynamic storage device, etc. The memory 520 can store an operating system 521 for controlling the operation of the electronic device 500, and a basic input / output system (BIOS) 522 for controlling the low-level operations of the electronic device 500. Additionally, it can store a web browser 523, data storage management 524, and an icon / font processing system 525, etc. The aforementioned icon / font processing system 525 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when implementing the technical solution provided in this application through software or firmware, the relevant program code is stored in the memory 520 and executed by the processor 510.

[0046] Input / output interface 513 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0047] Network interface 514 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0048] Bus 530 includes a pathway for transmitting information between various components of the device, such as processor 510, video display adapter 511, disk drive 512, input / output interface 513, network interface 514, and memory 520.

[0049] In addition, the electronic device 500 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database (not shown in the figure) for condition judgment.

[0050] It should be noted that although the above-described electronic device 500 only shows a processor 510, a video display adapter 511, a disk drive 512, an input / output interface 513, a network interface 514, a memory 520, and a bus 530, in specific implementations, the electronic device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0051] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause an electronic device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods of various embodiments or some parts of the embodiments of this application.

[0052] In a fourth embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: in response to a system management interrupt triggered by the current system, determining the faulty device that caused the system management interrupt and determining the type of error that caused the system management interrupt; in response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, obtaining an error timestamp variable and a cumulative error count variable, and determining a first error timestamp based on the current value of the error timestamp variable, and determining a first cumulative error count based on the current value of the cumulative error count variable; determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and performing a corresponding correctable error processing operation based on the second cumulative error count.

[0053] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

[0056] In a fifth embodiment, a computer program product is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: In response to a system management interrupt triggered by the current system, determining the faulty device that caused the system management interrupt and determining the type of error that caused the system management interrupt; In response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; In response to the faulty device experiencing a correctable error for the first time, obtaining an error timestamp variable and a cumulative error count variable, and determining a first error timestamp based on the current value of the error timestamp variable, and determining a first cumulative error count based on the current value of the cumulative error count variable; Determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; Performing the corresponding correctable error processing operation based on the second cumulative error count.

[0057] In a fifth embodiment, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it performs the following steps: in response to a system management interrupt triggered by the current system, determining the faulty device that caused the system management interrupt and determining the type of error that caused the system management interrupt; in response to the faulty device being a graphics processor and the error type including correctable errors, determining whether the faulty device is experiencing a correctable error for the first time; in response to the faulty device experiencing a correctable error for the first time, acquiring an error timestamp variable and a cumulative error count variable, determining a first error timestamp based on the current value of the error timestamp variable, and determining a first cumulative error count based on the current value of the cumulative error count variable; determining a second error timestamp corresponding to the current correctable error, and determining a second cumulative error count corresponding to the current correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count; and performing a corresponding correctable error processing operation based on the second cumulative error count.

[0058] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer program product, and when the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A method for correcting errors in a graphics processor, characterized in that, The method includes: In response to the current system triggering a system management interrupt, determine the faulty device that caused the current system to trigger the system management interrupt, and at the same time determine the error type that caused the current system to trigger the system management interrupt; In response to the fact that the error-reporting device is a graphics processor and the error type includes correctable errors, it is determined whether the error-reporting device is experiencing a correctable error for the first time; In response to the fact that the error-reporting device has encountered a correctable error for the first time, the error timestamp variable and the cumulative error count variable are obtained, and a first error timestamp is determined based on the current value of the error timestamp variable, and a first cumulative error count is determined based on the current value of the cumulative error count variable. Determine the second error reporting timestamp corresponding to this correctable error, and determine the second cumulative error reporting count corresponding to this correctable error based on the first error reporting timestamp, the second error reporting timestamp, and the first cumulative error reporting count; Based on the second cumulative number of errors, perform the corresponding correctable error handling operation; The step of determining the second cumulative error count corresponding to the correctable error based on the first error timestamp, the second error timestamp, and the first cumulative error count includes: The error reporting time difference is obtained based on the first error reporting timestamp and the second error reporting timestamp; Obtain the error reporting time difference threshold, and compare the error reporting time difference with the error reporting time difference threshold; In response to the error reporting time difference being less than or equal to the error reporting time difference threshold, the second cumulative error reporting number is obtained based on the first cumulative error reporting number and the second preset value; In response to the error reporting time difference being greater than the error reporting time difference threshold, the first cumulative error count is used as the second cumulative error count; The step of performing corresponding correctable error processing operations based on the second cumulative number of error reports includes: Obtain the cumulative error count threshold, and compare the second cumulative error count with the cumulative error count threshold; In response to the second cumulative error count being less than the cumulative error count threshold, the second cumulative error count is saved to the cumulative error count variable, the second error timestamp is saved to the error timestamp variable, and the correctable error that occurred in this instance is masked. In response to the second cumulative error count being equal to the cumulative error count threshold, a correctable error that occurred this time is reported.

2. The method according to claim 1, characterized in that, The method further includes: In response to the first correctable error occurring in the erroneous device, a cumulative error count variable is obtained, and an initial cumulative error count is determined based on the current value of the cumulative error count variable, wherein the initial cumulative error count is a first preset value; Based on the initial cumulative error count and the second preset value, a third cumulative error count is obtained, and the third cumulative error count is saved to the cumulative error count variable, wherein the third cumulative error count represents the cumulative number of correctable errors that occurred this time; Determine the third error reporting timestamp and save the third error reporting timestamp to the error reporting timestamp variable, wherein the third error reporting timestamp represents the error reporting timestamp corresponding to the correctable error that occurred this time.

3. The method according to claim 1, characterized in that, Before responding to a system management interrupt triggered by the current system, the method further includes: By traversing multiple high-speed expansion devices in the current system, multiple configuration spaces are obtained, wherein each of the multiple high-speed expansion devices corresponds one-to-one with the multiple configuration spaces; Extract the first number and the second number from the configuration space, wherein the first number and the second number are unique to the high-speed expansion device; Based on a plurality of first numbers and a plurality of second numbers, one or more graphics processors deployed in the current system are determined from the plurality of high-speed expansion devices.

4. The method according to claim 3, characterized in that, Before responding to a system management interrupt triggered by the current system, the method further includes: Multiple third numbers are generated and assigned to the multiple high-speed expansion devices, wherein each of the multiple third numbers corresponds one-to-one with the multiple high-speed expansion devices, and each third number is unique for the high-speed expansion device; By traversing the multiple configuration spaces, multiple first registers and multiple second registers are obtained, wherein the multiple first registers correspond one-to-one with the multiple configuration spaces, and the multiple second registers correspond one-to-one with the multiple configuration spaces; In response to the absence of data in the plurality of first registers and the plurality of second registers, it is determined that the plurality of high-speed expansion devices are in a normal state; In response to the presence of data in one or more first registers and / or one or more second registers, a signal is generated that triggers the system management interrupt.

5. The method according to claim 4, characterized in that, The device that causes the current system to trigger the system management interruption includes: Traverse the plurality of first registers and the plurality of second registers; In response to the presence of data in the second and / or third registers of the current high-speed expansion device, the current high-speed expansion device is determined to be the error-reporting device; Obtain the third number of the error-reporting device and the third number of the one or more graphics processors, and compare the third number of the error-reporting device with the third number of the one or more graphics processors; In response to the presence of a third number of the error-reporting device among the third numbers of the one or more graphics processors, the error-reporting device is determined to be a graphics processor; In response to the absence of a third number for the reporting device in the third number of the one or more graphics processors, the reporting device is determined to be another high-speed expansion device; The other high-speed expansion devices refer to high-speed expansion devices other than the one or more graphics processors among the plurality of high-speed expansion devices.

6. The method according to claim 4, characterized in that, The determination of the error type that caused the current system to trigger the system management interruption includes: Determine whether there is data in the first and second registers of the error-reporting device; In response to the presence of data in the first register of the error-reporting device and the absence of data in the second register of the error-reporting device, the error type is determined to be a correctable error. In response to the presence of data in both the first and second registers of the error-reporting device, the error type is determined to be either a correctable error or an uncorrectable error. In response to the absence of data in the first register of the error-reporting device and the presence of data in the second register of the error-reporting device, the error type is determined to be the uncorrectable error.

7. The method according to claim 1, characterized in that, The determination of whether the error-reporting device has encountered a correctable error for the first time includes: Determine whether the current value of the error timestamp variable is empty; In response to the current value of the error reporting timestamp variable being empty, it is determined that the error-reporting device has experienced a correctable error for the first time; In response to the current value of the error reporting timestamp variable being non-empty, it is determined that the error-reporting device has not experienced a correctable error for the first time.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the error-correcting processing method of a graphics processor as described in any one of claims 1 to 7 when executing the computer program.

Images