Wafer defect killing rate calculation method and device, equipment and storage medium

Abstract

The invention relates to the technical field of semiconductor detection, in particular to a wafer defect killing rate calculation method and device, equipment and a storage medium, and the method comprises the steps: obtaining a wafer target defect map and a wafer electrical property test map, the wafer target defect atlas comprises defect positions, defect types and defect sizes of chip unit defects on a wafer, and the wafer electrical test atlas comprises chip unit test results; based on a preset wafer template atlas, aligning the wafer target defect atlas with the wafer electrical property test atlas to obtain a coincident atlas; based on the coincidence atlas, determining statistical data of the chip unit; and processing the statistical data of the chip unit based on a preset wafer defect killing rate calculation formula to obtain the wafer defect killing rate. The method is convenient for improving the calculation efficiency and the calculation precision of the wafer defect killing rate.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a method, apparatus, equipment and storage medium for calculating wafer defect kill rate. Background Technology

[0002] To manufacture chips on wafers, multiple process stations are set up in sequence during production. Each process station is responsible for executing a corresponding process flow on the wafer. After the final process station completes its process flow, the wafer yield needs to be checked. The yield is the ratio of the number of effective cells on the wafer to the total number of cells. If the yield is too low (generally, a yield of over 90% is required), each process station needs to be investigated to identify the process station where the process flow is problematic. Specifically, the wafer defect kill rate for each process station can be determined by analyzing the wafer cell statistics after each process station completes its corresponding process flow. If the wafer defect kill rate is found to be too high, it can be determined that there is a problem with the process flow of that process station. The wafer defect kill rate is the ratio of the number of chip cells on the wafer that are rendered ineffective by defects to the total number of chip cells with defects, used to measure the degree to which defects cause chip cell failures on the wafer.

[0003] Currently, the method for calculating wafer defect kill rate is as follows: manually detect the number of chip cells on the wafer that are rendered ineffective due to defects, count the total number of chip cells with defects, and then calculate the corresponding wafer defect kill rate.

[0004] However, manually detecting the number of chip cells that are invalid due to defects on the wafer and counting the total number of defective chip cells is not only inefficient, but also often results in detection and statistical errors, leading to low accuracy in the calculated wafer defect kill rate. Furthermore, with the continuous improvement of wafer manufacturing processes, defects on wafers are becoming smaller and more densely distributed, further reducing the efficiency and accuracy of manually determining the wafer defect kill rate. Summary of the Invention

[0005] To improve the calculation efficiency and accuracy of wafer defect kill rate, this application provides a wafer defect kill rate calculation method, apparatus, device, and storage medium.

[0006] In a first aspect, this application provides a method for calculating wafer defect kill rate, including:

[0007] Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit;

[0008] Based on the preset wafer template pattern, the wafer target defect pattern and the wafer electrical test pattern are aligned to obtain the superimposed pattern;

[0009] Based on the overlap pattern, determine the chip unit statistical data;

[0010] Based on a preset formula for calculating wafer defect kill rate, the statistical data of the chip unit are processed to obtain the wafer defect kill rate.

[0011] Secondly, this application provides a wafer defect kill rate calculation device, comprising:

[0012] The image acquisition module is used to acquire wafer target defect images and wafer electrical test images. The wafer target defect images include the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test images include the test results of each chip unit.

[0013] The map alignment module is used to align the wafer target defect map with the wafer electrical test map based on a preset wafer template map to obtain an overlapping map;

[0014] The data statistics module is used to determine chip unit statistical data based on the overlap pattern;

[0015] The formula calculation module is used to process the statistical data of the chip unit based on the preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate.

[0016] Thirdly, this application provides a computer device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the method described above.

[0017] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method.

[0018] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0019] The aforementioned wafer defect kill rate calculation method, apparatus, equipment, and storage medium acquire a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type, and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit; based on a preset wafer template map, the wafer target defect map and the wafer electrical test map are aligned to obtain an overlap map; based on the overlap map, chip unit statistical data is determined; based on a preset wafer defect kill rate calculation formula, the chip unit statistical data is processed to obtain the wafer defect kill rate. By implementing the above methods, aligning the obtained wafer target defect map with the wafer electrical test map using a wafer template map helps improve the efficiency and accuracy of the alignment, thereby facilitating the improvement of the calculation efficiency and accuracy of the wafer defect kill rate. In addition, the overlap map obtained after alignment can clearly show the effectiveness of each chip unit and the presence of defects. Even if the defects are smaller and more densely distributed, it is possible to statistically analyze the effectiveness of the chip unit and the presence of defects, thereby obtaining chip unit statistical data for calculating the wafer defect kill rate. This further facilitates the improvement of the calculation efficiency and accuracy of the wafer defect kill rate.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a wafer defect kill rate calculation method provided in the embodiments of this application;

[0023] Figure 2 This is a schematic diagram of the structure of a wafer defect kill rate calculation device provided in the embodiments of this application;

[0024] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application;

[0025] Figure 4 This is an internal structural diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this disclosure.

[0027] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0028] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] Example 1

[0030] Figure 1 A flowchart of a wafer defect kill rate calculation method provided in Embodiment 1 of this application is shown below. Figure 1 The method can be executed by a device that performs the method, which can be implemented in software and / or hardware, and the method includes:

[0031] S110. Obtain the wafer target defect map and the wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0032] It should be noted that after the wafer is fabricated, it can be further processed using the corresponding chip fabrication process to manufacture chips based on the wafer. Before the chip fabrication process is executed, multiple chip units are pre-divided on the wafer. For example, the chip units are generally square, but there is no specific limitation. Taking one chip unit as an example, the chip unit can be processed into the corresponding chip through the above chip fabrication process.

[0033] The aforementioned chip manufacturing process is divided into different process nodes. Different process nodes are used to perform different node processes on chip units. For example, the node process can be to fabricate corresponding chip lines on the chip unit. In this embodiment, each process node has a corresponding process station, which is used to perform the corresponding node process on the chip unit. Taking one of the process stations as an example, after completing the execution of the corresponding node process, the station needs to further generate a wafer target defect image of the wafer where the chip unit is located. The wafer target defect image is used to show the existence of defects on each chip unit on the wafer. The existence of defects specifically includes the defect location, defect type and defect size of the defects on the chip unit.

[0034] Here, "defect location" refers to the position of the defect on the corresponding chip unit; "defect type" refers to the type of corresponding defect present on the chip unit. For example, defect types include inherent defects (such as crystal structure defects, surface / edge defects, etc.), photolithography-related defects (defects that occur on the wafer during photolithography, such as pattern distortion, bridging, disconnection, and photoresist pinholes, etc.), etching-related defects (defects that occur on the wafer during etching, such as over-etching, under-etching, and etching residue, etc.), and thin film deposition-related defects, etc. The above defect types are only examples and are not specifically limited. In addition, the process station may also cause corresponding processing defects during the processing of the chip unit, that is, the above defect types may also be processing defects; "defect size" refers to the size of the corresponding defect on the chip unit, such as the height and width of the box selected by the defect, etc., and is not specifically limited.

[0035] It should be noted that, taking one chip unit as an example, if there is a defect on that chip unit, the defect may cause the chip unit to fail, or it may still be effective. That is, if a chip unit has a defect, it is impossible to determine whether the chip unit is effective at that moment. After each chip unit on the wafer completes processing at each process station, in order to determine whether each chip unit is effective, this embodiment performs electrical testing on the wafer. Electrical testing is to check the circuit normality of the corresponding chip unit, such as checking whether the current and voltage of the circuit in the chip unit are normal, etc., and the specifics are not limited. After completing the electrical testing of each chip unit on the wafer, a wafer electrical test spectrum can be obtained. The wafer electrical test spectrum is used to show the test results of each chip unit. The test results include Pass and Fail. If the test result is Pass, it means that the corresponding chip unit is effective (the chip unit functions normally and can be used). If the test result is Fail, it means that the corresponding chip unit is ineffective (the chip unit functions abnormally and cannot be used).

[0036] S120. Based on the preset wafer template pattern, align the wafer target defect pattern with the wafer electrical test pattern to obtain an overlapping pattern.

[0037] It should be noted that both the wafer target defect map and the wafer electrical test map can be considered as a single image, and both are the same size. Since the wafer electrical test map displays the validity assessment results of chip cells, while the wafer target defect map displays the presence of defects in chip cells, aligning the wafer target defect map and the wafer electrical test map to merge them into a single map allows for a unified display of both chip cell validity assessment results and defect presence. This unified display facilitates further identification of valid defective chip cells, valid defect-free chip cells, invalid defective chip cells, and invalid defect-free chip cells on the wafer. This allows for the calculation of the wafer defect kill rate based on the chip cell validity assessment results and defect presence. Furthermore, this unified display effectively improves the calculation efficiency and accuracy of the wafer defect kill rate.

[0038] Specifically, in this embodiment, a wafer template map is preset. This wafer template map is used to show the shape that each chip unit on the wafer should be processed into after the wafer has been processed by each process station. Moreover, the wafer template map, the wafer target defect map, and the wafer electrical test map are all the same size. This can be used to realize the automatic alignment of the wafer target defect map and the wafer electrical test map, thereby achieving the overlap of the wafer target defect map and the wafer electrical test map. After the overlap, they will be combined into one map, and this map is recorded as the overlap map. This overlap map can uniformly display the validity judgment results and defect existence of each chip unit on the wafer.

[0039] S130. Based on the overlap map, determine the chip unit statistical data.

[0040] Since the overlap pattern can uniformly display the validity judgment results and defect status of each chip unit on the wafer, the corresponding chip unit statistics can be obtained by analyzing the overlap pattern. For example, the chip unit statistics may include the number of valid defective chip units, the number of valid defect-free chip units, the number of invalid defective chip units, and the number of invalid defect-free chip units.

[0041] S140. Based on the preset wafer defect kill rate calculation formula, process the chip unit statistical data to obtain the wafer defect kill rate.

[0042] In order to calculate the wafer defect kill rate, this embodiment has a corresponding wafer defect kill rate calculation formula. By substituting the above chip unit statistical data into the wafer defect kill rate calculation formula, the corresponding wafer defect kill rate can be obtained. The wafer defect kill rate is used to measure the degree to which defects cause chip unit failure in the wafer.

[0043] It should be noted that this embodiment acquires a wafer target defect map and a wafer electrical test map. The wafer target defect map includes the defect location, defect type, and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit. Based on a preset wafer template map, the wafer target defect map and the wafer electrical test map are aligned to obtain an overlap map. Based on the overlap map, chip unit statistical data is determined. Based on a preset wafer defect kill rate calculation formula, the chip unit statistical data is processed to obtain the wafer defect kill rate. By implementing the above methods, aligning the obtained wafer target defect map with the wafer electrical test map using a wafer template map helps improve the efficiency and accuracy of the alignment, thereby facilitating the improvement of the calculation efficiency and accuracy of the wafer defect kill rate. In addition, the overlap map obtained after alignment can clearly show the effectiveness of each chip unit and the presence of defects. Even if the defects are smaller and more densely distributed, it is possible to statistically analyze the effectiveness of the chip unit and the presence of defects, thereby obtaining chip unit statistical data for calculating the wafer defect kill rate. This further facilitates the improvement of the calculation efficiency and accuracy of the wafer defect kill rate.

[0044] Example 2

[0045] This application provides a wafer defect kill rate calculation method in Embodiment 2, which optimizes the "obtaining wafer target defect map and wafer electrical test map" in Embodiment 1. It should be noted that for parts not detailed in this embodiment, please refer to the descriptions in other embodiments. The method includes:

[0046] S211. Obtain the initial defect maps of the wafers corresponding to at least two process stations.

[0047] The wafer has multiple chip units. Taking one chip unit as an example, in order to process the chip unit and obtain the finished chip, multiple preset process stations are used to process the chip unit in sequence according to the processing order. After each chip unit completes the corresponding processing steps, the corresponding initial defect map of the wafer needs to be generated.

[0048] Taking one of the process stations as an example, the steps for generating the initial defect map of the wafer include: the process station acquires an image of the wafer after completing the corresponding processing step using an optical microscope, which is used as the wafer optical image; then, the wafer optical image is processed by a preset image processing algorithm to obtain the initial defect map of the wafer; wherein, the initial defect map of the wafer includes the defect location, defect type and defect size corresponding to each defect existing on the wafer optical image.

[0049] S212. Fuse the initial defect maps of each wafer to obtain a target defect map of the wafer; wherein, the target defect map of the wafer includes the defect location, defect type and defect size of each chip unit defect on the wafer.

[0050] It should be noted that each process station generates a corresponding initial wafer defect map. After each process station completes its corresponding processing steps on the wafer, a preset wafer testing station is required to perform electrical testing on the wafer to obtain a wafer electrical test map. Therefore, in an optional embodiment, the initial wafer defect map corresponding to each process station can be used as the wafer target defect map. Then, based on the wafer target defect map and the wafer electrical test map corresponding to each process station, the wafer defect kill rate corresponding to each process station is calculated according to the method shown in Embodiment 1. In this way, when a low wafer yield is found after each process station has completed its corresponding processing steps, and it is necessary to investigate each process station, the wafer defect kill rate corresponding to each process station can be used to identify the problematic process station.

[0051] Currently, due to the continuous advancement of wafer fabrication technology, low wafer yield is relatively rare. Therefore, it is only necessary to calculate the wafer defect kill rate once after the wafer has completed the corresponding processing steps at each process station. For this purpose, the wafer target defect map must be able to cover the defects corresponding to each process station.

[0052] To ensure that the target defect map of the wafer can cover the defects corresponding to each process station, this embodiment, after obtaining the initial defect maps of the wafer of the same size corresponding to each process station, aligns the initial defect maps of the wafer along the direction perpendicular to the surface of the initial defect map of the wafer, thereby achieving the overlap of the initial defect maps of the wafer, and then merges the initial defect maps of the wafer into a single map, so that the defects on the initial defect maps of the wafer are merged into a single map, and the merged map is denoted as the target defect map of the wafer.

[0053] S213. Obtain the wafer electrical test pattern corresponding to the wafer test site. The wafer electrical test pattern includes the test results of each chip unit.

[0054] After each process station completes its corresponding processing steps on the wafer, a preset wafer testing station is used to perform electrical tests on each chip unit on the wafer to determine the electrical compliance of each chip unit. This yields the chip unit test results for each chip unit, which include Pass and Fail. If it is Pass, it means that the corresponding chip unit is electrically qualified and is a valid chip unit; if it is Fail, it means that the corresponding chip unit is electrically unqualified and is an invalid chip unit.

[0055] S220. Based on the preset wafer template pattern, align the wafer target defect pattern with the wafer electrical test pattern to obtain an overlapping pattern.

[0056] S230. Based on the overlapping spectrum, determine the chip unit statistical data.

[0057] S240. Based on the preset wafer defect kill rate calculation formula, process the chip unit statistical data to obtain the wafer defect kill rate.

[0058] Example 3

[0059] This application provides a wafer defect kill rate calculation method in Embodiment 3. This method optimizes the "aligning the wafer target defect pattern with the wafer electrical test pattern based on a preset wafer template pattern to obtain an overlap pattern" in Embodiment 1. It should be noted that for parts not described in detail in this embodiment, please refer to the descriptions in other embodiments. The method includes:

[0060] S310. Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0061] S321. Based on a preset wafer template pattern, determine the source location information in the wafer electrical test pattern and the mapping location information in the wafer target defect pattern.

[0062] The preset wafer template pattern, wafer electrical test pattern, and wafer target defect pattern are all of the same size and correspond to the same wafer. The wafer template pattern displays multiple chip units. Taking one chip unit as an example, since the wafer template pattern, wafer electrical test pattern, and wafer target defect pattern all correspond to the same wafer, a chip unit in the wafer template pattern can be identified in both the wafer electrical test pattern and the wafer target defect pattern. The position information of the identified chip unit can be obtained, and the position information of the chip unit identified in the wafer electrical test pattern is recorded as the source position information, while the position information of the chip unit identified in the wafer target defect pattern is recorded as the mapping position information.

[0063] S322. Based on the source location information and the mapping location information, align the wafer target defect map and the wafer electrical test map to obtain an overlap map.

[0064] The source location information describes the location of the chip cell determined on the wafer electrical test pattern, while the mapping location information describes the location of the chip cell determined on the wafer target defect pattern. Therefore, by mapping the mapping location information to the coordinate system of the source location information, the wafer target defect pattern can be mapped to the coordinate system of the wafer electrical test pattern, and the wafer target defect pattern and the wafer electrical test pattern can be aligned and overlapped to obtain a pattern, which is recorded as the overlap pattern.

[0065] It should be noted that by using a preset wafer template pattern, the wafer target defect pattern and the wafer electrical test pattern can be aligned and overlapped. This allows for the analysis and statistics of subsequent chip unit data using a single overlapping pattern, thereby improving the calculation efficiency and accuracy of the wafer defect kill rate.

[0066] S330. Based on the overlap map, determine the chip unit statistical data.

[0067] S340. Based on the preset wafer defect kill rate calculation formula, process the statistical data of the chip unit to obtain the wafer defect kill rate.

[0068] Example 4

[0069] This application provides a wafer defect kill rate calculation method in Embodiment 4. This method optimizes the step in Embodiment 3, which involves "determining the source location information in the wafer electrical test pattern and the mapping location information in the wafer target defect pattern based on a preset wafer template pattern." It should be noted that for parts not detailed in this embodiment, please refer to the descriptions in other embodiments. This method includes:

[0070] S410. Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0071] S421A: Randomly select reference feature points on the preset wafer template pattern.

[0072] The reference feature point is a pixel randomly selected from the preset wafer template pattern.

[0073] S421B. Determine the reference feature point, the first mapped feature point corresponding to the position in the wafer electrical test pattern, and the second mapped feature point corresponding to the position in the wafer target defect pattern.

[0074] Since the wafer template pattern, wafer electrical test pattern, and wafer target defect pattern are all of the same size, when the reference feature point has been determined in the wafer template pattern, feature points with the same position as the reference feature point can be determined in the wafer electrical test pattern and the wafer target defect pattern, respectively. The feature point determined in the wafer electrical test pattern is recorded as the first mapped feature point, and the feature point determined in the wafer target defect pattern is recorded as the second mapped feature point.

[0075] S421C. Determine the first mapping chip unit of the first mapping feature point in the wafer electrical test pattern, and determine the second mapping chip unit of the second mapping feature point in the wafer target defect pattern.

[0076] The wafer electrical test pattern contains multiple chip units. The first mapped feature point is located in one of the chip units in the wafer electrical test pattern, and the chip unit where the first mapped feature point is located is denoted as the first mapped chip unit. Similarly, the chip unit where the second mapped point is located in the wafer target defect pattern is denoted as the second mapped chip unit.

[0077] S421D. Determine the source location information corresponding to the first mapping chip unit, and determine the mapping location information corresponding to the second mapping chip unit.

[0078] The first mapping chip unit has a corresponding position in the wafer electrical test pattern, and this position is recorded as the source position information. The source position information specifically includes: the upper left corner position of the first mapping chip unit (which is square), the height of the first mapping chip unit, and the width of the first mapping chip unit.

[0079] Similarly, the second mapping chip unit has a corresponding position in the wafer target defect map, and this position is recorded as the mapping position information. The mapping position information specifically includes: the upper left corner position of the second mapping chip unit (which is square), the height of the second mapping chip unit, and the width of the second mapping chip unit.

[0080] It should be noted that by randomly selecting reference feature points on the wafer template map, the corresponding source location information can be determined in the wafer electrical test map, and the corresponding mapping location information can be determined in the wafer target defect map. Both the source location information and the mapping location information are used to describe the position of chip cells at the same location on the wafer. Therefore, the wafer electrical test map and the wafer target defect map can be aligned by using the source location information and the mapping location information, and the alignment accuracy can be guaranteed, which facilitates further improvement of the calculation accuracy of the wafer defect kill rate.

[0081] S422. Based on the source location information and the mapping location information, align the wafer target defect map and the wafer electrical test map to obtain an overlap map.

[0082] S430. Based on the overlapping spectrum, determine the chip unit statistical data.

[0083] S440. Based on the preset wafer defect kill rate calculation formula, process the chip unit statistical data to obtain the wafer defect kill rate.

[0084] Example 5

[0085] This application provides a wafer defect kill rate calculation method in Embodiment 5. This method optimizes the "aligning the wafer target defect map and the wafer electrical test map based on the source location information and the mapping location information to obtain an overlap map" in Embodiment 3. It should be noted that for parts not described in detail in this embodiment, please refer to the descriptions in other embodiments. The method includes:

[0086] S510. Obtain the wafer target defect map and the wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0087] S521. Based on the preset wafer template pattern, determine the source location information in the wafer electrical test pattern and the mapping location information in the wafer target defect pattern.

[0088] S522A. Based on the source start position, source chip unit height, and source chip unit width in the source location information, and the mapping start position, mapping chip unit height, and mapping chip unit width in the mapping location information, determine the map transformation matrix.

[0089] The source location information specifically includes: the position of the upper left corner of the first mapping chip unit, the height of the first mapping chip unit, and the width of the first mapping chip unit; and the position of the upper left corner of the first mapping chip unit is recorded as the source starting position, the height of the first mapping chip unit is recorded as the source chip unit height, and the width of the first mapping chip unit is recorded as the source chip unit width.

[0090] The mapping position information specifically includes: the upper left corner position of the second mapping chip unit, the height of the second mapping chip unit, and the width of the second mapping chip unit; and the upper left corner position of the second mapping chip unit is recorded as the mapping start position, the height of the second mapping chip unit is recorded as the mapping chip unit height, and the width of the second mapping chip unit is recorded as the mapping chip unit width.

[0091] It should be noted that, using the source location information and the mapping location information mentioned above, a mapping matrix can be calculated to map the wafer target defect pattern to the coordinate system where the wafer electrical test pattern is located, and this mapping matrix is ​​denoted as the pattern transformation matrix.

[0092] S522B: Based on the spectrum transformation matrix, align the wafer target defect spectrum with the wafer electrical test spectrum to obtain an overlapping spectrum.

[0093] The image transformation matrix can not only be used to map the wafer target defect image to the coordinate system of the wafer electrical test image, but also to align and overlap the wafer target defect image and the wafer electrical test image in the coordinate system, thereby merging the wafer target defect image and the wafer electrical test image into a single image, and this image is denoted as the overlapping image.

[0094] S530. Based on the overlap map, determine the chip unit statistical data.

[0095] S540. Based on the preset wafer defect kill rate calculation formula, process the chip unit statistical data to obtain the wafer defect kill rate.

[0096] In an optional embodiment, Embodiment 5 of this application provides a method for calculating wafer defect kill rate. This method optimizes the step in Embodiment 4, which involves "aligning the wafer target defect map with the wafer electrical test map based on the source location information and the mapping location information to obtain an overlap map." It should be noted that for parts not detailed in this embodiment, please refer to the descriptions in other embodiments. This method includes:

[0097] S510. Obtain the wafer target defect map and the wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0098] S521A. Randomly select reference feature points on the preset wafer template pattern;

[0099] S521B. Determine the reference feature point, the first mapped feature point corresponding to the position in the wafer electrical test pattern, and the second mapped feature point corresponding to the position in the wafer target defect pattern;

[0100] S521C. Determine the first mapping chip unit of the first mapping feature point in the wafer electrical test pattern, and determine the second mapping chip unit of the second mapping feature point in the wafer target defect pattern.

[0101] S521D: Determine the source location information corresponding to the first mapping chip unit, and determine the mapping location information corresponding to the second mapping chip unit.

[0102] S522A. Based on the source start position, source chip unit height, and source chip unit width in the source location information, and the mapping start position, mapping chip unit height, and mapping chip unit width in the mapping location information, determine the map transformation matrix.

[0103] S522B: Based on the spectrum transformation matrix, align the wafer target defect spectrum with the wafer electrical test spectrum to obtain an overlapping spectrum.

[0104] S530. Based on the overlap map, determine the chip unit statistical data.

[0105] S540. Based on the preset wafer defect kill rate calculation formula, process the chip unit statistical data to obtain the wafer defect kill rate.

[0106] Example 6

[0107] This application provides a wafer defect kill rate calculation method in Embodiment Six. This method optimizes the "processing of chip cell statistical data based on a preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate" in Embodiment One. It should be noted that for parts not described in detail in this embodiment, please refer to the descriptions in other embodiments. The method includes:

[0108] S610. Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0109] S620. Based on the preset wafer template pattern, align the wafer target defect pattern with the wafer electrical test pattern to obtain an overlapping pattern.

[0110] S630. Based on the overlap map, determine the chip unit statistical data.

[0111] The chip unit statistics include: the number of valid missing units and the number of invalid missing units.

[0112] It should be noted that if the chip cell test result of a chip cell in a wafer is Pass, it means that the chip cell is a valid cell. Since the superimposed spectrum can show the presence of defects on each chip cell, if there are defects on a valid cell, then the valid cell is specifically a valid defective cell, and the number of valid defective cells in the superimposed spectrum is also the number of valid defective cells.

[0113] If the chip cell test result of a chip cell in a wafer is Fail, it means that the chip cell is invalid. Since the superimposed spectrum can show the existence of defects on each chip cell, if there are defects on the invalid cell, then the valid cell is specifically an invalid cell with defects. The number of invalid cells with defects in the superimposed spectrum is also the number of invalid cells with defects.

[0114] S640. Based on the preset wafer defect kill rate calculation formula, process the number of valid defective cells and the number of invalid defective cells in the chip cell statistics data to obtain the wafer defect kill rate.

[0115] The formula for calculating the wafer defect kill rate is as follows: ;in, Where X is the wafer defect kill rate, M is the number of invalid defective cells, and M is the number of valid defective cells.

[0116] It should be noted that the wafer defect kill rate calculation formula provided in this embodiment is... It places more emphasis on the impact of the number of defects on the wafer defect kill rate, and uses it to reflect the average kill probability of defects.

[0117] Example 7

[0118] This application provides a wafer defect kill rate calculation method in Embodiment 7. This method optimizes the "processing of chip cell statistical data based on a preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate" in Embodiment 1. It should be noted that for parts not described in detail in this embodiment, please refer to the descriptions in other embodiments. The method includes:

[0119] S710. Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit.

[0120] S720. Based on the preset wafer template pattern, align the wafer target defect pattern with the wafer electrical test pattern to obtain an overlapping pattern.

[0121] S730. Based on the overlap map, determine the chip unit statistical data.

[0122] The chip unit statistics include: the number of valid missing units, the number of valid complete units, the number of invalid missing units, and the number of invalid complete units.

[0123] It should be noted that if the chip cell test result of a chip cell in a wafer is Pass, it means that the chip cell is a valid cell. Since the superimposed spectrum can show the presence of defects on each chip cell, if there are defects on a valid cell, then the valid cell is specifically a valid defective cell, and the number of valid defective cells in the superimposed spectrum is also the number of valid defective cells; if there are no defects on a valid cell, then the valid cell is specifically a valid undefective cell, and the number of valid undefective cells in the superimposed spectrum is also the number of valid undefective cells.

[0124] If the chip cell test result of a chip cell in a wafer is Fail, it means that the chip cell is invalid. Since the superimposed spectrum can show the presence of defects on each chip cell, if there are defects on the invalid cell, then the valid cell is specifically an invalid cell with defects, and the number of invalid cells with defects in the superimposed spectrum is also the number of invalid cells with defects. If there are no defects on the invalid cell, then the valid cell is specifically an invalid cell without defects, and the number of invalid cells without defects in the superimposed spectrum is also the number of invalid cells without defects.

[0125] S740. Based on the preset wafer defect kill rate calculation formula, process the number of effective defective cells, the number of effective undefective cells, the number of invalid defective cells, and the number of invalid undefective cells in the chip cell statistics data to obtain the wafer defect kill rate.

[0126] The formula for calculating the wafer defect kill rate is as follows: ;in, Let X be the wafer defect kill rate, Y be the number of invalid defective cells, M be the number of valid defective cells, and N be the number of valid valid defective cells.

[0127] It should be noted that the wafer defect kill rate calculation formula provided in this embodiment is... It places greater emphasis on the effectiveness of each chip unit on the wafer and the impact of defects on the wafer defect kill rate, in order to reflect the degree of impact of defects on the overall yield.

[0128] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0129] Example 8

[0130] Based on the same inventive concept, this embodiment also provides a wafer defect kill rate calculation device for implementing the wafer defect kill rate calculation method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations of one or more wafer defect kill rate calculation device embodiments provided below can be found in the limitations of the wafer defect kill rate calculation method described above, and will not be repeated here.

[0131] In this embodiment, as Figure 2 As shown, a wafer defect kill rate calculation device is provided, comprising:

[0132] The image acquisition module is used to acquire wafer target defect images and wafer electrical test images. The wafer target defect images include the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test images include the test results of each chip unit.

[0133] The map alignment module is used to align the wafer target defect map with the wafer electrical test map based on a preset wafer template map to obtain an overlapping map;

[0134] The data statistics module is used to determine chip unit statistical data based on the overlap pattern;

[0135] The formula calculation module is used to process the statistical data of the chip unit based on the preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate.

[0136] Each module in the aforementioned wafer defect kill rate calculation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0137] It should be noted that this embodiment acquires a wafer target defect map and a wafer electrical test map. The wafer target defect map includes the defect location, defect type, and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit. Based on a preset wafer template map, the wafer target defect map and the wafer electrical test map are aligned to obtain an overlap map. Based on the overlap map, chip unit statistical data is determined. Based on a preset wafer defect kill rate calculation formula, the chip unit statistical data is processed to obtain the wafer defect kill rate. By implementing the above methods, aligning the obtained wafer target defect map with the wafer electrical test map using a wafer template map helps improve the efficiency and accuracy of the alignment, thereby facilitating the improvement of the calculation efficiency and accuracy of the wafer defect kill rate. In addition, the overlap map obtained after alignment can clearly show the effectiveness of each chip unit and the presence of defects. Even if the defects are smaller and more densely distributed, it is possible to statistically analyze the effectiveness of the chip unit and the presence of defects, thereby obtaining chip unit statistical data for calculating the wafer defect kill rate. This further facilitates the improvement of the calculation efficiency and accuracy of the wafer defect kill rate.

[0138] Example 9

[0139] In this embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows. Figure 3 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a method for calculating wafer defect kill rate.

[0140] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0141] Example 10

[0142] In this embodiment, a computer-readable storage medium is provided, such as... Figure 4As shown, a computer program is stored thereon, and when the computer program is executed by the processor, it implements the steps in the above-described method embodiments.

[0143] Example 11

[0144] In this embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0145] It should be noted that the information collected is information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data all comply with the relevant laws, regulations and standards of the relevant countries and regions, necessary confidentiality measures have been taken, and it does not violate public order and good morals. Corresponding operation portals are provided for users to choose to authorize or refuse.

[0146] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this disclosure may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this disclosure may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent disclosure. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the appended claims.

Claims

1. A method for calculating wafer defect kill rate, characterized in that, include: Obtain a wafer target defect map and a wafer electrical test map, wherein the wafer target defect map includes the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test map includes the test results of each chip unit; Based on the preset wafer template pattern, the wafer target defect pattern and the wafer electrical test pattern are aligned to obtain the superimposed pattern; Based on the overlap pattern, determine the chip unit statistical data; Based on a preset formula for calculating wafer defect kill rate, the statistical data of the chip unit are processed to obtain the wafer defect kill rate.

2. The method according to claim 1, characterized in that, The acquisition of the wafer target defect map and wafer electrical test map includes: Obtain the initial defect maps of the wafers corresponding to at least two process stations; By fusing the initial defect maps of each wafer, the target defect map of the wafer is obtained; Obtain the wafer electrical test spectrum corresponding to the wafer test site.

3. The method according to claim 1, characterized in that, The process of aligning the wafer target defect map with the wafer electrical test map based on a preset wafer template map to obtain an overlap map includes: Based on a preset wafer template pattern, the source location information in the wafer electrical test pattern and the mapping location information in the wafer target defect pattern are determined. Based on the source location information and the mapping location information, the wafer target defect map and the wafer electrical test map are aligned to obtain an overlap map.

4. The method according to claim 3, characterized in that, The determination of the source location information in the wafer electrical test pattern and the mapping location information in the wafer target defect pattern based on the preset wafer template pattern includes: Randomly select reference feature points on the preset wafer template pattern; Determine the reference feature point, the first mapped feature point corresponding to the position in the wafer electrical test pattern, and the second mapped feature point corresponding to the position in the wafer target defect pattern; The first mapped chip unit of the first mapped feature point in the wafer electrical test pattern is determined, and the second mapped chip unit of the second mapped feature point in the wafer target defect pattern is determined; The source location information corresponding to the first mapping chip unit is determined, and the mapping location information corresponding to the second mapping chip unit is determined.

5. The method according to any one of claims 3 or 4, characterized in that, The step of aligning the wafer target defect map and the wafer electrical test map based on the source location information and the mapping location information to obtain an overlap map includes: Based on the source start position, source chip unit height, and source chip unit width in the source location information, and the mapping start position, mapping chip unit height, and mapping chip unit width in the mapping location information, the map transformation matrix is ​​determined; Based on the spectrum transformation matrix, the wafer target defect spectrum and the wafer electrical test spectrum are aligned to obtain an overlapping spectrum.

6. The method according to claim 1, characterized in that, The chip unit statistics include: the number of valid missing units and the number of invalid missing units; Accordingly, the process of processing the chip cell statistical data based on the preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate includes: Based on the preset wafer defect kill rate calculation formula, the number of valid defective cells and the number of invalid defective cells in the chip cell statistics are processed to obtain the wafer defect kill rate. The formula for calculating the wafer defect kill rate is as follows: ;in, Where X is the wafer defect kill rate, M is the number of invalid defective cells, and M is the number of valid defective cells.

7. The method according to claim 1, characterized in that, The chip unit statistics include: the number of valid missing units, the number of valid intact units, the number of invalid missing units, and the number of invalid intact units; Accordingly, the process of processing the chip cell statistical data based on the preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate includes: Based on the preset wafer defect kill rate calculation formula, the number of effective defective cells, the number of effective undefective cells, the number of invalid defective cells, and the number of invalid undefective cells in the chip cell statistics are processed to obtain the wafer defect kill rate. The formula for calculating the wafer defect kill rate is as follows: ;in, Let X be the wafer defect kill rate, Y be the number of invalid defective cells, M be the number of valid defective cells, and N be the number of valid valid defective cells.

8. A wafer defect kill rate calculation device, characterized in that, The device includes: The image acquisition module is used to acquire wafer target defect images and wafer electrical test images. The wafer target defect images include the defect location, defect type and defect size of each chip unit defect on the wafer, and the wafer electrical test images include the test results of each chip unit. The map alignment module is used to align the wafer target defect map with the wafer electrical test map based on a preset wafer template map to obtain an overlapping map; The data statistics module is used to determine chip unit statistical data based on the overlap pattern; The formula calculation module is used to process the statistical data of the chip unit based on the preset wafer defect kill rate calculation formula to obtain the wafer defect kill rate.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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