Buffer die and stacked memory device including same

Abstract

A buffer die disposed in a wafer and a stacked memory device are provided. The buffer die includes: a write-in strobe signal generation circuit configured to generate a first write-in strobe signal and a second write-in strobe signal having a 180-degree phase difference based on being enabled in a wafer-level test of the buffer die; a division and conversion circuit configured to generate a plurality of divided clock signals having a 90-degree phase difference; a duty cycle adjustment circuit configured to generate a plurality of adjusted clock signals; a read strobe signal generation circuit configured to generate a first read strobe signal and a second read strobe signal having a 180-degree phase difference; a skew monitoring circuit configured to generate a first up / down signal; and a trimming circuit configured to generate a second upper / lower signal, generate a plurality of control code sets, and obtain a fuse calibration code.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0064914, filed on May 20, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a memory device, and more specifically, to a buffer die capable of transmitting and / or receiving data at relatively high speeds and having reduced power consumption, and a stacked memory device including the buffer die. Background Technology

[0004] Electronic devices (such as, but not limited to, smartphones, graphics accelerators, and artificial intelligence (AI) accelerators) can process data using memory devices (such as, but not limited to, dynamic random access memory (DRAM)). As the amount of data to be processed by electronic devices increases, memory devices with relatively high capacity and / or relatively high bandwidth may be required. That is, there is a growing demand for memory devices with wide input and / or output capabilities that can provide multi-channel interfaces (such as high-bandwidth memory capable of processing data at relatively high speeds).

[0005] When a memory device supports relatively high bandwidth, data can be transmitted between the memory controller and the memory device at relatively high speeds. To ensure data integrity when transmitting data at relatively high speeds, data strobe signals can be exchanged between the memory controller and the memory device. When transmitting data signals between the memory controller and the memory device, the data strobe signals can periodically switch between high and low levels. High-frequency data strobe signals may be required when transmitting data at relatively high speeds. However, data exchange based on high-frequency data strobe signals can lead to increased power consumption of the memory device, and therefore, the input and / or output characteristics of the memory device may degrade when skew occurs in the data strobe signals (e.g., changes in timing and / or phase). Summary of the Invention

[0006] One or more exemplary embodiments of this disclosure provide a buffer die capable of compensating for data gating skew by monitoring the margin of the data gating signal at the wafer level.

[0007] Furthermore, one or more exemplary embodiments of this disclosure provide a stacked memory device including a buffer die capable of compensating for skew of a data strobe signal.

[0008] According to an aspect of the disclosure, a buffer die disposed in a wafer includes a write strobe signal generation circuit, a divide and conversion circuit, a duty cycle adjustment circuit, a read strobe signal generation circuit, a skew monitoring circuit, and a trim circuit. The write strobe signal generation circuit is configured to generate a first write strobe signal and a second write strobe signal having a first phase difference of 180 degrees from the first write strobe signal based on being enabled in a wafer level testing of the buffer die. The divide and conversion circuit is configured to generate a plurality of divided clock signals including a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal. The plurality of divided clock signals are equivalent to each other having a second phase difference of 90 degrees. Generating the plurality of divided clock signals includes dividing the first write strobe signal and the second write strobe signal, and converting one or more levels of the divided write strobe signals. The duty cycle adjustment circuit is configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal. Generating the plurality of adjusted clock signals includes adjusting a duty cycle of each of the plurality of divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set. The read strobe signal generation circuit is configured to generate a first read strobe signal and a second read strobe signal having a third phase difference of 180 degrees from the first read strobe signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree. The skew monitoring circuit is configured to generate a first up / down signal by monitoring a first duty cycle of the first read strobe signal and a second duty cycle of the second read strobe signal. The trim circuit is configured to generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals, generate the plurality of control code sets based on an auto calibration code or a fuse calibration code, and obtain the fuse calibration code from an external testing device. The auto calibration code is generated based on the first up / down signal. The fuse calibration code has been generated based on the first up / down signal and the second up / down signal.

[0009] According to an aspect of the disclosure, a stacked memory device includes a buffer die and a plurality of core dies stacked on the buffer die. The buffer die includes an interface circuit configured to communicate with an external host device. The plurality of core dies is coupled to the buffer die through a plurality of through-silicon vias. The interface circuit is configured to receive a first write enable signal and a second write enable signal from the external host device, the second write enable signal having a first phase difference of 180 degrees from the first write enable signal. The interface circuit includes a divide and convert circuit, a duty cycle adjustment circuit, a read enable signal generation circuit, a skew monitoring circuit, and a trim circuit. The divide and convert circuit is configured to generate a plurality of divided clock signals including a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal. The plurality of divided clock signals are equivalent to each other having a second phase difference of 90 degrees. Generating the plurality of divided clock signals includes dividing the first write enable signal and the second write enable signal, and converting one or more levels of the divided write enable signals. The duty cycle adjustment circuit is configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal. Generating the plurality of adjusted clock signals includes adjusting a duty cycle of each of the plurality of divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set. The read enable signal generation circuit is configured to generate a first read enable signal and a second read enable signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree, the second read enable signal having a third phase difference of 180 degrees from the first read enable signal. The skew monitoring circuit is configured to generate a first up / down signal by monitoring a first duty cycle of the first read enable signal and a second duty cycle of the second read enable signal. The trim circuit is configured to generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals, and to generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code. The auto-calibration code is generated based on the first up / down signal. The fuse calibration code is input from an external test device based on a wafer level test performed on the buffer die and stored inside the trim circuit.

[0010] According to an aspect of the disclosure, a buffer die disposed in a wafer includes a write strobe signal generation circuit, a divide and convert circuit, a duty cycle adjustment circuit, a read strobe signal generation circuit, a skew monitoring circuit, and a trim circuit. The write strobe signal generation circuit is configured to generate a first write strobe signal and a second write strobe signal having a first phase difference of 180 degrees from the first write strobe signal based on being enabled in a wafer level testing of the buffer die. The divide and convert circuit is configured to generate a plurality of divided clock signals including a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal. The plurality of divided clock signals have a second phase difference of 90 degrees with respect to each other. Generating the plurality of divided clock signals includes dividing the first write strobe signal and the second write strobe signal, and converting one or more levels of the divided write strobe signals. The duty cycle adjustment circuit is configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal. Generating the plurality of adjusted clock signals includes adjusting a duty cycle of each of the plurality of divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set. The read strobe signal generation circuit is configured to generate a first read strobe signal and a second read strobe signal having a third phase difference of 180 degrees from the first read strobe signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree. The skew monitoring circuit is configured to generate a first up / down signal by monitoring a first duty cycle of the first read strobe signal and a second duty cycle of the second read strobe signal. The trim circuit is configured to generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals; generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code; obtain the fuse calibration code from an external testing device; activate a flip cancellation of the write strobe signal generation circuit by activating a skew; and generate the auto-calibration code by averaging a first auto-calibration code obtained based on the flip being deactivated and a second auto-calibration code obtained based on the flip being activated. The auto-calibration code is generated based on the first up / down signal. The fuse calibration code has been generated based on the first up / down signal and the second up / down signal.

[0011] Accordingly, the write strobe signal generation circuit is formed in each of the buffer dies on the wafer at a wafer level, the write strobe signal generation circuit generates the first write strobe signal and the second write strobe signal, and compensates for skew between the first read strobe signal and the second read strobe signal at a wafer level by monitoring duty cycles of the first read strobe signal and the second read strobe signal based on the first write strobe signal and the second write strobe signal. Accordingly, defective buffer dies can be screened at a wafer level, and because the buffer dies passing the wafer level test are packaged into the stacked memory device with the core dies passing the wafer level test, the yield of the stacked memory device can be increased and the performance of the stacked memory device can be enhanced.

[0012] Additional aspects can be set forth in part in the description which follows, and, in part, can be apparent from the description, and / or can be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0014] FIG. 1 is a schematic diagram of a wafer on which a plurality of buffer dies are disposed according to an example embodiment;

[0015] FIG. 2 is a block diagram illustrating an example of a buffer die in FIG. 1 according to an example embodiment;

[0016] FIG. 3 is a block diagram illustrating an example of a buffer die in FIG. 2 according to an example embodiment;

[0017] FIG. 4 is a block diagram illustrating an example of a write strobe signal (WDQS) generation circuit in a buffer die of FIG. 3 according to an example embodiment;

[0018] FIG. 5 is a block diagram illustrating an example of a frequency division and conversion circuit in a buffer die of FIG. 3 according to an example embodiment;

[0019] FIG. 6A is a circuit diagram illustrating an example of a first duty cycle adjuster in a duty cycle adjustment circuit in a buffer die of FIG. 3 according to an example embodiment;

[0020] FIG. 6B illustrates that the duty cycle adjustment circuit in FIG. 3 according to an example embodiment adjusts each of duty cycles of the first divided clock signal to the fourth divided clock signal;

[0021] FIG. 7 This illustrates an example embodiment. FIG. 3 A block diagram of an example of a read strobe (RDQS) generation circuit in a buffer die;

[0022] FIG. 8 This illustrates an example embodiment. FIG. 7 Timing diagram of example operation of the RDQS generation circuit;

[0023] FIG. 9 An example embodiment is shown. FIG. 7 Examples of first and second predetermined mode data in the gating signal generation circuit;

[0024] FIG. 10 An example embodiment is shown. FIG. 3 The frequency of the clock signal buffer die;

[0025] FIG. 11 This illustrates an example embodiment. FIG. 3 A block diagram of an example delay controller in a buffer die;

[0026] FIG. 12 This illustrates an example embodiment. FIG. 11 A circuit diagram of an example of the first decoder in the delay controller;

[0027] FIG. 13 An example embodiment is shown. FIG. 12 An example of the first selected calibration code and the first control code set in the first decoder;

[0028] FIG. 14A , FIG. 14B and FIG. 14C This illustrates an embodiment. FIG. 4 A diagram illustrating the offset compensation scheme for the WDQS generation circuit;

[0029] FIG. 15 This is a flowchart illustrating the manufacturing process of a stacked memory device according to an example embodiment;

[0030] FIG. 16 This illustrates an example embodiment. FIG. 15 A flowchart of the process for generating control code sets;

[0031] FIG. 17 This is a block diagram illustrating a stacked memory device according to an example embodiment;

[0032] FIG. 18 This illustrates an example embodiment. FIG. 17 A block diagram of an example of a stacked memory device;

[0033] FIG. 19 is a block diagram illustrating an example of a first core die in a stacked memory device according to an example embodiment; FIG. 18

[0034] FIG. 20 illustrates an example of a first memory bank array in a first core die according to an example embodiment; FIG. 19

[0035] FIG. 21 is a diagram illustrating a semiconductor package according to an example embodiment; and

[0036] FIG. 22 is a diagram illustrating an example of a semiconductor package according to an example embodiment. DETAILED DESCRIPTION

[0037] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are to be considered in an exemplary sense rather than limiting. Accordingly, those of ordinary skill in the art can recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0038] ​​In the description of the drawings, like reference numbers can be used to refer to like or associated elements. It will be understood that a singular form of a noun can include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," can include any one of the items enumerated together with all possible combinations of the items enumerated. As used herein, the terms such as "first" and "second" can be used to simply distinguish a corresponding component from another, and do not limit the components in other aspects (e.g., importance or order). It will be understood that, if a term "operatively" or "communicatively" is used or not used in using the term "coupled with" or "connected with," if an element (for example, a first element) is referred to as "coupled with" or "connected with" another element (for example, a second element), it means that the element can be directly connected with the other element (for example, wiredly connected), wirelessly connected with the other element, or connected with the other element via a third element.

[0039] It will be understood that when an element or layer is referred to as being "on", "above", "over", "under", "below", "underneath", "connected to" or "coupled to" another element or layer, it can be directly on, above, over, under, below, underneath, connected to, or coupled to the other element or layer, or one or more intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on", "directly above", "directly over", "directly under", "directly below", "directly underneath", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

[0040] The terms “upper,” “middle,” “lower,” and the like can be replaced with terms such as “first,” “second,” “third” to describe the relative positions of elements. The terms “first,” “second,” “third” can be used to describe various elements, but these elements are not limited by the terms, and a “first element” can be referred to as a “second element.” Alternatively or additionally, the terms “first,” “second,” “third,” and the like can be used to distinguish components from each other, and do not limit the present disclosure. For example, the terms “first,” “second,” “third,” and the like can not necessarily involve any form of order or numerical meaning.

[0041] As used herein, when an element or layer is referred to as “through” another element or layer, the element or layer can pass through at least a portion of the other element or layer, where the portion can include a small portion of the other element or can include the entire dimension (e.g., length, width, depth) of the other element.

[0042] Reference throughout this disclosure to “one embodiment,” “an embodiment,” “example embodiment,” or similar language can indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Thus, the phrases “in one embodiment,” “in an embodiment,” “in an example embodiment,” and similar language throughout this disclosure can, but not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto, and can be implemented in various other forms.

[0043] It will be understood that the particular order or hierarchy of blocks in the disclosed processes / flowcharts is an example of illustrative methods. Based upon design preferences, it is understood that the particular order or hierarchy of blocks in the processes / flowcharts can be reordered. Also, some blocks can be combined or omitted. The accompanying claims present elements of the various blocks in example order, and are not meant to be limited to the particular order or hierarchy presented.

[0044] Embodiments herein can be described and shown by blocks that perform the described function or functions, as shown in the attached drawings. These blocks (which can be referred to herein as units or modules, or named such as devices, logic, circuitry, counters, comparators, generators, converters, etc.) can be physically implemented by analog and / or digital circuitry comprising one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0045] In the present disclosure, the indefinite article is intended to include one or more items and can be used interchangeably with “one or more.” In cases where only one item is intended, the term “one” or similar language is used. For example, the term “processor” can refer to a single processor or multiple processors. When a processor is described as performing an operation and the processor is referred to as performing an additional operation, the multiple operations can be performed by either the single processor or any one or combination of the multiple processors.

[0046] Various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0047] FIG. 1 is a schematic diagram of a wafer on which a plurality of buffer dies are disposed (e.g., formed) according to example embodiments. FIG. 2 is a schematic diagram of a wafer on which a plurality of buffer dies are disposed (e.g., formed) according to example embodiments. FIG. 1 is a close-up view of a die in

[0048] Referring to FIG. 1 and FIG. 2 A plurality of dies 180 can be formed on the wafer 170 through a fabrication (FAB) process. The plurality of dies 180 can be singulated along the scribe lines 175. The plurality of dies 180 can be manufactured as individual unit chips or packages through an assembly process.

[0049] Between the FAB process and the assembly process, a wafer-level test process and / or an electronic die sorting (EDS) process can be performed. Electrical characteristics of the semiconductor devices 200 formed in each of the plurality of dies 180 can be tested during the wafer-level test process and / or the EDS process. The wafer-level test process can be and / or can include a process in which a test operation signal can be applied to a die of the plurality of dies 180 formed on the wafer 170, and a test result signal output by the die 180 in response to the test operation signal can be analyzed to determine whether the die 180 has a defect.

[0050] An automatic test equipment (ATE) 40 can provide the test operation signal, can transmit the test operation signal to the die 180 via a probe card, and can determine whether the die 180 has a defect by receiving a test result signal in response to the test operation signal from the die 180 via the probe card.

[0051] Each of the plurality of dies 180 can include a plurality of test pads (e.g., a first test pad 191, a second test pad 192, a third test pad 193, a fourth test pad 194, a fifth test pad 195, and a sixth test pad 196) thereon, which can support the wafer-level test. When the probe card physically and / or electrically contacts the plurality of test pads 191 to 196, the die 180 can perform a test mode in response to the test operation signal.

[0052] As FIG. 2 illustrated, the die 180 can include a plurality of test pads 191 to 196 and a semiconductor device 200. In an embodiment, the semiconductor device 200 can be provided as a buffer die.

[0053] In an embodiment, the first test pad 191 can receive a test enable signal, and the second test pad 192 to the sixth test pad 196 can receive test operation signals that can be applied to the semiconductor device 200. The test operation signals can include, but are not limited to, a test clock signal, a test command signal, a test mode signal, etc. for controlling the operation of the semiconductor device 200. The die 180 can be connected to the ATE 40 having probes through the plurality of test pads 191 to 196 to perform wafer level testing.

[0054] Hereinafter, the semiconductor device 200 can be referred to as a buffer die.

[0055] When the buffer die 200 is tested at a wafer level and after the buffer die 200 is packaged into a stacked memory device having a plurality of core dies, the buffer die 200 can compensate for skew based on a set of control codes obtained in the wafer level testing of the buffer die 200.

[0056] FIG. 3 is a block diagram illustrating an example of a buffer die in FIG. 2 according to an example embodiment.

[0057] Referring to FIG. 3 , the buffer die 200 can include a write data strobe (WDQS) generation circuit 210, a divide and conversion circuit 230, a duty cycle adjustment circuit 240, a clock tree 245, a read data strobe (RDQS) generation circuit 250, a skew monitoring circuit 260, and a trim circuit 270.

[0058] The WDQS generation circuit 210 can be enabled in the wafer level testing of the buffer die 200 in response to a test enable signal TEN, and can generate a first write data strobe WDQS and a second write data strobe WDQSB having a phase difference of 180 degrees from the first write data strobe WDQS. The test enable signal TEN can be provided from the ATE in FIG. 1 .

[0059] The dividing and converting circuit 230 can receive the first write enable signal WDQS and the second write enable signal WDQSB through the first terminal T11 and the second terminal T12, and can generate a plurality of divided clock signals (e.g., a first divided clock signal DCLKI, a second divided clock signal DCLKQ, a third divided clock signal DCLKIB, and a fourth divided clock signal DCLKQB) having a 90-degree phase difference from each other by dividing the first write enable signal WDQS and the second write enable signal WDQSB, respectively, and by converting a level of the divided signals. After the buffer die 200 is packaged into a stacked memory device, the WDQS generating circuit 210 can be deactivated, and the dividing and converting circuit 230 can receive the first write enable signal WDQS and the second write enable signal WDQSB from an external host device through the first terminal T11 and the second terminal T12.

[0060] The duty cycle adjustment circuit 240 can generate a plurality of adjusted clock signals (e.g., a first adjusted clock signal ACLKI, a second adjusted clock signal ACLKQ, a third adjusted clock signal ACLKB, and a fourth adjusted clock signal ACLKQB) by adjusting a duty cycle of each of the plurality of divided clock signals DCLKI to DCLKQB based on a corresponding control code from a plurality of control code sets (e.g., a first control code set CCD1, a second control code set CCD2, a third control code set CCD3, and a fourth control code set CCD4).

[0061] A plurality of read clock signals (e.g., a first read clock signal CLKI, a second read clock signal CLKQ, a third read clock signal CLKB, and a fourth read clock signal CLKQB) can be obtained by passing the plurality of adjusted clock signals ACLKI to ACLKQB through the clock tree 245. The plurality of read clock signals CLKI to CLKQB can be provided to the RDQS generating circuit 250.

[0062] The RDQS generating circuit 250 can generate a first read enable signal RDQS and a second read enable signal RDQSB having a 180-degree phase difference from the first read enable signal RDQS based on a first predetermined pattern data PTD1, a second predetermined pattern data PTD2, and the plurality of read clock signals CLKI to CLKQB. In an embodiment, the RDQS generating circuit 250 can provide the first read enable signal RDQS and the second read enable signal RDQSB to the skew monitoring circuit 260.

[0063] The skew monitoring circuit 260 can receive the first and second read strobe signals RDQS and RDQSB through the third and fourth terminals T21 and T22, can generate the first up / down signal UP / DN1 by monitoring duty cycles of the first and second read strobe signals RDQS and RDQSB, can store the first and second read strobe signals RDQS and RDQSB therein, and can provide the first and second read strobe signals RDQS and RDQSB to the trimming circuit 270.

[0064] The trimming circuit 270 can generate the second up / down signal UP / DN2 by monitoring duty cycles of the plurality of read clock signals CLKI to CLKQB, can provide the second up / down signal UP / DN2 to the skew monitoring circuit 260, can generate a plurality of control code sets CCD1 to CCD4 based on at least one of an auto-calibration code ACD or a fuse calibration code TCD, and can provide the plurality of control code sets CCD1 to CCD4 to the duty cycle adjustment circuit 240. The auto-calibration code ACD can be generated based on the first up / down signal UP / DN1.

[0065] The fuse calibration code FCD can be input from an external test device (e.g., the ATE 40 in FIG. 1) based on the first up / down signal UP / DN1 and the second up / down signal UP / DN2. FIG. 1

[0066] The duty cycle adjustment circuit 240 can include a first duty cycle adjuster DCA1 240a, a second duty cycle adjuster DCA2 240b, a third duty cycle adjuster DCA3 240c, and a fourth duty cycle adjuster DCA4 240d.

[0067] The first duty cycle adjuster 240a can generate a first adjusted clock signal ACLKI by adjusting an amount of delay of at least one of a rising edge or a falling edge of the first divided clock signal DCLKI based on the first control code set CCD1. The second duty cycle adjuster 240b can generate a second adjusted clock signal ACLKQ by adjusting an amount of delay of at least one of a rising edge or a falling edge of the second divided clock signal DCLKQ based on the second control code set CCD2. The third duty cycle adjuster 240c can generate a third adjusted clock signal ACLKIB by adjusting an amount of delay of at least one of a rising edge or a falling edge of the third divided clock signal DCLKIB based on the third control code set CCD3. The fourth duty cycle adjuster 240d can generate a fourth adjusted clock signal ACLKQB by adjusting an amount of delay of at least one of a rising edge or a falling edge of the fourth divided clock signal DCLKQB based on the fourth control code set CCD4.

[0068] ​The skew monitoring circuit 260 can include a first duty cycle monitor DCM1 261 and a first code storage 263.

[0069] The first duty cycle monitor 261 can generate a first up / down signal UP / DN1 by monitoring duty cycles of the first read strobe signal RDQS and the second read strobe signal RDQSB, and can store the first up / down signal UP / DN1 in the first code storage 263.

[0070] The trimming circuit 270 can include a second duty cycle monitor DCM2 271, an auto calibration logic 273, a second code storage 275, and a delay controller 280.

[0071] The second duty cycle monitor 271 can generate a second up / down signal UP / DN2 by monitoring duty cycles of each of the plurality of read clock signals CLKI to CLKQB, and can store the second up / down signal UP / DN2 in the first code storage 263.

[0072] The first code storage 263 can store the first up / down signal UP / DN1 and the second up / down signal UP / DN2 by accumulating the first up / down signal UP / DN1 and the second up / down signal UP / DN2, respectively. An external test device (e.g., the ATE 40 in FIG. 1 ) can read the first up / down signal UP / DN1 and the second up / down signal UP / DN2 from the first code storage 263, and can store a fuse calibration code FCD in the second code storage 275 based on the first up / down signal UP / DN1 and the second up / down signal UP / DN2.

[0073] The auto calibration logic 273 can generate an auto calibration code ACD based on the first up / down signal UP / DN1, can generate a first selection signal SS1 and a second selection signal SS2, can generate an auto calibration enable signal AC_EN, can provide the first selection signal SS1 and the second selection signal SS2 to the WDQS generation circuit 210, and can provide the auto calibration enable signal AC_EN to the delay controller 280.

[0074] The first selection signal SS1 can be associated with a frequency of each of the first write strobe signal WDQS and the second write strobe signal WDQSB, and the second selection signal SS2 can be associated with a phase of each of the first write strobe signal WDQS and the second write strobe signal WDQSB. When the second selection signal SS2 indicates that a flip is activated, the phase of each of the first write strobe signal WDQS and the second write strobe signal WDQSB can be inverted.

[0075] The delay controller 280 can select the automatic calibration code ACD or the fuse calibration code FCD in response to the automatic calibration enable signal AC_EN, can generate a plurality of control code sets CCD1 to CCD4 based on the selected calibration code, and can provide the plurality of control code sets CCD1 to CCD4 to the duty adjustment circuit 240.

[0076] When the automatic calibration enable signal AC_EN is activated, the delay controller 280 can select the automatic calibration code ACD, and can generate a plurality of control code sets CCD1 to CCD4 based on the automatic calibration code ACD. When the automatic calibration enable signal AC_EN is deactivated, the delay controller 280 can select the fuse calibration code FCD, and can generate a plurality of control code sets CCD1 to CCD4 based on the fuse calibration code FCD.

[0077] Conventionally, after a buffer die is packaged into a stacked memory device with a core die, a duty cycle of a data strobe signal can be monitored at a package level, and skew of the data strobe signal can be compensated based on a result of the monitoring. In this way, a buffer die having a defect can be screened before packaging.

[0078] However, according to an example embodiment, the WDQS generation circuit 210 can be formed in each of the buffer dies on a wafer at a wafer level, the WDQS generation circuit 210 can generate a first write strobe signal WDQS and a second write strobe signal WDQSB, and skew between a first read strobe signal RDQS and a second read strobe signal RDQSB can be compensated by monitoring a duty cycle of the first read strobe signal RDQS and the second read strobe signal RDQSB based on the first write strobe signal WDQS and the second write strobe signal WDQSB at a wafer level. That is, the buffer die 200 can monitor a duty cycle of a data strobe signal, can compensate for skew of the data strobe signal based on a result of the monitoring, and can screen a buffer die having a defect at a wafer level. Furthermore, because the buffer die that passes the wafer level test is packaged into a stacked memory device with a core die that passes the wafer level test, yield of the stacked memory device can be improved, and performance of the stacked memory device can be enhanced.

[0079] FIG. 4 is a block diagram illustrating an example of a WDQS generation circuit in a buffer die of FIG. 3 .

[0080] Referring to FIG. 4 , the WDQS generation circuit 210 can include a source clock generator 211, a phase splitter 216, a first driver 217, a second driver 218, a selective inverting circuit 220, and an amplifier 225.

[0081] The source clock generator 211 can output the first source clock signal SCLK1 or the second source clock signal SCLK2 as the source clock signal SCLK in response to the first selection signal SS1. The first source clock signal SCLK1 can have a first frequency, and the second source clock signal SCLK2 can have a second frequency less than the first frequency.

[0082] The source clock generator 211 can include an oscillator OSC 212, a phase-locked loop (PLL) circuit 213, and a multiplexer (MUX) 214. The oscillator 212 can generate the first source clock signal SCLK1 toggling at a first frequency. The PLL circuit 213 can generate the second source clock signal SCLK2 toggling at a second frequency. The multiplexer 214 can output the first source clock signal SCLK1 or the second source clock signal SCLK2 as the source clock signal SCLK in response to the first selection signal SS1.

[0083] The phase splitter 216 can receive the source clock signal SCLK and can generate the first split clock signal PCLKI and the second split clock signal PCLKIB by splitting phases of the source clock signal SCLK.

[0084] The first driver 217 can drive the first split clock signal PCLKI and provide the first split clock signal PCLKI to the selective flipping circuit 220, and the second driver 218 can drive the second split clock signal PCLKIB and provide the second split clock signal PCLKIB to the selective flipping circuit 220.

[0085] The selective flipping circuit 220 can output the first split clock signal PCLKI or the second split clock signal PCLKIB as the first selected clock signal SDQS1 in response to the second selection signal SS2 indicating whether flipping is activated, and can output the other of the first split clock signal PCLKI or the second split clock signal PCLKIB as the second selected clock signal SDQS2.

[0086] The selective flipping circuit 220 can include a first multiplexer 221 and a second multiplexer 223.

[0087] The first multiplexer 221 can receive the first split clock signal PCLKI and the second split clock signal PCLKIB, can provide the first split clock signal PCLKI as the first selected clock signal SDQS1 in response to the second selection signal SS2 indicating that flipping is deactivated, and can provide the second split clock signal PCLKIB as the second selected clock signal SDQS2 in response to the second selection signal SS2 indicating that flipping is activated.

[0088] The second multiplexer 223 can receive the first split clock signal PCLKI and the second split clock signal PCLKIB, can provide the second split clock signal PCLKIB as the first selected data signal SDQS1 in response to the second selection signal SS2 indicating that the flipping is deactivated, and can provide the first split clock signal PCLKI as the second selected data signal SDQS2 in response to the second selection signal SS2 indicating that the flipping is activated.

[0089] That is, the selective flipping circuit 220 can output the first split clock signal PCLKI and the second split clock signal PCLKIB as the first selected data signal SDQS1 and the second selected data signal SDQS2, respectively, in response to the second selection signal SS2 indicating that the flipping is deactivated, and can output the second split clock signal PCLKIB and the first split clock signal PCLKI as the first selected data signal SDQS1 and the second selected data signal SDQS2, respectively, in response to the second selection signal SS2 indicating that the flipping is activated.

[0090] The amplifier 225 can output the first write data signal WDQS and the second write data signal WDQSB by amplifying the first selected data signal SDQS1 and the second selected data signal SDQS2.

[0091] The auto-calibration logic 273 in the trimming circuit 270 can eliminate the offset of the WDQS generation circuit 210 by activating the flipping using the second selection signal SS2, and can generate the auto-calibration code ACD by averaging the first auto-calibration code obtained when the flipping is deactivated and the second auto-calibration code obtained when the flipping is activated.

[0092] FIG. 5 is a block diagram illustrating an example of a frequency division and conversion circuit in a buffer die according to an example embodiment. FIG. 3

[0093] Referring to FIG. 5 , the frequency division and conversion circuit 230 can include a clock division circuit 231, a current mode logic (CML) driver 235, and a CML to complementary metal oxide semiconductor (CMOS) level (C2C) converter 237.

[0094] The clock division circuit 231 can generate the first divided data signal dDQSI and the third divided data signal dDQSIB having a 180-degree phase difference by dividing the frequency of the first write data signal WDQS, and can generate the second divided data signal dDQSQ and the fourth divided data signal dDQSQB having a 180-degree phase difference by dividing the frequency of the second write data signal WDQSB.

[0095] ​The clock dividing circuit 231 can include a first clock divider 232 and a second clock divider 234. The first clock divider 232 can generate a first divided clock signal dDQSI and a third divided clock signal dDQSIB by dividing a frequency of the first write enable signal WDQS by two (2). The second clock divider 234 can generate a second divided clock signal dDQSQ and a fourth divided clock signal dDQSQB by dividing a frequency of the second write enable signal WDQSB by two (2).

[0096] The CML driver 235 can generate a plurality of intermediate clock signals (e.g., a first intermediate clock signal ICLKI, a second intermediate clock signal ICLKQ, a third intermediate clock signal ICLKIB, and a fourth intermediate clock signal ICLKQB) by driving a plurality of divided clock signals (e.g., the first divided clock signal dDQSI, the second divided clock signal dDQSQ, the third divided clock signal dDQSIB, and the fourth divided clock signal dDQSQB) having CML levels, respectively.

[0097] The C2C converter 237 can generate a plurality of divided clock signals DCLKI to DCLKQB having CMOS levels based on the plurality of intermediate clock signals ICLKI to ICLKQB, respectively. That is, the C2C converter 237 can generate the plurality of divided clock signals DCLKI to DCLKQB having CMOS levels by converting each level of the plurality of intermediate clock signals ICLKI to ICLKQB.

[0098] FIG. 6A is a circuit diagram illustrating an example of a first duty cycle adjuster in a duty cycle adjuster in a buffer die according to an example embodiment. FIG. 3 is a circuit diagram illustrating an example of a first duty cycle adjuster in a duty cycle adjuster in a buffer die according to an example embodiment.

[0099] Referring to FIG. 6A The first duty cycle adjuster 240a can include a plurality of inverters (e.g., a first inverter INV11, a second inverter INV12, a third inverter INV13, and a fourth inverter INV14) and a plurality of delay units (e.g., a first delay unit DC1, a second delay unit DC2, a third delay unit DC3, a fourth delay unit DC4, a fifth delay unit DC5, a sixth delay unit DC6, and a seventh delay unit DC7).

[0100] The plurality of inverters INV11 to INV14 can be connected in series.

[0101] The first delay cell DC1 and the second delay cell DC2 can be coupled between two adjacent inverters (e.g., the first inverter INV11 and the second inverter INV12), the third delay cell DC3 and the fourth delay cell DC4 can be coupled between two adjacent inverters (e.g., the second inverter INV12 and the third inverter INV13), the fifth delay cell DC5 and the sixth delay cell DC6 can be coupled between two adjacent inverters (e.g., the third inverter INV13 and the fourth inverter INV14), and the seventh delay cell DC7 can be coupled to an output of the last inverter (e.g., the fourth inverter INV14). In an embodiment, the first delay cell DC1, the second delay cell DC2, the third delay cell DC3, the fourth delay cell DC4, the fifth delay cell DC5, and the sixth delay cell DC6 can be referred to as a plurality of first delay cells, and the seventh delay cell DC7 can be referred to as a second delay cell.

[0102] The first delay cell DC1 can include a first p-channel metal-oxide-semiconductor (PMOS) capacitor (e.g., a first MOS capacitor) PC1 coupled to a supply voltage VDD, a first n-channel metal-oxide-semiconductor (NMOS) capacitor (e.g., a second MOS capacitor) NC1 coupled to a ground voltage VSS, a first PMOS transistor PM1 coupled to a gate of the first PMOS capacitor PC1, and a first NMOS transistor NM1 coupled to a gate of the first NMOS capacitor NC1.

[0103] The first PMOS transistor PM1 can have a source coupled to the gate of the first PMOS capacitor PC1, a gate to receive a seventh inverted version CCD17B of a corresponding seventh bit CCD17 of the first control code set CCD1, and a drain coupled to a first node N11. The first node N11 can be commonly coupled to the drain of the first PMOS transistor PM1, an output of the first inverter INV11, and an input of the second inverter INV12. The first NMOS transistor NM1 can have a source coupled to the gate of the first NMOS capacitor NC1, a gate to receive the corresponding seventh bit CCD17 of the first control code set CCD1, and a drain coupled to the first node N11. The source of the first PMOS transistor PM1 and the source of the first NMOS transistor NM1 can be coupled to each other.

[0104] The second delay cell DC2 can include a second PMOS capacitor PC2 coupled to the supply voltage VDD, a second NMOS capacitor NC2 coupled to the ground voltage VSS, a second PMOS transistor PM2 coupled to a gate of the second PMOS capacitor PC2, and a second NMOS transistor NM2 coupled to a gate of the second NMOS capacitor NC2.

[0105] The second PMOS transistor PM2 can have a source coupled to a gate of the second PMOS capacitor PC2, a gate to receive a sixth inverted version CCD16B of a corresponding sixth bit CCD16 of the first control code set CCD1, and a drain coupled to the first node N11. The second NMOS transistor NM2 can have a source coupled to a gate of the second NMOS capacitor NC2, a gate to receive the corresponding sixth bit CCD16 of the first control code set CCD1, and a drain coupled to the first node N11. The source of the second PMOS transistor PM2 and the source of the second NMOS transistor NM2 can be coupled to each other.

[0106] The third delay cell DC3 can include a third PMOS capacitor PC3 coupled to the supply voltage VDD, a third NMOS capacitor NC3 coupled to the ground voltage VSS, a third PMOS transistor PM3 coupled to a gate of the third PMOS capacitor PC3, and a third NMOS transistor NM3 coupled to a gate of the third NMOS capacitor NC3.

[0107] The third PMOS transistor PM3 can have a source coupled to a gate of the third PMOS capacitor PC3, a gate to receive a fifth inverted version CCD15B of a corresponding fifth bit CCD15 of the first control code set CCD1, and a drain coupled to a second node N12. The second node N12 can be commonly coupled to the drain of the third PMOS transistor PM3, an output of a second inverter INV12, and an input of a third inverter INV13. The third NMOS transistor NM3 can have a source coupled to a gate of the third NMOS capacitor NC3, a gate to receive the corresponding fifth bit CCD15 of the first control code set CCD1, and a drain coupled to the second node N12. The source of the third PMOS transistor PM3 and the source of the third NMOS transistor NM3 can be coupled to each other.

[0108] The fourth delay cell DC4 can include a fourth PMOS capacitor PC4 coupled to the supply voltage VDD, a fourth NMOS capacitor NC4 coupled to the ground voltage VSS, a fourth PMOS transistor PM4 coupled to a gate of the fourth PMOS capacitor PC4, and a fourth NMOS transistor NM4 coupled to a gate of the fourth NMOS capacitor NC4.

[0109] The fourth PMOS transistor PM4 can have a source coupled to a gate of the fourth PMOS capacitor PC4, a gate to receive a fourth inverted version CCD14B of a corresponding fourth bit CCD14 of the first control code set CCD1, and a drain coupled to the second node N12. The fourth NMOS transistor NM4 can have a source coupled to a gate of the fourth NMOS capacitor NC4, a gate to receive the corresponding fourth bit CCD14 of the first control code set CCD1, and a drain coupled to the second node N12. The source of the fourth PMOS transistor PM4 and the source of the fourth NMOS transistor NM4 can be coupled to each other.

[0110] The fifth delay cell DC5 can include a fifth PMOS capacitor PC5 coupled to the supply voltage VDD, a fifth NMOS capacitor NC5 coupled to the ground voltage VSS, a fifth PMOS transistor PM5 coupled to a gate of the fifth PMOS capacitor PC5, and a fifth NMOS transistor NM5 coupled to a gate of the fifth NMOS capacitor NC5.

[0111] The fifth PMOS transistor PM5 can have a source coupled to a gate of the fifth PMOS capacitor PC5, a gate to receive a third inverted version CCD13B of a corresponding third bit CCD13 of the first control code set CCD1, and a drain coupled to a third node N13. The third node N13 can be commonly coupled to the drain of the fifth PMOS transistor PM5, an output of a third inverter INV13, and an input of a fourth inverter INV14. The fifth NMOS transistor NM5 can have a source coupled to a gate of the fifth NMOS capacitor NC5, a gate to receive the corresponding third bit CCD13 of the first control code set CCD1, and a drain coupled to the third node N13. The source of the fifth PMOS transistor PM5 and the source of the fifth NMOS transistor NM5 can be coupled to each other.

[0112] The sixth delay cell DC6 can include a sixth PMOS capacitor PC6 coupled to the supply voltage VDD, a sixth NMOS capacitor NC6 coupled to the ground voltage VSS, a sixth PMOS transistor PM6 coupled to a gate of the sixth PMOS capacitor PC6, and a sixth NMOS transistor NM6 coupled to a gate of the sixth NMOS capacitor NC6.

[0113] The sixth PMOS transistor PM6 can have a source coupled to a gate of the sixth PMOS capacitor PC6, a gate to receive a second inverted version CCD12B of a corresponding second bit CCD12 of the first control code set CCD1, and a drain coupled to the third node N13. The sixth NMOS transistor NM6 can have a source coupled to a gate of the sixth NMOS capacitor NC6, a gate to receive the corresponding second bit CCD12 of the first control code set CCD1, and a drain coupled to the third node N13. The source of the sixth PMOS transistor PM6 and the source of the sixth NMOS transistor NM6 can be coupled to each other.

[0114] The seventh delay cell DC7 can include a seventh PMOS capacitor PC7 coupled to the power supply voltage VDD, a seventh NMOS capacitor NC7 coupled to the ground voltage VSS, a seventh PMOS transistor PM7 coupled to a gate of the seventh PMOS capacitor PC7, and a seventh NMOS transistor NM7 coupled to a gate of the seventh NMOS capacitor NC7.

[0115] The seventh PMOS transistor PM7 can have a source coupled to a gate of the seventh PMOS capacitor PC7, a gate to receive a first inverted version CCD11B of a corresponding first bit CCD11 of the first control code set CCD1, and a drain coupled to an output node NO coupled to an output of the fourth inverter INV14. The seventh NMOS transistor NM7 can have a source coupled to a gate of the seventh NMOS capacitor NC7, a gate to receive the corresponding first bit CCD11 of the first control code set CCD1, and a drain coupled to the output node NO. The source of the seventh PMOS transistor PM7 and the source of the seventh NMOS transistor NM7 can be coupled to each other.

[0116] The first duty cycle adjuster 240a can generate the first adjusted clock signal ACLKI by adjusting an amount of delay of at least one of rising and falling edges of the first divided clock signal DCLKI based on the first bit CCD11 to the seventh bit CCD17 and the first inverted version CCD11B to the seventh inverted version CCD17B of the first control code set CCD1.

[0117] Although an example of a configuration of the first duty cycle adjuster 240a in the duty cycle adjustment circuit 240 is shown in FIG. 6A However, the respective configurations of the second duty cycle adjuster 240b, the third duty cycle adjuster 240c, and the fourth duty cycle adjuster 240d can be substantially similar and / or identical to the configuration of the first duty cycle adjuster 240a.

[0118] That is, the second duty cycle adjuster 240b can generate the second adjusted clock signal ACLKQ by adjusting an amount of delay of at least one of a rising edge and a falling edge of the second divided clock signal DCLKQ based on bits and inverted versions of the second control code set CCD2. The third duty cycle adjuster 240c can generate the third adjusted clock signal ACLKIB by adjusting an amount of delay of at least one of a rising edge and a falling edge of the third divided clock signal DCLKIB based on bits and inverted versions of the third control code set CCD3. The fourth duty cycle adjuster 240d can generate the fourth adjusted clock signal ACLKQB by adjusting an amount of delay of at least one of a rising edge and a falling edge of the fourth divided clock signal DCLKQB based on bits and inverted versions of the fourth control code set CCD4.

[0119] FIG. 6B It is shown FIG. 3 that the duty cycle adjustment circuit adjusts a duty cycle of each of the plurality of divided clock signals DCLKI to DCLKQB.

[0120] Referring to FIG. 3 and FIG. 6B , the first duty cycle adjuster 240a can generate the first adjusted clock signal ACLKI by adjusting an amount of delay of a rising edge of the first divided clock signal DCLKI (operation 241a) and / or by adjusting an amount of delay of a falling edge of the first divided clock signal DCLKI (operation 241b) based on the first control code set CCD1. The second duty cycle adjuster 240b can generate the second adjusted clock signal ACLKQ by adjusting an amount of delay of a rising edge of the second divided clock signal DCLKQ (operation 242a) and / or by adjusting an amount of delay of a falling edge of the second divided clock signal DCLKQ (operation 242b) based on the second control code set CCD2. The third duty cycle adjuster 240c can generate the third adjusted clock signal ACLKIB by adjusting an amount of delay of a rising edge of the third divided clock signal DCLKIB (operation 243a) and / or by adjusting an amount of delay of a falling edge of the third divided clock signal DCLKIB (operation 243b) based on the third control code set CCD3. The fourth duty cycle adjuster 240d can generate the fourth adjusted clock signal ACLKQB by adjusting an amount of delay of a rising edge of the fourth divided clock signal DCLKQB (operation 244a) and / or by adjusting an amount of delay of a falling edge of the fourth divided clock signal DCLKQB (operation 244b) based on the fourth control code set CCD4.

[0121] FIG. 7 is a block diagram showing an example of an RDQS generation circuit in a buffer die according to an example embodiment. FIG. 3

[0122] Referring to FIG. 7 ​The RDQS generation circuit 250 can include a first multiplexer 251, a second multiplexer 252, a first driver 253, and a second driver 254.

[0123] The first multiplexer 251 can sequentially select bits of the first predetermined pattern data PTD1 based on a four-phase clock signal CLK_4P including a plurality of read clock signals CLKI to CLKQB, and the first driver 253 can output the first read strobe signal RDQS by driving an output of the first multiplexer 251. The first multiplexer 251 can sequentially select bits of the first predetermined pattern data PTD1 at respective rising edges of the plurality of read clock signals CLKI to CLKQB.

[0124] The second multiplexer 252 can sequentially select bits of the second predetermined pattern data PTD2 based on the four-phase clock signal CLK_4P including the plurality of read clock signals CLKI to CLKQB, and the second driver 254 can output the second read strobe signal RDQSB by driving an output of the second multiplexer 252. The second multiplexer 252 can sequentially select bits of the second predetermined pattern data PTD2 at respective rising edges of the plurality of read clock signals CLKI to CLKQB.

[0125] For example, the bits of the first predetermined pattern data PTD1 can correspond to "H," "L," "H," and "L," and the bits of the second predetermined pattern data PTD2 can correspond to "L," "H," "L," and "H." However, the present disclosure is not limited in this regard, and the first predetermined pattern data PTD1 and the second predetermined pattern data PTD2 can correspond to other patterns. As used herein, "H" can refer to a logic high level, and "L" can refer to a logic low level. Alternatively, "H" can refer to a logic low level, and "L" can refer to a logic high level. Each bit of the first predetermined pattern data PTD1 can be complementary to a corresponding bit of the second predetermined pattern data PTD2. As a result, the first read strobe signal RDQS and the second read strobe signal RDQSB can have a phase difference of 180 degrees.

[0126] FIG. 8 is a timing diagram illustrating an example operation of an RDQS generation circuit of FIG. 7

[0127] Referring to FIG. 7 and FIG. 8 ​When the bits of the first predetermined pattern data PTD1 correspond to "H", "L", "H", and "L", the first multiplexer 251 can output the first read strobe signal RDQS by sequentially selecting the bits of the first predetermined pattern data PTD1 at each rising edge of the plurality of read clock signals CLKI to CLKQB. As a result, the first read strobe signal RDQS can have the same bits as the bits of the first predetermined pattern data PTD1, and the frequency of the first read strobe signal RDQS can be twice (2) the frequency of each of the plurality of read clock signals CLKI to CLKQB.

[0128] FIG. 8 Generating the first read strobe signal RDQS is shown. In an embodiment, each bit of the first predetermined pattern data PTD1 can be complementary to a corresponding bit of the second predetermined pattern data PTD2, and thus, the first read strobe signal RDQS and the second read strobe signal RDQSB can have a phase difference of 180 degrees.

[0129] FIG. 9 An example of first predetermined pattern data and second predetermined pattern data in a strobe signal generation circuit according to example embodiments is shown. FIG. 7

[0130] Referring to FIG. 7 and FIG. 9 , each bit of the first predetermined pattern data PTD1 can be complementary to a corresponding bit of the second predetermined pattern data PTD2.

[0131] The first predetermined pattern data PTD1 having bits of "H", "L", "H", and "L" and the second predetermined pattern data PTD2 having bits of "L", "H", "L", and "H" can be referred to as default pattern data.

[0132] Each phase of the first read strobe signal RDQS and the second read strobe signal RDQSB can be determined by the first predetermined pattern data PTD1 and the second predetermined pattern data PTD2 at a rising edge of each of the plurality of read clock signals CLKI to CLKQB.

[0133] FIG. 10 A frequency of a clock signal buffer die according to example embodiments is shown. FIG. 3

[0134] Referring to FIG. 3 , FIG. 4 and FIG. 10 ​​When a frequency of the first source clock signal SCLK1 generated by the oscillator 212 is about 8 gigabits per second (Gbps), for example, each of the first write enable signal WDQS and the second write enable signal WDQSB can be about 8 Gbps in frequency, each of the plurality of read clock signals CLKI to CLKQB included in the four-phase clock signal CLK_4P can be about 4 Gbps in frequency, and each of the first read enable signal RDQS and the second read enable signal RDQSB can be about 8 Gbps in frequency.

[0135] FIG. 11 is a block diagram illustrating an example of a delay controller in a buffer die of FIG. 3 according to an example embodiment.

[0136] Referring to FIG. 11 , the delay controller 280 can include a first multiplexer 281, a second multiplexer 282, a third multiplexer 283, a fourth multiplexer 284, a first decoder 290a, a second decoder 290b, a third decoder 290c, and a fourth decoder 290d.

[0137] The first multiplexer 281 can output a first selected calibration code SCD1 by selecting a first automatic sub-code S_ACD1 of an automatic calibration code ACD or a first fuse sub-code S_FCD1 of a fuse calibration code FCD based on an automatic calibration code enable signal AC_EN. The first decoder 290a can generate a first control code set CCD1 by decoding the first selected calibration code SCD1. The first automatic sub-code S_ACD1 and the first fuse sub-code S_FCD1 can be associated with a duty cycle of a first divided clock signal DCLKI.

[0138] The second multiplexer 282 can output a second selected calibration code SCD2 by selecting a second automatic sub-code S_ACD2 of the automatic calibration code ACD or a second fuse sub-code S_FCD2 of the fuse calibration code FCD based on the automatic calibration code enable signal AC_EN. The second decoder 290b can generate a second control code set CCD2 by decoding the second selected calibration code SCD2. The second automatic sub-code S_ACD2 and the second fuse sub-code S_FCD2 can be associated with a duty cycle of a second divided clock signal DCLKQ.

[0139] The third multiplexer 283 can output a third selected calibration code SCD3 by selecting the third automatic sub-code S_ACD3 of the automatic calibration code ACD or the third fuse sub-code S_FCD3 of the fuse calibration code FCD based on the automatic calibration code enable signal AC_EN. The third decoder 290c can generate a third control code set CCD3 by decoding the third selected calibration code SCD3. The third automatic sub-code S_ACD3 and the third fuse sub-code S_FCD3 can be associated with a duty cycle of the third divided clock signal DCLKIB.

[0140] The fourth multiplexer 284 can output a fourth selected calibration code SCD4 by selecting the fourth automatic sub-code S_ACD4 of the automatic calibration code ACD or the fourth fuse sub-code S_FCD4 of the fuse calibration code FCD based on the automatic calibration code enable signal AC_EN. The fourth decoder 290d can generate a fourth control code set CCD4 by decoding the fourth selected calibration code SCD4. The fourth automatic sub-code S_ACD4 and the fourth fuse sub-code S_FCD4 can be associated with a duty cycle of the fourth divided clock signal DCLKIQ.

[0141] Each of the first multiplexer 281, the second multiplexer 282, the third multiplexer 283, and the fourth multiplexer 284 can select a respective one of the first automatic sub-code S_ACD1, the second automatic sub-code S_ACD2, the third automatic sub-code S_ACD3, and the fourth automatic sub-code S_ACD4 in response to the automatic calibration code enable signal AC_EN being activated (e.g., when the automatic calibration code enable signal AC_EN has a logic high level), and can select a respective one of the first fuse sub-code S_FCD1, the second fuse sub-code S_FCD2, the third fuse sub-code S_FCD3, and the fourth fuse sub-code S_FCD4 in response to the automatic calibration code enable signal AC_EN being deactivated (e.g., when the automatic calibration code enable signal AC_EN has a logic low level).

[0142] The first automatic sub-code S_ACD1, the second automatic sub-code S_ACD2, the third automatic sub-code S_ACD3, and the fourth automatic sub-code S_ACD4 can be included in the automatic calibration code ACD described with reference to FIG. 3 The first fuse sub-code S_FCD1, the second fuse sub-code S_FCD2, the third fuse sub-code S_FCD3, and the fourth fuse sub-code S_FCD4 can be included in the fuse calibration code FCD described with reference to FIG. 3 The first selected calibration code SCD1, the second selected calibration code SCD2, the third selected calibration code SCD3, and the fourth selected calibration code SCD4 can be included in the selected calibration code SCD.

[0143] FIG. 12 is a circuit diagram illustrating an example of a first decoder in a delay controller of FIG. 11

[0144] Referring to FIG. 12 , the first decoder 290a can include a plurality of inverters (e.g., a first inverter INV21, a second inverter INV22, a third inverter INV23, a fourth inverter INV24, a fifth inverter INV25, a sixth inverter INV26, and a seventh inverter INV27), a plurality of NOR gates (e.g., a first NOR gate 291, a second NOR gate 292, a third NOR gate 293, and a fourth NOR gate 294), and a plurality of NAND gates (e.g., a first NAND gate 295, a second NAND gate 296, a third NAND gate 297, and a fourth NAND gate 298).

[0145] The first inverter INV21 can invert a first bit SCD11 of the first selected calibration code SCD1. The second inverter INV22 can invert a second bit SCD12 of the first selected calibration code SCD1. The third inverter INV23 can invert a third bit SCD13 of the first selected calibration code SCD1.

[0146] The first NOR gate 291 can output a seventh bit CCD17 of the first control code set CCD1 by performing a NOR operation on outputs of the first inverter INV21, the second inverter INV22, and the third inverter INV23. The second NOR gate 292 can output a sixth bit CCD16 of the first control code set CCD1 by performing a NOR operation on outputs of the first inverter INV21 and the second inverter INV22. The first NAND gate 295 can perform a NAND operation on outputs of the second inverter INV22 and the third inverter INV23, the fourth inverter INV24 can invert an output of the first NAND gate 295, and the third NOR gate 293 can output a fifth bit CCD15 of the first control code set CCD1 by performing a NOR operation on outputs of the second inverter INV22 and the fourth inverter INV24.

[0147] ​The fifth inverter INV25 can output the fourth bit CCD14 of the first control code set CCD1 by inverting the output of the first inverter INV21. The fourth NOR gate 294 can perform a NOR operation on the outputs of the second inverter INV22 and the third inverter INV23, the sixth inverter INV26 can invert the output of the fourth NOR gate 294, and the second NAND gate 296 can output the third bit CCD13 of the first control code set CCD1 by performing a NAND operation on the outputs of the first inverter INV21 and the sixth inverter INV26. The third NAND gate 297 can output the second bit CCD12 of the first control code set CCD1 by performing a NAND operation on the outputs of the first inverter INV21 and the second inverter INV22. The fourth NAND gate 298 can output the first bit CCD11 of the first control code set CCD1 by performing a NAND operation on the outputs of the first inverter INV21, the second inverter INV22, and the third inverter INV23.

[0148] The first decoder 290a can generate the first control code set CCD1 including seven (7) bits by decoding the three (3) bits of the first selected calibration code SCD1.

[0149] Although FIG. 12 The configuration of the first decoder 290a in the delay controller 280 of FIG. 11 The respective configurations of the second decoder 290b, the third decoder 290c, and the fourth decoder 290d can be substantially similar and / or identical to the configuration of the first decoder 290a.

[0150] FIG. 13 An example of the first selected calibration code and the first control code set in the first decoder according to example embodiments is shown. FIG. 12

[0151] Referring to FIG. 12 and FIG. 13 ​When the binary value of the first selected calibration code SCD1 including the bits SCD11, SCD12, and SCD13 is sequentially increased from zero (for example, "0" or "000") to seven (for example, "7" or "111"), the number of bits having a logic high level in the first control code set CCD1 (for example, the first bit CCD11, the second bit CCD12, the third bit CCD13, the fourth bit CCD14, the fifth bit CCD15, the sixth bit CCD16, and the seventh bit CCD17) can be sequentially increased from zero (0) to seven (7). In an embodiment, the first selected calibration code SCD1 of "100" and the first control code set CCD1 of "1111100" can be set as default values. However, the disclosure is not limited thereto, and the first selected calibration code SCD1 and the first control code set CCD1 can be set as other default values. That is, the first decoder 290a can decode the first selected calibration code SCD1 so that the number of bits having a logic high level in the first control code set CCD1 can be sequentially increased and / or decreased from the default values.

[0152] FIG. 14A , FIG. 14B and FIG. 14C are diagrams illustrating an offset compensation scheme of a WDQS generation circuit according to an embodiment. FIG. 4

[0153] In FIG. 14A , FIG. 14B and FIG. 14C , I / IB ofs can refer to an offset between the first signal and the third signal having a phase difference of 180 degrees, Q / QB ofs can refer to an offset between the second signal and the fourth signal having a phase difference of 180 degrees, and a read path R_PTH 1410 can refer to a path provided by the frequency division and conversion circuit 230, the duty cycle adjustment circuit 240, the clock tree 245, the RDQS generation circuit 250, and the skew monitoring circuit 260 in FIG. 3 , and a duty cycle monitor (DCM) 1420 can refer to the first duty cycle monitor 261 and the second duty cycle monitor 271 in FIG. 3 . In addition, +α can refer to an offset of the WDQS generation circuit 210, and +β can refer to an offset of the read path R_PTH 1410.

[0154] Referring to FIG. 14A ​When the flip is deactivated in response to the second selection signal SS2 having a logical low level, the first signal and the third signal of the WDQS generation circuit 210 can have an offset of +a, and the first signal and the third signal of the read path R_PTH 1410 can have an offset of +a+ß. Accordingly, the DCM 1420 can monitor the duty cycle such that the second signal and the fourth signal of the read path R_PTH 1410 can have an offset of +a+ß.

[0155] Referring to FIG. 14B When the flip is activated in response to the second selection signal SS2 having a logical high level, the first signal and the third signal of the WDQS generation circuit 210 have a zero (e.g., "0") offset, the second signal and the fourth signal of the WDQS generation circuit 210 can have an offset of +a, and the second signal and the fourth signal of the read path R_PTH 1410 can have an offset of +a. Accordingly, the DCM 1420 can monitor the duty cycle such that the second signal and the fourth signal of the read path R_PTH 1410 can have an offset of -a+ß.

[0156] Referring to FIG. 14C When the trim circuit 270 averages the first auto-calibration code regarding the offset +a+ß obtained when the flip is deactivated and the second auto-calibration code regarding the offset -a+ß obtained when the flip is activated, the offset of the WDQS generation circuit 210 can be eliminated, the first signal and the third signal of the read path R_PTH 1410 can have an offset of +ß, and the second signal and the fourth signal of the read path R_PTH 1410 can have an offset of +ß.

[0157] FIG. 15 FIG. 1 is a flowchart illustrating a manufacturing process of a stacked memory device according to an example embodiment.

[0158] Referring to FIGS. 1-15 A plurality of first dies 180 can be disposed on the first wafer 170 (operation S110). The ATE 40 can perform an ESD test on each of the buffer dies 200 disposed in the plurality of first dies 180 to generate a control code set for compensating for skew between a first read strobe signal RDQS and a second read strobe signal in each of the buffer dies 200 (operation S130).

[0159] The ATE 40 can determine whether each of the first dies 180 passes the test based on a result of the wafer-level test (operation S150).

[0160] In parallel with operations S110, S130, and S150, a plurality of second dies can be disposed on a second wafer (operation S210). The ATE can perform an ESD test on each of a plurality of volatile memory devices (e.g., core dies) disposed in the second dies (operation S230). The ATE can determine whether each of the core dies passes the test based on a result of the ESD test (operation S250).

[0161] When a first die of the plurality of first dies 180 fails the ESD test (NO in operation S150), the corresponding first die can be processed as a failed die (operation S160). When a first die of the plurality of first dies 180 passes the ESD test (YES in operation S150), a control code set can be stored in the second code storage 275 in the corresponding first die as a fuse calibration code FCD (operation S170).

[0162] When a second die of the plurality of second dies fails the ESD test (NO in operation S250), the corresponding second die can be processed as a failed die (operation S260). When a second die of the plurality of second dies passes the ESD test (YES in operation S250), the corresponding buffer die 200 that passes the ESD test and a portion of the volatile memory devices that pass the ESD test can be packaged into a high bandwidth memory (HBM) (operation S310). The HBM (e.g., a stacked memory device) can be shipped as a product (operation S330).

[0163] FIG. 16 is a flowchart illustrating an operation of generating a control code set in FIG. 15 according to an example embodiment.

[0164] Referring to FIG. 3 and FIG. 16 To generate a control code set (operation S130), the WDQS generation circuit 210 can generate a first write strobe signal WDQS and a second write strobe signal WDQSB having a 180-degree phase difference based on a source clock signal SCLK (operation S135). The RDQS generation circuit 250 can generate a first read strobe signal RDQS and a second read strobe signal RDQSB having a 180-degree phase difference based on the first predetermined pattern data PTD1, the second predetermined pattern data PTD2, and a plurality of read clock signals CLKI to CLKQB that can be generated based on the first write strobe signal WDQS and the second write strobe signal WDQSB (operation S140). The trimming circuit 270 can generate a plurality of control code sets CCD1 to CCD4 based on monitoring a duty cycle of the first read strobe signal RDQS and the second read strobe signal RDQSB (operation S145).

[0165] That is, according to a manufacturing process of the stacked memory device, the WDQS generation circuit 210 can be formed in each of the buffer dies on a wafer before being packaged into the HBM, the WDQS generation circuit 210 can generate the first write strobe signal WDQS and the second write strobe signal WDQSB, and can compensate for skew between the first read strobe signal RDQS and the second read strobe signal RDQSB by monitoring duty cycles of the first read strobe signal RDQS and the second read strobe signal RDQSB, which can be generated based on the first write strobe signal WDQS and the second write strobe signal WDQS.

[0166] FIG. 17 is a block diagram illustrating a stacked memory device according to an example embodiment.

[0167] Referring to FIG. 17 The stacked memory device 70 can include a buffer die 300 and a plurality of core dies (e.g., a first core die 400a, a second core die 400b, a third core die 400c, and a fourth core die 400d). In an embodiment, the buffer die 300 can be referred to as an interface die, a base die, a logic die, a master die, etc., and each of the plurality of core dies 400a to 400d can be referred to as a memory die, a slave die, etc. Although FIG. 17 The stacked memory device 700 is illustrated as having four core dies 400a to 400d, but the present disclosure is not limited in this regard, and the number of core dies can be varied differently. For example, the stacked memory device 70 can include 8, 12, or 16 core dies.

[0168] The buffer die 300 and the plurality of core dies 400a to 400d can be stacked and can be electrically connected by using through silicon vias (TSVs). As such, the stacked memory device 70 can have a three-dimensional (3D) memory structure in which a plurality of dies 300 and 400a to 400D can be stacked. For example, the stacked memory device 70 can be implemented in compliance with HBM and / or hybrid memory cube (HMC) standards.

[0169] The stacked memory device 70 can support a plurality of channels (or banks) that can be independent of each other in function. For example, as FIG. 17As shown in FIG. 6, the stacked memory device 70 can support multiple channels (e.g., a first channel CH0, a second channel CH1, a third channel CH2, a fourth channel CH3, a fifth channel CH4, a sixth channel CH5, a seventh channel CH6, and an eighth channel CH7). The stacked memory device 70 can support 1024 DQ inputs / outputs (I / Os) in a case where each of the multiple channels CH0 to CH7 supports 128 DQ I / Os. However, the present disclosure is not limited thereto. For example, the stacked memory device 70 can support 1024 or more DQ I / Os and can support 8 or more channels (e.g., 16 channels). In a case where the stacked memory device 70 supports 16 channels, each of the multiple channels can support 64 DQ I / Os.

[0170] Each of the multiple core dies 400a to 400d can support at least one channel. For example, as shown in FIG. 4, the multiple core dies 400a to 400d can support a first channel CH0, a second channel CH1, a third channel CH2, and a fourth channel CH3, respectively. In this case, the multiple core dies 400a to 400d can support different channels. However, the present disclosure is not limited thereto. For example, at least two of the core dies 400a to 400d can support the same channel. As another example, each of the core dies 400a to 400d can support a first channel CH0. FIG. 17 As shown in FIG. 6, the multiple core dies 400a to 400d can support channel pairs (e.g., a first pair including the first channel CH0 and the third channel CH2, a second pair including the second channel CH1 and the fourth channel CH3, a third pair including the fifth channel CH4 and the seventh channel CH6, and a fourth pair including the sixth channel CH5 and the eighth channel CH7), respectively. In this case, the multiple core dies 400a to 400d can support different channels. However, the present disclosure is not limited thereto. For example, at least two of the core dies 400a to 400d can support the same channel. As another example, each of the core dies 400a to 400d can support a first channel CH0.

[0171] Each of the multiple channels CH0 to CH7 can form an independent command and data interface. For example, each channel can be independently clocked based on independent timing requirements, and the channels can be unsynchronized with each other. As another example, based on independent commands, each channel can change a power state and / or can perform a refresh.

[0172] Each of the multiple channels CH0 to CH7 can include multiple memory banks 401. Each of the memory banks 401 can include memory cells connected with word lines and / or bit lines, row decoders, column decoders, sense amplifiers, etc. For example, as shown in FIG. 6, each of the memory banks 401 can include a plurality of memory cells 402 connected with word lines WL0 to WLm and bit lines BL0 to BLn. FIG. 17As shown, each of the plurality of channels CH0 to CH7 can support eight memory banks 401, such as a plurality of memory banks including a first memory bank Bank0, a second memory bank Bankl, a third memory bank Bank2, a fourth memory bank Bank3, a fifth memory bank Bank4, a sixth memory bank Bank5, a seventh memory bank Bank6, and an eighth memory bank Bank7. However, the present disclosure is not limited thereto. For example, each of the plurality of channels CH0 to CH7 can support eight (8) or more memory banks 401. Although FIG. 17 The memory banks are shown as belonging to a memory bank of a channel included in one core die, but the present disclosure is not limited in this respect. For example, the memory banks belonging to a channel can be distributed into multiple core dies. As another example, in a case where each of the plurality of core dies 400a to 400d supports a first channel CH0, the memory banks included in the first channel CH0 can be distributed into the first core die 400a, the second core die 400b, the third core die 400c, and the fourth core die 400d.

[0173] In an example embodiment, one channel can be divided into two pseudo-channels that can operate independently from each other. For example, the pseudo-channels can share the command and the clock input (e.g., clock signal, clock enable signal, etc.) of the corresponding channel, but can independently decode and execute the command. For example, in a case where one channel supports 128 DQ I / Os, each of the pseudo-channels can support 64 DQ I / Os. As another example, in a case where one channel supports 64 DQ I / Os, each of the pseudo-channels can support 32 DQ I / Os.

[0174] The buffer die 300 and the plurality of core dies 400a to 400d can each include a TSV region 402. The TSVs configured to penetrate the buffer die 300 and the plurality of core dies 400a to 400d can be disposed in the TSV region 402. The buffer die 300 can exchange signals and / or data with the plurality of core dies 400a to 400d through the TSVs. Each of the plurality of core dies 400a to 400d can exchange signals and / or data with the buffer die 300 through the TSVs, and the plurality of core dies 400a to 400d can exchange signals and / or data with each other through the TSVs. In this case, signals and / or data can be independently exchanged through the respective TSVs of each channel. For example, in the case where an external host device transmits a command and an address to a first channel CH0 to access a memory cell of the first core die 400a, the buffer die 300 can transmit a control signal to the first core die 400a through a TSV corresponding to the first channel CH0, and can access the memory cell of the first channel CH0.

[0175] The buffer die 300 can include a physical layer PHY 310. The physical layer PHY 310 can include an interface circuit 311 for communication with an external host device. For example, the interface circuit 311 can include a WDQS generation circuit 210, a frequency division and conversion circuit 230, a duty cycle adjustment circuit 240, a clock tree 245, an RDQS generation circuit 250, a skew monitoring circuit 260, and a trimming circuit 270 of FIG. 2. FIG. 3

[0176] In an example embodiment, the buffer die 300 can include channel controllers corresponding to channels, respectively. The channel controllers can manage memory reference operations of the corresponding channels, and can determine timing requirements of the corresponding channels.

[0177] In an example embodiment, the buffer die 300 can include a plurality of pins for receiving signals from an external host device. Through the plurality of pins, the buffer die 300 can receive a clock signal CK, a command / address signal, a write data strobe signal, and a data signal DQ, and can transmit a read data strobe signal and a data signal. For example, for each channel, the buffer die 300 can include two (2) pins for receiving a clock signal, fourteen (14) pins for receiving a command / address signal, eight (8) pins for receiving a write data strobe signal, eight (8) pins for transmitting a read data strobe signal, and 128 pins for transmitting and / or receiving a data signal. However, the disclosure is not limited in this regard. ​

[0178] FIG. 18 is a block diagram illustrating an example of a stacked memory device according to an example embodiment. FIG. 17

[0179] Referring to FIG. 18 , the stacked memory device 70a can include a buffer die 300, a first core die 400a, and a second core die 400b. The first core die 400a and the second core die 400b can support the same channel CHa among a plurality of channels. In this case, the first core die 400a and the second core die 400b can be distinguished by using a stack identifier SID. For example, the first core die 400a can correspond to a first stack identifier SID0, and the second core die 400b can correspond to a second stack identifier SID1. FIG. 18 It is illustrated that there is no other core die interposed between the first core die 400a and the second core die 400b. However, the disclosure is not limited to this aspect. That is, another core die can be interposed between the first core die 400a and the second core die 400b.

[0180] The buffer die 300 and the first core die 400a and the second core die 400b can communicate with each other through the first TSV 302 and the second TSV 303 placed in the TSV region 301. For example, the buffer die 300 can transmit an internal command I CMD to the first core die 400a and / or the second core die 400b through the first TSV 302, and can exchange data DTA with the first core die 400a and / or the second core die 400b through the second TSV 303. In FIG. 18 It is illustrated in that the buffer die 300 communicates with the first core die 400a and the second core die 400b by using the same first TSV 302 and second TSV 303. However, the disclosure is not limited to this aspect. For example, the buffer die 300 can communicate by using separate TSVs corresponding to the first core die 400a and the second core die 400b, respectively.

[0181] The buffer die 300 can include an interface circuit 311. The interface circuit 311 can include a command / address (C / A) receiver 312, a control logic circuit 313, a WDQS divider 314, an RDQS transceiver 315, a data transceiver 316, and an RDQS generator 320. The RDQS generator 320 can include the divider and conversion circuit 230, the duty cycle adjustment circuit 240, the clock tree 245, the RDQS generation circuit 250, the skew monitoring circuit 260, and the trimming circuit 270 described with reference to FIG. 3

[0182] ​​The C / A receiver 312 can receive the command CMD and the stack identifier SID by latching the command / address signal C / A based on the clock signal CK. The stack identifier SID can be an address indicating at least one core die to identify a core die supporting a same channel. The received command CMD and the stack identifier SID can be provided to the control logic circuit 313.

[0183] The control logic circuit 313 can generate an internal command ICMD based on the stack identifier SID, and can transmit the internal command ICMD to at least one of the first core die 400a and the second core die 400b. For example, in a case where the stack identifier SID indicates a first stack identifier SID0, the control logic circuit 313 can transmit the internal command ICMD to the first core die 400a.

[0184] In an embodiment, the internal command ICMD can be generated in a format different from a format of the command CMD in compliance with an internal communication protocol between the buffer die 300 and the first core die 400a and the second core die 400b, or can be generated in a same format as the format of the command CMD. The internal command ICMD can be transmitted to at least one of the first core die 400a and the second core die 400b through the first TSV 302.

[0185] In an example embodiment, as FIG. 18 illustrated, in a case where the internal command ICMD and the data DTA are transmitted to the first core die 400a and the second core die 400b through the common first TSV 302 and the second TSV 303, the buffer die 300 can transmit the stack identifier SID to the first core die 400a and the second core die 400b. The first core die 400a and the second core die 400b can decode the transmitted stack identifier SID to selectively receive the internal command ICMD and the data DTA. For example, in a case where the stack identifier SID indicates the first stack identifier SID0, the first core die 400a can receive the internal command ICMD and the data DTA transmitted through the first TSV 302 and the second TSV 303. In this case, the second core die 400b can not receive the internal command ICMD and the data DTA transmitted through the first TSV 302 and the second TSV 303.

[0186] In an example embodiment, in a case where the internal command ICMD and the data DTA are transmitted to the first core die 400a and the second core die 400b through separate TSVs, the buffer die 300 can transmit the internal command ICMD and the data DTA to a core die corresponding to the stack identifier SID through the separate TSVs.

[0187] In a case where the first core die 400a and the second core die 400b support the same channel CHa, the stacked memory device 70a can perform a write operation and a read operation on at least one of the first core die 400a and the second core die 400b according to the stack identifier SID.

[0188] The WDQS divider 314 can receive the write enable signal WDQS and can generate an internal write enable signal dWDQS based on the write enable signal WDQS. The RDQS generator 320 can generate the read enable signal RDQS based on the internal write enable signal dWDQS and can provide the read enable signal RDQS to the RDQS transceiver 315.

[0189] The RDQS transceiver 315 can transmit the read enable signal RDQS to an external host device.

[0190] The data transceiver 316 can transmit and / or receive a data signal DQ including data DTA based on the internal write data enable signal dWDQS. In a write operation, the data transceiver 316 can receive the data DTA by latching the data signal DQ based on the internal write data enable signal dWDQS. The received data DTA can be transmitted to at least one of the first core die 400a and the second core die 400b through the second TSV 303. In a read operation, the data transceiver 316 can receive the data DTA transmitted from at least one of the first core die 400a and the second core die 400b through the second TSV 303. The data transceiver 316 can transmit a data signal DQ including the data DTA to an external host device based on the internal write data enable signal dWDQS. The data DTA can be aligned with a switching timing of the read data enable signal RDQS and can be transmitted.

[0191] The first core die 400a can include a command decoder 411a, a data I / O buffer 520a, and a memory cell array 510. The command decoder 411a, the data I / O buffer 520a, and the memory cell array 510 can be circuits that support the channel CHa. The command decoder 411a can decode an internal command I CMD transmitted from the buffer die 300 through the first TSV 302. The command decoder 411a can control the data I / O buffer 520a and the memory cell array 510 according to the internal command I CMD.

[0192] The data I / O buffer 520a can exchange data DTA with the buffer die 300 through the second TSV 303. In a write operation, the data I / O buffer 520a can receive data DTA transmitted from the buffer die 300 through the second TSV 303 and can transmit the data DTA to the memory cell array 510. The memory cell array 510 can store the data DTA. In a read operation, the data I / O buffer 520a can read data DTA from the memory cell array 510 and can transmit the received data DTA to the buffer die 300 through the second TSV 303.

[0193] In example embodiments, the buffer die 300 can further include an error correction code (ECC) engine for detecting and / or correcting errors of the data DTA. For example, in a write operation, the ECC engine can generate error detection bits (e.g., parity bits) for the data DTA received through the data transceiver 316. In a read operation, the ECC engine can detect and / or correct errors of the data DTA transferred from the first core die 400a by using the error detection bits, and can transfer the error-corrected data DTA to the data transceiver 316.

[0194] The second core die 400b can include a command decoder 411b, a data I / O buffer 520b, and a memory cell array 610. The second core die 400b can be similar to the first core die 400a in many respects and can include additional features not mentioned above. Accordingly, repeated descriptions of the second core die 400b described above with reference to the first core die 400a can be omitted for the sake of brevity.

[0195] FIG. 19 is a block diagram illustrating an example of a first core die in a stacked memory device according to an example embodiment. FIG. 18 is a block diagram illustrating an example of a first core die in a stacked memory device according to an example embodiment.

[0196] Referring to FIG. 19 The first core die 400a can include a control logic circuit 410, an address register 420, a bank control logic 430, a row address (RA) multiplexer 440, a column address (CA) latch 450, a row decoder 460, a column decoder 470, a memory cell array 510, a sense amplifier unit 485, an input / output (I / O) gating circuit 490, a refresh counter 445, a data I / O buffer 520a, and an ECC engine 590.

[0197] The array of memory cells 510 can include a plurality of memory bank arrays (e.g., a first memory bank array 510a through a sixteenth memory bank array 510p). The row decoders 460 can include a plurality of row decoders (e.g., a first row decoder 460a through a sixteenth row decoder 460p) respectively coupled to the plurality of memory bank arrays 510a-510p. The column decoders 470 can include a plurality of column decoders (e.g., a first column decoder 470a through a sixteenth column decoder 470p) respectively coupled to the plurality of memory bank arrays 510a-510p. The sense amplifier units 485 can include a plurality of sense amplifiers (e.g., a first sense amplifier 485a through a sixteenth sense amplifier 485p) respectively coupled to the plurality of memory bank arrays 510a-510p. The plurality of memory bank arrays 510a-510p, the plurality of row decoders 460a-460p, the plurality of column decoders 470a-470p, and the plurality of sense amplifiers 485a-485p can form a plurality of memory banks (a first memory bank through a sixteenth memory bank).

[0198] Each of the plurality of memory bank arrays 510a-510p can include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0199] The address register 420 can receive an address ADDR including a bank address BANK ADDR, a row address ROW ADDR, and a column address COL ADDR from the buffer die 300. The address register 420 can provide the received bank address BANK ADDR to the bank control logic 430, the received row address ROW ADDR to the row address multiplexer 440, and the received column address COL ADDR to the column address latch 450.

[0200] The bank control logic 430 can generate bank control signals in response to the bank address BANK ADDR. At least one of the plurality of row decoders 460a-460p corresponding to the bank address BANK ADDR can be activated in response to the bank control signals, and at least one of the plurality of column decoders 470a-470p corresponding to the bank address BANK ADDR can be activated in response to the bank control signals.

[0201] The row address multiplexer 440 can receive the row address ROW_ADDR from the address register 420 and can receive the refresh row address REF_ADDR from the refresh counter 445. The row address multiplexer 440 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 440 can be applied to the plurality of row decoders 460a to 460p.

[0202] The refresh counter 445 can sequentially increase and / or decrease the refresh row address REF_ADDR under the control of the control logic circuit 410.

[0203] An activated one of the plurality of row decoders 460a to 460p can decode the row address RA output from the row address multiplexer 440 and can activate a word line corresponding to the row address RA. For example, the activated memory bank row decoder can apply a word line driving voltage to a word line corresponding to the row address RA.

[0204] The column address latch 450 can receive the column address COL_ADDR from the address register 420 and can temporarily store the received column address COL_ADDR. In an example embodiment, in a burst mode, the column address latch 450 can generate a column address COL_ADDR' that is incremented from the received column address COL_ADDR. The column address latch 450 can apply the temporarily stored or generated column address COL_ADDR' to the plurality of column decoders 470a to 470p.

[0205] An activated one of the plurality of column decoders 470a to 470p can decode the column address COL_ADDR' output from the column address latch 450 and can control the I / O gate circuit 490 to output data corresponding to the column address COL_ADDR.

[0206] The I / O gate circuit 490 can include a circuit for gating input / output data. The I / O gate circuit 490 can further include a read data latch for storing data output from the plurality of memory bank arrays 510a to 510p and a write driver for writing data to the plurality of memory bank arrays 510a to 510p.

[0207] A codeword CW read from one of the memory bank arrays 510a-510p can be read by a sense amplifier coupled to the memory bank array from which the data is to be read and can be stored in a read data latch. The codeword CW stored in the read data latch can be provided to the ECC engine 590. The ECC engine 590 can perform ECC decoding on the codeword CW to provide data DTA to the data I / O buffer 520a. The data I / O buffer 520a can convert the data DTA to a data signal DQ and can send the data signal DQ to the buffer die 300.

[0208] Data DTA to be written into one of the memory bank arrays 510a-510p can be provided from the data I / O buffer 520a to the ECC engine 590. The ECC engine 590 can perform ECC encoding on the data DTA to generate parity bits and the ECC engine 590 can provide the data DTA and the parity bits to the I / O gating circuit 490. The I / O gating circuit 490 can write the data DTA and the parity bits into a subpage in the one memory bank array through a write driver.

[0209] The ECC engine 590 can perform ECC encoding and / or ECC decoding on the data DTA based on a second control signal CTL2 from the control logic circuit 410.

[0210] The control logic circuit 410 can control operations of the first core die 400a. For example, the control logic circuit 410 can generate control signals for the first core die 400a to perform write operations and read operations. The control logic circuit 410 can include a command decoder 411a that decodes internal commands ICMD received from the buffer die 300 and can include a mode register 412 that can set an operating mode of the first core die 400a.

[0211] The control logic circuit 410 can generate a first control signal CTL1 to control the I / O gating circuit 490 and can generate a second control signal CTL2 to control the ECC engine 590 by decoding internal commands ICMD.

[0212] FIG. 20 An example of a first memory bank array in a first core die is shown in accordance with an example embodiment. FIG. 19 An example of a first memory bank array in a first core die is shown in accordance with an example embodiment.

[0213] Reference is made to FIG. 20The first memory bank array 510a can include a plurality of word lines (e.g., a first word line WL0, a second word line WL1, through an (m-2)th word line WLm-2, and an (m-1)th word line WLm-1, where m is a positive integer greater than two (2)), a plurality of bit lines (e.g., a first bit line BTL0, a second bit line BTL1, a third bit line BTL2, through an (n-2)th bit line BTLn-2, and an (n-1)th bit line BTLn-1, where n is a positive integer greater than two (2)), and a plurality of memory cells MC disposed at intersections between the plurality of word lines WL0 through WLm-1 and the plurality of bit lines BTL0 through BTLn-1. Each of the plurality of memory cells MC can include a cell transistor coupled to each of the plurality of word lines WL0 through WLm-1 and each of the plurality of bit lines BTL0 through BTLn-1, and a cell capacitor coupled to the cell transistor. Each of the memory cells MC can have a dynamic random access memory (DRAM) cell structure. Each of the plurality of word lines WL0 through WLm-1 can extend in a first direction D1, and each of the plurality of bit lines BTL1 through BTLn-1 can extend in a second direction D2 crossing the first direction D1.

[0214] The plurality of word lines WL0 through WLm-1 coupled to the plurality of memory cells MC can be referred to as rows of the first memory bank array 510a, and the plurality of bit lines BTL0 through BTLn-1 coupled to the plurality of memory cells MC can be referred to as columns of the first memory bank array 510a.

[0215] FIG. 21 is a diagram illustrating a semiconductor package according to an example embodiment.

[0216] Referring to FIG. 21 The semiconductor package 1000 can include a stacked memory device 1100, a system on chip (SoC) 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 can include a buffer die 1110 and a plurality of core dies (e.g., a first core die 1120, a second core die 1130, a third core die 1140, and a fourth core die 1150). The buffer die 1110 can correspond to the buffer die 300 of FIG. 17 , and the plurality of core dies 1120 through 1150 can respectively correspond to the plurality of core dies 400a through 400d of FIG. 17 .

[0217] Each of the plurality of core dies 1120 to 1150 can include an array of memory cells. The buffer die 1110 can include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 can be electrically connected with the physical layer 1210 of the SoC 1200. Through the physical layer 1111, the stacked memory device 1100 can receive signals from and / or can transmit signals to the SoC 1200. The physical layer 1111 can include an interface circuit as described with reference to the interface circuit of the buffer die 300. FIG. 18

[0218] The direct access area 1112 can provide an access path that enables testing of the stacked memory device 1100 without passing through the SoC 1200. The direct access area 1112 can include conductors (e.g., ports or pins) that can directly communicate with an external test device. Test signals and data received through the direct access area 1112 can be transferred to the plurality of core dies 1120 to 1150 through the TSVs. For testing the plurality of core dies 1120 to 1150, data read from the plurality of core dies 1120 to 1150 can be transferred to a test device through the TSVs and the direct access area 1112. Accordingly, direct access testing can be performed with respect to the plurality of core dies 1120 to 1150.

[0219] The buffer die 1110 and the plurality of core dies 1120 to 1150 can be electrically connected through the TSVs 1101 and the bumps 1102. The buffer die 1110 can receive signals from the SoC 1200 that can be provided to each channel through the bumps 1102 allocated for each channel. For example, the bumps 1102 can be and / or can include micro bumps.

[0220] The SoC 1200 can perform applications supported by the semiconductor package 1000 using the stacked memory device 1100. For example, the SoC 1200 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), a digital signal processor (DSP), etc., and can perform specialized computing.

[0221] ​The SoC 1200 can include a physical layer 1210 and a memory controller 1220. The physical layer 1210 can include I / O circuitry to exchange signals with the physical layer 1111 of the stacked memory device 1100. The SoC 1200 can provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 can be transmitted to the plurality of core dies 1120 to 1150 through the interface circuitry of the physical layer 1111 and the TSVs 1101.

[0222] The memory controller 1220 can control overall operations of the stacked memory device 1100. The memory controller 1220 can provide signals for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210.

[0223] The interposer 1300 can connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 can connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200, and can provide a physical path formed by using a conductive material. As such, the stacked memory device 1100 and the SoC 1200 can be stacked on the interposer 1300, and can exchange signals with each other.

[0224] The bumps 1103 can be attached on the upper surface of the package substrate 1400, and the solder balls 1104 can be attached on the lower surface of the package substrate 1400. For example, the bumps 1103 can be and / or can include flip-chip bumps. The interposer 1300 can be stacked on the package substrate 1400 through the bumps 1103. The semiconductor package 1000 can exchange signals with another external package or semiconductor device through the solder balls 1104. For example, the package substrate 1400 can be a printed circuit board (PCB).

[0225] FIG. 22 FIG. 1 is a diagram illustrating an embodiment example of a semiconductor package according to an example embodiment.

[0226] Referring to FIG. 22 The semiconductor package 2000 can include a plurality of stacked memory devices HBM 2100 and a GPU 2200. The plurality of stacked memory devices HBM 2100 and the GPU 2200 can be stacked on an interposer 2300, and the interposer 2300 can be stacked on a package substrate 2400. The semiconductor package 2000 can exchange signals with any other external package or semiconductor device through solder balls 2001 attached on the lower surface of the package substrate 2400.

[0227] Each of the plurality of stacked memory devices HBM 2100 can be implemented in compliance with the HBM standard. However, the present disclosure is not limited thereto. For example, each of the plurality of stacked memory devices HBM 2100 can be implemented based on a graphics double data rate (GDDR), a hybrid memory cube (HMC), or a wide I / O standard.

[0228] The GPU 2200 can include a memory controller (MCT) 2210.

[0229] Example embodiments can be applied to a system using a semiconductor memory device and a stacked memory device.

[0230] While the present disclosure has been shown and described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that numerous modifications in form and detail can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A buffer die disposed in a wafer, the buffer die comprising: a write enable signal generation circuit configured to generate a first write enable signal and a second write enable signal based on being enabled in wafer level testing of the buffer die, the second write enable signal having a first phase difference of 180 degrees from the first write enable signal; a divide and convert circuit configured to generate a plurality of divided clock signals including a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal, the plurality of divided clock signals having a second phase difference of 90 degrees with respect to each other, the generating of the plurality of divided clock signals including dividing the first write enable signal and the second write enable signal and converting one or more levels of the divided write enable signals; a duty cycle adjustment circuit configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal, the generating of the plurality of adjusted clock signals including adjusting a duty cycle of each of the plurality of divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set; a read enable signal generation circuit configured to generate a first read enable signal and a second read enable signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree, the second read enable signal having a third phase difference of 180 degrees from the first read enable signal; a skew monitoring circuit configured to generate a first up / down signal by monitoring a first duty cycle of the first read enable signal and a second duty cycle of the second read enable signal; and a trim circuit configured to: generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals; generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code, the auto-calibration code being generated based on the first up / down signal; and obtain the fuse calibration code from an external test device, the fuse calibration code having been generated based on the first up / down signal and the second up / down signal.

2. The buffered die of claim 1, wherein, the write enable signal generation circuit includes: a source clock generator configured to output a first source clock signal or a second source clock signal as a source clock signal based on a first selection signal, the first source clock signal having a first frequency, and the second source clock signal having a second frequency less than the first frequency; a phase splitter configured to generate a first split clock signal and a second split clock signal by splitting a phase of the source clock signal; the divide and convert circuit includes: a first divider configured to divide the first split clock signal by a first division factor to generate the first divided clock signal; a second divider configured to divide the second split clock signal by a second division factor to generate the second divided clock signal; a first converter configured to convert a level of the first divided clock signal to generate a first converted clock signal; a second converter configured to convert a level of the second divided clock signal to generate a second converted clock signal; the duty cycle adjustment circuit includes: a first duty cycle adjuster configured to adjust a duty cycle of the first converted clock signal based on the first control code set to generate the first adjusted clock signal; a second duty cycle adjuster configured to adjust a duty cycle of the second converted clock signal based on the second control code set to generate the second adjusted clock signal; a third duty cycle adjuster configured to adjust a duty cycle of the first divided clock signal based on the third control code set to generate the third adjusted clock signal; a fourth duty cycle adjuster configured to adjust a duty cycle of the second divided clock signal based on the fourth control code set to generate the fourth adjusted clock signal; the read enable signal generation circuit includes: a first read enable generator configured to generate the first read enable signal based on the first predetermined pattern data and the first adjusted clock signal; a second read enable generator configured to generate the second read enable signal based on the second predetermined pattern data and the second adjusted clock signal; and the skew monitoring circuit includes: a first up / down generator configured to generate the first up / down signal based on the first read enable signal and the first adjusted clock signal; a second up / down generator configured to generate the second up / down signal based on the second read enable signal and the second adjusted clock signal. a selective flipping circuit configured to output the first split clock signal or the second split clock signal as a first selected clock signal and output a remaining one of the first split clock signal and the second split clock signal as a second selected clock signal based on a second selection signal indicating whether a flip is activated; and an amplifier configured to output the first write select signal and the second write select signal by amplifying the first selected clock signal and the second selected clock signal.

3. The buffered die of claim 2, wherein, the selective flipping circuit is further configured to: output the first split clock signal and the second split clock signal as the first selected clock signal and the second selected clock signal, respectively, based on the second selection signal indicating that the flip is deactivated; and output the first split clock signal and the second split clock signal as the second selected clock signal and the first selected clock signal, respectively, based on the second selection signal indicating that the flip is activated. the trimming circuit is further configured to:

4. The buffered die of claim 2, wherein, eliminate an offset of the write select signal generation circuit by activating the flip; and generate the auto-calibration code by averaging a first auto-calibration code obtained based on the flip being deactivated and a second auto-calibration code obtained based on the flip being activated. the frequency dividing and converting circuit includes: a clock frequency dividing circuit configured to:

5. The buffered die of claim 1, wherein, generate a first divided clock signal and a third divided clock signal having a fourth phase difference of 180 degrees from the first divided clock signal by frequency dividing a first frequency of the first write select signal; and generate a second divided clock signal and a fourth divided clock signal having a fifth phase difference of 180 degrees from the second divided clock signal by frequency dividing a second frequency of the second write select signal; a current mode logic driver configured to generate a plurality of intermediate clock signals having current mode logic levels by driving the first divided clock signal, the second divided clock signal, the third divided clock signal, and the fourth divided clock signal; and a current mode logic to complementary metal oxide semiconductor converter configured to generate the plurality of divided clock signals having complementary metal oxide semiconductor levels based on the plurality of intermediate clock signals. the clock frequency dividing circuit includes: a first clock divider configured to generate the first divided clock signal and the third divided clock signal by frequency dividing the first frequency of the first write select signal; and 6. The buffered die of claim 5, wherein, a second clock divider configured to generate the second divided clock signal and the fourth divided clock signal by frequency dividing the second frequency of the second write select signal. the duty cycle adjustment circuit includes: a first duty cycle adjuster configured to generate the first adjusted clock signal by adjusting a first delay amount of at least one of a first rising edge and a first falling edge of the first divided clock signal based on the first set of control codes; and 7. The buffered die of claim 1, wherein, a second duty cycle adjuster configured to generate the second adjusted clock signal by adjusting a second delay amount of at least one of a second rising edge and a second falling edge of the second divided clock signal based on the second set of control codes. ​ a second duty cycle adjuster configured to generate the second adjusted clock signal based on the second set of control codes by adjusting a second delay amount of at least one of a second rising edge and a second falling edge of the second divided clock signal; a third duty cycle adjuster configured to generate the third adjusted clock signal based on the third set of control codes by adjusting a third delay amount of at least one of a third rising edge and a third falling edge of the third divided clock signal; and a fourth duty cycle adjuster configured to generate the fourth adjusted clock signal based on the fourth set of control codes by adjusting a fourth delay amount of at least one of a fourth rising edge and a fourth falling edge of the fourth divided clock signal.

8. The buffered die of claim 7, wherein, Each of the first duty cycle adjuster, the second duty cycle adjuster, the third duty cycle adjuster, and the fourth duty cycle adjuster includes: a plurality of inverters coupled in series with each other; a plurality of first delay cells coupled between adjacent inverters of the plurality of inverters; and a second delay cell coupled to an output of a last inverter of the plurality of inverters.

9. The buffered die of claim 8, wherein, Each of the plurality of first delay cells includes: a first metal oxide semiconductor capacitor coupled to a supply voltage; a second metal oxide semiconductor capacitor coupled to a ground voltage; a p-channel metal oxide semiconductor transistor including: a first source coupled to a first gate of the first metal oxide semiconductor transistor; a first drain coupled to a first node; and a second gate configured to receive an inverted version of a respective bit of the first set of control codes; and an n-channel metal oxide semiconductor transistor including: a second drain coupled to the first node; a third gate configured to receive the respective bit of the first set of control codes; and a second source coupled to a fourth gate of the second metal oxide semiconductor capacitor, wherein an output of a first inverter of the plurality of inverters and an input of a second inverter of the plurality of inverters are commonly coupled to the first node, wherein the first inverter and the second inverter are adjacent inverters of the plurality of inverters, and wherein the first source of the p-channel metal oxide semiconductor transistor and the second source of the n-channel metal oxide semiconductor transistor are coupled to each other.

10. The buffered die of claim 8, wherein, The second delay cell includes: a first metal oxide semiconductor capacitor coupled to a supply voltage; a second metal oxide semiconductor capacitor coupled to a ground voltage; a p-channel metal oxide semiconductor transistor including: a first source coupled to a first gate of the first metal oxide semiconductor transistor; a first drain coupled to an output node, the output node coupled to an output of the last inverter; and a third gate configured to receive an inverted version of a respective bit of the first set of control codes; and an n-channel metal oxide semiconductor transistor including: a second drain coupled to the output node; a third gate configured to receive the respective bit of the first set of control codes; and a second source coupled to a fourth gate of the second metal oxide semiconductor capacitor, wherein an output of a first inverter of the plurality of inverters and an input of a second inverter of the plurality of inverters are commonly coupled to the first node, wherein the first inverter and the second inverter are adjacent inverters of the plurality of inverters, and wherein the first source of the p-channel metal oxide semiconductor transistor and the second source of the n-channel metal oxide semiconductor transistor are coupled to each other. a fourth gate configured to receive the respective bit of the first set of control codes; and a second source coupled to a second gate of the second metal-oxide-semiconductor capacitor, wherein the first source of the p-channel metal-oxide-semiconductor transistor and the second source of the n-channel metal-oxide-semiconductor transistor are coupled to each other.

11. The buffered die of claim 1, wherein, The read strobe signal generation circuit includes: a first multiplexer configured to sequentially select first bits of the first predetermined pattern data at respective first rising edges of the plurality of read clock signals; a first driver configured to output the first read strobe signal by driving an output of the first multiplexer; a second multiplexer configured to sequentially select second bits of the second predetermined pattern data at respective second rising edges of the plurality of read clock signals; and a second driver configured to output the second read strobe signal by driving an output of the second multiplexer, wherein each bit of the first predetermined pattern data is complementary to a respective bit of the second predetermined pattern data, and wherein a first frequency of the first read strobe signal is twice a second frequency of the second read strobe signal.

12. The buffered die of claim 1, wherein, The skew monitoring circuit includes: a first duty cycle monitor configured to generate the first up / down signal by monitoring the first duty cycle of the first read strobe signal and the second duty cycle of the second read strobe signal; and a first code storage configured to store the first up / down signal and the second up / down signal by accumulating the first up / down signal and the second up / down signal.

13. The buffered die of claim 12, wherein, The trimming circuit includes: a second duty cycle monitor configured to generate the second up / down signal by monitoring duty cycles of the plurality of read clock signals; an auto-calibration logic configured to: generate the auto-calibration code based on the first up / down signal; generate a first selection signal and a second selection signal; generate an auto-calibration enable signal; and provide the first selection signal and the second selection signal to the write strobe signal generation circuit; a second code storage configured to store the fuse calibration code; and a delay controller configured to: select the auto-calibration code or the fuse calibration code based on the auto-calibration enable signal; and generate the plurality of sets of control codes based on the selected calibration code.

14. The buffered die of claim 13, wherein, The trimming circuit is further configured to: read the first up / down signal and the second up / down signal from the first code storage; and store the fuse calibration code in the second code storage based on the first up / down signal and the second up / down signal.

15. The buffered die of claim 13, wherein, The delay controller includes: a first multiplexer configured to output a first selected calibration code by selecting a first auto-sub-code of the auto-calibration code or a first fuse sub-code of the fuse calibration code based on the auto-calibration enable signal; a first decoder configured to generate the first set of control codes by decoding the first selected calibration code; a second multiplexer configured to output a second selected calibration code by selecting, based on the auto-calibration enable signal, a second auto-sub-code of the auto-calibration code or a second fuse sub-code of the fuse calibration code; a second decoder configured to generate the second control code set by decoding the second selected calibration code; a third multiplexer configured to output a third selected calibration code by selecting, based on the auto-calibration enable signal, a third auto-sub-code of the auto-calibration code or a third fuse sub-code of the fuse calibration code; a third decoder configured to generate the third control code set by decoding the third selected calibration code; a fourth multiplexer configured to output a fourth selected calibration code by selecting, based on the auto-calibration enable signal, a fourth auto-sub-code of the auto-calibration code or a fourth fuse sub-code of the fuse calibration code; and a fourth decoder configured to generate the fourth control code set by decoding the fourth selected calibration code.

16. The buffered die of claim 15, wherein, the first decoder is further configured to: decode the first selected calibration code such that a number of bits in the first control code set having a logical high level is sequentially increased or decreased from a default value.

17. A stacked memory device comprising: a buffer die comprising interface circuitry configured to communicate with an external host device; and a plurality of core dies stacked on the buffer die and coupled to the buffer die by a plurality of through-silicon vias, wherein the interface circuitry comprises: write select signal generation circuitry configured to generate, based on being enabled in a wafer-level testing of the buffer die, a first write select signal and a second write select signal having a first phase difference of 180 degrees from the first write select signal, frequency division and conversion circuitry configured to generate a plurality of frequency divided clock signals including a first frequency divided clock signal, a second frequency divided clock signal, a third frequency divided clock signal, and a fourth frequency divided clock signal having a second phase difference of 90 degrees from one another, the generating of the plurality of frequency divided clock signals including frequency dividing and converting one or more levels of the frequency divided write select signals; duty cycle adjustment circuitry configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal, the generating of the plurality of adjusted clock signals including adjusting a duty cycle of each of the plurality of frequency divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set; a read selection signal generation circuit configured to generate a first read selection signal and a second read selection signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree; a skew monitoring circuit configured to generate a first up / down signal by monitoring a first duty cycle of the first read selection signal and a second duty cycle of the second read selection signal; and a trim circuit configured to: generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals; generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code, the auto-calibration code being generated based on the first up / down signal, wherein the fuse calibration code is input from an external test device based on a wafer level test performed on the buffer die and stored internally in the trim circuit.

18. The stacked memory device of claim 17, wherein, the trim circuit includes: a second duty cycle monitor configured to generate the second up / down signal by monitoring duty cycles of the plurality of read clock signals; an auto-calibration logic configured to: generate the auto-calibration code based on the first up / down signal; generate a first selection signal and a second selection signal; generate an auto-calibration enable signal; and provide the first selection signal and the second selection signal to the write selection signal generation circuit; a second code storage configured to store the fuse calibration code; and a delay controller configured to: select the auto-calibration code or the fuse calibration code based on the auto-calibration enable signal; and generate the plurality of control code sets based on the selected calibration code.

19. The stacked memory device of claim 17, wherein, the interface circuit is configured to: generate an internal command based on a command received from a memory controller in the external host device; provide the internal command to a target core die in the plurality of core dies through a first through silicon via in the plurality of through silicon vias; and provide data to the target core die through a second through silicon via in the plurality of through silicon vias, wherein each of the plurality of core dies includes: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines and storing the data; and a command decoder configured to control access to the memory cell array based on the internal command.

20. A buffer die disposed in a wafer, the buffer die comprising: a write selection signal generation circuit configured to generate a first write selection signal and a second write selection signal based on being enabled in a wafer level test of the buffer die, the second write selection signal having a first phase difference of 180 degrees from the first write selection signal; a read selection signal generation circuit configured to generate a first read selection signal and a second read selection signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree; a skew monitoring circuit configured to generate a first up / down signal by monitoring a first duty cycle of the first read selection signal and a second duty cycle of the second read selection signal; and a trim circuit configured to: generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals; generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code, the auto-calibration code being generated based on the first up / down signal, wherein the fuse calibration code is input from an external test device based on a wafer level test performed on the buffer die and stored internally in the trim circuit. the trim circuit includes: a second duty cycle monitor configured to generate the second up / down signal by monitoring duty cycles of the plurality of read clock signals; an auto-calibration logic configured to: generate the auto-calibration code based on the first up / down signal; generate a first selection signal and a second selection signal; generate an auto-calibration enable signal; and provide the first selection signal and the second selection signal to the write selection signal generation circuit; a second code storage configured to store the fuse calibration code; and a delay controller configured to: select the auto-calibration code or the fuse calibration code based on the auto-calibration enable signal; and generate the plurality of control code sets based on the selected calibration code. the interface circuit is configured to: generate an internal command based on a command received from a memory controller in the external host device; provide the internal command to a target core die in the plurality of core dies through a first through silicon via in the plurality of through silicon vias; and provide data to the target core die through a second through silicon via in the plurality of through silicon vias, wherein each of the plurality of core dies includes: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines and storing the data; and a command decoder configured to control access to the memory cell array based on the internal command. a frequency dividing and converting circuit configured to generate a plurality of divided clock signals including a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth divided clock signal, the plurality of divided clock signals having a second phase difference of 90 degrees with respect to each other, the generating of the plurality of divided clock signals including frequency dividing the first write enable signal and the second write enable signal and converting one or more levels of the frequency divided write enable signals; a duty cycle adjustment circuit configured to generate a plurality of adjusted clock signals including a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal, the generating of the plurality of adjusted clock signals including adjusting a duty cycle of each of the plurality of divided clock signals based on a respective control code set of a plurality of control code sets including a first control code set, a second control code set, a third control code set, and a fourth control code set; a read enable signal generating circuit configured to generate a first read enable signal and a second read enable signal based on a first predetermined pattern data, a second predetermined pattern data, and a plurality of read clock signals obtained by passing the plurality of adjusted clock signals through a clock tree, the second read enable signal having a third phase difference of 180 degrees with respect to the first read enable signal; a skew monitoring circuit configured to generate a first up / down signal by monitoring a first duty cycle of the first read enable signal and a second duty cycle of the second read enable signal; and a trimming circuit configured to: generate a second up / down signal by monitoring duty cycles of the plurality of read clock signals; generate the plurality of control code sets based on an auto-calibration code or a fuse calibration code, the auto-calibration code being generated based on the first up / down signal; and obtain the fuse calibration code from an external test device, the fuse calibration code having been generated based on the first up / down signal and a second up / down signal; eliminate skew of the write enable signal generating circuit by activating a flip; generate the auto-calibration code by averaging a first auto-calibration code obtained based on the flip being deactivated and a second auto-calibration code obtained based on the flip being activated.

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