Memory device, memory system and operating method thereof

Abstract

A method of operating a memory device includes applying a first program voltage to a selected word line corresponding to a target memory cell group, applying a first verify voltage to a selected word line corresponding to the target memory cell group, a predetermined number of program pulses are applied to a selected word line corresponding to the second memory cell of the target memory cell group, and a first program pulse or a last program pulse of the predetermined number of program pulses is applied to the selected word line corresponding to the second memory cell, and a second program pulse is applied to the selected word line corresponding to the second memory cell during application of the first program pulse or the last program pulse of the predetermined number of program pulses to the selected word line corresponding to the second memory cell. A first bit line bias voltage is applied to a first bit line corresponding to the second memory cell in the target memory cell group.

Description

Technical Field

[0001] This disclosure relates to memory devices, memory systems, and methods of operating thereof. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash and NAND flash. Flash memory can perform various operations, such as reading, programming (writing), and erasing. For NAND flash memory, erasure operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a method of operating a memory device includes: applying a first programming voltage to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the first memory cell being in a first programming state and the second memory cell being in a second programming state; applying a first verification voltage to the selected word line corresponding to the target memory cell group; applying a predetermined number of programming pulses to the selected word line corresponding to the second memory cell; and applying a first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell.

[0004] In some embodiments, the method further includes: determining the first bit line bias voltage based on the cell information of the second memory cell.

[0005] In some implementations, the cell information is obtained before the first memory cell passes the first verification at the first verification voltage.

[0006] In some implementations, the first bit line bias voltage is different from the first bit line voltage, wherein the first bit line voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the predetermined number of programming pulses (excluding the first or last programming pulse) to the selected word line corresponding to the second memory cell.

[0007] In some embodiments, the method further includes: disabling programming of the first memory cell in response to the first memory cell passing the first verification at the first verification voltage; applying the predetermined number of programming pulses to a selected word line corresponding to the second memory cell in response to the second memory cell passing the first verification at the first verification voltage; and disabling programming of the second memory cell.

[0008] In some implementations, applying a predetermined number of programming pulses to a selected word line corresponding to the second memory cell includes applying n programming pulses to a selected word line corresponding to the (n+1)th memory cell in the target memory cell group, where n is an integer greater than 0.

[0009] In some implementations, the first bit line bias voltage is a 3-bit line (3BL) bias voltage. During the application of the last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell in the target memory cell group, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

[0010] In some implementations, the 3BL bias voltage is greater than 0V and less than 2.2V.

[0011] In some implementations, during the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

[0012] In some implementations, the first bit line bias voltage is greater than 0V and less than 2.2V.

[0013] In some implementations, during the application of the first programming pulse of the predetermined number of programming pulses to a selected word line corresponding to the second memory cell, the first bit line bias voltage is determined based on the following: determining that the first bit line corresponds to a first group of memory cells that are programmed faster than the second group of memory cells, wherein the target memory cell group includes the first group of memory cells and the second group of memory cells.

[0014] In another aspect, a memory device includes: a memory cell array comprising memory cells, and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: apply a first programming voltage to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the first memory cell being in a first programming state and the second memory cell being in a second programming state; apply a first verification voltage to the selected word line corresponding to the target memory cell group; apply a predetermined number of programming pulses to the selected word line corresponding to the second memory cell; and during the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell in the target memory cell group, apply a first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group.

[0015] In some implementations, the peripheral circuitry is further configured to determine the first bit line bias voltage based on the cell information of the second memory cell.

[0016] In some implementations, the cell information is obtained before the first memory cell passes the first verification at the first verification voltage.

[0017] In some implementations, the first bit line bias voltage is different from the first bit line voltage, wherein the first bit line voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the predetermined number of programming pulses (excluding the first or last programming pulse) to the selected word line corresponding to the second memory cell.

[0018] In some embodiments, the peripheral circuitry is further configured to: disable programming of the first memory cell in response to the first memory cell passing the first verification at the first verification voltage; and apply the predetermined number of programming pulses to a selected word line corresponding to the second memory cell in response to the second memory cell passing the first verification at the first verification voltage, and disable programming of the second memory cell.

[0019] In some embodiments, the peripheral circuitry configured to apply a predetermined number of programming pulses to a selected word line corresponding to the second memory cell is further configured to apply n programming pulses to a selected word line corresponding to the (n+1)th memory cell in the target memory cell group, where n is an integer greater than 0.

[0020] In some implementations, the first bit line bias voltage is a 3-bit line (3BL) bias voltage. The peripheral circuitry is configured to apply the first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell.

[0021] In some implementations, the 3BL bias voltage is greater than 0V and less than 2.2V.

[0022] In some embodiments, the peripheral circuitry is configured to apply a first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell.

[0023] In some implementations, the first bit line bias voltage is greater than 0V and less than 2.2V.

[0024] In some implementations, during the application of the first programming pulse of the predetermined number of programming pulses to a selected word line corresponding to the second memory cell, the peripheral circuitry is configured to determine the first bit line bias voltage based on the following: determining that the first bit line corresponds to a first group of memory cells that can be programmed faster than the second group of memory cells. The target memory cell group includes the first group of memory cells and the second group of memory cells.

[0025] In another aspect, a memory system includes: a memory device and a memory controller coupled to the memory device. The memory device includes: a memory cell array comprising memory cells and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: apply a first programming voltage to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the first memory cell being in a first programming state and the second memory cell being in a second programming state; apply a first verification voltage to the selected word line corresponding to the target memory cell group; apply a predetermined number of programming pulses to the selected word line corresponding to the second memory cell; and during the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell in the target memory cell group, apply a first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0027] Figure 1 A schematic circuit diagram of an example memory device including peripheral circuitry according to some embodiments of the present disclosure is shown.

[0028] Figure 2 A block diagram of an example memory device including a memory cell array and peripheral circuitry according to some embodiments of the present disclosure is shown.

[0029] Figure 3A Example voltage schemes applied to a memory device according to some embodiments of this disclosure are shown.

[0030] Figure 3B Another example voltage scheme for applying voltage to a memory device according to some embodiments of this disclosure is shown.

[0031] Figure 3C The distribution of Vt is shown as an example voltage scheme applied to a memory device according to some embodiments of the present disclosure.

[0032] Figure 3D A view showing the slope of an example voltage scheme applied to a memory device according to some embodiments of this disclosure is shown.

[0033] Figure 3E The threshold voltage (Vt) distribution of an example voltage scheme applied to a memory device is shown according to some embodiments of the present disclosure.

[0034] Figure 3F Example voltage schemes applied to a memory device according to some embodiments of this disclosure are shown.

[0035] Figure 3G Example voltage schemes applied to a memory device according to some embodiments of this disclosure are shown.

[0036] Figure 3H The distribution of Vt is shown as an example voltage scheme applied to a memory device according to some embodiments of the present disclosure.

[0037] Figure 3I The Vt distribution of an example voltage scheme according to some embodiments of this disclosure is shown.

[0038] Figure 3JExample voltage schemes applied to a memory device according to some embodiments of this disclosure are shown.

[0039] Figure 3K Example voltage schemes applied to a memory device according to some embodiments of this disclosure are shown.

[0040] Figure 3L The distribution of Vt is shown as an example voltage scheme applied to a memory device according to some embodiments of the present disclosure.

[0041] Figure 4A A flowchart illustrating an example method of operating a memory device according to some embodiments of this disclosure is shown.

[0042] Figure 4B A flowchart illustrating an example method of operating a memory device according to some embodiments of this disclosure is shown.

[0043] Figure 5 A block diagram of an example system having a memory device according to some embodiments of the present disclosure is shown.

[0044] Figure 6A A view of an example memory card having a memory device according to some embodiments of the present disclosure is shown.

[0045] Figure 6B A view of an example solid-state drive (SSD) having a memory device according to some embodiments of the present disclosure is shown.

[0046] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0047] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other and in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0048] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "the" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0049] With advancements in 3D NAND technology, more storage bits are being incorporated into a single cell in an effort to achieve better storage density. Quad-level cell (QLC), containing four bits per cell, is currently the most popular technology on the market. To program a memory device in a QLC architecture, first and second (e.g., coarse and fine) programming steps can be performed. Because more programming processes are introduced, longer programming times are expected. Therefore, reducing programming time is crucial in QLC architecture applications.

[0050] To address one or more of the aforementioned problems, this disclosure presents a solution employing several programming schemes to program, verify, and disable memory cells in an attempt to simplify the process and reduce overall programming time. Specifically, this disclosure describes a solution in which memory cells corresponding to adjacent programming states (e.g., first programming state P1 and second programming state P2) are grouped and verified by the same verification voltage. A predetermined number of programming pulses are then applied to memory cells corresponding to certain programming states (e.g., memory cells corresponding to adjacent programming states other than the first memory cell, such as the second memory cell in the second programming state P2). Furthermore, when the first or last programming pulse of the predetermined number of programming pulses is applied to a memory cell (e.g., the second memory cell or other memory cells besides the first memory cell), a predetermined bit line bias voltage can be applied to the bit lines corresponding to these memory cells. In this way, the threshold voltage (Vt) distribution can be further narrowed, and inter-cell variations in the voltage distribution can be reduced.

[0051] Figure 1A schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. In some embodiments, the memory cell array 101 may be a NAND flash memory cell array, wherein the memory cells 106 are provided in the form of an array of three-dimensional (3D) NAND memory strings 108, each 3D NAND memory string 108 extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically above the substrate. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor. Each array of 3D NAND memory strings 108 may include one or more 3D memory devices.

[0052] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single bit of data in four or more memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to take one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0053] like Figure 1As shown, each 3D NAND memory string 108 may include a source select transistor 110 at its source end and a drain select transistor 112 at its drain end. The source select transistor 110 and drain select transistor 112 may be configured to activate the selected 3D NAND memory string 108 (column in the array) during read and program operations. In some embodiments, the sources of the source select transistors 110 of the 3D NAND memory strings 108 in the same block 104 are coupled to, for example, ground via the same source line (SL) 114 (e.g., common SL). According to some embodiments, the drain select transistor 112 of each 3D NAND memory string 108 is coupled to a corresponding bit line 116 from which data can be read or programmed via an output bus (not shown). In some implementations, each 3D NAND memory string 108 is configured to be selected or not selected by applying a selection signal (e.g., a selection voltage higher than the threshold voltage of the drain selection transistor 112) or a deselection signal (e.g., a deselection voltage such as 0V) to the corresponding drain selection transistor 112 via one or more drain select lines 113 and / or by applying a selection voltage (e.g., a selection voltage higher than the threshold voltage of the source selection transistor 110) or a deselection voltage (e.g., 0V) to the corresponding source selection transistor 110 via one or more source select lines 115.

[0054] like Figure 1 As shown, the 3D NAND memory string 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114. In some embodiments, each block 104 is a basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. Memory cells 106 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to a row of memory cells 106, which is a basic data unit for program and read operations. Each word line 118 may be coupled to multiple control gates (gate electrodes) at each memory cell 106 in the corresponding row and gate lines coupling the control gates.

[0055] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, source select line 115, and drain select line 113. As described above, peripheral circuitry 102 can include any suitable circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to each target memory cell 106 via word line 118, source line 114, source select line 115, and drain select line 113 and via bit line 116, and by sensing voltage and / or current signals from each target memory cell 106. Peripheral circuitry 102 can include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0056] Figure 2 Example peripheral circuitry 102 is shown, including page buffer 204, column decoder / bit line driver 206, row decoder / word line driver 208, voltage generator 210, control logic 212, register 214, interface (I / F) 216, and data bus 218. It should be understood that additional peripheral circuitry 102 may also be included in some examples.

[0057] Page buffer 204 can be configured to buffer data read from or programmed into memory cell array 101 according to control signals of control logic 212. In one example, page buffer 204 can store one or more pages of programming data (write data) to be programmed into one or more rows of memory cell array 101. In another example, page buffer 204 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118.

[0058] The row decoder / word line driver 208 can be configured to be controlled by control logic 212 to select or deselect block 104 of memory cell array 101 and select or deselect word line 118 of selected block 104. The row decoder / word line driver 208 can also be configured to drive memory cell array 101. For example, the row decoder / word line driver 208 can use a word line voltage generated from voltage generator 210 to drive memory cell 106 coupled to selected word line 118. In some embodiments, the row decoder / word line driver 208 may include a decoder and a string driver (driving transistor) coupled to the local word line and word line 118.

[0059] Voltage generator 210 can be configured to be controlled by control logic 212 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.) to be supplied to memory cell array 101. In some embodiments, voltage generator 210 is part of a voltage source that provides voltages at various levels across different peripheral circuits 102, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 210 to, for example, line decoder / word line driver 208 and page buffer 204 are higher than certain levels sufficient to perform memory operations. For example, the voltage supplied to page buffer 204 may be between 2V and 3.3V, such as 3V, and the voltage supplied to line decoder / word line driver 208 may be greater than 3.3V, for example, between 3.3V and 30V.

[0060] The column decoder / bit line driver 206 can be configured to be controlled by control logic 212 and to select one or more 3D NAND memory strings 108 by applying a bit line voltage generated from voltage generator 210. For example, the column decoder / bit line driver 206 can apply a column signal to select a set of N bits of data to be output in a read operation from page buffer 204.

[0061] Control logic 212 may be coupled to each peripheral circuit 102 and configured to control the operation of the peripheral circuit 102. Register 214 may be coupled to control logic 212 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 102. Control logic 212 is configured to control the operation in embodiments of this disclosure. For example, control logic 212 is configured to control voltage generator 210 to apply word line voltages to implement the voltage scheme disclosed in this disclosure.

[0062] Interface 216 may be coupled to control logic 212 and configured to interface memory cell array 101 with a memory controller (not shown). In some embodiments, interface 216 acts as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to control logic 212, and to buffer and relay status information received from control logic 212 to the memory controller and / or host. Interface 216 may also be coupled to page buffer 204 and column decoder / bitline driver 206 via data bus 218, and acts as an input / output (I / O) interface and data buffer to buffer and relay programming data received from the memory controller and / or host to page buffer 204, and to buffer and relay data read from page buffer 204 to the memory controller and / or host. In some embodiments, interface 216 and data bus 218 are part of the I / O circuitry of peripheral circuitry 102.

[0063] Figure 3A Example voltage schemes applied to a memory device according to some embodiments of this disclosure are shown. For example... Figure 3AAs shown, during the first programming operation, a programming voltage (Vpgm) is applied to the selected word line corresponding to the selected memory cell during the programming phase. A pass voltage (Vpass_p) during the programming phase can be applied to the non-selected word line corresponding to the non-selected memory cell. During the verification phase, one or more verification voltages corresponding to one or more programming states (e.g., first programming state P1, second programming state P2, ... and fifteenth programming state P15) are applied to the selected word line corresponding to the selected memory cell. Simultaneously, a pass voltage (Vpass_v) during the verification phase can be applied to the non-selected word line corresponding to the non-selected memory cell. In some embodiments, the programming voltage Vpgm is between 10V and 30V. For example, the programming voltage may include 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30V. In some implementations, the pass voltage Vpass_p during the programming phase is between 9V and 12V. For example, Vpass_p can include 9.0, 9.1, 9.2, 9.3, 9.4, 9.5, 9.6, 9.7, 9.8, 9.9, 10.0, 10.1, 10.2, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 10.9, 11.0, 11.1, 11.2, 11.3, 11.4, 11.5, 11.6, 11.7, 11.8, 11.9, or 12.0V. In some implementations, the pass voltage Vpass_v during the verification phase is between 6V and 9V. For example, Vpass_v can include 6.0, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.8, 6.9, 7.0, 7.1, 7.2, 7.3, 7.4, 7.5, 7.6, 7.7, 7.8, 7.9, 8.0, 8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, or 9.0V. Although Figure 3A Fifteen verification voltages are shown for verifying the 15 programmed states, but it should be understood that... Figure 3A This is for illustrative purposes only and does not represent the actual waveform of the verification voltage applied to the selected word line during the verification phase. For example, after applying a programming voltage, not all 15 programming states may be verified. In some implementations, one of the verification voltages may be applied after a programming voltage. In other implementations, some verifications may be omitted; for example, two programming voltages may be applied together with only one verification voltage.

[0064] To further reduce the verification process and time, such as Figure 3BAs shown, memory cells corresponding to predetermined programming states are grouped, and the same verification voltage is applied to memory cells in the same group of programming states. For example, a first programming voltage is applied to a selected word line corresponding to a first target memory cell group, and a second programming voltage is applied to a selected word line corresponding to a second target memory cell group, and so on. The first target memory cell group includes, for example, a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The target programming state of the first memory cell is a first programming state, the target programming state of the second memory cell is a second programming state, the target programming state of the third memory cell is a third programming state, and the target programming state of the fourth memory cell is a fourth programming state. For example, as... Figure 3C As shown, four memory cells corresponding to four programming states (P1 / P2 / P3 / P4) are in an erase state (ER) before they are programmed to their respective programming states (P1 / P2 / P3 / P4). It should be noted that the memory cells can be programmed to their respective intermediate programming states after a first programming operation (i.e., coarse programming by applying at least one programming pulse), and a second programming operation (e.g., fine programming) may be required to program the memory cells to their corresponding target programming states.

[0065] Next, a first verification voltage is applied to selected word lines corresponding to the first target memory cell group. That is, the first, second, third, and fourth memory cells are subjected to the first verification voltage and pass verification. After the memory cells are programmed and verified using the first verification voltage, the threshold voltages of the four memory cells are at least all distributed in the first programming state. In some embodiments, after the programming pulse is applied, the four memory cells that passed verification using the first verification voltage are no longer verified, thereby reducing the time required for additional verification. For example, a verification inhibit voltage (e.g., 0V or below certain bit line voltages during normal verification) is applied to the bit lines coupled to these four memory cells, so that these four memory cells are not verified during subsequent verification. Instead, the memory cells that failed verification are programmed as usual in subsequent programming operations.

[0066] Next, a predetermined number of programming pulses are applied to selected word lines corresponding to memory cells (e.g., a second, third, or fourth memory cell). When a programming pulse is applied to a selected word line, programming of the first memory cell is disabled (e.g., by applying a programming disable voltage (e.g., a high voltage Vdd) to the bit line coupled to the first memory cell). After applying one programming pulse to the second memory cell, programming of the second memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the second memory cell). After applying two programming pulses to the third memory cell, programming of the third memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the third memory cell). Next, a third programming pulse is applied to the fourth memory cell (i.e., a total of three programming pulses). Thus, after applying corresponding programming pulses to the four memory cells and verifying them using a first verification voltage, the threshold voltages of the four memory cells are at least all distributed in their corresponding intermediate programming states. Next, an additional programming process (e.g., a second programming operation (e.g., fine programming)) can be applied to the four memory cells so that the four memory cells can be programmed to their corresponding target programming states. In some implementations, n programming pulses are applied to each (n+1)th memory cell, where n is an integer greater than 0. For example, in an implementation where the first target memory cell group comprises two memory cells, a programming pulse is applied to the second memory cell after verification. In an implementation where the first target memory cell group comprises four memory cells, a programming pulse is applied to the second memory cell, two programming pulses are applied to the third memory cell, and three programming pulses are applied to the fourth memory cell. In some implementations, at least one programming pulse is applied to at least one memory cell of the nth memory cell. The larger n is, the more programming pulses are applied to the nth memory cell. For example, the fourth memory cell receives more programming pulses than the third, second, or first memory cell.

[0067] In some implementations, a 3-bit line (3BL) bias voltage scheme is applied to all bit lines corresponding to a selected memory cell during the application of the programming pulse. However, as... Figure 3E As shown, the threshold voltage Vt distribution narrows each time a programming pulse is applied to the memory cell under the 3BL bias voltage scheme. That is, the slope of the incremental step programming pulse (ISPP) becomes smaller and cannot be recovered, as... Figure 3D As shown, as the slope decreases, the programming time for each memory location slows down. This slow programming problem leads to longer programming times, thus reducing programming efficiency.

[0068] To address this slow programming problem, during the application of the first or last programming pulse of a predetermined number of programming pulses to the selected word line corresponding to the second memory cell, a first bit line bias voltage is applied to the bit line (e.g., the first bit line) corresponding to the memory cell (e.g., the second memory cell) in the target memory cell group other than the first memory cell. For example, in an embodiment where the first target memory cell group comprises four memory cells, one programming pulse is applied to the second memory cell, two programming pulses are applied to the third memory cell, and three programming pulses are applied to the fourth memory cell.

[0069] In some implementations, such as Figure 3F As shown, the first bit line bias voltage is applied to the memory cell only during the period when the last programming pulse is applied to the memory cell. For example, during the period when the last (e.g., the only) programming pulse is applied to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell. During the period when the last (e.g., the second) programming pulse is applied to the third memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the third memory cell. And during the period when the last (e.g., the third) programming pulse is applied to the fourth memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the fourth memory cell. During the period when the remaining predetermined number of programming pulses are applied to the memory cells, a default bit line bias voltage is applied to the memory cells. In some embodiments, the default bit line bias voltage is 0V.

[0070] like Figure 3F As shown, taking the fourth memory cell corresponding to the fourth programming state as an example, after programming the fourth memory cell and later verifying it at a first verification voltage for the first programming state, three programming pulses are applied to the fourth memory cell. During the application of the last (e.g., the third) programming pulse to the fourth memory cell, a 3BL voltage is applied to the bit line corresponding to the fourth memory cell. After verification and the application of the programming pulses, programming of the fourth memory cell in subsequent programming stages is prohibited by applying a programming disable signal to the bit line corresponding to the fourth memory cell. Figure 3HAs shown, the 3BL bias voltage scheme is disabled during verification and the application of the first two programming pulses, and enabled during the application of the last programming pulse. Therefore, the Vt distribution per memory cell (e.g., memory cells in programming states P2, P3, and P4) is only slightly compressed, without significantly reducing programming speed. This minimizes the problem of slow programming. After the programming pulse is applied, these memory cells that passed verification using the first verification voltage are no longer verified, thus reducing the time required for additional verification. For example, a verification disable voltage (e.g., 0V or below the default bit line voltage during the verification process) is applied to the bit lines coupled to these memory cells, so that these memory cells are not verified during subsequent verification periods.

[0071] In some implementations, such as Figure 3G As shown, a first bit line bias voltage is applied to the memory cell only during the application of the first programming pulse of the programming pulses to the memory cell. For example, during the application of the first (e.g., the only) programming pulse to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell. During the application of the first (e.g., the first of two) programming pulse to the third memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the third memory cell. And during the application of the first (e.g., the first of three) programming pulse to the fourth memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the fourth memory cell. During the application of the remaining predetermined number of programming pulses to the memory cells, a default bit line bias voltage is applied to the memory cells. In some embodiments, the default bit line bias voltage is 0V.

[0072] In some implementations, the first line bias voltage (e.g., 3BL bias voltage) is determined based on cell information of the target memory cell group other than the first memory cell (e.g., the second, third, fourth, etc.). In some implementations, the cell information includes the initial threshold voltage distribution of the memory cells or the programming speed of the memory cells. In some implementations, the cell information is obtained before the first memory cell passes the first verification at the first verification voltage. For example, as... Figure 3IAs shown, cell information can be obtained by determining whether a memory cell is in the 2BL programming region or the 3BL programming region. For example, it can be determined that a 3BL bias voltage scheme may need to be applied to the second memory cell corresponding to the second programming state and the fourth memory cell corresponding to the fourth programming state, while the third memory cell corresponding to the third programming state may not. It should also be noted that if a memory cell corresponds to a bit line to which no 3BL bias voltage is applied, a default bit line voltage is applied to those memory cells. The default bit line voltage is different from the 3BL bias voltage. In some implementations, the 3BL bias voltage is greater than 0V and less than 2.2V. For example, the 3BL bias voltage includes 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, or 2.1V.

[0073] Figure 3J Another example method of operating a memory device according to some embodiments of the present disclosure is illustrated. In this embodiment, during the application of a first programming pulse of a predetermined number of programming pulses to a selected word line corresponding to a second memory cell, a first bit line bias voltage is applied to a bit line (e.g., the first bit line) corresponding to a memory cell (e.g., the second memory cell) other than the first memory cell in the target memory cell group. The first bit line bias voltage is applied to the memory cell only during the application of the first programming pulse of the programming pulses to the memory cell. For example, during the application of the first (e.g., the only) programming pulse to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell. During the application of the first (e.g., the first of two) programming pulse to the third memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the third memory cell. And during the application of the first (e.g., the first of three) programming pulse to the fourth memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the fourth memory cell. During the application of the remaining predetermined number of programming pulses to the memory cells, a default bit line bias voltage is applied to the memory cells. In this embodiment, the first line bias voltage differs from the 3BL bias voltage in the previous embodiment. Note that these two embodiments can be implemented individually or in combination.

[0074] like Figure 3JAs shown, taking the fourth memory cell corresponding to the fourth programming state as an example, after programming the fourth memory cell and later verifying it at the first verification voltage for the first programming state, three programming pulses are applied to the fourth memory cell. Furthermore, during the application of the first programming pulse to the fourth memory cell, a first bit line voltage is applied to the first bit line corresponding to the fourth memory cell. This first bit line voltage differs from the default bit line voltage. And after verification and the application of the programming pulses, programming of the fourth memory cell is prohibited in subsequent programming stages by applying a programming disable signal to the bit line corresponding to the fourth memory cell.

[0075] Figure 3K Another example method of operating a memory device according to some embodiments of the present disclosure is shown. In this embodiment, during the application of the last programming pulse of a predetermined number of programming pulses to a selected word line corresponding to a second memory cell, a first line bias voltage is applied to a bit line (e.g., the first bit line) corresponding to a memory cell (e.g., the second memory cell) in the target memory cell group other than the first memory cell. The first line bias voltage is applied to the memory cell only during the application of the last programming pulse to the memory cell. For example, during the application of the last (e.g., the only) programming pulse to the second memory cell, the first line bias voltage is applied to the first bit line corresponding to the second memory cell. During the application of the last (e.g., the second of two) programming pulse to the third memory cell, the first line bias voltage is applied to the first bit line corresponding to the third memory cell. And during the application of the last (e.g., the third of three) programming pulse to the fourth memory cell, the first line bias voltage is applied to the first bit line corresponding to the fourth memory cell. During the application of the remaining predetermined number of programming pulses to the memory cells, a default bit line bias voltage is applied to the memory cells. In some implementations, the default bit line bias voltage is 0V.

[0076] like Figure 3K As shown, taking the fourth memory cell corresponding to the fourth programming state as an example, after programming the fourth memory cell and later verifying it at the first verification voltage for the first programming state, three programming pulses are applied to the fourth memory cell. Furthermore, during the application of the third programming pulse to the fourth memory cell, a first bit line voltage is applied to the first bit line corresponding to the fourth memory cell. This first bit line voltage differs from the default bit line voltage. And after verification and the application of the programming pulses, programming of the fourth memory cell is prohibited in subsequent programming stages by applying a programming disable signal to the bit line corresponding to the fourth memory cell.

[0077] In some implementations, the first line bias voltage is determined based on cell information of the target memory cell group, excluding the first memory cell (e.g., the second, third, fourth, etc.). In some implementations, the cell information includes the initial threshold voltage distribution of the memory cells or the programming speed of the memory cells. In some implementations, the cell information is obtained before the first memory cell passes the first verification at the first verification voltage. For example, as... Figure 3L As shown, cell information can be obtained by determining whether a memory cell is a slow cell or a fast cell. For example, it can be determined that the second memory cell corresponding to the second programming state and the fourth memory cell corresponding to the fourth programming state are fast cells and may require the application of a first line bias voltage, while the third memory cell corresponding to the third programming state may not. In response to determining that the fourth memory cell corresponding to P4 is a fast cell, and applying the first line bias voltage during the application of the first programming pulse, the Vt distribution of the fast cell (i.e., the fourth memory cell) is thus compressed and narrowed. In some embodiments, the first line bias voltage is greater than 0V and less than 2.2V. For example, the first line bias voltage includes 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, or 2.1V.

[0078] Figure 4A A flowchart of an example method 400 for operating a memory device according to some embodiments of the present disclosure is shown. In some embodiments, method 400 is a first programming operation. That is, a second programming operation may be applied to the memory device after method 400 is performed.

[0079] Method 400 begins with operation 402, in which a first programming voltage is applied to a selected word line corresponding to a target memory cell group. The target memory cell group is a set of memory cells selected in the current programming operation. In some embodiments, the target memory cell group includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell.

[0080] Next, referring to operation 404, a first verification voltage is applied to selected word lines corresponding to the target group of memory cells. For example, first, second, third, and fourth memory cells are subjected to the first verification voltage and pass verification. In some embodiments, these memory cells that have been verified by using the first verification voltage are no longer verified after the programming pulse is applied. For example, a verification inhibit voltage (e.g., 0V or lower than certain bit line voltages during normal verification) is applied to the bit lines coupled to these memory cells, so that these memory cells are not verified during subsequent verification.

[0081] Next, refer to operation 406, in which a predetermined number of programming pulses are applied to selected word lines corresponding to memory cells (e.g., second, third, or fourth memory cells) of the first target memory cell group other than the first memory cell.

[0082] When a programming pulse is applied to a selected word line, programming of the first memory cell is disabled (e.g., by applying a programming disable voltage (e.g., a high voltage Vdd) to the bit line coupled to the first memory cell). After applying one programming pulse to the second memory cell, programming of the second memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the second memory cell). After applying two programming pulses to the third memory cell, programming of the third memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the third memory cell). Next, a third programming pulse is applied to the fourth memory cell (i.e., a total of three programming pulses). Therefore, after applying corresponding programming pulses to the four memory cells and verifying them using a first verification voltage, the threshold voltages of the four memory cells are at least all distributed in their corresponding intermediate programming states. Next, an additional programming process (e.g., a second programming operation (e.g., fine programming)) can be applied to the four memory cells such that the four memory cells can be programmed to their corresponding target programming states.

[0083] In some embodiments, the predetermined number of programming pulses applied to the memory cells includes n programming pulses applied to the (n+1)th memory cell, where n is an integer greater than 0. For example, in an embodiment where the first target memory cell group comprises four memory cells, one programming pulse is applied to the second memory cell, two programming pulses are applied to the third memory cell, and three programming pulses are applied to the fourth memory cell. In some embodiments, at least one programming pulse is applied to at least one memory cell of the nth memory cell. The larger n is, the more programming pulses are applied to the nth memory cell. For example, the fourth memory cell receives more programming pulses than the third, second, or first memory cell.

[0084] Next, referring to operation 408, during the application of the last programming pulse of a predetermined number of programming pulses to the selected word line corresponding to a memory cell (e.g., a second memory cell) in the target memory cell group other than the first memory cell, a first bit line bias voltage is applied to the first bit line corresponding to the memory cell (e.g., a second, third, or fourth memory cell) in the target memory cell group other than the first memory cell. For example, during the application of the last (e.g., the only) programming pulse to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell. During the application of the last (e.g., the second of two) programming pulse to the third memory cell, the first bit line bias voltage may be applied to the first bit line corresponding to the third memory cell. And during the application of the last (e.g., the third of three) programming pulse to the fourth memory cell, the first bit line bias voltage may be applied to the first bit line corresponding to the fourth memory cell. During the application of the remaining predetermined number of programming pulses to the memory cells, a default bit line bias voltage is applied to the memory cells. In some embodiments, the first bit line bias voltage herein is a 3BL bias voltage. Furthermore, the first bit line bias voltage can be determined based on cell information of at least the second memory cell and can be obtained before the first memory cell passes the first verification at the first verification voltage. In some embodiments, the cell information includes the initial threshold voltage distribution of the memory cell or the programming speed of the memory cell. In some embodiments, the default bit line bias voltage is 0V.

[0085] Figure 4B A flowchart of an example method 410 for operating a memory device according to some embodiments of the present disclosure is shown.

[0086] Method 410 begins with operation 412, in which it is determined that the first set of memory cells is programmed faster than the second set of memory cells. The first set of memory cells and the second set of memory cells correspond to the first bit line. In some embodiments, the first set of memory cells are the fast memory cells described above, and the second set of memory cells are the slow memory cells described above.

[0087] Next, refer to operation 414, in which a first programming voltage is applied to a selected word line corresponding to a target memory cell group. For example, the first target memory cell group is a set of memory cells selected in the current programming operation. In some embodiments, the first target memory cell group includes a first set of memory cells and a second set of memory cells, comprising a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. For example, the first set of memory cells includes at least one memory cell (e.g., a fourth memory cell) from the first target memory cell group.

[0088] Next, referring to operation 416, a first verification voltage is applied to selected word lines corresponding to the target group of memory cells. For example, first, second, third, and fourth memory cells are subjected to the first verification voltage and pass verification. In some embodiments, these memory cells that have been verified by using the first verification voltage are no longer verified after the programming pulse is applied. For example, a verification inhibit voltage (e.g., 0V or below certain bit line voltages during normal verification) is applied to the bit lines coupled to these memory cells, so that these memory cells are not verified during subsequent verification.

[0089] Next, refer to operation 418, in which a predetermined number of programming pulses are applied to selected word lines corresponding to memory cells other than the first memory cell (e.g., the second, third, or fourth memory cell) of the first group of memory cells.

[0090] When a programming pulse is applied to a selected word line, programming of the first memory cell is disabled (e.g., by applying a programming disable voltage (e.g., a high voltage Vdd) to the bit line coupled to the first memory cell). After one programming pulse is applied to the second memory cell, programming of the second memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the second memory cell). After two programming pulses are applied to the third memory cell, programming of the third memory cell is disabled (e.g., by applying a programming disable voltage to the bit line coupled to the third memory cell). Next, a third programming pulse is applied to the fourth memory cell (i.e., a total of three programming pulses). Therefore, after the four memory cells have been given corresponding programming pulses and verified by using a first verification voltage, the threshold voltages of the four memory cells are at least all distributed in their corresponding intermediate programming states. Next, an additional programming process (e.g., a second programming operation (e.g., fine programming)) can be applied to the four memory cells so that the four memory cells can be programmed to their corresponding target programming states.

[0091] In some implementations, the predetermined number of programming pulses applied to the memory cells includes n programming pulses applied to the (n+1)th memory cell, where n is an integer greater than 0. For example, in an implementation where the first target memory cell group comprises four memory cells, one programming pulse is applied to the second memory cell, two programming pulses are applied to the third memory cell, and three programming pulses are applied to the fourth memory cell.

[0092] Next, referring to operation 420, during the application of the first programming pulse of a predetermined number of programming pulses to a selected word line corresponding to a memory cell (e.g., a second memory cell) in the target memory cell group other than the first memory cell, a first bit line bias voltage is applied to the first bit line corresponding to the memory cell (e.g., a second memory cell) in the target memory cell group other than the first memory cell. For example, during the application of the first programming pulse to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell. During the application of the first programming pulse to the third memory cell, the first bit line bias voltage can be applied to the first bit line corresponding to the third memory cell. And during the application of the first programming pulse to the fourth memory cell, the first bit line bias voltage can be applied to the first bit line corresponding to the fourth memory cell. During the application of the remaining predetermined number of programming pulses to the memory cells, a default bit line bias voltage is applied to the memory cells. In some embodiments, the first bit line bias voltage herein is not the 3BL bias voltage. Furthermore, the first bit line bias voltage can be determined based on at least the cell information of the second memory cell and can be obtained before the first memory cell passes the first verification at the first verification voltage. Furthermore, it can be determined based on operation 412, which identifies which memory cells are fast memory cells (e.g., the first group of memory cells) and which are slow memory cells (e.g., the second group of memory cells). In some embodiments, cell information includes the initial threshold voltage distribution of the memory cells or the programming speed of the memory cells.

[0093] Figure 5 A block diagram of a system 500 having a memory device according to some aspects of this disclosure is shown. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 5 As shown, system 500 may include a host 508 and a memory system 502 having one or more memory devices 504 and a memory controller 506. The host 508 may be a processor of an electronic device (such as a central processing unit (CPU)) or a system-on-a-chip (SoC), such as an application processor (AP). The host 508 may be configured to send data to or receive data from the memory device 504.

[0094] Memory device 504 can be any memory device disclosed herein, such as memory device 100. In some embodiments, each memory device 504 includes a memory device as described in detail above.

[0095] According to some embodiments, a memory controller 506 is coupled to a memory device 504 and a host 508 and is configured to control the memory device 504. The memory controller 506 can be any memory controller disclosed herein. The memory controller 506 manages data stored in the memory device 504 and communicates with the host 508. In some embodiments, the memory controller 506 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 506 can be configured to control the operation of the memory device 504, such as read, erase, and program operations. The memory controller 506 may also be configured to manage various functions relating to data stored or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 504. Any other suitable function, such as formatting the memory device 504, may also be performed by the memory controller 506. The memory controller 506 may communicate with an external device (e.g., a host 508) according to a specific communication protocol. For example, the memory controller 506 may communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0096] The memory controller 506 and one or more memory devices 504 can be integrated into various types of memory devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 502 can be implemented and packaged into different types of end electronic products. Figure 6AIn one example shown, the memory controller 506 and a single memory device 504 can be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may also include a connection between the memory card 602 and a host computer (e.g., Figure 5 The memory card connector 604 is coupled to the host 508. In such a... Figure 6B In another example shown, the memory controller 506 and multiple memory devices 504 can be integrated into the SSD 606. The SSD 606 may also include a connection between the SSD 606 and a host (e.g., Figure 5 The SSD connector 608 is coupled to the host 508 in the memory card 602. In some embodiments, the storage capacity and / or operating speed of the SSD 606 is greater than that of the memory card 602.

[0097] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementations.

[0098] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method of operating a memory device, comprising: A first programming voltage is applied to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the target programming state of the first memory cell is a first programming state, and the target programming state of the second memory cell is a second programming state. A first verification voltage is applied to the selected word line corresponding to the target memory cell group; A predetermined number of programming pulses are applied to the selected word line corresponding to the second memory cell; and During the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, a first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

2. The method according to claim 1, further comprising: The first bit line bias voltage is determined based on the cell information of the second memory cell.

3. The method according to claim 2, wherein: The cell information is obtained before the first memory cell passes the first verification under the first verification voltage.

4. The method according to claim 1, wherein: The first bit line bias voltage is different from the first bit line voltage, wherein the first bit line voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the predetermined number of programming pulses (excluding the first programming pulse or the last programming pulse) to the selected word line corresponding to the second memory cell.

5. The method according to claim 1, further comprising: In response to the first memory cell passing the first verification under the first verification voltage, programming of the first memory cell is prohibited; In response to the second memory cell passing the first verification at the first verification voltage, the predetermined number of programming pulses are applied to the selected word line corresponding to the second memory cell; as well as Programming of the second memory cell is prohibited.

6. The method according to claim 1, wherein, Applying a predetermined number of programming pulses to a selected word line corresponding to the second memory cell includes: n programming pulses are applied to the selected word line corresponding to the (n+1)th memory cell in the target memory cell group, where n is an integer greater than 0.

7. The method according to claim 1, wherein, The first bit line bias voltage is a 3-bit line (3BL) bias voltage, and wherein, during the application of the last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell in the target memory cell group, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

8. The method according to claim 7, wherein, The 3BL bias voltage is greater than 0V and less than 2.2V.

9. The method according to claim 1, wherein, During the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, the first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

10. The method according to claim 9, wherein, The first bit line bias voltage is greater than 0V and less than 2.2V.

11. The method according to claim 9, wherein, During the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, the first bit line bias voltage is determined based on the following: The first bit line is determined to correspond to a first group of memory cells that can be programmed faster than the second group of memory cells, wherein the target memory cell group includes the first group of memory cells and the second group of memory cells.

12. A memory device, comprising: A memory cell array, the memory cell array comprising memory cells; as well as Peripheral circuitry coupled to the memory cell array, wherein the peripheral circuitry is configured as follows: A first programming voltage is applied to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the target programming state of the first memory cell is a first programming state, and the target programming state of the second memory cell is a second programming state. A first verification voltage is applied to the selected word line corresponding to the target memory cell group; A predetermined number of programming pulses are applied to the selected word line corresponding to the second memory cell; and During the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, a first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

13. The memory device according to claim 12, wherein, The peripheral circuit is also configured to: The first bit line bias voltage is determined based on the cell information of the second memory cell.

14. The memory device according to claim 13, wherein: The cell information is obtained before the first memory cell passes the first verification under the first verification voltage.

15. The memory device according to claim 12, wherein: The first bit line bias voltage is different from the first bit line voltage, wherein the first bit line voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the predetermined number of programming pulses (excluding the first programming pulse or the last programming pulse) to the selected word line corresponding to the second memory cell.

16. The memory device according to claim 12, wherein, The peripheral circuit is also configured to: In response to the first memory cell passing the first verification under the first verification voltage, programming of the first memory cell is prohibited; In response to the second memory cell passing the first verification at the first verification voltage, the predetermined number of programming pulses are applied to the selected word line corresponding to the second memory cell; as well as Programming of the second memory cell is prohibited.

17. The memory device according to claim 12, wherein, The peripheral circuitry configured to apply a predetermined number of programming pulses to a selected word line corresponding to the second memory cell is further configured to: n programming pulses are applied to the selected word line corresponding to the (n+1)th memory cell in the target memory cell group, where n is an integer greater than 0.

18. The memory device according to claim 12, wherein, The first bit line bias voltage is a 3-bit line (3BL) bias voltage, and wherein the peripheral circuitry is configured to apply the first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell.

19. The memory device according to claim 18, wherein, The 3BL bias voltage is greater than 0V and less than 2.2V.

20. The memory device according to claim 12, wherein, The peripheral circuitry is configured to apply a first bit line bias voltage to the first bit line corresponding to the second memory cell in the target memory cell group during the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell.

21. The memory device according to claim 20, wherein, The first bit line bias voltage is greater than 0V and less than 2.2V.

22. The memory device according to claim 20, wherein, During the application of the first programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, the peripheral circuitry is configured to determine the first bit line bias voltage based on: The first bit line is determined to correspond to a first group of memory cells that can be programmed faster than the second group of memory cells, wherein the target memory cell group includes the first group of memory cells and the second group of memory cells.

23. A memory system, comprising: Memory devices; as well as A memory controller coupled to the memory device, wherein the memory device includes: Memory cell array, the memory cell array comprising memory cells; and Peripheral circuitry coupled to the memory cell array, wherein the peripheral circuitry is configured as follows: A first programming voltage is applied to a selected word line corresponding to a target memory cell group, wherein the target memory cell group includes a first memory cell and a second memory cell, the target programming state of the first memory cell is a first programming state, and the target programming state of the second memory cell is a second programming state. A first verification voltage is applied to the selected word line corresponding to the target memory cell group; A predetermined number of programming pulses are applied to the selected word line corresponding to the second memory cell; and During the application of the first or last programming pulse of the predetermined number of programming pulses to the selected word line corresponding to the second memory cell, a first bit line bias voltage is applied to the first bit line corresponding to the second memory cell in the target memory cell group.

Images