Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises the following steps: providing a silicon substrate, etching the silicon substrate to form a plurality of grooves, and taking the silicon substrate between two adjacent grooves as a cathode; forming a stress layer to fill the grooves and apply stress to the cathode; when the conductive type of the silicon substrate is N type, the stress layer applies compressive stress to the cathode; when the conductive type of the silicon substrate is P type, the stress layer applies tensile stress to the cathode; sequentially forming an insulating layer and a metal layer to cover the cathode and the stress layer; etching the metal layer to form a plurality of first openings penetrating through the metal layer; etching the insulating layer along the first openings to form a plurality of second openings penetrating through the insulating layer, and the second openings expose part of the surface of the side of the cathode and the anode, and the exposed cathode serves as an emitter of the cathode. The application can inhibit the surface electron emission characteristics of the emitter of the cathode, so as to regulate the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Applying a sufficiently high electric field (greater than 10 V / cm) to the solid surface of a semiconductor device allows electrons inside the solid to overcome the surface potential barrier and tunnel to the vacuum level, resulting in field emission of surface electrons. In recent years, semiconductor devices based on surface electron emission characteristics have attracted widespread attention in high-frequency applications such as millimeter waves / terahertz and extreme environments due to their advantages such as fast response speed, wide operating temperature range, radiation resistance, and compatibility with current semiconductor manufacturing technologies.

[0003] The modulation of the surface electron emission properties of the cathode in semiconductor devices is a crucial method for achieving device performance control. Currently, device performance control is mainly achieved through the following means: 1. Reducing the work function of the semiconductor surface through doping techniques; 2. Using materials with negative electron affinity, such as graphene and nanodiamond, as emitters; 3. In terms of device structure, compressing the device channel length and optimizing the shape of the nano-emitter; 4. Using vacuum or special gas encapsulation methods. However, these methods suffer from problems in practical applications, including poor device performance, high processing precision requirements, and the need for special materials and packaging technologies, hindering the development of cathode electron emission device design and manufacturing technology. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can suppress the surface electron emission characteristics of the cathode emitter, thereby regulating the performance of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0006] A silicon substrate is provided, wherein the conductivity type of the silicon substrate is N-type or P-type, and the silicon substrate is etched to form a plurality of grooves, wherein the silicon substrate between two adjacent grooves serves as a cathode;

[0007] A stress layer is formed to fill the groove to apply stress to the cathode. When the conductivity type of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode. When the conductivity type of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode.

[0008] An insulating layer and a metal layer are sequentially formed to cover the cathode and the stress layer;

[0009] The metal layer is etched to form a plurality of first openings penetrating the metal layer, the first openings being located above the groove, the remaining metal layer serving as the anode; and,

[0010] The insulating layer is etched along the first opening to form a plurality of second openings penetrating the insulating layer. The second openings communicate with the first openings and expose a portion of the surface of the cathode and the anode that are close to each other. The exposed cathode serves as the emitter of the cathode.

[0011] Optionally, when the stress layer applies compressive stress to the cathode, the stress layer may be made of germanium-silicon.

[0012] Optionally, when the stress layer applies tensile stress to the cathode, the stress layer may be made of silicon carbide.

[0013] Optionally, the stress layer may be formed using an epitaxial growth process.

[0014] Optionally, the thickness of the insulating layer is less than 100 nm.

[0015] Optionally, the insulating layer may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0016] Optionally, the metal layer may be made of at least one of aluminum, titanium, copper, tungsten and gold, and a metal adhesion layer may be formed between the metal layer and the insulating layer.

[0017] Optionally, the steps of etching the metal layer and etching the insulating layer include:

[0018] A patterned photoresist layer is formed on the metal layer;

[0019] Using the patterned photoresist layer as a mask, the metal layer is etched using a dry etching process to form the first opening;

[0020] Using the patterned photoresist layer as a mask, a wet etching process is used to etch the insulating layer along the first opening to form the second opening;

[0021] Remove the patterned photoresist layer.

[0022] Optionally, the width of the first opening is smaller than the width of the groove, and the width of the second opening is larger than the width of the groove.

[0023] The present invention also provides a semiconductor device, comprising:

[0024] A silicon substrate, wherein the conductivity type of the silicon substrate is N-type or P-type, and a plurality of grooves are formed in the silicon substrate, wherein the silicon substrate between two adjacent grooves serves as a cathode;

[0025] A stress layer fills the groove to apply stress to the cathode. When the conductivity type of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode; when the conductivity type of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode.

[0026] An insulating layer and a metal layer are arranged sequentially from bottom to top on the cathode, with the metal layer serving as the anode;

[0027] A plurality of first openings penetrate the metal layer, and the first openings are located above the groove;

[0028] Several second openings penetrate the insulating layer, the second openings communicating with the first openings and exposing a portion of the surface of the cathode and the anode on the side closest to each other, the exposed cathode serving as the emitter of the cathode.

[0029] In the semiconductor device and its fabrication method provided by the present invention, a silicon substrate is provided, the silicon substrate having an N-type or P-type conductivity. The silicon substrate is etched to form a plurality of grooves, and the silicon substrate between two adjacent grooves serves as a cathode. A stress layer is formed to fill the grooves to apply stress to the cathode. When the silicon substrate has an N-type conductivity, the stress layer applies compressive stress to the cathode, and when the silicon substrate has a P-type conductivity, the stress layer applies tensile stress to the cathode. An insulating layer and a metal layer are formed sequentially to cover the cathode and the stress layer. The metal layer is etched to form a plurality of first openings penetrating the metal layer. The first openings are located above the grooves, and the remaining metal layer serves as an anode. The insulating layer is etched along the first openings to form a plurality of second openings penetrating the insulating layer. The second openings communicate with the first openings and expose a portion of the surface of the cathode and anode that are close to each other. The exposed cathode serves as the emitter of the cathode. This invention applies strained silicon technology in reverse. When the conductivity of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode. When the conductivity of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode. This changes the energy band distribution on the cathode surface and the electron mobility near the cathode surface, thereby affecting the number of electrons emitted by the cathode emitter and suppressing the surface electron emission characteristics of the cathode emitter, thus regulating the performance of the semiconductor device. Attached Figure Description

[0030] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0031] Figures 2-8 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0032] The attached figures are labeled as follows:

[0033] 10-Silicon substrate; 12-Groove; 20-Cathode; 22-Emitter of cathode; 30-Stress layer; 40-Insulating layer; 50-Metal layer; 52-Anode; 60-Patterned photoresist layer; 71-First opening; 72-Second opening. Detailed Implementation

[0034] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0035] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, and “one end” and “the other end” generally refer to two corresponding parts. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] Figure 1 A flowchart illustrating the method for fabricating the semiconductor device provided by this invention. Please refer to... Figure 1 This invention provides a method for fabricating a semiconductor device, comprising:

[0037] Step S1: Provide a silicon substrate, the silicon substrate being of N-type or P-type conductivity, and etch the silicon substrate to form several grooves, with the silicon substrate between two adjacent grooves serving as the cathode;

[0038] Step S2: Form a stress layer to fill the groove to apply stress to the cathode. When the conductivity type of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode. When the conductivity type of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode.

[0039] Step S3: Sequentially form an insulating layer and a metal layer to cover the cathode and the stress layer;

[0040] Step S4: Etch the metal layer to form several first openings penetrating the metal layer. The first openings are located above the grooves, and the remaining metal layer serves as the anode.

[0041] Step S5: Etch the insulating layer along the first opening to form a plurality of second openings penetrating the insulating layer. The second openings are connected to the first opening and expose a portion of the surface of the cathode and anode that are close to each other. The exposed cathode serves as the emitter of the cathode.

[0042] Figures 2-8 This is a cross-sectional schematic diagram of the corresponding steps in the semiconductor device fabrication method provided in this embodiment. The following is in conjunction with... Figures 2-8 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0043] Execution step S1: Please refer to Figure 2 A silicon substrate 10 is provided, and the conductivity type of the silicon substrate 10 is N-type or P-type. The silicon substrate 10 is etched to form a plurality of grooves 12, and the silicon substrate 10 between two adjacent grooves 12 serves as the cathode 20 of the device.

[0044] Execution step S2: Please refer to Figure 3 An epitaxial growth process is used to form a stress layer 30 to fill the grooves and apply stress to the cathode 20. The stress layer 30 and the top surface of the cathode 20 are flush. When the conductivity type of the silicon substrate 10 is N-type (i.e., the conductivity type of the cathode 20 is N-type), the stress layer 30 applies compressive stress to the cathode 20, increasing the surface potential barrier and reducing the electron mobility of the cathode 20, thereby suppressing surface electron emission of the cathode 20. That is, under the same anode voltage, the number of electrons emitted by the cathode is reduced, or, to obtain the same cathode emission current, a higher anode voltage needs to be applied, thereby reducing the operating current of the device or increasing the operating voltage. When the conductivity type of the silicon substrate 10 is P-type (i.e., the conductivity type of the cathode 20 is P-type), the stress layer 30 applies tensile stress to the cathode 20, increasing the surface potential barrier and reducing the electron mobility of the cathode 20, thereby suppressing surface electron emission of the cathode 20. That is, under the same anode voltage, the number of electrons emitted by the cathode is reduced, or, to obtain the same cathode emission current, a higher anode voltage needs to be applied, thereby reducing the operating current of the device or increasing the operating voltage. In this embodiment, when the stress layer 30 applies compressive stress to the cathode 20, the material of the stress layer 30 includes germanium-silicon; when the stress layer 30 applies tensile stress to the cathode 20, the material of the stress layer 30 includes silicon carbide, but is not limited thereto. Stress layers 30 made of different materials have different stress properties. Strain material is epitaxially grown around the cathode 20 to allow the stress layer 30 to apply compressive or tensile stress to the cathode 20. In this embodiment, when the stress layer 30 applies stress (tensile and compressive stress) to the cathode 20, the stress layer 30 applies stress to the cathode 20 along the planar direction of the silicon substrate 10.

[0045] Execution step S3: Please refer to Figure 4An insulating layer 40 and a metal layer 50 are sequentially formed to cover the cathode 20 and the stress layer 30. In this embodiment, the insulating layer 40 may be made of silicon oxide, silicon nitride, or silicon oxynitride; the metal layer 50 may be made of at least one of aluminum, titanium, copper, tungsten, and gold, and is not limited thereto. Furthermore, a metal adhesion layer (not shown in the figure) is formed between the metal layer 50 and the insulating layer 40. The metal adhesion layer may be made of titanium nitride, and is not limited thereto. In this embodiment, the thickness of the insulating layer 40 is preferably less than 100 nm to facilitate the formation of an electron transport channel, and is not limited thereto.

[0046] Execution step S4: Please refer to Figure 5 A patterned photoresist layer 60 is formed on the metal layer 50, and the patterned photoresist layer 60 has patterned openings (not shown in the figure); please refer to [reference needed]. Figure 5 and reference Figure 6 Using a patterned photoresist layer 60 as a mask, a plurality of first openings 71 penetrating the metal layer 50 are etched along the pattern openings. The first openings 71 are located directly above the groove 12 (stress layer 30), and the width of the first openings 71 is smaller than the width of the groove 12. The projection of the first openings 71 onto the silicon substrate 10 is within the range of the projection of the groove 12 onto the silicon substrate 10, and the retained metal layer serves as the anode 52 of the device. In this embodiment, a dry etching process is used to etch the metal layer 50 to form the first openings 71. The dry etching process is generally anisotropic etching, which can control the width of the first openings 71 and make the sidewall morphology of the first openings 71 better.

[0047] Execution step S5: Please refer to Figure 7 and Figure 8Using a patterned photoresist layer 60 as a mask, a plurality of second openings 72 penetrating the insulating layer 40 are formed by etching along the first opening 71. The second openings 72 communicate with the first opening 71 and expose a portion of the surface of the cathode 20 and the anode 52 on the side closest to each other (a portion of the upper surface of the cathode 20 and a portion of the lower surface of the anode 52), as well as the surface of the stress layer 30. The exposed cathode 20 serves as the emitter 22 of the cathode. The second openings 72 are located above the groove 12 (stress layer 30), and the width of the second openings 72 is greater than the width of the groove 12. The projection of the groove 12 on the silicon substrate 10 is within the range of the projection of the second openings 72 on the silicon substrate 10. In this embodiment, a wet etching process is used to etch the insulating layer 40 to form the second opening 72. The wet etching process is isotropic etching. Since the insulating layer 40, stress layer 30, silicon substrate 10, and metal layer 50 are made of different materials, a larger etchant is selected based on the material differences to etch the insulating layer 40 to form a second opening 72 with a width greater than the first opening 71, thereby exposing a portion of the surface of the cathode 20 and anode that are close to each other. Subsequently, a photoresist stripping process is used to remove the patterned photoresist layer 60.

[0048] The semiconductor device provided in this embodiment is a cathode electron emission device. After the second opening 71 is formed, a portion of the surface of the cathode 20 and the anode 52 on the side that are close to each other faces each other. The other portion of the surface of the cathode 20 and the anode 52 on the side that are close to each other is isolated by the insulating layer 40. The portion of the cathode 20 facing each other (i.e. the exposed cathode 20) serves as the emitter 22 of the cathode. The emitter 22 of the cathode is in contact with the stress layer 30 and is directly subjected to the stress of the stress layer 30 to change the band distribution on the surface of the cathode 20 and the electron mobility near the surface of the cathode 20. The change in the band distribution (barrier change) on the surface of the cathode 20 will cause a change in the emission current of the emitter 22 of the cathode, which significantly affects the electron emission characteristics of the emitter 22 of the cathode. This embodiment utilizes the reverse application of strained silicon technology. When the conductivity type of the silicon substrate 10 is N-type, the stress layer 30 applies compressive stress to the cathode 20. When the conductivity type of the silicon substrate 10 is P-type, the stress layer 30 applies tensile stress to the cathode 20. By applying reverse stresses to the silicon substrate 10 according to different conductivity types (generally tensile stress is applied to N-type silicon substrates and compressive stress is applied to P-type silicon substrates), the number of electrons emitted by the emitter 22 of the cathode is affected, the surface electron emission characteristics of the emitter 22 of the cathode are suppressed, and the voltage and current performance of the semiconductor device is controlled, thereby controlling the performance of the semiconductor device.

[0049] This embodiment also provides a semiconductor device, which is prepared using the semiconductor device fabrication method described above. Please refer to... Figure 8 , Figure 8This is a cross-sectional schematic diagram of a semiconductor device, which includes a silicon substrate 10, a stress layer 30, an insulating layer 40, a metal layer, a plurality of first openings 71, and a plurality of second openings 72. The silicon substrate 10 has an N-type or P-type conductivity and contains a plurality of recesses 12. The silicon substrate between two adjacent recesses 12 serves as a cathode 20. The stress layer 30 fills the recesses 12 to apply stress to the cathode 20, and the top surfaces of the stress layer 30 and the cathode 20 are flush. When the silicon substrate 10 has an N-type conductivity (i.e., the cathode 20 has an N-type conductivity), the stress layer 30 applies compressive stress to the cathode 20, increasing the surface potential barrier and decreasing the electron mobility of the cathode 20, thereby suppressing surface electron emission of the cathode 20. That is, under the same anode voltage, the number of electrons emitted by the cathode decreases, or, to obtain the same cathode emission current, a higher anode voltage needs to be applied, thereby reducing the operating current of the device or increasing the operating voltage. When the silicon substrate 10 has a P-type conductivity (i.e., the cathode 20 has a P-type conductivity), the stress layer 30 applies tensile stress to the cathode 20, increasing the surface potential barrier and decreasing the electron mobility of the cathode 20, thereby suppressing surface electron emission of the cathode 20. That is, under the same anode voltage, the number of electrons emitted by the cathode decreases, or, to obtain the same cathode emission current, a higher anode voltage needs to be applied, thereby reducing the operating current of the device or increasing the operating voltage. In this embodiment, when the stress layer 30 applies compressive stress to the cathode 20, the material of the stress layer 30 includes germanium silicon; when the stress layer 30 applies tensile stress to the cathode 20, the material of the stress layer 30 includes silicon carbide, but is not limited thereto.

[0050] The insulating layer 40 and the metal layer are located on the cathode 20 from bottom to top, with the metal layer serving as the anode 52; and a metal adhesion layer (not shown in the figure) is also formed between the metal layer 50 and the insulating layer 40. The material and thickness requirements of the insulating layer 40, the metal layer and the metal adhesion layer are as described above.

[0051] A plurality of first openings 71 penetrate the metal layer and are located directly above the groove 12 (stress layer 30). The width of the first openings 71 is less than the width of the groove 12, and the projection of the first openings 71 on the silicon substrate 10 is within the range of the projection of the groove 12 on the silicon substrate 10.

[0052] Several second openings 72 penetrate the insulating layer 40, communicate with the first opening 71, and expose a portion of the surface of the cathode 20 and the anode 52 on the side adjacent to each other (a portion of the upper surface of the cathode 20 and a portion of the lower surface of the anode 52), as well as the surface of the stress layer 30. The exposed cathode 20 serves as the emitter 22 of the cathode. The second openings 72 are located above the groove 12 (stress layer 30), and the width of the second openings 72 is greater than the width of the groove 12. The projection of the groove 12 onto the silicon substrate 10 is within the range of the projection of the second openings 72 onto the silicon substrate 10.

[0053] In summary, in the semiconductor device and its fabrication method provided by the present invention, a silicon substrate is provided, the silicon substrate having an N-type or P-type conductivity. The silicon substrate is etched to form a plurality of grooves, and the silicon substrate between two adjacent grooves serves as a cathode. A stress layer is formed to fill the grooves to apply stress to the cathode. When the silicon substrate has an N-type conductivity, the stress layer applies compressive stress to the cathode; when the silicon substrate has a P-type conductivity, the stress layer applies tensile stress to the cathode. An insulating layer and a metal layer are sequentially formed to cover the cathode and the stress layer. The metal layer is etched to form a plurality of first openings penetrating the metal layer, the first openings being located above the grooves, and the remaining metal layer serving as an anode. The insulating layer is etched along the first openings to form a plurality of second openings penetrating the insulating layer, the second openings communicating with the first openings and exposing a portion of the surface of the cathode and anode on the side closest to each other, the exposed cathode serving as the emitter of the cathode. This invention applies strained silicon technology in reverse. When the conductivity of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode. When the conductivity of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode. This changes the energy band distribution on the cathode surface and the electron mobility near the cathode surface, thereby affecting the number of electrons emitted by the cathode emitter and suppressing the surface electron emission characteristics of the cathode emitter, thus regulating the performance of the semiconductor device.

[0054] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A silicon substrate is provided, wherein the conductivity type of the silicon substrate is N-type or P-type, and the silicon substrate is etched to form a plurality of grooves, wherein the silicon substrate between two adjacent grooves serves as a cathode; A stress layer is formed to fill the groove to apply stress to the cathode. When the conductivity type of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode. When the conductivity type of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode. An insulating layer and a metal layer are sequentially formed to cover the cathode and the stress layer; The metal layer is etched to form a plurality of first openings penetrating the metal layer, the first openings being located above the groove, and the remaining metal layer serving as the anode; as well as, The insulating layer is etched along the first opening to form a plurality of second openings penetrating the insulating layer. The second openings communicate with the first openings and expose a portion of the surface of the cathode and the anode that are close to each other. The exposed cathode serves as the emitter of the cathode.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the stress layer applies compressive stress to the cathode, the material of the stress layer includes germanium and silicon.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the stress layer applies tensile stress to the cathode, the stress layer is made of silicon carbide.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The stress layer is formed using an epitaxial growth process.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The thickness of the insulating layer is less than 100 nm.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The insulating layer is made of silicon oxide, silicon nitride, or silicon oxynitride.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The metal layer is made of at least one of aluminum, titanium, copper, tungsten and gold, and a metal adhesion layer is formed between the metal layer and the insulating layer.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The steps of etching the metal layer and etching the insulating layer include: A patterned photoresist layer is formed on the metal layer; Using the patterned photoresist layer as a mask, the metal layer is etched using a dry etching process to form the first opening; Using the patterned photoresist layer as a mask, a wet etching process is used to etch the insulating layer along the first opening to form the second opening; Remove the patterned photoresist layer.

9. The method for fabricating a semiconductor device as described in claim 1 or 8, characterized in that, The width of the first opening is smaller than the width of the groove, and the width of the second opening is larger than the width of the groove.

10. A semiconductor device, characterized in that, include: A silicon substrate, wherein the conductivity type of the silicon substrate is N-type or P-type, and a plurality of grooves are formed in the silicon substrate, wherein the silicon substrate between two adjacent grooves serves as a cathode; A stress layer fills the groove to apply stress to the cathode. When the conductivity type of the silicon substrate is N-type, the stress layer applies compressive stress to the cathode; when the conductivity type of the silicon substrate is P-type, the stress layer applies tensile stress to the cathode. An insulating layer and a metal layer are arranged sequentially from bottom to top on the cathode, with the metal layer serving as the anode; A plurality of first openings penetrate the metal layer, and the first openings are located above the groove; Several second openings penetrate the insulating layer, the second openings communicating with the first openings and exposing a portion of the surface of the cathode and the anode on the side closest to each other, the exposed cathode serving as the emitter of the cathode.

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