Isolation power supply chip packaging structure and manufacturing method thereof

Abstract

The invention discloses an isolated power supply chip packaging structure and a manufacturing method thereof, and relates to the technical field of packaging substrates. The method comprises the following steps: preparing a substrate; a first coil and a second coil are respectively arranged on the upper and lower surfaces of the substrate; forming cavities in the substrate to form a plurality of cavity structures; a transmitting chip is placed in one cavity structure, and a receiving chip is placed in the other cavity structure; performing plastic packaging on the transmitting chip and the receiving chip through the first dielectric layer; the first dielectric layer covers the upper and lower surfaces of the substrate, and the cavity structure is filled with the first dielectric layer; drilling the first dielectric layer to form a first blind hole communicated with the first circuit, the transmitting chip and the receiving chip; and performing hole-filling electroplating on the first blind hole to form a first conductive blind hole, and forming a second circuit in conductive connection with the first conductive blind hole on the surface of the first dielectric layer to obtain the isolated power supply chip packaging structure. According to the method provided by the embodiment of the invention, the packaging process can be simplified, and the product integration degree is improved.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, and in particular to an isolated power supply chip packaging structure and its manufacturing method. Background Technology

[0002] With the continuous development of electronic information technology, electronic products are required to be smaller and thinner. This makes the high-density integration, miniaturization, and multifunctionality of packaging substrates for electronic components such as chips an inevitable trend. Therefore, reducing product size and thickness and improving the stability and reliability of the packaging structure through embedding within the substrate is particularly crucial for the development of high integration, miniaturization, and thinning of semiconductor packaging and final products.

[0003] Current methods for packaging isolated power supplies involve placing the transformer inside the substrate, then surface-mounting the receiver and transmitter chips for packaging and overmolding, followed by another molding process on the lead frame to complete the isolated power supply chip in a single-open-package (SOP) configuration. This existing solution requires two molding processes, resulting in a complex workflow, low product integration, and an inability to meet the current trend towards thinner and lighter electronic products. Summary of the Invention

[0004] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes an isolated power supply chip packaging structure and its fabrication method, which can simplify the process flow and improve product integration.

[0005] On one hand, the method for fabricating an isolated power supply chip package structure according to an embodiment of the present invention includes the following steps:

[0006] Prepare a substrate; the upper and lower surfaces of the substrate are provided with first lines that are electrically connected to each other.

[0007] A first coil and a second coil are respectively disposed on the upper and lower surfaces of the substrate;

[0008] A cavity is formed in the substrate to create a plurality of cavity structures;

[0009] A transmitting chip is placed in one of the cavity structures, and a receiving chip is placed in the other cavity structure;

[0010] The transmitting chip and the receiving chip are encapsulated by a first dielectric layer; the first dielectric layer covers the upper and lower surfaces of the substrate and fills the cavity structure;

[0011] Drill a hole in the first dielectric layer to form a first blind via that communicates with the first line, the transmitting chip, and the receiving chip;

[0012] The first blind via is filled by electroplating to form a first conductive blind via, and a second line is formed on the surface of the first dielectric layer that is conductively connected to the first conductive blind via, thereby obtaining an isolated power chip package structure.

[0013] According to some embodiments of the present invention, the preparation of the substrate includes:

[0014] Prepare a support plate; the support plate has a through post inside, and a third line is provided on the upper and lower surfaces of the support plate, the third line being electrically connected to the through post;

[0015] A third coil and a fourth coil are respectively disposed on the upper and lower surfaces of the bearing plate;

[0016] A second dielectric layer is pressed onto the upper and lower surfaces of the bearing plate, respectively; the second dielectric layer covers the third circuit.

[0017] A second conductive blind via is provided within the second dielectric layer and is conductively connected to the third circuit.

[0018] The first line is formed on the surface of the second dielectric layer and is electrically connected to the second conductive blind hole.

[0019] According to some embodiments of the present invention, the step of forming cavities in the substrate to create a plurality of cavity structures includes:

[0020] Drilling is performed on the substrate to form the cavity structure that penetrates the second dielectric layer and the carrier plate;

[0021] Alternatively, sacrificial copper pillars can be provided within the second dielectric layer and the carrier plate, and the sacrificial copper pillars can be etched to obtain the cavity structure that penetrates the second dielectric layer and the carrier plate.

[0022] According to some embodiments of the present invention, placing a transmitting chip in one of the cavity structures and a receiving chip in the other cavity structure includes:

[0023] An adhesive element is disposed on the surface of the second dielectric layer;

[0024] The transmitting chip and the receiving chip are placed in their respective cavity structures and fixed by the adhesive.

[0025] According to some embodiments of the present invention, the encapsulation of the transmitter chip and the receiver chip through the first dielectric layer includes:

[0026] The first medium material is pressed from the side of the second medium layer away from the adhesive, so that the first medium material covers the side of the second medium layer away from the adhesive and fills the cavity structure;

[0027] Remove the adhesive and press a second medium material onto the side of the second medium layer near the adhesive, so that the second medium material covers the side of the second medium layer near the adhesive; the first medium material and the second medium material constitute the first medium layer.

[0028] According to some embodiments of the present invention, both the transmitting chip and the receiving chip are provided with connection terminals, and the first conductive blind via is conductively connected to the first line, the second line, the connection terminal of the transmitting chip and the connection terminal of the receiving chip, respectively.

[0029] According to some embodiments of the present invention, after performing a fill plating process on the first blind via to form a first conductive blind via, and forming a second line conductively connected to the first conductive blind via on the surface of the first dielectric layer to obtain an isolated power chip package structure, the method further includes:

[0030] A solder resist layer is disposed on the surface of the first dielectric layer; the solder resist layer covers the second circuit.

[0031] The solder mask layer is made into a window, and a pad corresponding to the second circuit is formed at the window.

[0032] The pads are surface treated to form a surface treatment layer.

[0033] On the other hand, the isolated power chip packaging structure according to embodiments of the present invention is manufactured by the method for manufacturing the isolated power chip packaging structure described in the above-mentioned embodiments, and the isolated power chip packaging structure includes:

[0034] The substrate has a first line electrically connected to each other on its upper and lower surfaces, a first coil and a second coil respectively on its upper and lower surfaces, and a plurality of cavity structures.

[0035] The transmitting chip is disposed within one of the cavity structures;

[0036] The receiving chip is disposed within another of the aforementioned cavity structures;

[0037] A first dielectric layer covers the upper and lower surfaces of the substrate, and the first dielectric layer fills the cavity structure;

[0038] A first conductive blind via is disposed within the first dielectric layer and is conductively connected to the first line, the transmitting chip, and the receiving chip;

[0039] The second line is disposed on the surface of the first dielectric layer and is electrically connected to the first conductive blind via.

[0040] According to some embodiments of the present invention, the substrate includes:

[0041] A support plate, wherein a conductive post is provided inside the support plate, a third line is provided on the upper and lower surfaces of the support plate, the third line is electrically connected to the conductive post, and a third coil and a fourth coil are respectively provided on the upper and lower surfaces of the support plate.

[0042] A second dielectric layer is disposed on the upper and lower surfaces of the carrier plate, and the second dielectric layer covers the third circuit.

[0043] The second conductive blind via is disposed within the second dielectric layer and is conductively connected to the third circuit. The first circuit is disposed on the surface of the second dielectric layer and is conductively connected to the second conductive blind via.

[0044] According to some embodiments of the present invention, the isolated power chip package structure further includes a solder resist layer, the solder resist layer is disposed on the surface of the first dielectric layer, the solder resist layer covers the second circuit, and the solder resist layer is provided with pads corresponding to the second circuit, the pads being provided with a surface treatment layer.

[0045] The isolated power supply chip packaging structure and its manufacturing method according to embodiments of the present invention have at least the following beneficial effects: the transmitting chip and the receiving chip are embedded together inside the packaging structure, thereby reducing the thickness and size of the product, resulting in high product integration. At the same time, the entire process only requires one molding step, reducing packaging difficulty and promoting the development of thinner and lighter electronic products.

[0046] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0047] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0048] Figure 1 This is a flowchart illustrating the steps of a method for fabricating an isolated power supply chip packaging structure according to an embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram of the structure of the support plate according to an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the substrate structure according to an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure of the substrate after a cavity is formed in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the structure of the adhesive component disposed on the substrate according to an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the structure after placing the transmitting chip and the receiving chip in the cavity structure according to an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the structure after the first dielectric material is laminated onto the substrate according to an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram of the structure of the transmitting chip and the receiving chip after plastic encapsulation according to an embodiment of the present invention;

[0056] Figure 9 This is a schematic diagram of the isolated power supply chip packaging structure according to an embodiment of the present invention;

[0057] Figure 10 This is a schematic diagram of the isolated power supply chip package structure after solder masking according to an embodiment of the present invention;

[0058] Figure 11 This is a schematic diagram of a multilayer inductor coil according to an embodiment of the present invention;

[0059] Figure 12 This is a schematic diagram of parallel multi-inductor coils connected in series according to an embodiment of the present invention. Detailed Implementation

[0060] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0061] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0062] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0063] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0064] With the continuous development of electronic information technology, electronic products are required to be smaller and thinner. This makes the high-density integration, miniaturization, and multifunctionality of packaging substrates for electronic components such as chips an inevitable trend. Therefore, reducing product size and thickness and improving the stability and reliability of the packaging structure through embedding within the substrate is particularly crucial for the development of high integration, miniaturization, and thinning of semiconductor packaging and final products.

[0065] Current methods for packaging isolated power supplies involve placing the transformer inside the substrate, then surface-mounting the receiver and transmitter chips for packaging and overmolding, followed by another molding process on the lead frame to complete the isolated power supply chip in a single-open-package (SOP) configuration. This existing solution requires two molding processes, resulting in a complex workflow, low product integration, and an inability to meet the current trend towards thinner and lighter electronic products.

[0066] To address the aforementioned issues, this invention proposes an isolated power supply chip packaging structure and its fabrication method. The transmitting chip and the receiving chip are embedded together inside the packaging structure, thereby reducing the thickness and size of the product and achieving high product integration. Furthermore, the entire process requires only one molding step, reducing packaging difficulty and promoting the development of thinner and lighter electronic products.

[0067] The following description, in conjunction with the accompanying drawings, details the isolated power supply chip packaging structure and its fabrication method according to embodiments of the present invention.

[0068] On the one hand, such as Figure 1As shown, the method for fabricating an isolated power supply chip package structure according to an embodiment of the present invention includes, but is not limited to, steps S100 to S700:

[0069] Step S100: Prepare substrate 100; the upper and lower surfaces of substrate 100 are provided with first lines 110 that are electrically connected to each other.

[0070] Specifically, such as Figure 3 As shown, a first line 110 is provided on the upper and lower surfaces of the substrate 100, and a conductive line for conducting the upper and lower surfaces of the substrate 100 is provided inside the substrate 100, so that the first line 110 on the upper and lower surfaces of the substrate 100 are electrically connected to each other.

[0071] Step S200: A first coil 200 and a second coil 300 are respectively disposed on the upper and lower surfaces of the substrate 100;

[0072] Specifically, in order to set the first coil 200 and the second coil 300 on the upper and lower surfaces of the substrate 100, the following method can be adopted: attach a photosensitive dry film to the upper and lower surfaces of the substrate 100, expose and develop the photosensitive dry film to form a window pattern corresponding to the first coil 200 and the second coil 300, perform electroplating at the window pattern to form the first coil 200 and the second coil 300, and then remove the photosensitive dry film.

[0073] Step S300: Open cavities in the substrate 100 to form a plurality of cavity structures 800;

[0074] Specifically, such as Figure 4 As shown, by creating a cavity in the substrate 100, a chip can be embedded inside the cavity structure 800. Embedding the chip in the cavity structure 800 can reduce the package volume, reduce the product size and thickness, improve the stability and reliability of the package structure, and meet the requirements of miniaturization.

[0075] Step S400: Place the transmitting chip 1000 in one of the cavity structures 800 and the receiving chip 1100 in the other cavity structure 800.

[0076] Specifically, such as Figure 6As shown, in this example, the transmitting chip 1000 and the receiving chip 1100 are located on opposite sides of the first coil 200 and the second coil 300. The transmitting chip 1000 and the receiving chip 1100 work together to achieve signal or energy transmission under electrical isolation. The transmitting chip 1000 converts the original control signal (such as a PWM waveform) into a form suitable for isolated transmission via high-frequency carrier modulation, and then drives the first coil 200 / second coil 300 to convert the electrical signal into a magnetic or electric field signal, achieving electrical isolation. The receiving chip 1100 receives the modulated signal (such as magnetic / electric field changes) transmitted by the first coil 200 / second coil 300 and demodulates it back to the original electrical signal. The first coil 200 and the second coil 300 act as magnetic coupling carriers, transmitting energy or signals between the transmitting chip 1000 and the receiving chip 1100, achieving electrically isolated transmission through electromagnetic induction.

[0077] Step S500: The transmitter chip 1000 and receiver chip 1100 are encapsulated through the first dielectric layer 1200;

[0078] Specifically, such as Figure 7 and Figure 8 As shown, after the transmitter chip 1000 and receiver chip 1100 are placed inside the cavity structure 800, the transmitter chip 1000 and receiver chip 1100 are encapsulated by the first dielectric layer 1200, thus completing the encapsulation and fixation of the transmitter chip 1000 and receiver chip 1100. The first dielectric layer 1200 covers the upper and lower surfaces of the substrate 100 and also covers the first circuit 110.

[0079] Step S600: Drill a hole in the first dielectric layer 1200 to form a first blind hole that communicates with the first line 110, the transmitting chip 1000 and the receiving chip 1100;

[0080] Specifically, since the first dielectric layer 1200 covers the upper and lower surfaces of the substrate 100 and covers the first line 110, the transmitting chip 1000 and the receiving chip 1100, in order to enable the first line 110, the transmitting chip 1000 and the receiving chip 1100 to communicate with external lines / devices, it is necessary to drill holes in the first dielectric layer 1200 to form a first blind hole communicating with the first line 110.

[0081] Step S700: Fill the first blind hole 1300 with electroplating to form the first conductive blind hole 1300, and form the second line 1400 on the surface of the first dielectric layer 1200 that is conductively connected to the first conductive blind hole 1300 to obtain the isolated power chip package structure.

[0082] Specifically, such as Figure 9As shown, after drilling a hole in the first dielectric layer 1200 to form a first blind via, the first blind via needs to be filled by electroplating to form a first conductive blind via 1300. The first conductive blind via 1300 is electrically connected to the first circuit 110, the transmitting chip 1000, and the receiving chip 1100. Simultaneously, during the electroplating process, a second circuit 1400 is formed on the surface of the first dielectric layer 1200, conductively connected to the first conductive blind via 1300. This allows the second circuit 1400 to be conductively connected to the first circuit 110, the transmitting chip 1000, and the receiving chip 1100 through the first conductive blind via 1300, ultimately forming a... Figure 9 The isolated power supply chip package structure is shown.

[0083] Traditional methods for manufacturing isolated power supplies typically involve placing the transformer inside a substrate, then mounting the transmitter and receiver chips onto the substrate surface, followed by chip packaging and overmolding (secondary injection molding / overmolding). The chip is then placed on a lead frame and molded again to achieve a finished isolated power supply chip in an SOP (Small Outline Package) form. This traditional method requires two molding processes, resulting in a complex workflow, low product integration, and a large product thickness and size, which cannot meet the trend towards thinner and lighter electronic products. However, the isolated power supply chip packaging structure method described in this application embeds the transformer coil, transmitter chip 1000, and receiver chip 1100 together within the packaging structure, thereby reducing the product thickness and size, achieving high product integration, and requiring only one molding step, simplifying packaging and promoting the development of thinner and lighter electronic products.

[0084] Furthermore, such as Figure 2 and Figure 3 As shown, step S100 above, preparing the substrate 100, specifically includes the following five sub-steps:

[0085] Step S110: Prepare a support plate 400; the support plate 400 is provided with a through post 410 that penetrates the support plate 400, and a third line 420 is provided on the upper and lower surfaces of the support plate 400, and the third line 420 is electrically connected to the through post 410.

[0086] Step S120: A third coil 500 and a fourth coil 600 are respectively set on the upper and lower surfaces of the support plate 400;

[0087] Step S130: Press the second dielectric layer 700 onto the upper and lower surfaces of the carrier plate 400 respectively; the second dielectric layer 700 covers the third circuit 420, the third coil 500 and the fourth coil 600;

[0088] Step S140: A second conductive blind via 710 is provided in the second dielectric layer 700 to be conductively connected to the third line 420;

[0089] Step S150: A first line 110 is provided on the surface of the second dielectric layer 700 and is electrically connected to the second conductive blind via 710.

[0090] Specifically, such as Figure 1 As shown, a plurality of conductive posts 410 are provided inside the support plate 400. Third circuits 420 are provided on both the upper and lower surfaces of the support plate 400, and the third circuits 420 on the upper and lower surfaces of the support plate 400 are electrically connected through the conductive posts 410. Simultaneously, a third coil 500 and a fourth coil 600 are respectively provided on the upper and lower surfaces of the support plate 400. Then, a second dielectric layer 700 is pressed onto the upper and lower surfaces of the support plate 400, covering the third circuits 420, the third coils 500, and the fourth coils 600. Next, a second conductive blind hole 710, electrically connected to the third circuits 420, is provided within the second dielectric layer 700, enabling the conductive connection between the first circuit 110 and the third circuits 420. Finally, a first circuit 110, electrically connected to the second conductive blind hole 710, is provided on the surface of the second dielectric layer 700. It should be noted that the first coil 200 and the third coil 500 can both be the primary winding of the transformer, and the second coil 300 and the fourth coil 600 can both be the secondary winding of the transformer; alternatively, the first coil 200 and the second coil 300 can both be the primary winding of the transformer, and the third coil 500 and the fourth coil 600 can both be the secondary winding of the transformer. When the first coil 200, the second coil 300, the third coil 500, and the fourth coil 600 form a multilayer inductor, the schematic diagram is as follows. Figure 11 As shown; when the first coil 200, the second coil 300, the third coil 500, and the fourth coil 600 form a parallel multi-inductor series connection, the schematic diagram is as follows. Figure 12 As shown. It should be noted that the substrate 100 can be made as follows: Figure 3 The structure shown can also be adopted as follows: Figure 2 The structure of the bearing plate 400 shown is as follows: Figure 3 The structure of the substrate 100 shown is as follows: Figure 2 The structure shown is the result of adding layers to the carrier plate 400. Furthermore, the substrate 100 can also be... Figure 3 The structure is obtained by adding layers based on the structure of the substrate 100 shown.

[0091] Furthermore, in some embodiments of this application, after preparing the substrate 100, it is necessary to create cavities in the substrate 100 to form several cavity structures 800. Specifically, this can be achieved by drilling holes in the substrate 100 to form cavity structures 800 penetrating the second dielectric layer 700 and the carrier plate 400; or by setting sacrificial copper pillars within the second dielectric layer 700 and the carrier plate 400, and etching the sacrificial copper pillars to obtain cavity structures 800 penetrating the second dielectric layer 700 and the carrier plate 400. In other words, cavities can be created in the substrate 100 by CNC cutting or laser cutting to form cavity structures 800, or sacrificial copper pillars can be pre-set within the carrier plate 400 and the second dielectric layer 700 to obtain cavity structures 800.

[0092] Furthermore, such as Figure 5 As shown, step S400 above, which involves placing a transmitter chip 1000 in one cavity structure 800 and a receiver chip 1100 in another cavity structure 800, includes the following two sub-steps:

[0093] Step S410: Apply adhesive 900 to the surface of substrate 100;

[0094] Step S420: Place the transmitter chip 1000 and receiver chip 1100 in their respective cavity structures 800 and fix them in place using the adhesive 900.

[0095] Specifically, the adhesive component 900 can be a tack tape or other adhesive device to fix the transmitter chip 1000 and receiver chip 1100 inside the cavity structure 800, so as to facilitate the subsequent encapsulation of the transmitter chip 1000 and receiver chip 1100.

[0096] Furthermore, in some embodiments of this application, the above-described step S500: encapsulating the transmitter chip 1000 and receiver chip 1100 through the first dielectric layer 1200, includes the following two sub-steps:

[0097] Step S510: Press the first dielectric material from the side of the substrate 100 away from the adhesive 900, so that the first dielectric material covers the side of the substrate 100 away from the adhesive 900 and fills the cavity structure 800.

[0098] Step S520: Remove the adhesive 900 and press the second dielectric material onto the side of the substrate 100 near the adhesive 900, so that the second dielectric material covers the side of the substrate 100 near the adhesive 900; the first dielectric material and the second dielectric material constitute the first dielectric layer 1200.

[0099] Specifically, such as Figure 7As shown, assuming the adhesive 900 is disposed on the upper surface of the substrate 100, the transmitter chip 1000 and receiver chip 1100 are placed from below, and a first dielectric material is pressed onto the lower surface, covering the lower surface of the substrate 100 and filling the cavity structure 800. Then, the adhesive 900 is removed, and a second dielectric material is pressed onto the upper surface of the substrate 100, covering the upper surface of the substrate 100. Alternatively, assuming the adhesive 900 is disposed on the lower surface of the substrate 100, the transmitter chip 1000 and receiver chip 1100 are placed from above, and a first dielectric material is pressed onto the upper surface, covering the upper surface of the substrate 100 and filling the cavity structure 800. Then, the adhesive 900 is removed, and a second dielectric material is pressed onto the lower surface of the substrate 100, covering the upper surface of the substrate 100. The first and second dielectric materials use the same insulating material, such as ABF or PID material.

[0100] like Figure 9 As shown, in this example, both the transmitting chip 1000 and the receiving chip 1100 are provided with connection terminals 1110. The first conductive blind via 1300 is conductively connected to the first line 110, the second line 1400, the connection terminals 1110 of the transmitting chip 1000, and the connection terminals 1110 of the receiving chip 1000, respectively. The second line 1400 is conductively connected to the first line 110, the transmitting chip 1000, and the receiving chip 1100 through the first conductive blind via 1300.

[0101] Furthermore, such as Figure 10 As shown, in some embodiments of this application, after step S700, the following three steps are further included:

[0102] A solder resist layer 1500 is disposed on the surface of the first dielectric layer 1200; the solder resist layer 1500 covers the second circuit 1400;

[0103] A window is made in the solder mask layer 1500, and a pad 1600 corresponding to the second line 1400 is formed at the window.

[0104] The pad 1600 is surface treated to form a surface treatment layer 1700.

[0105] By providing a solder resist layer 1500 on the surface of the first dielectric layer 1200, the second circuit 1400 can be protected. By opening a window in the solder resist layer 1500 and forming a pad 1600 corresponding to the second circuit 1400 at the opening, the second circuit 1400 can be exposed, making it easier for external devices to make conductive connections with the second circuit 1400 through the pad 1600. At the same time, the pad 1600 is surface treated, such as by nickel plating and gold plating, to form a surface treatment layer 1700, thereby protecting the pad 1600.

[0106] According to the manufacturing method of the isolated power supply chip packaging structure of this application, the transmitter chip 1000 and the receiver chip 1100 are embedded together inside the packaging structure, thereby reducing the thickness and size of the product and achieving high product integration. At the same time, the entire process only requires one molding step, reducing packaging difficulty and promoting the development of thinner and lighter electronic products.

[0107] On the other hand, this application also proposes an isolated power supply chip packaging structure, which is manufactured by the method for manufacturing the isolated power supply chip packaging structure described in the above embodiments; the isolated power supply chip packaging structure includes:

[0108] The substrate 100 has a first line 110 that is electrically connected to each other on its upper and lower surfaces. A first coil 200 and a second coil 300 are respectively provided on the upper and lower surfaces of the substrate 100. The substrate 100 has a plurality of cavity structures 800.

[0109] The transmitter chip 1000 is housed within one of the cavity structures 800;

[0110] The receiver chip 1100 is located inside another cavity structure 800;

[0111] The first dielectric layer 1200 covers the upper and lower surfaces of the substrate 100, and the first dielectric layer 1200 fills the cavity structure 800.

[0112] A first conductive blind via 1300 is disposed within the first dielectric layer 1200 and is conductively connected to the first line 110, the transmitting chip 1000, and the receiving chip 1100.

[0113] The second line 1400 is disposed on the surface of the first dielectric layer 1200 and is electrically connected to the first conductive blind via 1300.

[0114] It should be noted that the isolated power chip packaging structure of this embodiment corresponds to the manufacturing method of the isolated power chip packaging structure of the above-mentioned embodiments, and the content of the manufacturing method of the isolated power chip packaging structure of the above-mentioned embodiments is applicable to this embodiment.

[0115] According to the isolated power supply chip packaging structure of this application, the transmitter chip 1000 and the receiver chip 1100 are embedded together inside the packaging structure, thereby reducing the thickness and size of the product and achieving high product integration. At the same time, the entire process only requires one molding step, reducing packaging difficulty and promoting the development of thinner and lighter electronic products.

[0116] Further, in this example, the substrate 100 includes:

[0117] The support plate 400 has a through post 410 inside it, and a third line 420 is provided on the upper and lower surfaces of the support plate 400. The third line 420 is electrically connected to the through post 410. A third coil 500 and a fourth coil 600 are respectively provided on the upper and lower surfaces of the support plate 400.

[0118] The second dielectric layer 700 is disposed on the upper and lower surfaces of the carrier plate 400, and the second dielectric layer 700 covers the third line 420;

[0119] The second conductive blind via 710 is disposed within the second dielectric layer 700 and is conductively connected to the third line 420. The first line 110 is disposed on the surface of the second dielectric layer 700 and is conductively connected to the second conductive blind via 710.

[0120] Specifically, such as Figure 1 As shown, a plurality of conductive posts 410 are provided inside the support plate 400. Third circuits 420 are provided on both the upper and lower surfaces of the support plate 400, and the third circuits 420 on the upper and lower surfaces of the support plate 400 are electrically connected through the conductive posts 410. Simultaneously, a third coil 500 and a fourth coil 600 are respectively provided on the upper and lower surfaces of the support plate 400. Then, a second dielectric layer 700 is pressed onto the upper and lower surfaces of the support plate 400, covering the third circuits 420, the third coils 500, and the fourth coils 600. Next, a second conductive blind hole 710, electrically connected to the third circuits 420, is provided within the second dielectric layer 700, enabling the conductive connection between the first circuit 110 and the third circuits 420. Finally, a first circuit 110, electrically connected to the second conductive blind hole 710, is provided on the surface of the second dielectric layer 700. It should be noted that the first coil 200 and the third coil 500 can both be the primary winding of the transformer, and the second coil 300 and the fourth coil 600 can both be the secondary winding of the transformer; alternatively, the first coil 200 and the second coil 300 can both be the primary winding of the transformer, and the third coil 500 and the fourth coil 600 can both be the secondary winding of the transformer. When the first coil 200, the second coil 300, the third coil 500, and the fourth coil 600 form a multilayer inductor, the schematic diagram is as follows. Figure 11As shown; when the first coil 200, the second coil 300, the third coil 500, and the fourth coil 600 form a parallel multi-inductor series connection, the schematic diagram is as follows. Figure 12 As shown. It should be noted that the substrate 100 can be made as follows: Figure 3 The structure shown can also be adopted as follows: Figure 2 The structure of the bearing plate 400 shown is as follows: Figure 3 The structure of the substrate 100 shown is as follows: Figure 2 The structure shown is the result of adding layers to the carrier plate 400. Furthermore, the substrate 100 can also be... Figure 3 The structure is obtained by adding layers based on the structure of the substrate 100 shown.

[0121] Furthermore, in some embodiments of this application, the isolated power supply chip package structure further includes a solder resist layer 1500, which is disposed on the surface of the first dielectric layer 1200, covers the second line 1400, and has pads 1600 corresponding to the second line 1400. The pads 1600 are provided with a surface treatment layer 1700.

[0122] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for fabricating an isolated power supply chip package structure, characterized in that, Includes the following steps: Prepare a substrate; the upper and lower surfaces of the substrate are provided with first lines that are electrically connected to each other. A first coil and a second coil are respectively disposed on the upper and lower surfaces of the substrate; A cavity is formed in the substrate to create a plurality of cavity structures; A transmitting chip is placed in one of the cavity structures, and a receiving chip is placed in the other cavity structure; The transmitting chip and the receiving chip are encapsulated using a first dielectric layer; The first dielectric layer covers the upper and lower surfaces of the substrate, and the first dielectric layer fills the cavity structure; Drill a hole in the first dielectric layer to form a first blind via that communicates with the first line, the transmitting chip, and the receiving chip; The first blind via is filled by electroplating to form a first conductive blind via, and a second line is formed on the surface of the first dielectric layer that is conductively connected to the first conductive blind via, thereby obtaining an isolated power chip package structure.

2. The method for fabricating the isolated power supply chip packaging structure according to claim 1, characterized in that, The preparation of the substrate includes: Prepare a support plate; the support plate has a through post inside, and a third line is provided on the upper and lower surfaces of the support plate, the third line being electrically connected to the through post; A third coil and a fourth coil are respectively disposed on the upper and lower surfaces of the bearing plate; A second dielectric layer is pressed onto the upper and lower surfaces of the carrier plate, respectively; the second dielectric layer covers the third circuit, the third coil, and the fourth coil; A second conductive blind via is provided within the second dielectric layer and is conductively connected to the third circuit. The first line is formed on the surface of the second dielectric layer and is electrically connected to the second conductive blind hole.

3. The method for fabricating the isolated power supply chip packaging structure according to claim 2, characterized in that, The step of creating cavities in the substrate to form a plurality of cavity structures includes: Drilling is performed on the substrate to form the cavity structure that penetrates the second dielectric layer and the carrier plate; Alternatively, sacrificial copper pillars can be provided within the second dielectric layer and the carrier plate, and the sacrificial copper pillars can be etched to obtain the cavity structure that penetrates the second dielectric layer and the carrier plate.

4. The method for fabricating the isolated power supply chip packaging structure according to claim 1, characterized in that, The step of placing a transmitting chip in one of the cavity structures and a receiving chip in the other cavity structure includes: An adhesive is provided on the surface of the substrate; The transmitting chip and the receiving chip are placed in their respective cavity structures and fixed by the adhesive.

5. The method for fabricating the isolated power supply chip packaging structure according to claim 4, characterized in that, The process of encapsulating the transmitter chip and the receiver chip through a first dielectric layer includes: A first dielectric material is pressed onto the side of the substrate away from the adhesive, such that the first dielectric material covers the side of the substrate away from the adhesive and fills the cavity structure; Remove the adhesive and press a second dielectric material onto the side of the substrate near the adhesive, so that the second dielectric material covers the side of the substrate near the adhesive; the first dielectric material and the second dielectric material constitute the first dielectric layer.

6. The method for fabricating the isolated power supply chip packaging structure according to claim 5, characterized in that, Both the transmitting chip and the receiving chip are provided with connection terminals, and the first conductive blind hole is conductively connected to the first line, the second line, the connection terminal of the transmitting chip, and the connection terminal of the receiving chip, respectively.

7. The method for fabricating the isolated power supply chip packaging structure according to claim 1, characterized in that, After performing a fill plating process on the first blind via to form a first conductive blind via, and forming a second line conductively connected to the first conductive blind via on the surface of the first dielectric layer to obtain the isolated power supply chip package structure, the process further includes: A solder resist layer is disposed on the surface of the first dielectric layer; the solder resist layer covers the second circuit. The solder mask layer is made into a window, and a pad corresponding to the second circuit is formed at the window. The pads are surface treated to form a surface treatment layer.

8. An isolated power supply chip packaging structure, characterized in that, The isolated power chip package structure is manufactured using the method described in any one of claims 1-7; the isolated power chip package structure includes: The substrate has a first line electrically connected to each other on its upper and lower surfaces, a first coil and a second coil respectively on its upper and lower surfaces, and a plurality of cavity structures. The transmitting chip is disposed within one of the cavity structures; The receiving chip is disposed within another of the aforementioned cavity structures; A first dielectric layer covers the upper and lower surfaces of the substrate, and the first dielectric layer fills the cavity structure; A first conductive blind via is disposed within the first dielectric layer and is conductively connected to the first line, the transmitting chip, and the receiving chip; The second line is disposed on the surface of the first dielectric layer and is electrically connected to the first conductive blind via.

9. The isolated power supply chip packaging structure according to claim 8, characterized in that, The substrate includes: A support plate, wherein a conductive post is provided inside the support plate, a third line is provided on the upper and lower surfaces of the support plate, the third line is electrically connected to the conductive post, and a third coil and a fourth coil are respectively provided on the upper and lower surfaces of the support plate. A second dielectric layer is disposed on the upper and lower surfaces of the carrier plate, and the second dielectric layer covers the third circuit. The second conductive blind via is disposed within the second dielectric layer and is conductively connected to the third circuit. The first circuit is disposed on the surface of the second dielectric layer and is conductively connected to the second conductive blind via.

10. The isolated power supply chip packaging structure according to claim 8, characterized in that, The isolated power chip package structure further includes a solder resist layer, which is disposed on the surface of the first dielectric layer, covers the second circuit, and has pads corresponding to the second circuit. The pads are provided with a surface treatment layer.

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