Multi-substrate laminated packaging structure and packaging method

Abstract

The invention belongs to the field of packaging structures, and particularly relates to a multi-substrate laminated packaging structure and a packaging method. The structure comprises a main packaging substrate, N sub packaging substrates, N groups of metal supporting pieces and a plastic packaging protection part, the N sub-packaging substrates are sequentially arranged on the upper side of the main packaging substrate from bottom to top; a gap is formed between the main packaging substrate and the adjacent sub packaging substrate, and a gap is formed between every two adjacent sub packaging substrates; the N groups of metal supporting pieces are respectively arranged in the N intervals; the bare chip is electrically connected to the upper surface of the main packaging substrate; the chip device is electrically connected to one side or two sides of the N sub-packaging substrates; the passive electronic component is electrically connected to the main packaging substrate and one side or two sides of the N sub packaging substrates; and the plastic package protection component is arranged on the upper surface of the main package substrate and wraps all the bare chips, the sub-package substrates, the metal supporting pieces, the chip devices and the passive electronic components on the upper side of the main package substrate. The size of the packaging structure can be reduced.

Description

Technical Field

[0001] This invention relates to a packaging structure, specifically to a multi-substrate stacked packaging structure and packaging method. Background Technology

[0002] As electronic products trend towards miniaturization and high density, three-dimensional packaging, which integrates multiple chips and devices into a single package, has become a new direction to meet technological advancements. Among these, stacked packaging has broad application prospects due to its high integration, small package size, and low manufacturing cost.

[0003] Currently, the main packaging stacking technologies in the industry include component stacking and wafer TSV (through silicon via) stacking. Component stacking generally refers to PiP (Package in Package) technology and PoP (Package on Package) technology, which involves stacking two or more packaged finished products and finally encapsulating them with epoxy resin, leaving external signal interfaces. TSV technology, on the other hand, involves creating vertical vias between different wafers for signal connection, thus achieving stacking.

[0004] Existing PiP and PoP packaging technologies require multiple molding processes, resulting in a cumbersome workflow. Furthermore, the size reduction of products manufactured using PiP and PoP packaging technologies is limited. The technological challenge of TSV technology lies in the interconnect vias between wafers. The processing of these vias is complex, costly, and the technology is not yet mature. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems of existing packaging technologies, such as cumbersome process flow, limited size reduction, or complex process and high cost, and to provide a multi-substrate stacked packaging structure and packaging method.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A multi-substrate stacked packaging structure is used for packaging chip devices, passive electronic components, and bare chips; the passive electronic components include inductors, capacitors, and resistors.

[0008] Its special feature is:

[0009] Includes main packaging substrate, sub-packaging substrate, metal support components, and plastic encapsulation protection components;

[0010] There are N sub-package substrates; there are N groups of metal supports, each group has M components; N≥1, M≥4;

[0011] N sub-package substrates are arranged sequentially from bottom to top on the upper side of the main package substrate; a gap is provided between the main package substrate and the adjacent sub-package substrate, and between two adjacent sub-package substrates when N>1.

[0012] The lengths of the N sets of metal supports are adapted to the heights of the N intervals. The N sets of metal supports are respectively set in the N intervals, and the M metal supports in the same set are located in different positions. The metal supports are used to support the sub-package substrate above them, and at the same time to realize the electrical connection between the main package substrate and the sub-package substrate, or to realize the electrical connection between the main package substrate and the sub-package substrate, or between adjacent sub-package substrates.

[0013] There are one or more bare chips, electrically connected to the upper surface of the main packaging substrate; there are multiple chip devices, each electrically connected to one or both sides of N sub-packaging substrates; there are multiple passive electronic components, each electrically connected to one or both sides of the main packaging substrate and the N sub-packaging substrates.

[0014] The plastic encapsulation protection component is located on the upper surface of the main packaging substrate and covers all bare chips, sub-package substrates, metal supports, chip devices and passive electronic components located on the upper side of the main packaging substrate.

[0015] Furthermore, the dimensions of each of the N sub-package substrates are smaller than the dimensions of the main package substrate, and the dimensions of the N sub-package substrates decrease sequentially from bottom to top.

[0016] Furthermore, multiple electrical pads are provided on the upper and lower surfaces of the main packaging substrate and the N sub-packaging substrates;

[0017] The bare chip is connected to a preset bonding position on one side of the main packaging substrate by bonding wire; the passive electronic components are soldered to the lower surface of the main packaging substrate by electrical pads, and the chip devices and passive electronic components are soldered to the sub-packaging substrate by corresponding electrical pads.

[0018] Solder balls are soldered to the other side of the main packaging substrate via electrical pads;

[0019] The two ends of the N sets of metal support members are respectively welded to the main packaging substrate and the adjacent sub-packaging substrate through corresponding electrical pads, and between two adjacent sub-packaging substrates when N>1.

[0020] Furthermore, the metal support components are made of highly conductive materials, including gold and copper;

[0021] The metal support is a solid or hollow cylinder or polygonal prism.

[0022] Furthermore, the safe distance between the outer periphery of the end of the metal support and the corresponding bare chip, chip device or passive electronic component is greater than 0.5 mm.

[0023] Furthermore, the main packaging substrate and N sub-packaging substrates are arranged in parallel to each other, and when N>1, the spacing between the main packaging substrate and the adjacent sub-packaging substrate, as well as between two adjacent sub-packaging substrates, is equal.

[0024] The length of the metal support is greater than the maximum height of the bare chip, chip device or passive electronic component within the corresponding interval, so that the bare chip, chip device and passive electronic component do not interfere with the main packaging substrate or sub-packaging substrate in the length direction of the metal support.

[0025] Furthermore, the material of the plastic-encapsulated protective component is epoxy resin.

[0026] Furthermore, the main packaging substrate is a rigid packaging substrate, a flexible packaging substrate, or a ceramic substrate, and the sub-packaging substrate is a rigid packaging substrate, a flexible packaging substrate, a ceramic substrate, or a conventional printed circuit board.

[0027] Meanwhile, the present invention also provides a multi-substrate stacked packaging method for realizing the aforementioned multi-substrate stacked packaging structure, which is characterized by including the following steps:

[0028] Step 1: Connect the selected passive electronic components to the lower surface of the main packaging substrate;

[0029] Step 2: Connect bare chips, passive electronic components and / or chip devices to the upper surface of the main packaging substrate;

[0030] Step 3: Define N sub-package substrates from bottom to top as the 1st sub-package substrate, the 2nd sub-package substrate, ..., the Nth sub-package substrate; and define N sets of metal supports as the 1st metal support set, the 2nd metal support set, ..., the Nth metal support set.

[0031] The Nth part of the chip device and / or passive electronic components are electrically connected to the upper surface, lower surface, or both surfaces of the Nth sub-package substrate, and the upper end of the Nth group of metal supports is electrically connected to the lower surface of the Nth sub-package substrate; and so on, the first part of the chip device and / or passive electronic components are electrically connected to the upper surface, lower surface, or both surfaces of the first sub-package substrate, and the upper end of the first group of metal supports is electrically connected to the lower surface of the first sub-package substrate.

[0032] Step 4: Electrically connect the lower end of the Nth group of metal supports to the upper surface of the (N-1)th sub-package substrate, and so on, electrically connect the lower end of the 1st group of metal supports to the upper surface of the main package substrate.

[0033] Step 5: After melting the molding compound, wrap it around the upper surface of the main packaging substrate, as well as all bare chips, sub-packaging substrates, metal supports, chip devices, and passive electronic components located on the upper side of the main packaging substrate, to form a molding compound and complete the packaging.

[0034] Furthermore, it also includes: Step 6, soldering solder balls onto electrical pads on the lower surface of the main packaging substrate.

[0035] The beneficial effects of this invention are:

[0036] 1. This invention uses stacked packaging substrates (main packaging substrate and sub-packaging substrate) to replace the stacking of finished package components, and uses metal support components to replace the interconnect vias between TSV wafers, which simplifies the process; at the same time, by stacking multiple packaging substrates vertically, compared with the horizontal layout of a single packaging substrate, the size of the entire packaging structure is greatly reduced.

[0037] 2. The various sub-package substrates of this invention are welded together using metal support members. After the sub-package substrates are supported by the corresponding metal support members, the sub-package substrates can be used for double-sided component placement, thereby effectively reducing the package size and improving the package efficiency.

[0038] 3. The components on each sub-package substrate and the metal support components between the package substrates of this invention can be automatically mounted using surface mount technology, which is highly efficient and low in cost. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of an embodiment of a multi-substrate stacked packaging structure of the present invention (electrical pads are not shown in the figure).

[0040] In the picture:

[0041] 01-Chip devices, 02-Passive electronic components, 03-Bare chips;

[0042] 1-Main packaging substrate, 2-Sub-packaging substrate, 3-Metal support component, 4-Plastic encapsulation protection component, 5-Bonding wire, 6-Solder ball. Detailed Implementation

[0043] To make the objectives, advantages, and features of the present invention clearer, the following detailed description of a multi-substrate stacked packaging structure and packaging method proposed by the present invention, in conjunction with the accompanying drawings and specific embodiments, will further clarify these points. The advantages and features of the present invention will become clearer from the following specific embodiments.

[0044] It should be noted that in this embodiment, "upper" and "lower" are both relative to the context. Figure 1 The orientation of the paper in the image is for reference.

[0045] This embodiment presents a multi-substrate stacked packaging structure, mainly used for packaging devices such as chip device 01, passive electronic components 02, and bare chip 03. It should be noted that the aforementioned passive electronic components 02 generally refer to devices such as inductors, capacitors, and resistors.

[0046] See Figure 1 This embodiment describes a multi-substrate stacked packaging structure, which mainly includes a main packaging substrate 1, a sub-packaging substrate 2, a metal support 3, and a plastic encapsulation protection component 4.

[0047] Specifically, the main packaging substrate 1 is a rigid packaging substrate, a flexible packaging substrate, or a ceramic substrate. The sub-packaging substrate 2 can be a rigid packaging substrate, a flexible packaging substrate, or a ceramic substrate, or it can be a low-cost ordinary printed circuit board. The number of sub-packaging substrates 2 is N, and the number of metal supports 3 is N groups, with M components in each group; N≥1, M≥4; in this embodiment, the number of sub-packaging substrates 2 and the number of metal supports 3 in two groups, with 4 components in each group, are used as an example. In other embodiments of the present invention, the specific number of metal supports 4 can be set according to the number of signals, with one metal support 4 corresponding to one signal.

[0048] Two sub-package substrates 2 are disposed above the main package substrate 1. The main package substrate 1 and the two sub-package substrates 2 are arranged parallel to each other, and the spacing between the main package substrate 1 and its adjacent sub-package substrate 2, as well as between two adjacent sub-package substrates 2, is equal. Of course, the equal spacing here is only for ease of manufacturing and installation; in other embodiments of the present invention, the spacing may be unequal. Spacing is provided between the main package substrate 1 and its adjacent sub-package substrate 2, as well as between two adjacent sub-package substrates 2. The size of both sub-package substrates 2 is smaller than the size of the main package substrate 1, and the sub-package substrate 2 stacked on top is smaller than the sub-package substrate 2 stacked on top.

[0049] In this embodiment, the metal support 3 is a hollow cylinder made of copper. In other embodiments of the present invention, it can also be made of highly conductive materials such as gold. Alternatively, the metal support 3 can be made into a solid structure, or a polygonal prism structure can be used to replace the cylindrical structure.

[0050] The lengths of the two sets of metal support members 3 are adapted to the heights of the two intervals. The two sets of metal support members 3 are respectively set in the two intervals. The upper surface of the main packaging substrate 1 and the upper and lower surfaces of the sub-packaging substrate 2 are each provided with four electrical pads adapted to the metal support members 3. The two ends of the four metal support members 3 in the first set are respectively welded to the four electrical pads on the upper surface of the main packaging substrate 1 and the four electrical pads on the lower surface of the lower sub-packaging substrate 2. The two ends of the four metal support members 3 in the second set are respectively welded to the four electrical pads on the lower surface of the upper sub-packaging substrate 2 and the four electrical pads on the upper surface of the lower sub-packaging substrate 2. The four metal support members 3 in the two sets are located in different positions. The metal support members 3 do not touch each other or other components. Thus, the metal support members 3 realize the electrical connection between the main packaging substrate 1 and the sub-packaging substrate 2, and between adjacent sub-packaging substrates 2, while also stably supporting the sub-packaging substrate 2, making the entire packaging structure more stable.

[0051] In this embodiment, the example uses one bare chip 03, three chip devices 01, and five passive electronic components 02. In other embodiments of the present invention, the quantities of bare chip 03, chip devices 01, and passive electronic components 02 need to be set according to specific requirements.

[0052] An electrical pad for soldering bare chip 03 is provided at the center of the upper surface of the main packaging substrate 1. The bare chip 03 is glued to the set position and then soldered to the corresponding bonding position on the upper surface of the main packaging substrate 1 by bonding wire 5 to achieve electrical connection between the two.

[0053] Two electrical pads for soldering passive electronic components 02 are provided in the middle of the lower surface of the main packaging substrate 1. The two passive electronic components 02 are soldered onto these two electrical pads respectively. At the same time, several electrical pads for soldering solder balls 6 are provided in the remaining area of ​​the lower surface of the main packaging substrate 1. Solder balls 6 are soldered onto these electrical pads, and electrical connection with external circuits can be achieved through the solder balls 6.

[0054] Two electrical pads are provided on the upper surface of the lower sub-package substrate 2 for soldering chip device 01 and passive electronic component 02, respectively; a third passive electronic component and one of the chip devices 01 are soldered onto these two electrical pads to achieve electrical connection.

[0055] An electrical pad for soldering chip device 01 is provided on the lower surface of the upper sub-package substrate 2, and the second chip device 01 is soldered on the electrical pad.

[0056] Three electrical pads are provided on the upper surface of the upper sub-package substrate 2 for soldering chip device 01 and passive electronic component 02 respectively; the third chip device 01 is soldered on the electrical pad located in the middle, and the fourth and fifth passive electronic components are soldered on the two electrical pads located on the two sides respectively.

[0057] A safety distance of at least 0.5 mm is provided between the outer periphery of the ends of the metal support 3 connected to the surfaces of the bare chip 03, the chip device 01, and the passive electronic component 02.

[0058] The length of the metal support 3 must be greater than the maximum height of the bare chip 03, chip device 01 or passive electronic component 02 in the corresponding interval, to ensure that there is no interference between the bare chip 03, chip device 01 and passive electronic component 02 in the length direction of the metal support 3.

[0059] In this embodiment, the material used for the molding and protective component 4 is epoxy resin. After the epoxy resin melts, it forms the molding and protective component 4, which wraps around one side of the main packaging substrate 1. At the same time, it effectively protects the bare chip 03, as well as all the sub-packaging substrates 2, metal support members 3, chip devices 01, and passive electronic components 02.

[0060] The following steps are used in the specific packaging process:

[0061] (1) Provide a main packaging substrate 1 and solder the chip device 01 onto the corresponding electrical pads on the lower surface of the main packaging substrate 1.

[0062] (2) The bare chip 03 is first attached to the corresponding position on the upper surface of the main packaging substrate 1 with glue, and then the bonding wire 5 is used to attach it to the corresponding bonding position on the upper surface of the main packaging substrate 1 to realize the electrical connection between the bare chip 03 and the main packaging substrate 1.

[0063] (3) Provide an upper sub-package substrate 2, and solder passive electronic components 02, etc., onto corresponding electrical pads on the upper surface of the upper sub-package substrate 2 using solder. Chip devices 01 are soldered onto corresponding electrical pads on the upper surface of the upper sub-package substrate 2.

[0064] (4) One end of the metal pillar support is soldered to the corresponding electrical pad on the lower surface of the upper sub-package substrate 2 by solder.

[0065] (5) The passive electronic components 02 and the chip devices 01 are soldered onto the corresponding electrical pads on the upper surface of the lower sub-package substrate 2 using solder.

[0066] (6) The metal pillar support is soldered to the corresponding electrical pad on the lower surface of the lower sub-package substrate 2 by soldering one end.

[0067] (7) First, the upper sub-package substrate 2 with the metal pillar support has been welded as a component. Then, the other end of the metal pillar support is welded to the corresponding electrical pad on the upper surface of the lower sub-package substrate 2. The metal pillar support must not touch the electronic components.

[0068] (8) Then the lower sub-package substrate 2 that has been stacked is treated as a component and soldered to the corresponding electrical pad on the upper surface of the main package substrate 1 through the other end of the metal pillar support. The metal pillar support must not touch the electronic components.

[0069] (9) After the epoxy resin melts, it encapsulates all the stacked sub-package substrates 2, electronic components (except for the components on the lower surface of the main package substrate 1) and the upper surface of the main package substrate 1 to form a plastic-encapsulated protective component 4.

[0070] (10) Finally, the solder ball 6 is electrically connected to the electrical pad on the lower surface of the main packaging substrate 1 by soldering.

Claims

1. A multi-substrate stacked packaging structure for packaging a chip device (01), passive electronic components (02), and a bare chip (03); wherein the passive electronic components (02) include inductors, capacitors, and resistors; Its features are: It includes a main packaging substrate (1), a sub-packaging substrate (2), a metal support (3), and a plastic encapsulation protection component (4); The number of sub-package substrates (2) is N; the number of metal support members (3) is N groups, with M members in each group; N≥1, M≥4; N sub-package substrates (2) are arranged sequentially from top to bottom on the upper side of the main package substrate (1); there is a gap between the main package substrate (1) and the adjacent sub-package substrates (2), and between two adjacent sub-package substrates (2) when N>1. The lengths of the N sets of metal support members (3) are respectively adapted to the heights of the N intervals; the N sets of metal support members (3) are respectively arranged in the N intervals, and the metal support members (3) are used to support the sub-package substrate (2) above them, and at the same time to realize the electrical connection between the main package substrate (1) and the sub-package substrate (2), or to realize the electrical connection between the main package substrate (1) and the sub-package substrate (2), and between adjacent sub-package substrates (2); The bare chip (03) is one or more, electrically connected to the upper surface of the main packaging substrate (1); the chip device (01) is multiple, electrically connected to the upper surface, lower surface or upper and lower surface of N sub-packaging substrates (2); the passive electronic component (02) is multiple, electrically connected to the lower surface of the main packaging substrate (1), and the upper surface, lower surface or upper and lower surface of N sub-packaging substrates (2); The plastic encapsulation protection component (4) is disposed on the upper surface of the main packaging substrate (1) and covers all bare chips (03), sub-packaging substrates (2), metal support components (3), chip devices (01) and passive electronic components (02) on the upper side of the main packaging substrate (1).

2. The multi-substrate stacked packaging structure according to claim 1, characterized in that: The dimensions of each of the N sub-package substrates (2) are smaller than the dimensions of the main package substrate (1), and the dimensions of the N sub-package substrates (2) decrease sequentially from bottom to top.

3. A multi-substrate stacked packaging structure according to claim 1 or 2, characterized in that: The main packaging substrate (1) and the N sub-packaging substrates (2) are provided with multiple electrical pads on their upper and lower surfaces; The bare chip (03) is connected to a preset bonding position on the upper surface of the main packaging substrate (1) by a bonding wire (5); the passive electronic component (02) is soldered to the lower surface of the main packaging substrate (1) by a corresponding electrical pad; the chip device (01) and the passive electronic component (02) are soldered to the sub-packaging substrate (2) by a corresponding electrical pad. The lower surface of the main packaging substrate (1) is soldered with solder balls (6) through corresponding electrical pads. The solder balls (6) are used to make electrical connections with external circuits. The two ends of the metal support members (3) in the N groups are respectively welded to the main packaging substrate (1) and the adjacent sub-packaging substrate (2) through corresponding electrical pads, and between two adjacent sub-packaging substrates (2) when N>1.

4. The multi-substrate stacked packaging structure according to claim 1, characterized in that: The metal support (3) is made of a highly conductive material, including gold and copper; The metal support (3) is a solid or hollow cylinder or polygonal prism.

5. A multi-substrate stacked packaging structure according to claim 1 or 4, characterized in that: The safe distance between the outer periphery of the end of the metal support (3) and the corresponding bare chip (03), chip device (01) or passive electronic component (02) is greater than 0.5 mm.

6. The multi-substrate stacked packaging structure according to claim 5, characterized in that: The main packaging substrate (1) and N sub-packaging substrates (2) are arranged parallel to each other; The length of the metal support (3) is greater than the maximum height of the bare chip (03), chip device (01) and passive electronic component (02) within the corresponding interval, so that the bare chip (03), chip device (01) and passive electronic component (02) do not interfere with the main packaging substrate (1) or sub-packaging substrate (2) in the length direction of the metal support (3).

7. The multi-substrate stacked packaging structure according to claim 1, characterized in that: The material of the encapsulated protective component (4) is epoxy resin.

8. A multi-substrate stacked packaging structure according to claim 1 or 7, characterized in that: The main packaging substrate (1) is a rigid packaging substrate, a flexible packaging substrate, or a ceramic substrate, and the sub-packaging substrate (2) is a rigid packaging substrate, a flexible packaging substrate, a ceramic substrate, or a common printed circuit board.

9. A multi-substrate stacked packaging method for implementing the multi-substrate stacked packaging structure according to any one of claims 1-8, characterized in that, Includes the following steps: Step 1: Connect the set passive electronic components (02) to the lower surface of the main packaging substrate (1); Step 2: Connect bare chips (03), passive electronic components (02) and / or chip devices (01) to the upper surface of the main packaging substrate (1); Step 3: Define N sub-package substrates (2) from bottom to top as the 1st sub-package substrate, the 2nd sub-package substrate, ..., the Nth sub-package substrate; N sets of metal supports (3) are the 1st metal support, the 2nd metal support, ..., the Nth metal support; The Nth part of the chip device (01) and / or passive electronic components (02) are electrically connected to the upper surface, lower surface or upper and lower surfaces of the Nth sub-package substrate, and the upper end of the Nth group of metal supports is electrically connected to the lower surface of the Nth sub-package substrate; and so on, the first part of the chip device (01) and / or passive electronic components (02) are electrically connected to the upper surface, lower surface or upper and lower surfaces of the first sub-package substrate, and the upper end of the first group of metal supports is electrically connected to the lower surface of the first sub-package substrate; Step 4: Electrically connect the lower end of the Nth group of metal supports to the upper surface of the N-1th sub-package substrate, and so on, electrically connect the lower end of the 1st group of metal supports to the upper surface of the main package substrate (1). Step 5: After melting the plastic encapsulation protective material, wrap it around the upper surface of the main packaging substrate (1), as well as all bare chips (03), sub-packaging substrates (2), metal support (3), chip devices (01) and passive electronic components (02) located on the upper side of the main packaging substrate (1), to form a plastic encapsulation protective component (4) and complete the encapsulation.

10. A multi-substrate stacked packaging method according to claim 9, characterized in that, Also includes: Step 6: Solder the solder ball (6) onto the electrical pad on the lower surface of the main packaging substrate (1).

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