Flexible interconnection and mode smooth switching method of distributed power generation system

Abstract

The application discloses a flexible interconnection and mode smooth switching method of a distributed power generation system, and relates to the technical field of distributed power generation. The method comprises the following steps: continuously collecting direct-current voltage and current of source-side rectifiers of each power generation unit, and establishing droop control relationship; in a normal mode, collecting back-to-back rectifier output current and intermediate capacitor voltage, using phase-locked control to keep the current and load current in phase, and combining with a dq coordinate model to realize voltage regulation; when detecting source-side rectifier failure, generating an alternating-current current reference value based on intermediate capacitor voltage deviation, inputting the alternating-current current reference value into a single current loop controller for voltage stabilization, introducing phase advance, adaptive gain and anti-integral saturation mechanism, and guaranteeing fast response and stable operation; in a mode switching process, weighting and fusing normal and fault control quantities, and realizing dynamic consistency through pole matching and reference pre-alignment; and the method can significantly reduce intermediate capacitor voltage fluctuation, shorten recovery time, and improve system stability and reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of distributed power generation, in particular to a flexible interconnection and mode smooth switching method of a distributed power generation system. BACKGROUND

[0002] At present, the energy structure transformation and the new power system construction with new energy as the main body improve the power grid's acceptance requirements for renewable energy, and the distributed power generation system has become the main power supply of the direct current power grid. However, the regulation means of the traditional distribution network is very limited in action speed and control accuracy, and cannot effectively achieve the above goals, therefore, using new power electronic devices to realize active, flexible and fault-tolerant regulation of the direct current power grid has become the focus of attention of scholars and researchers.

[0003] A typical direct current microgrid is composed of multiple distributed generators and source side rectifiers, the direct current bus and the output current of the rectifier of each distributed generator present droop characteristics, the output direct current and the direct current voltage reference value of the source side rectifier of each generator are obtained to get the reference value of the output direct current voltage, and the power distribution between the distributed generators is realized. With the gradual promotion of the position of the distributed power generation system in the direct current power grid, the power supply fault tolerance of the distributed power generation system has become the current research focus, and the control of the flexible interconnection system of the distributed power generation based on the back-to-back converter has become the focus of attention. Under normal conditions, the back-to-back converter is responsible for the energy flow between the two power generation units to realize flexible power flow and prevent engine surge caused by excessive output of the generator. When the source side rectifier of one of the power generation units fails, the back-to-back converter is responsible for transporting the power of the power generation unit to another power transmission line. However, the switching between the normal phase-locked and fault VI modes of the flexible interconnection device will inevitably cause fluctuations and impact problems of the system, and the existing research on this aspect still has deficiencies, 1) the control strategy of the flexible interconnection device of the distributed power generation from normal switching to fault is insufficient; 2) the fast switching of the mode when the source side rectifier of the flexible interconnection device fails has not been completely solved. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a flexible interconnection and mode smooth switching method of a distributed power generation system, which solves the problem that the control structures of the flexible interconnection device in the existing distributed power generation system are inconsistent between the normal mode and the fault mode, and the intermediate capacitor voltage is difficult to maintain quickly and stably in the switching process.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] The first aspect of the present application provides a flexible interconnection and mode smooth switching method of a distributed power generation system, which comprises: collecting DC voltage and DC current of source side rectifiers of each power generation unit, establishing droop control relationship;

[0008] Based on the droop control relationship, collecting output current of back-to-back rectifiers and intermediate capacitor voltage, performing phase-locked control in normal mode, and performing voltage regulation and current in-phase control according to the intermediate capacitor voltage;

[0009] When detecting source side rectifier failure, collecting deviation of intermediate capacitor voltage and reference voltage, generating AC current reference value and inputting single current loop controller for voltage stabilization regulation, meanwhile, improving dynamic performance through phase advance and adaptive gain mode, and suppressing abnormal fluctuation;

[0010] On the basis of single current loop control result, collecting control signal, generating weight coefficient through low-pass filter, weighting and fusing normal mode control quantity and failure mode control quantity, and realizing mode smooth switching through pole matching and reference pre-alignment.

[0011] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the establishment of the droop control relationship comprises: continuously collecting DC voltage and DC current of source side rectifiers of each power generation unit; determining power sharing ratio based on collected data, and generating droop curve;

[0012] When the voltage deviation is less than the first voltage fluctuation threshold, the droop curve is corrected in a smooth scheduling mode; when the voltage deviation exceeds the second voltage support threshold, the slope of the droop curve is adjusted.

[0013] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the phase-locked control in normal mode comprises: collecting output current of back-to-back rectifiers and intermediate capacitor voltage; comparing the output current with load current, and generating control signal consistent with the phase of the load current through phase-locked loop; generating current reference based on the intermediate capacitor voltage, and inputting to single current loop controller; setting cross-coupling feedforward compensation in the current loop controller to offset the coupling between current components; the current loop controller adopts two-degree-of-freedom structure, and reference instruction channel and feedback channel are separately set; anti-integral saturation processing is set in the integral unit of the current loop to limit integral accumulation when the current approaches threshold.

[0014] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the voltage regulation and adjustment comprises, when the source side rectifier fault is detected, the deviation of the intermediate capacitor voltage and the reference voltage is detected, the deviation is filtered to generate a filtered voltage deviation; the AC current reference value is generated based on the voltage deviation, and the reference pre-alignment is performed at the moment of entering the fault mode, and the reference value is initialized to the continuous state before switching; the AC current reference value is input to the single current loop controller to perform voltage regulation and adjustment.

[0015] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the generation of the AC current reference value comprises introducing a phase lead element in the voltage deviation channel, generating a lead component by combining amplitude limiting differentiation processing and low pass filtering; the lead component and the voltage deviation are superimposed as the reference value input to the single current loop controller.

[0016] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the single current loop controller comprises an adaptive gain scheduling module and an anti-integral saturation module; the adaptive gain scheduling module adjusts the control gain according to the size of the voltage deviation; the anti-integral saturation module freezes the integrator when the current output approaches the preset threshold, and unfreezes the integrator when the output returns to the safe range or the error direction is opposite to the output direction.

[0017] As a preferred scheme of the flexible interconnection and mode smooth switching method of the distributed power generation system, wherein: the smooth switching of the mode comprises weighting and fusing the normal mode control quantity and the fault mode control quantity by using the weight coefficient to obtain the final control quantity; reference pre-alignment is performed on the control quantity to be taken over during the switching process to maintain continuity with the control state before switching; and the weight time constant and the loop parameter are set by pole matching to make the dynamic characteristics of the normal mode and the fault mode consistent, so as to realize smooth transition.

[0018] In a second aspect, the present application provides a flexible interconnection and mode smooth switching system of a distributed power generation system, comprising: a data acquisition module for continuously acquiring the DC voltage and DC current of the source side rectifier of each power generation unit, and acquiring the output current and intermediate capacitor voltage of the back-to-back rectifier;

[0019] A droop control module for establishing a droop control relationship based on the collected data and forming a droop control curve, and implementing smooth scheduling or slope adjustment of the droop control curve according to a preset strategy during operation;

[0020] The phase-locked and reference generation module is configured to perform phase-locked control, generate a current reference according to the intermediate capacitor voltage, and provide a reference instruction to the current loop in the normal mode;

[0021] The reference shaping module is configured to filter the voltage deviation and generate a phase-advanced component in the fault mode, perform reference pre-alignment, and output an alternating current reference value;

[0022] The single-current-loop control module is configured to receive the alternating current reference value and perform single-current-loop voltage regulation, and the module internally implements dq cross-term feedforward compensation and a two-degree-of-freedom control structure.

[0023] The adaptive gain scheduling module, as a submodule of the single-current-loop control module, is configured to adjust the control gain according to the voltage deviation.

[0024] The anti-integral saturation module, as a submodule of the single-current-loop control module, is configured to freeze the integral when the current approaches a preset threshold and unfreeze the integral when a recovery condition is met.

[0025] The weight generation module is configured to collect mode control signals and generate a weight coefficient through low-pass filtering.

[0026] The fusion and output alignment module is configured to fuse the normal mode control quantity and the fault mode control quantity by weighting according to the weight coefficient, and perform pre-alignment of the reference or the output to ensure continuity when switching.

[0027] The parameter tuning and pole matching module is configured to tune the weight time constant and the loop parameter according to the system working condition to realize consistency of mode dynamics.

[0028] The amplitude limiting and safety unification module is configured to implement amplitude limiting, saturation protection, and safety strategy on the reference value and the control output.

[0029] In a third aspect, the present application provides a computer device including a memory and a processor, and the memory stores a computer program, wherein the computer program is executed by the processor to implement any step of the flexible interconnection and mode smooth switching method of the distributed power generation system according to the first aspect of the present application.

[0030] In a fourth aspect, the present application provides a computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement any step of the flexible interconnection and mode smooth switching method of the distributed power generation system according to the first aspect of the present application.

[0031] The application has the beneficial effects that: by introducing a unified single current loop control structure in the flexible interconnection device of the distributed power generation system, the normal mode and the fault mode maintain the same order control mode, avoiding the problem of mismatching between single loop and double loop in the traditional method when switching. The power sharing of the multi-source side rectifier is realized by using the droop control relationship, and in the normal mode, the output current and the load current are kept in phase through phase-locked control, thereby ensuring the stability of the intermediate capacitor voltage. In the fault mode, the AC current reference value is generated based on the voltage deviation, and combined with filtering, phase advance and reference pre-alignment processing, the dynamic response speed and the continuity of the current reference are effectively improved. The adaptive gain scheduling is introduced in the single current loop controller, which makes the operation more smooth in the small deviation condition, and has stronger voltage support capability in the large deviation; at the same time, the anti-integral saturation mechanism is matched, the integrator is frozen when the current approaches the threshold, and the integrator is unfrozen when the condition is met, thereby suppressing overshoot and rebound. In the mode switching process, the low-pass filter is used to generate the weight coefficient, the control quantities of the normal mode and the fault mode are weighted and fused, and the dynamic characteristics consistency is ensured through pole matching, so that the transition process is more stable. The overall scheme can keep the intermediate capacitor voltage stable under complex conditions, reduce the switching impact, and improve the reliability and operation safety of the system. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 The figure is a flexible interconnection device diagram of a distributed power generation system considering distributed power generation.

[0034] Figure 2 The figure is a flexible interconnection device rectifier #2 fault scenario of a distributed power generation system.

[0035] Figure 3 The figure is a rectifier #2 control block diagram of a distributed power generation system.

[0036] Figure 4 The figure is a back-to-back inverter control block diagram of a distributed power generation system.

[0037] Figure 5 The figure is a rectifier #1 control block diagram of a distributed power generation system.

[0038] Figure 6 The figure is a traditional back-to-back rectifier control block diagram of a distributed power generation system.

[0039] Figure 7A classical VSC structure for a distributed generation system.

[0040] Figure 8 A s-domain block diagram in dq coordinate system for an AC side of a distributed generation system

[0041] Figure 9 A control block diagram for a normal operating condition of an optimized back-to-back rectifier of a distributed generation system.

[0042] Figure 10 A control block diagram for a new control strategy of a normal-fault mode for a distributed generation system.

[0043] Figure 11 A time-domain simulation diagram for a 0.1s constant voltage control of a normal-fault mode for a distributed generation system.

[0044] Figure 12 A time-domain simulation diagram for a 0.1s constant voltage control of a normal-fault mode for a distributed generation system.

[0045] Figure 13 A flow chart of a flexible interconnection and mode smooth switching method for a distributed generation system. DETAILED DESCRIPTION

[0046] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] In the following description, a lot of specific details are set forth in order to provide a thorough understanding of the present application, but the present application can be practiced in other manners different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present application, so the present application is not limited to the specific embodiments disclosed below.

[0048] Secondly, the "one embodiment" or "embodiment" referred to herein means that a specific feature, structure or characteristic can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an embodiment that is independent of or mutually exclusive of other embodiments.

[0049] Reference Figure 1 , 2 , 3, 5, 6, 8, 9, 10, 13, which is an embodiment of the present application, provides a flexible interconnection and mode smooth switching method for a distributed generation system, comprising the following steps:

[0050] S1: Collecting the DC voltage and DC current of the source side rectifier of each power generation unit, and establishing a droop control relationship.

[0051] InFigure 1 With Figure 3 The DC terminal voltage and DC terminal current of each generator unit source side rectifier are continuously collected and sent to the droop control unit for real-time processing. Based on the collected data, the equivalent relationship between the unit active power and DC current is determined according to the dq coordinate transformation and power model in Figure 3

[0052]

[0053] wherein, P2represents the output active power of rectifier #2; Vd2represents the d-axis voltage component of rectifier #2 in the dq coordinate system; Id2represents the d-axis current component of rectifier #2 in the dq coordinate system; Vq2represents the q-axis voltage component of rectifier #2 in the dq coordinate system; Iq2represents the q-axis current component of rectifier #2 in the dq coordinate system; Idc2represents the DC side current of rectifier #2; Vdc represents the DC bus voltage.

[0054] Under the parallel structure shown in Figure 5 , based on the active power / DC current relationship, the power sharing ratio of each generator unit is determined and the total bus current relationship:

[0055]

[0056]

[0057] and the dynamic response of the bus capacitor and intermediate capacitor is considered, respectively satisfying:

[0058]

[0059]

[0060] wherein, P1represents the output active power of rectifier #1; P2represents the output active power of rectifier #2; K represents the power distribution ratio coefficient; Idc1represents the DC side current of rectifier #1; Idc2represents the DC side current of rectifier #2; Idc represents the total DC current on the DC bus; C represents the DC bus capacitor; dVdc / dt represents the rate of change of DC bus voltage.​ Indicates DC bus current; Indicates the DC load current; This refers to the intermediate capacitor in a back-to-back converter. This represents the rate of change of the voltage across the intermediate capacitor; This indicates the DC current on the back-to-back rectifier side; This indicates the DC current on the back-to-back inverter side.

[0061] This ensures that the dynamic constraints of the bus voltage and intermediate voltage are correctly described and controlled under load or fault conditions. The droop control curve is then used as a voltage-current reference mapping for each unit (see...). Figure 5 (Power sharing illustration). During operation, when the intermediate capacitor voltage deviation meets the following conditions, the droop control curve is corrected according to a preset strategy:

[0062] When the voltage deviation is less than the preset first voltage fluctuation threshold, a smooth scheduling method is used to correct the droop control curve in order to reduce the voltage-current slope change in the steady state region and suppress micro-amplitude oscillations.

[0063] When the voltage deviation exceeds the preset second voltage support threshold, the slope of the droop control curve is adjusted to enhance the voltage support capability, thereby improving the bus voltage recovery rate and maintaining system stability under large disturbance conditions.

[0064] The data acquisition function is provided by Figure 1 The system implementation shown is used to acquire real-time output voltage, current, and bus status information of each power supply unit; the formation and adjustment of the droop curve are handled by... Figure 3 The rectifier control unit shown executes the process, generating a droop curve and updating parameters in real time based on the collected data; the dynamic relationship between power sharing and capacitors is... Figure 5 The parallel power sharing and capacitor loop are reflected; the smoothing and slope adjustment of the droop curve are executed in real time as the droop control unit is built-in.

[0065] The dynamic model of the inner current loop is expressed as follows:

[0066]

[0067] in, Indicates the inductance of the system coil; This represents the resistance of the system coil; This represents the current component along the d-axis. Represents the current component along the q-axis; and These represent the rates of change of the d-axis and q-axis current components with respect to time, respectively. This represents the integral coefficient of the current loop controller; This represents the proportional gain of the current loop controller; and This represents the integral state variables of the current loop controller in the d-axis and q-axis directions; and These represent the rates of change of the integral state variable; This represents the active power of the system; This represents the proportional constant related to power regulation; Represents the q-axis voltage component; Represents the steady-state d-axis voltage component; Indicates the reference value for the q-axis current; This represents the proportional gain coefficient of the DC voltage control loop; This represents the integral gain coefficient of the DC voltage control loop; This represents the rate of change of the integral state variable in the DC voltage control loop; Represents the integral state variable of the DC voltage controller; Indicates a reference value for DC voltage; This represents the actual DC voltage of the system; Indicates the DC voltage loop control parameters; Indicates the DC side current; This represents the d-axis voltage component.

[0068] Existing DC microgrids often experience power distribution drift, small bus oscillations, and circulating current issues in multi-source parallel scenarios, which are particularly pronounced during load steps or source-side disturbances. Traditional approaches typically set a fixed slope at a single operating point, which makes it difficult to simultaneously ensure smooth steady-state operation with small deviations and rapid support with large deviations. This results in fluctuating power sharing ratios, slow bus recovery, and insufficient parallel operation consistency.

[0069] The process begins with continuously acquiring the DC voltage and current of the source-side rectifier, establishing a droop relationship, and correcting it online. The acquisition link is configured with millisecond-level refresh and de-jitter strategies. The voltage channel employs two-stage anti-interference filtering, and the current channel uses a unified timestamp to ensure that multiple rectifiers participate in load sharing on the same time base. The droop curve is implemented in the control unit using a lookup table, supporting online interpolation and fault bypass. A dual-threshold scheduling strategy is employed: small fluctuations enter a smoothing correction interval, while larger deviations enter an enhanced slope interval.

[0070] The advantages are reflected in three aspects: stable load sharing ratio, faster bus stabilization, and significantly reduced circulating current. The curve slope decreases under small disturbances to suppress jitter, while increasing the slope under large disturbances to enhance support; the two ranges automatically switch, avoiding manual compromise. Simulation comparisons show that the voltage drop is reduced by approximately 20-30% compared to the fixed slope algorithm, and the steady-state load sharing error converges to the 1% level; parallel operation consistency is improved, and subsequent mode switching is smoother.

[0071] S2: Collecting the output current of the back-to-back rectifier and the intermediate capacitor voltage, performing phase-locked control in normal mode, and regulating the voltage and performing current in-phase control according to the intermediate capacitor voltage based on the droop control relationship.

[0072] In normal mode, as shown in FIG. 2(a), the control target of the back-to-back rectifier is to keep the intermediate capacitor voltage Figure 1 stable, and make the output current Figure 6 consistent in phase with the load current . The system first collects the output current of the back-to-back rectifier and the intermediate capacitor voltage, and realizes in-phase operation of the output current and the load current through a phase-locked loop, which satisfies the relationship:

[0073]

[0074]

[0075] wherein represents the phase angle of the output current of the back-to-back rectifier; represents the phase angle of the load current, represents the amplitude of the output current of the back-to-back rectifier; represents the amplitude of the load current.

[0076] wherein represents the output power of the rectifier, represents the load power. This relationship guarantees stable distribution of power between the rectifier and the load. At the same time, the controller regulates the intermediate capacitor voltage based on the dq coordinate system model of Figure 8 , and the dynamic process is:

[0077]

[0078]

[0079] wherein represents the d-axis voltage command component; represents the AC side resistance; represents the d-axis current component in the dq coordinate system; represents the synchronous rotating angular frequency; represents the AC side inductance; represents the q-axis current component in the dq coordinate system; represents the derivative of the d-axis current component with respect to time; represents the derivative of the q-axis current component with respect to time; represents the d-axis voltage source component in the dq coordinate system; ​​represents a q-axis voltage command component; represents a q-axis voltage source component in the dq coordinate system.

[0080] In the execution of the above-mentioned current control, the controller sets a feedforward compensation in the cross-coupling term during the process of regulating the capacitor voltage, so that the d-axis and q-axis currents can be independently regulated, thereby avoiding the dynamic distortion caused by the coupling effect. The cross-coupling term is the q-axis current component in the d-axis voltage equation and the d-axis current component in the q-axis voltage equation.

[0081] At the same time, the current loop adopts a two-degree-of-freedom structure, and the reference signal channel contains a fast response control link, and the feedback channel contains a disturbance suppression control link, so that the intermediate capacitor voltage can remain stable under external disturbance without affecting the fast tracking of the current command.

[0082] In addition, in order to prevent the saturation effect of the current loop integrator under large amplitude voltage regulation or sudden working conditions, the controller sets an anti-saturation constraint mechanism in the integral channel. When the output current approaches the limit value, the integrator is temporarily frozen, avoiding the current rebound caused by integral accumulation and recovery, thereby ensuring the smoothness in the voltage regulation process.

[0083] Through the above control, the back-to-back rectifier can Figure 6 (a) In the normal mode, the intermediate capacitor voltage can be stably maintained and the phase consistency of the current can be achieved, and under the joint action of cross-coupling compensation, two-degree-of-freedom control and anti-integral saturation, the rectifier has faster dynamic response and higher robustness.

[0084] If the normal mode relies only on amplitude regulation, reactive power backflow and power swing are easy to occur; if multiple loops are stacked, additional lag and inconsistent order are introduced. The goal is to achieve stable intermediate capacitor voltage without interrupting power supply, while keeping the rectifier output current and load current in phase, reducing reactive power back and forth and loss.

[0085] The flow cooperates with voltage regulation in phase-locked control. The output current and intermediate capacitor voltage of the back-to-back rectifier are collected, and the phase-locked loop makes the output current and load current in phase; the reference directly comes from the intermediate capacitor voltage, reducing the multi-stage series lag. The cross-coupling feedforward channel is set inside the current loop to real-time offset the mutual influence between the direct axis and the cross axis; the two-degree-of-freedom structure is adopted, the reference channel focuses on fast tracking, and the feedback channel focuses on disturbance suppression.

[0086] The advantage lies in the simultaneous improvement of tracking speed and steady-state quality. The phase constraint significantly reduces the reactive component; the cross feedforward reduces the dynamic distortion caused by the coupling between the axes; the two-degree-of-freedom structure shortens the rising edge without sacrificing disturbance resistance; the saturation management suppresses overshoot and rebound. The comprehensive effect is that the voltage setting time is shortened, the overshoot is reduced, the harmonic content is decreased, and the control quantity changes less during subsequent switching.

[0087] S3: When the source-side rectifier fails, the deviation of the intermediate capacitor voltage from the reference voltage is detected, an AC current reference value is generated and input to a single current loop controller for voltage regulation, while the dynamic performance is improved through phase lead and adaptive gain, and abnormal fluctuations are suppressed.

[0088] When the source-side rectifier fails, the system enters the fault mode. As shown in Figure 2 , rectifier #2 exits the operation and the back-to-back rectifier takes over the task of maintaining the intermediate capacitor voltage , and its control structure is as shown in Figure 9 . First, the intermediate capacitor voltage is sampled and compared with the reference voltage , and the voltage deviation is obtained:

[0089]

[0090] To improve the signal quality, the voltage deviation is filtered using a low-pass filter:

[0091]

[0092] The smoothed voltage deviation is obtained. At the same time, a phase lead element is introduced in the voltage deviation channel, and a limiting differential processing is used:

[0093]

[0094] wherein represents the deviation of the intermediate capacitor voltage; represents the reference voltage value of the intermediate capacitor; represents the actual collected intermediate capacitor voltage; represents the transfer function of the low-pass filter; represents the Laplace operator; represents the cutoff angular frequency of the low-pass filter. represents the transfer function of the phase lead element; represents the time constant of the lead element; represents the limiting angular frequency of the lead element.

[0095] The lead component is generated and superimposed with the filtered voltage deviation as the subsequent reference input.

[0096] Reference pre-alignment is performed at the moment of entering the fault mode, so that the current reference value remains continuous with the current before switching, avoiding step:

[0097]

[0098] wherein The AC q-axis current reference value at the moment of entering the fault mode is represented by Iq_ref; The actual q-axis current before the fault occurs is represented by Iq; The proportional coefficient for generating the current reference is represented by Kp; The voltage deviation amount before switching is represented by ΔV.

[0099] Based on the voltage deviation amount generated by the above processing, the AC current reference value is formed in real time:

[0100]

[0101]

[0102]

[0103] wherein, The AC q-axis current reference value generated in real time is represented by Iq_ref; The proportional coefficient adaptively adjusted according to the size of the voltage deviation is represented by Kp; The absolute value of the voltage deviation is represented by ΔV; The leading component generated by the phase leading element is represented by Iq_lead; The reference value of the gain in the small deviation area is represented by Kp0; The limit value of the gain in the large deviation area is represented by Kp1; The smooth scheduling function is represented by f(ΔV); The scale coefficient of the voltage deviation is represented by K; The hyperbolic tangent function is represented by tanh(ΔV / K).

[0104] The design provides a smooth response in the small deviation area and automatically enhances the voltage support capability in the large deviation area.

[0105] The AC current reference value is input into a single current loop controller to perform voltage stabilization adjustment. According to the dq modeling relationship (see Figure 8 ), the dynamic equation of the current loop is:

[0106]

[0107]

[0108] wherein, The d-axis voltage instruction component is represented by Vd; The AC side resistance is represented by R; The d-axis current component in the dq coordinate system is represented by Id; The synchronous rotation angular frequency is represented by ω; The AC side inductance is represented by L; The q-axis current component in the dq coordinate system is represented by Iq; The derivative of the d-axis current component with respect to time is represented by Id; The derivative of the q-axis current component with respect to time is represented by Iq. represents the d-axis voltage source component in dq coordinate system; dq dynamic equation q-axis; represents the q-axis voltage command component; represents the q-axis voltage source component in dq coordinate system.

[0109] The controller introduces dq cross-term feedforward compensation in the calculation to decouple the d-axis and q-axis current independently, ensuring control accuracy. In the adjustment process, the single current loop controller introduces a phase lead element and combines adaptive gain scheduling, so that the tracking speed and steady-state performance of the reference current are considered. At the same time, the integral saturation constraint is set in the loop: when the current output approaches the preset threshold , the integrator is frozen; when the output returns to the safe range, or the error direction is opposite to the output direction, the integrator is unfrozen, thereby preventing the rebound and overshoot caused by the integral accumulation.

[0110] Finally, the current loop output acts on the power conversion link to form active power:

[0111]

[0112] and maintains energy consistency with the DC side current:

[0113]

[0114] Thus, in the fault mode, only through a single current loop, the intermediate capacitor voltage is controlled to be stable, ensuring the stable operation of the system.

[0115] wherein, represents the active power; represents the d-axis voltage component in dq coordinate system; represents the q-axis voltage component in dq coordinate system; represents the intermediate capacitor; represents the rate of change of the intermediate capacitor voltage; represents the DC side current of the back-to-back rectifier; represents the DC side current of the back-to-back inverter.

[0116] After the source side rectifier fails, the double loop structure often causes large switching impact, slow recovery, and high peak current due to the lag and order difference of the outer loop. The goal is to complete voltage stabilization and energy supply maintenance under a unified structure, reduce the phase and delay burden introduced by additional links, and ensure controllability during fault instant and recovery process.

[0117] The flow enters the single current loop voltage stabilizing mode: the deviation from the intermediate capacitor voltage and the reference value is obtained, a phase advance component is formed by low-pass and amplitude limiting differentiation for reference shaping; reference pre-alignment is performed at switching instant to make the reference continuous with the current before switching and eliminate the step; adaptive gain scheduling is adopted for reference generation, small deviation area prioritizes static stability and large deviation area prioritizes recovery speed. Cross-coupling feedforward and integral saturation management are continued to be used in the loop to avoid rebound and secondary overshoot.

[0118] The advantages are reflected in two links: continuous reference side and robust loop side. Reference pre-alignment reduces transient jump and adaptive gain takes into account smoothness and speed; loop feedforward and saturation management suppress coupling and overdrive. Compared with the traditional double loop, the fault transient voltage drop is shallower, the current peak is lower, the setting time is shorter, there is no high-frequency ringing in the switching window, and it is easy to seamlessly connect with the normal mode. In the fault mode, by canceling the voltage outer loop, only a single current loop is retained to realize the voltage stabilizing control of the intermediate capacitor, which fundamentally solves the switching impact and slow recovery problem caused by the inconsistent control order of the normal mode and the fault mode in the traditional scheme. The architecture keeps the control structure unified, and combines phase advance, adaptive gain scheduling and integral saturation constraint, which not only improves the dynamic performance of voltage regulation, but also effectively suppresses current overshoot and oscillation, ensuring the smoothness of mode switching process and the reliability of operation

[0119] S4: On the basis of the single current loop control result, the control signal is collected, the weight coefficient is generated through a low-pass filter, the normal mode control quantity and the fault mode control quantity are weighted and fused, and mode smooth switching is realized through pole matching and reference pre-alignment.

[0120] After entering the mode switching window, instead of relying only on an empirical low-pass weight, an energy-aware predictive mode deformation is first performed: the equivalent model in the switching window is obtained through online identification; a short-term predictive optimization is constructed, considering energy consistency, trajectory smoothness, pole consistency and device constraints; a continuous reference and parameter deformation trajectory is output; on this basis, the low-pass weight is used for weighted fusion, and the reference pre-alignment and pole matching are completed to complete the takeover.

[0121] As shown in Figure 8 and Figure 9 , the energy dynamics of the intermediate capacitor voltage is the core model:

[0122]

[0123] In the switching window, the above formula and the dq current loop are discretized and identified online to obtain the equivalent mapping in the window:

[0124]

[0125] ​wherein is the recognition coefficient updated with the window scrolling; is the small signal quantity relative to the current working point; represents the discrete time is the small deviation quantity of the intermediate capacitor voltage relative to its steady-state value; represents the discrete time is the intermediate capacitor voltage deviation quantity; represents the discrete time is the q-axis current reference value change quantity at the discrete time represents the discrete time is the small deviation quantity of the inverter actual output current at the discrete time is the autoregressive coefficient of the intermediate capacitor voltage; is the equivalent gain coefficient of the current reference change on the intermediate capacitor voltage; is the equivalent coupling coefficient of the inverter output current change on the intermediate capacitor voltage.

[0126] The relationship explicitly shows the short-time coupling of the “reference side-energy side-execution side” as the constraint basis of the prediction link.

[0127] In the prediction window of 20-50 ms, the time trajectories of the reference and the parameters (including , the current loop gain and the dq instruction of the fault channel) are jointly optimized to achieve: the energy consistency goal: the deviation of the intermediate capacitor voltage to the reference is minimized; the trajectory smoothness goal: the reference and the parameters are continuous in value, slope and acceleration ; the pole consistency goal: the dominant closed-loop dynamics of the fault channel is aligned with the normal channel; the device and safety constraints: including the dq instruction amplitude and change rate limiting, the current peak and climb rate limiting, the gain value and change rate limiting, and the margin to prevent PWM / device saturation.

[0128] If there is a future risk of exceeding the limit in the prediction window, the predictive anti-integration saturation is triggered in advance in the current period: the integrator is frozen (or switched to feedforward priority), and after the risk is removed or the error direction is reversed, it is automatically unfrozen to avoid secondary overshoot and rebound.

[0129] The , and the dq instruction of the fault channel output by the optimizer are realized by using a five-order spline high-order smooth basis function, ensuring that the second-order derivative is continuous . In this way, there will be no “acceleration mutation”-induced spikes and EMI during switching, and the trajectory can be directly fed into the power conversion link.

[0130] The fault channel closed-loop main pole based on online identification is aligned with the target main pole of the normal channel; and the fine tuning within a limited range is allowed in the optimization process The parameters corresponding to the weight time constant are used to keep the dominant time constant and damping consistent between the two channels, achieving dynamic consistency.

[0131] After completing the predicted trajectory, the weight is generated and the control quantities of the two channels are fused according to the existing process: Figure 10

[0132]

[0133] Among them, is the first-order low-pass filter weight, is continuously driven by the foregoing Switching start point executes reference pre-alignment to keep the initial state of the takeover channel consistent with that before switching; then, under the joint action of weight buffer and pole consistency, smooth takeover is completed; represents the integrated control quantity of the system at time , that is, the total control output after the weighted fusion of the normal mode control quantity and the fault mode control quantity; represents the control output quantity in normal mode; represents the control output quantity in fault mode.

[0134] In the mode switching process, the specific execution steps are as follows:

[0135] First, when entering the switching window, the system samples the intermediate capacitor voltage, AC current reference value, dq control instruction and DC current, and completes the reference pre-alignment initialization, so that the control quantity to be taken over keeps continuous in the initial state with that before switching.

[0136] Secondly, online identification is performed to update the equivalent relationship coefficient between the capacitor voltage and the current, and to estimate the closed-loop main pole of the fault channel, providing accurate model support for subsequent prediction optimization.

[0137] Subsequently, based on the updated model, a short-time prediction optimization problem is constructed, considering energy consistency, second-order continuity of trajectory, pole consistency and physical constraints of control quantity in the optimization process, and through rolling solution, continuous feasible reference trajectory and parameter deformation results are obtained.

[0138] During the prediction process, if the calculation result shows that current or voltage overrun may occur in the future, the prediction-based anti-saturation mechanism is triggered immediately, the integrator is frozen in the current period, and the integrator is unfrozen when the saturation risk is removed or the error direction is reversed, to ensure the stability of the system.

[0139] ​Then, the low-pass filter is used to generate the weight coefficient, the control quantity of the normal mode and the fault mode is weighted and fused according to the weight, and the fused result is output to the execution end to complete the control in the current period.

[0140] Finally, the above process is continuously repeated in a rolling manner until the mode switching process is completed, so as to ensure that the intermediate capacitor voltage remains stable during the entire switching period and the system dynamic characteristics remain continuous and consistent.

[0141] When switching between the normal mode and the fault mode, the traditional method relies on a single low-pass filter to generate a weight coefficient to smooth the transition, but this method has the problems of large lag and inability to guarantee energy consistency, which can easily cause fluctuations in the intermediate capacitor voltage at the switching moment. The embodiment adds an energy-aware predictive mode deformation link before the weighted fusion, obtains an intermediate capacitor dynamic model through online identification, and establishes a short-time prediction equation within the switching window, so as to predict the future voltage deviation and control quantity trend before switching.

[0142] In the prediction link, the energy consistency of the intermediate capacitor voltage is taken as the core target, and second-order smoothness constraints and pole matching constraints are added, so as to ensure that the generated reference trajectory is not only continuous in value, but also continuous in rate of change and acceleration. This design avoids current spikes and voltage jitter at the switching moment, making the switching process continuous and controllable in the mathematical sense. At the same time, the predictive anti-integral saturation mechanism freezes the integrator in advance before possible overload, avoiding secondary overshoot and rebound caused by post-correction.

[0143] Through the joint action of the prediction model, the smoothness constraint and the online pole matching, the normal mode and the fault mode can maintain dynamic consistency during the switching process, ensuring that the intermediate capacitor voltage is always stable around the reference value. Compared with the traditional method relying on empirical filtering, this method forms a closed-loop design in the physical constraint, energy coupling and control logic level, greatly reduces the switching impact, significantly improves the robustness, and thus makes substantial progress in system reliability and dynamic performance.

[0144] The embodiment also provides a flexible interconnection and mode smooth switching system of a distributed power generation system, which comprises a data acquisition module configured to continuously acquire DC voltage and DC current of a source-side rectifier of each power generation unit, and acquire output current and intermediate capacitor voltage of a back-to-back rectifier.

[0145] A droop control module is configured to establish a droop control relationship and form a droop control curve based on the acquired data, and implement smooth scheduling or slope adjustment on the droop control curve according to a preset strategy during operation.

[0146] The phase-locked and reference generation module is configured to perform phase-locked control, generate a current reference according to the intermediate capacitor voltage and provide a reference instruction to the current loop in the normal mode.

[0147] The reference shaping module is configured to filter the voltage deviation and generate a phase-advance component, perform reference pre-alignment and output an alternating current reference value in the fault mode.

[0148] The single-current-loop control module is configured to receive the alternating current reference value and perform single-current-loop voltage regulation, and the dq cross term feedforward compensation and two-degree-of-freedom control structure are realized inside the module.

[0149] The adaptive gain scheduling module, as a submodule of the single-current-loop control module, is configured to adjust the control gain according to the voltage deviation.

[0150] The anti-integral saturation module, as a submodule of the single-current-loop control module, is configured to freeze the integral when the current approaches a preset threshold and unfreeze the integral when the recovery condition is met.

[0151] The weight generation module is configured to collect mode control signals and generate a weight coefficient through low-pass filtering.

[0152] The fusion and output alignment module is configured to fuse the normal mode control quantity and the fault mode control quantity according to the weight coefficient, and perform pre-alignment of the reference or the output to ensure continuity when switching.

[0153] The parameter setting and pole matching module is configured to set the weight time constant and the loop parameter according to the system working condition to realize the consistency of the mode dynamics.

[0154] The amplitude limiting and safety unification module is configured to implement amplitude limiting, saturation protection and safety strategy on the reference value and the control output.

[0155] Referring to Figure 4 , Figure 7 , Figure 11 , Figure 12 , an embodiment of the present application provides a flexible interconnection and mode smooth switching method of a distributed power generation system, in order to verify the beneficial effects of the present application, scientific demonstration is carried out through simulation experiment.

[0156] The test object is a flexible interconnection system of two distributed power generation unit interconnection systems and a set of back-to-back converters. The power converter adopts a three-phase two-level VSC topology, as shown in Figure 7Switching stage modeling with real device parameters: switching frequency 10.00 kHz, sampling period 50.00 μs, AC side equivalent inductance 99.00 μH, equivalent resistance 1.06 mΩ, DC bus capacitor 3.00 mF, intermediate capacitor 3.00 mF; line inductances L1=1.00 mH, L2=0.50 mH. System bus target values set as: DC bus voltage 540.00 V, intermediate capacitor voltage 800.00 V. Machine side provided by the coupling of "back-to-back inverter and SG1" shown in FIG. 1, which provides an electromagnetic-mechanical linkage boundary: SG1's electrical angular frequency corresponds to the pole pair number p=2, moment of inertia J=0.012 kg·m², viscous damping B=0.0015 N·m·s / rad, permanent magnet flux linkage 0.20 Wb, and the given torque on the mechanical side is gradually changed in the interval 3.00-7.00 N·m to cover medium and light load conditions. Figure 4

[0157] Figure 4 The mathematical model of the back-to-back PWM converter is represented as:

[0158]

[0159] wherein, represents the inductance of the motor coil; represents the resistance of the coil; represents the d-axis current of the high-frequency component; represents the q-axis current of the high-frequency component; and represent the derivative of the d-axis current with respect to time and the derivative of the q-axis current with respect to time, respectively; and represent the state quantities used for "accumulating current error" inside the controller; and represent the speed of change of these accumulated quantities; represents the strength of integral regulation in the inverter current control loop, which is used to control the influence of error accumulation on the system; and represent the strength of proportional regulation, which is used to control the immediate response of the current to the deviation; represents the high-frequency power; represents the number of pole pairs of the motor; represents the magnetic flux of the permanent magnet; represents the speed of the motor in the high-frequency state; and represent the two components of the high-frequency voltage, corresponding to the d-axis and q-axis directions, respectively; and represent the reference value or steady-state component of the current, which is used as the target for control comparison;​ Indicates the voltage of the DC power supply; This indicates the current that the inverter absorbs or outputs from the DC side.

[0160] The control structure strictly follows weights 1–7: S1 establishes a droop relationship and enables dual-threshold scheduling (first threshold ±5.00 V, second threshold ±20.00 V) to ensure smoothing of small deviations and support for large deviations; S2 executes phase-locked loop and in-phase control in normal mode, with the current loop adopting a cross-coupled feedforward and two-degree-of-freedom structure, and the integrator unit having anti-saturation constraints. Typical parameters: rectifier side current loop proportional / integral 2.00 / 20000.00, inverter side 0.87 / 4000.00; droop allocation coefficient k1=k2=0.25. S3 cancels the voltage outer loop in fault mode, retaining only the single current loop regulation, and adds limiting differentiation and phase lead to the voltage deviation channel, while performing adaptive gain scheduling according to the deviation amplitude; the reference pre-alignment ensures continuity between the reference and actual current at the moment of switching. When switching modes, S4 introduces a short-time prediction model based on the dynamic relationship between intermediate capacitor voltage and DC current, along with online pole matching, in addition to the traditional first-order low-pass weighting and weighted fusion. Within a prediction window of 30.00 ms (rolling step size of 0.50 ms), energy consistency, second-order continuity (C²), and dominant pole consistency are jointly optimized. If a future limit violation is predicted, the integrator is pre-frozen in advance and unfrozen after the risk of exceeding the limit is eliminated or the error direction is reversed.

[0161] The simulation platform uses a time-domain discrete electromagnetic switch stage model. The fault injection is set to an open circuit on the DC side of rectifier #2 at t=0.10 s (equivalent to the source-side rectifier shutting down), and the fault lasts for 150.00 ms. The comparison scheme is "traditional dual-loop + LPF weighted switching" (as a comparison scheme). Figure 11 (Corresponding situation), the tested scheme is "unified single current loop + predictive mode deformation + online pole matching" (corresponding to) Figure 12 Two sets of schemes were operated separately under identical load, grid, and device parameters. Key performance indicators included: minimum intermediate capacitor voltage, recovery time (±2% bandwidth), overshoot, peak rectifier q-axis current, peak DC bus voltage ripple, grid-side current THD, weighted 10–90% rise time, and the number and duration of integrator freeze / unfreeze cycles. All measurements were sampled and recorded at 10.00 kHz, and statistics were compiled for a single switching window.

[0162] DC bus reference value: 540.00 V; intermediate capacitor reference value: 800.00 V.

[0163] Prediction window: 30.00 ms; rolling step: 0.50 ms; initial value of first-order weight time constant: 5.00 ms.

[0164] Thresholds: first voltage fluctuation threshold 5.00 V; second voltage support threshold 20.00 V.

[0165] Comparison results (traditional dual loop + LPF, see Figure 11 ): minimum intermediate capacitor voltage: 795.80 V.

[0166] Voltage overshoot peak: +3.20 V (803.20 V).

[0167] Recovery time (±2%): 38.00 ms.

[0168] q-axis current peak: 12.40 A.

[0169] DC bus ripple peak (against 540.00 V): 8.10 V.

[0170] Grid-side current THD: 3.20 %.

[0171] Weight 10-90% rise time: 5.50 ms.

[0172] Freeze times of integrator: 2 times; cumulative freeze duration: 10.00 ms.

[0173] Measured results (unified single loop + predictive mode deformation + pole matching, see Figure 12 ):

[0174] Minimum intermediate capacitor voltage: 797.00 V.

[0175] Voltage overshoot peak: +1.20 V (801.20 V).

[0176] Recovery time (±2%): 24.00 ms.

[0177] q-axis current peak: 9.80 A.

[0178] DC bus ripple peak (against 540.00 V): 4.80 V.

[0179] Grid-side current THD: 2.10 %.

[0180] Weight 10-90% rise time (adaptive with trajectory): 6.20 ms.

[0181] Freeze times of integrator: 1 time; cumulative freeze duration: 6.00 ms.

[0182] Supplementary statistics:

[0183] Normal / fault dominant pole difference (amplitude angle difference): traditional 18.00°; measured 6.00°.

[0184] Switching window ringing amplitude (percentage of 800.00 V): traditional 2.50% lasting 12.00 ms; measured 0.90% lasting 6.00 ms.

[0185] The above comparison shows that the unified single current loop architecture combined with predictive mode transformation and online pole matching can significantly improve the switching transient and recovery quality without changing the hardware and rated point settings. First, from the perspective of energy consistency, the intermediate capacitor is the energy buffer core during switching. The traditional double loop is affected by the difference in the lag and order of the outer loop, and cannot coordinate the reference side and the execution side at the same time when the fault enters, resulting in the lowest point of the capacitor voltage falling to 795.80 V. The unified single loop reduces the lag of one level of loop, and cooperates with the energy deviation minimization constraint in the prediction window, so that the reference trajectory is continuous at three levels of value, slope and acceleration, and the lowest point is improved to 797.00 V. The capacitor voltage overshoot is reduced from +3.20 V to +1.20 V, which shows that the C² continuity of the trajectory effectively suppresses the second-order response caused by the "acceleration mutation".

[0186] Second, from the perspective of dynamic consistency and pole alignment, the traditional scheme has a large deviation of the closed-loop dominant pole before and after switching (amplitude angle difference 18.00°), and although the weight fusion can be gradually changed, the difference in dynamics on both sides still induces ringing and secondary swing. By obtaining the closed-loop dominant pole of the fault channel through online identification, and incorporating pole consistency into the prediction target, the deviation is converged to 6.00° under the parameter limited fine-tuning, so that the synthesized channel after weight fusion maintains a unified time constant and damping, thereby reducing the ringing amplitude from 2.50% to 0.90% and shortening the duration from 12.00 ms to 6.00 ms. Although the weight 10-90% rise time increases slightly (5.50 ms→6.20 ms), the equivalent response of the synthesized channel is smoother, avoiding a larger peak cost, and ultimately shortening the recovery time from 38.00 ms to 24.00 ms.

[0187] Again, from the current quality and device constraints, the traditional double loop causes the q-axis current peak value of 12.40 A due to the insufficient reference step and decoupling at the initial stage of the fault; the unified single loop combined with cross feedforward and adaptive gain scheduling makes the fault initial value and reference continuous and the phase margin more sufficient, and the peak value is reduced to 9.80 A. Correspondingly, the DC bus ripple peak value is reduced from 8.10 V to 4.80 V, and the grid-side current THD is reduced from 3.20% to 2.10%, which embodies the synergistic effect of the continuous reference trajectory and decoupling compensation. The predictive anti-integral saturation is more forward-looking than the threshold trigger, and the freezing number is reduced from 2 to 1, and the cumulative freezing time is shortened to 6.00 ms, avoiding the secondary overshoot caused by repeated freezing / thawing.

[0188] Finally, from the perspective of modeling and scenario coverage, Figure 7 The two-level topology of the unified single loop ensures that the device level constraints are directly reflected in the prediction constraints, Figure 4 The SG1 coupling of the unified single loop makes the electromechanical dynamics have a substantial impact on the reference shaping and pole estimation during the medium voltage maintenance process, which together constitute a "source-grid-load-control" closed loop scenario, making the results have engineering extrapolation value. Figure 11 / Figure 12 The comparison waveforms intuitively show that under the same fault injection, the unified single loop plus predictive mode deformation and online pole matching can recover to the steady state interval in a shorter time and significantly reduce the switching impact and current peak. In summary, the method is not a conventional fine-tuning of a single control loop, but rather a core goal of energy consistency and dynamic consistency, which synchronously deforms the reference and parameters and coordinates the constraints within the switching window, improving the stability and controllability of the switching stage from the system level.

[0189] The embodiment also provides a computer device suitable for the flexible interconnection and mode smooth switching method of the distributed power generation system, which comprises a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the flexible interconnection and mode smooth switching method of the distributed power generation system proposed in the above embodiment.

[0190] The computer device can be a terminal, which comprises a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved by WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0191] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to implement the method for implementing flexible interconnection and mode smooth switching of a distributed power generation system according to the above embodiment. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic storage, a flash memory, a magnetic disk or an optical disk.

[0192] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and all of them should be covered in the scope of the claims of the present application.

Claims

1. A method for flexible interconnection and smooth mode switching of a distributed generation system, characterized in that, include: Collect the DC voltage and DC current of the source-side rectifier of each power generation unit and establish the droop control relationship; Based on the droop control relationship, the output current of the back-to-back rectifier and the voltage of the intermediate capacitor are collected. In normal mode, phase-locked control is performed, and voltage regulation and current in-phase control are performed according to the voltage of the intermediate capacitor. When a source-side rectifier fault is detected, the deviation between the intermediate capacitor voltage and the reference voltage is collected, an AC current reference value is generated and input into a single current loop controller for voltage regulation, and dynamic performance is improved and abnormal fluctuations are suppressed through phase lead and adaptive gain. Based on the single current loop control results, control signals are acquired, weighting coefficients are generated by low-pass filtering, and normal mode control quantities and fault mode control quantities are weighted and fused. Smooth mode switching is achieved through pole matching and reference pre-alignment.

2. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 1, characterized in that: The establishment of the droop control relationship includes continuously collecting DC voltage and DC current data from the source-side rectifiers of each power generation unit; determining the power sharing ratio based on the collected data; and generating a droop curve. When the voltage deviation is less than the first voltage fluctuation threshold, a smoothing scheduling method is used to correct the droop curve; when the voltage deviation exceeds the second voltage support threshold, the slope of the droop curve is adjusted.

3. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 2, characterized in that: The phase-locked control (PLC) operation in normal mode includes: acquiring the output current of the back-to-back rectifier and the intermediate capacitor voltage; comparing the output current with the load current and generating a control signal with the same phase as the load current through a PLC; generating a current reference based on the intermediate capacitor voltage and inputting it to a single current loop controller; setting cross-coupling feedforward compensation in the current loop controller to cancel the coupling between current components; the current loop controller adopts a two-degree-of-freedom structure with separate reference command channels and feedback channels; and setting anti-integral saturation processing in the integrator unit of the current loop to limit integral accumulation when the current approaches a threshold.

4. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 3, characterized in that: The voltage regulation includes, when a source-side rectifier fault is detected, acquiring the deviation between the intermediate capacitor voltage and the reference voltage, filtering the deviation, and generating a filtered voltage deviation. An AC current reference value is generated based on the voltage deviation, and reference pre-alignment is performed at the moment of entering the fault mode to initialize the reference value to a state that is continuous with the current before switching; the AC current reference value is input to the single current loop controller to perform voltage regulation.

5. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 4, characterized in that: The method of generating AC current reference value includes introducing a phase lead element in the voltage deviation channel and generating a lead component by combining amplitude limiting differential processing and low-pass filtering. The lead component and the voltage deviation are superimposed and used as a reference value input to the single current loop controller.

6. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 5, characterized in that: The single current loop controller includes an adaptive gain scheduling module and an anti-integral saturation module; the adaptive gain scheduling module adjusts the control gain according to the magnitude of the voltage deviation; the anti-integral saturation module freezes the integrator when the current output approaches a preset threshold, and unfreezes the integrator when the output returns to a safe range, or when the error direction is opposite to the output direction.

7. The method for flexible interconnection and smooth mode switching of a distributed generation system as described in claim 6, characterized in that: The smooth switching of the modes includes: within the switching window, establishing a short-time prediction model based on the dynamic relationship between the intermediate capacitor voltage and the DC current; generating a reference trajectory that satisfies energy constraints and second-order continuity; when the prediction results indicate that there may be a risk of exceeding limits in the future, performing pre-freezing on the integral unit and unfreezing it when the conditions recover; during the weighted fusion process, performing reference pre-alignment on the control quantity that is about to be taken over, and tuning the weight time constant and loop parameters in combination with online pole matching, so that the normal mode and the fault mode are consistent in dynamic characteristics, thereby achieving a smooth transition.

8. A flexible interconnection and smooth mode switching system for a distributed generation system, based on the flexible interconnection and smooth mode switching method for a distributed generation system according to any one of claims 1 to 7, characterized in that: The data acquisition module is used to continuously acquire the DC voltage and DC current of the source-side rectifiers of each power generation unit, as well as the output current and intermediate capacitor voltage of the back-to-back rectifiers. The droop control module is used to collect data, establish droop control relationships, and form droop control curves. During operation, it performs smooth scheduling or slope adjustment on the droop control curves according to preset strategies. The phase-locked loop and reference generation module is used to perform phase-locked control in normal mode, generate a current reference based on the intermediate capacitor voltage, and provide reference commands to the current loop. The reference shaping module is used to filter voltage deviation and generate phase lead components in fault mode, perform reference pre-alignment and output AC current reference value. The single current loop control module is used to receive AC current reference values ​​and perform single current loop voltage regulation. The module internally implements dq cross term feedforward compensation and a two-degree-of-freedom control structure. The adaptive gain scheduling module, as a sub-module of the single current loop control module, is used to adjust the control gain according to the voltage deviation. The anti-integral saturation module, as a sub-module of the single current loop control module, is used to freeze the integral when the current approaches a preset threshold and unfreeze the integral when the recovery condition is met. The weight generation module is used to acquire mode control signals and generate weight coefficients through low-pass filtering; The fusion and output alignment module is used to perform weighted fusion of normal mode control quantity and fault mode control quantity according to the weight coefficient, and to perform pre-alignment of reference or output during switching to ensure continuity. The parameter tuning and pole matching module is used to tune the weight time constant and loop parameters according to the system operating conditions to achieve dynamic consistency of the mode. The amplitude limiting and safety consistency module is used to implement amplitude limiting, saturation protection and safety strategies for reference values ​​and control outputs.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the flexible interconnection and smooth mode switching method for the distributed generation system according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the flexible interconnection and smooth mode switching method for the distributed generation system according to any one of claims 1 to 7.

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