Buck-boost pulse power suppression circuit suitable for airborne high-voltage bus

Abstract

The invention discloses a buck-boost pulse power suppression circuit suitable for an airborne high-voltage bus. The buck-boost pulse power suppression circuit comprises a high-voltage DC bus output module, a phase-shifted full-bridge DC / DC converter module, a bidirectional Sepic converter module and a pulse load module, the high-voltage direct-current bus output module is respectively connected with the input end of the phase-shifted full-bridge DC / DC converter module and the bidirectional Sepic converter module, and the output end of the phase-shifted full-bridge DC / DC converter module is connected with the pulse load module. Through the design structure that the bidirectional Sepic converter is directly connected to the two ends of the high-voltage direct-current bus in parallel, the pulse load power suppression circuit can rapidly and effectively suppress bus current pulsation, the impact of pulse load power changes on a power supply system is reduced, and stable operation of the system is guaranteed.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses. Background Technology

[0002] With the continuous development of airborne power supply systems, the proportion of pulse load modules is also increasing, as seen in applications such as phased array radar, synthetic aperture radar, and electromagnetic pulse weapons. Pulse load modules, characterized by wide frequency bands and strong pulse variations, generate significant current ripples during operation. This current behavior can cause a series of power quality problems. When the power supply system has limited capacity, it may struggle to respond promptly to changes in the pulse load modules, leading to fluctuations in bus voltage and current, reduced power quality, and even jeopardizing the safe and stable operation of the airborne power supply system.

[0003] To reduce the impact of the strong pulse characteristics of the pulse load module on the power supply system and balance the instantaneous power difference between the pulse load module and the power supply system, existing pulse power suppression circuits mainly use parallel or two-stage topologies to charge and discharge the energy storage device, thereby suppressing DC bus voltage fluctuations and improving system stability. The parallel topology and power flow diagrams are shown below. Figure 1 As shown, where, Figure 1 (a) is a parallel topology diagram. Figure 1 (b) shows the power flow direction under heavy load in a parallel topology. Figure 1 (c) is the power flow diagram of the parallel topology under light load. The two-stage topology and its power flow diagram are shown below. Figure 2 As shown, where, Figure 2 (a) is a two-level topology diagram. Figure 2 (b) is the power flow diagram of a two-stage topology under heavy load. Figure 2 (c) is the power flow diagram of a two-level topology under light load.

[0004] The parallel topology uses a bidirectional converter connected in parallel between the front-end converter and the pulse load module to charge and discharge the energy storage capacitor, allowing the front-end power supply system to provide only average power. The bidirectional DC / DC converter is typically a bidirectional Buck / Boost converter, allowing the energy storage capacitor C... s Voltage v at both ends Cs Fluctuations are minimized to reduce capacitor size. Under heavy load, the upstream converter provides average power P. ave The bidirectional DC / DC converter provides pulsating power P pul ,like Figure 1 (b) Under light load, the upstream converter still provides average power, and the bidirectional DC / DC converter absorbs excess power to achieve power balance, such as... Figure 1(c) The two-stage topology consists of a cascaded front-stage converter and a rear-stage converter. The front-stage converter provides the average power to the pulsed load module, and the intermediate decoupling capacitor C... s Provides pulsed power for pulsed load modules, suitable for medium and high frequency pulsed load modules.

[0005] Existing parallel pulse power suppression circuits typically connect a bidirectional converter in parallel between the front-end and the pulse load module. However, due to the low voltage level of the pulse load module and the parasitic parameters of components such as the DC internal resistance of the bidirectional converter, the voltage gain and efficiency of the bidirectional converter will drop sharply after the duty cycle increases to a certain extent. Therefore, the voltage of the energy storage capacitor is generally controlled below 200V, and it is difficult to increase the voltage fluctuation range, which limits the reduction of the capacitance value of the energy storage capacitor and the increase of power density. Summary of the Invention

[0006] To address the aforementioned issues, this application provides a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses, aiming to reduce DC bus input current ripple and improve the stability of the DC bus and the upstream power supply system.

[0007] The first aspect of this invention provides a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses, comprising: a high-voltage DC bus output module, a phase-shifted full-bridge DC / DC converter module, a bidirectional Sepic converter module, and a pulse load module; The high-voltage DC bus output module is connected to the input terminal of the phase-shifted full-bridge DC / DC converter module and the bidirectional Sepic converter module, respectively. The output terminal of the phase-shifted full-bridge DC / DC converter module is connected to the pulse load module.

[0008] In one optional implementation, the phase-shifted full-bridge DC / DC converter module includes switching transistors S1, S2, S3, and S4, an inductor L3, diodes D1, D2, D3, and D4, and a transformer T1. The drains of both switching transistors S1 and S2 are connected to the high-voltage DC bus output module. The source of switching transistor S1 is connected to one end of inductor L3 and the drain of switching transistor S3. The source of switching transistor S2 is connected to one end of the primary winding of transformer T1 and the drain of switching transistor S4. The other end of inductor L3 is connected to the other end of the primary winding of transformer T1. The source of switching transistor S4 is connected to the source of switching transistor S3 and the high-voltage DC bus output module. One end of the secondary winding of transformer T1 is connected to the anode of diode D1 and the cathode of diode D3. The cathode of diode D1 is connected to the cathode of diode D2 and the pulse load module. The anode of diode D2 is connected to the other end of the secondary winding of transformer T1 and the cathode of diode D4. The anode of diode D3 is connected to the anode of diode D4 and the pulse load module.

[0009] In one optional implementation, the control circuit of the phase-shifted full-bridge DC / DC converter module includes: a voltage loop comparator, a voltage loop PI regulator, a current loop comparator, a current loop PI regulator, and a phase-shift modulator. Used to transfer pulse load voltage v o and given voltage v o_ref The difference voltage is obtained by subtracting the values ​​using a voltage loop comparator. The compensation current reference value i is obtained through the voltage loop PI regulator. o_ref , will pulse load current i o With the compensation current reference quantity i o_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The switching control signal is obtained through the current loop PI regulator, and then driven by the phase-shift modulator to drive the switching transistors S1, S2, S3 and S4 of the phase-shift full-bridge converter module.

[0010] In one optional implementation, the bidirectional Sepic converter module includes: inductor L1, inductor L2, and switching transistor S. a Switch S b Intermediate capacitor C m and energy storage capacitor C s ; One end of the inductor L1 is connected to the high-voltage DC bus output module, and the other end of the inductor L1 is connected to the switching transistor S. a The drain and intermediate capacitor C m One end is connected to the intermediate capacitor C. m The other end is connected to one end of inductor L2 and the switch S respectively. b The source connection of the switch S b The drain and energy storage capacitor C s The positive terminal is connected to the energy storage capacitor C.s The negative terminals are respectively connected to the other end of inductor L2 and switch S. a The source and high-voltage DC bus output module are connected.

[0011] In one optional implementation, the control module of the bidirectional Sepic converter module includes: a voltage loop control unit and a current loop control unit; The voltage loop control unit includes a voltage loop comparator and a voltage loop PI regulator; used to convert the energy storage capacitor voltage v Cs and reference voltage v Cs_ref The difference voltage is obtained by performing a difference operation using a voltage loop comparator. The first compensation current reference quantity i is generated by adjusting the voltage loop PI regulator. b_ref1 ; The current loop control unit includes a second-order low-pass filter, a current loop comparator, a current loop PI regulator, and a PWM modulator; it is used to input the phase-shifted full-bridge converter module's input current i in The input current i is obtained through a second-order low-pass filter. in The continuous value of the input current i in The continuous value and reference current i in_ref The second compensation current reference value i is obtained by subtraction using a current loop comparator. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtracting the current through a current loop comparator. b_ref The bidirectional Sepic converter module will compensate for the current i b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The current loop PI regulator generates a switching control signal, which is then used by a PWM modulator to control the switching transistor S of the bidirectional Sepic converter module. a and switching transistor S b Drive it.

[0012] In one optional implementation, the operating modes of the bidirectional Sepic converter module include: Light load mode: Part of the energy from the high-voltage DC bus output module is transmitted through inductors L1 and L2 and the intermediate capacitor C. m To the energy storage capacitor C s Charge; Heavy load mode: Energy storage capacitor C s Discharge occurs, and the bidirectional Sepic converter module charges the high-voltage DC bus output module.

[0013] A second aspect of this invention provides a method for suppressing buck-boost pulse power in airborne high-voltage buses, comprising the following steps: S1. Real-time acquisition of energy storage capacitor voltage v Cs Phase-shifted full-bridge DC / DC converter module input current i in Bidirectional Sepic converter module compensation current i b Pulse load voltage v o and pulse load current i o ; S2, Extract the input current i of the phase-shifted full-bridge converter module in Continuous values; S3, change the voltage v of the energy storage capacitor Cs and reference voltage v Cs_ref Perform the subtraction to generate the difference voltage. The difference voltage PI regulation is performed to generate the first compensation current reference quantity i b_ref1 ; S4, Input current i in The continuous value and reference current i in_ref The second compensation current reference quantity i is obtained by performing the difference operation. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtraction. b_ref The bidirectional Sepic converter module will compensate for the current i. b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The PI controller generates a switch control signal. S5. Control the switching transistor S of the bidirectional Sepic converter module via a PWM modulator. a and switching transistor S b On and off; S6, the pulse load voltage v o and given voltage v o_ref The difference voltage is obtained by performing subtraction. The reference quantity i for generating the compensation current is obtained through PI regulation. o_ref ; S7, the pulse load current i o With the compensation current reference quantity i o_ref The difference is used to obtain the deviation. The PI controller generates a switch control signal. S8. The phase-shifting full-bridge converter module switches S1, S2, S3 and S4 are controlled by the phase-shifting modulator. S9. When the pulse load is in a light load state, control the switching transistor S. a / Switching transistor S b This allows energy to flow from the high-voltage DC bus output module to the energy storage capacitor C. s ; S10. When the pulse load is under heavy load, control the switching transistor S10. a / Switching transistor S b Energy is transferred from the energy storage capacitor C s The flow is directed to the high-voltage DC bus output module.

[0014] A third aspect of the present invention provides an electronic device, characterized in that it includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses.

[0015] A fourth aspect of the present invention provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and the computer program, when executed by a processor, is applicable to a buck-boost pulse power suppression circuit for an airborne high-voltage bus.

[0016] In this embodiment, the present invention, through a design structure in which a bidirectional Sepic converter is directly connected in parallel across the two ends of a high-voltage DC bus, enables the pulse load power suppression circuit to quickly and effectively suppress bus current ripple, reducing the impact of pulse load power variations on the power supply system and ensuring stable system operation. While effectively suppressing input current ripple, compared to topologies using traditional bidirectional Buck / Boost converters, the buck-boost operating mode effectively increases the voltage fluctuation range of the energy storage capacitor, thereby significantly reducing the required capacitance value and improving the power density of the pulse load power supply system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 It shows the parallel topology and power flow diagram; Figure 1 (a) is a diagram of a parallel topology; Figure 1 (b) is the power flow diagram of the parallel topology under heavy load; Figure 1(c) is the power flow diagram of the parallel topology under light load; Figure 2 It is a two-level topology and power flow diagram; Figure 2 (a) is a two-level topology diagram; Figure 2 (b) is the power flow diagram of a two-stage topology under heavy load; Figure 2 (c) is the power flow diagram of the two-stage topology under light load; Figure 3 This is a topology circuit diagram of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in one embodiment of this application. Figure 4 This is a schematic diagram of the working mode of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in an embodiment of this application. Figure 4 (a) is a light-load mode circuit diagram of a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application; Figure 4 (b) is a heavy-load mode circuit diagram of a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application; Figure 4 (c) is a waveform diagram of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application; Figure 5 This is a block diagram of the control principle of a phase-shifting full-bridge converter for a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in one embodiment of this application. Figure 6 This is a block diagram illustrating the control principle of a bidirectional Sepic converter for a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in one embodiment of this application. Figure 7 This is a waveform diagram of the bus input current when the pulse frequency is not connected to a bidirectional converter, according to an embodiment of this application. Figure 7 (a) is a waveform diagram of the bus input current when the pulse frequency is 10Hz and no bidirectional converter is connected, according to an embodiment of this application; Figure 7 (b) is a waveform diagram of the bus input current when the pulse frequency is 20Hz and no bidirectional converter is connected, according to an embodiment of this application; Figure 8 This application presents a simulation experiment waveform diagram according to an embodiment; Figure 8(a) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 30% proposed in an embodiment of this application; Figure 8 (b) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 50% proposed in an embodiment of this application; Figure 8 (c) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 70% proposed in an embodiment of this application; Figure 8 (d) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 30% proposed in an embodiment of this application; Figure 8 (e) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 50% proposed in an embodiment of this application; Figure 8 (f) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 70% proposed in an embodiment of this application; Figure 9 This is a circuit diagram of a conventional bidirectional Buck / Boost converter proposed in one embodiment of this application; Figure 10 This application presents a simulation waveform diagram of a conventional bidirectional Buck / Boost converter according to an embodiment of the present application. Figure 10 (a) is a simulation waveform diagram of a conventional bidirectional Buck / Boost converter when the pulse frequency is 10Hz according to an embodiment of this application; Figure 10 (b) is a simulation waveform diagram of a conventional bidirectional Buck / Boost converter when the pulse frequency is 20Hz, according to an embodiment of this application; Figure 11 This is a schematic diagram of an electronic device according to this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Please refer to Figure 3 , Figure 3 This is a topology diagram of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, proposed in one embodiment of this application. Figure 3As shown, a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses includes: a high-voltage DC bus output module, a phase-shifted full-bridge DC / DC converter module, a bidirectional Sepic converter module, and a pulse load module; The high-voltage DC bus output module is connected to the input terminal of the phase-shifted full-bridge DC / DC converter module and the bidirectional Sepic converter module, respectively. The output terminal of the phase-shifted full-bridge DC / DC converter module is connected to the pulse load module.

[0021] In this embodiment, i bus For the DC bus input current, V in i is the DC bus voltage. in i is the input current of the phase-shifted full-bridge converter. b For compensating the current of the bidirectional EPIC converter, V o The voltage across the pulse load, i o This is the pulse load current.

[0022] Furthermore, the phase-shifted full-bridge DC / DC converter module includes switching transistors S1, S2, S3, and S4, inductor L3, diodes D1, D2, D3, and D4, and transformer T1; The drains of both switching transistors S1 and S2 are connected to the high-voltage DC bus output module. The source of switching transistor S1 is connected to one end of inductor L3 and the drain of switching transistor S3. The source of switching transistor S2 is connected to one end of the primary winding of transformer T1 and the drain of switching transistor S4. The other end of inductor L3 is connected to the other end of the primary winding of transformer T1. The source of switching transistor S4 is connected to the source of switching transistor S3 and the high-voltage DC bus output module. One end of the secondary winding of transformer T1 is connected to the anode of diode D1 and the cathode of diode D3. The cathode of diode D1 is connected to the cathode of diode D2 and the pulse load module. The anode of diode D2 is connected to the other end of the secondary winding of transformer T1 and the cathode of diode D4. The anode of diode D3 is connected to the anode of diode D4 and the pulse load module.

[0023] Further, please refer to Figure 5 , Figure 5 This is a block diagram illustrating the control principle of a phase-shifting full-bridge converter for a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in one embodiment of this application. Figure 5 As shown, the control circuit of the phase-shifted full-bridge DC / DC converter module includes: a voltage loop comparator, a voltage loop PI regulator, a current loop comparator, a current loop PI regulator, and a phase-shift modulator; Used to transfer pulse load voltage v oand given voltage v o_ref The difference voltage is obtained by subtracting the values ​​using a voltage loop comparator. The compensation current reference value i is obtained through the voltage loop PI regulator. o_ref , will pulse load current i o With the compensation current reference quantity i o_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The switching control signal is obtained through the current loop PI regulator, and then driven by the phase-shift modulator to drive the switching transistors S1, S2, S3 and S4 of the phase-shift full-bridge converter module.

[0024] Furthermore, the bidirectional Sepic converter module includes: inductor L1, inductor L2, and switching transistor S. a Switch S b Intermediate capacitor C m and energy storage capacitor C s ; One end of the inductor L1 is connected to the high-voltage DC bus output module, and the other end of the inductor L1 is connected to the switching transistor S. a The drain and intermediate capacitor C m One end is connected to the intermediate capacitor C. m The other end is connected to one end of inductor L2 and the switch S respectively. b The source connection of the switch S b The drain and energy storage capacitor C s The positive terminal is connected to the energy storage capacitor C. s The negative terminals are respectively connected to the other end of inductor L2 and switch S. a The source and high-voltage DC bus output module are connected.

[0025] Further, please refer to Figure 6 , Figure 6 This is a block diagram illustrating the control principle of a bidirectional Sepic converter for a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in one embodiment of this application. Figure 6 As shown, the control module of the bidirectional Sepic converter module includes: a voltage loop control unit and a current loop control unit; The voltage loop control unit includes a voltage loop comparator and a voltage loop PI regulator; used to convert the energy storage capacitor voltage v Cs and reference voltage v Cs_ref The difference voltage is obtained by performing a difference operation using a voltage loop comparator. The first compensation current reference quantity i is generated by adjusting the voltage loop PI regulator. b_ref1 ; The current loop control unit includes a second-order low-pass filter, a current loop comparator, a current loop PI regulator, and a PWM modulator; it is used to input the phase-shifted full-bridge converter module's input current i in The input current i is obtained through a second-order low-pass filter. in The continuous value of the input current i in The continuous value and reference current i in_ref The second compensation current reference value i is obtained by subtraction using a current loop comparator. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtracting the current through a current loop comparator. b_ref The bidirectional Sepic converter module will compensate for the current i b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The current loop PI regulator generates a switching control signal, which is then used by a PWM modulator to control the switching transistor S of the bidirectional Sepic converter module. a and switching transistor S b Drive it.

[0026] Further, please refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the operating mode of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses, as proposed in an embodiment of this application; wherein, Figure 4 (a) is a light-load mode circuit diagram of a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application; Figure 4 (b) is a heavy-load mode circuit diagram of a buck-boost pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application; Figure 4 (c) is a waveform diagram of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage buses according to an embodiment of this application. Figure 4 As shown, the operating modes of the bidirectional Sepic converter module include: Light load mode: Part of the energy from the high-voltage DC bus output module is transmitted through inductors L1 and L2 and the intermediate capacitor C. m To the energy storage capacitor C s Charge; Heavy load mode: Energy storage capacitor C s Discharge occurs, and the bidirectional Sepic converter module charges the high-voltage DC bus output module.

[0027] In this embodiment, pulse load current i is included. o Bidirectional EPIC converter compensation current i b DC bus input current ibus and the energy storage capacitor voltage v cs . According to the change of the pulsed load current i o , it is divided into two operating modes.

[0028] Mode I [0 < t < t1]: The operating mode of the pulsed load power converter is as shown in Figure 4 (a). In this stage, the pulsed load is in a light load state. At this time, part of the energy of the front-stage power supply system is supplied to the load, and the remaining energy passes through the inductor L1, inductor L2 and the intermediate capacitor C m to charge the energy storage capacitor C s . The current flow direction is from the front-stage power supply V in to the capacitor C s . When the switching transistor S a is turned on, the front-stage power supply system V in charges the inductor L1, and the intermediate capacitor C m charges the inductor L2. Since there is no loop in C s , its voltage remains unchanged; when the switching transistor S b is turned on, the inductors L1 and L2 release energy to charge the capacitor C s .

[0029] Mode II [t1 < t < t2]: The operating mode of the bidirectional converter is as shown in Figure 4 (b). In this stage, the pulsed load is in a heavy load state. At this time, all the energy of the front-stage power supply system is supplied to the load, and at the same time the energy storage capacitor C s discharges, and the current flow direction is from the capacitor C s to the front-stage power supply V in . When the switching transistor S a is turned on, the inductor L1 charges the front-stage power supply system V in , and the inductor L2 charges the intermediate capacitor C m ; when the switching transistor S b is turned on, the energy storage capacitor C s charges the inductor L2, and the intermediate capacitor C m charges the inductor L1 and the front-stage power supply V in .

[0030] The embodiment of the present disclosure also provides a buck-boost type pulsed power suppression method applicable to an airborne high-voltage bus, including the following steps: S1. Real-time collect the energy storage capacitor voltage v Cs , the input current i in of the phase-shifted full-bridge DC / DC converter module, the compensation current i b of the bidirectional Sepic converter module, the pulsed load voltage v o and the pulsed load current i o ; S2, Extract the input current i of the phase-shifted full-bridge converter module in Input current i in Continuous values; S3, change the voltage v of the energy storage capacitor Cs and reference voltage v Cs_ref Perform the subtraction to generate the difference voltage. The difference voltage PI regulation is performed to generate the first compensation current reference quantity i b_ref1 ; S4, Input current i in The continuous value and reference current i in_ref The second compensation current reference quantity i is obtained by performing the difference operation. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtraction. b_ref The bidirectional Sepic converter module will compensate for the current i. b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The PI controller generates a switch control signal. S5. Control the switching transistor S of the bidirectional Sepic converter module via a PWM modulator. a and switching transistor S b On and off; S6, the pulse load voltage v o and given voltage v o_ref The difference voltage is obtained by performing subtraction. The reference quantity i for generating the compensation current is obtained through PI regulation. o_ref ; S7, the pulse load current i o With the compensation current reference quantity i o_ref The difference is used to obtain the deviation. The PI controller generates a switch control signal. S8. The phase-shifting full-bridge converter module switches S1, S2, S3 and S4 are controlled by the phase-shifting modulator. In this embodiment, the function of the phase-shifting full-bridge converter S1-S4 is to control the switching transistors S1-S4 so that the input energy matches the energy demand of the pulse load in real time, and to ensure that the pulse load voltage is stable at a given value.

[0031] S9. When the pulse load is in a light load state, control the switching transistor S. a / Switching transistor S b This allows energy to flow from the high-voltage DC bus output module to the energy storage capacitor C. s ; S10. When the pulse load is under heavy load, control the switching transistor S10. a / Switching transistor S b Energy is transferred from the energy storage capacitor C s The flow is directed to the high-voltage DC bus output module.

[0032] For example, a simulation platform for pulse power suppression circuit was built based on Matlab / Simulink, and simulation experiments were conducted under pulse load power of 540 / 1540W. The specific simulation parameters of the platform are shown in Table 1.

[0033] Table 1 Simulation Platform Parameters

[0034] First, a simulation test was performed on the circuit without the bidirectional converter to detect the effect of the pulsed load on the bus input current ripple. The bus input current waveform with a 50% pulsed load duty cycle is shown in the figure. Figure 7 , Figure 7 This is a waveform diagram of the bus input current when the pulse frequency is not connected to a bidirectional converter, according to an embodiment of this application. Figure 7 (a) is a waveform diagram of the bus input current when the pulse frequency is 10Hz and no bidirectional converter is connected, according to an embodiment of this application; Figure 7 (b) is a waveform diagram of the bus input current when the pulse frequency is 20Hz and no bidirectional converter is connected, according to an embodiment of this application.

[0035] The step-up / step-down pulse power suppression circuit for airborne high-voltage DC buses proposed in this invention was simulated and tested under operating conditions of pulse frequencies of 10Hz and 20Hz, and duty cycles of 30%, 50%, and 70%, respectively. The bus input current i bus Bidirectional Sepic converter compensation current i b and energy storage capacitor voltage v Cs Please refer to the simulation waveform. Figure 8 , Figure 8 This is a simulation experiment waveform diagram proposed in one embodiment of this application. Wherein, Figure 8 (a) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 30% proposed in an embodiment of this application; Figure 8 (b) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 50% proposed in an embodiment of this application; Figure 8 (c) is a simulation waveform diagram of a pulse frequency of 10Hz and a duty cycle of 70% proposed in an embodiment of this application; Figure 8 (d) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 30% proposed in an embodiment of this application; Figure 8(e) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 50% proposed in an embodiment of this application; Figure 8 (f) is a simulation waveform diagram of a pulse frequency of 20Hz and a duty cycle of 70% proposed in an embodiment of this application.

[0036] In comparison, a simulation test was performed on a circuit connected to a traditional bidirectional Buck / Boost converter. Please refer to the circuit diagram below. Figure 9 , Figure 9 This is a circuit diagram of a conventional bidirectional Buck / Boost converter proposed in one embodiment of this application. Simulation tests were conducted under operating conditions of pulse frequencies of 10Hz and 20Hz and a duty cycle of 50%, with the bus input current i... bus Bidirectional Sepic converter compensation current i b and energy storage capacitor voltage v Cs Please refer to the simulation waveform. Figure 10 , Figure 10 This is a simulation waveform diagram of a conventional bidirectional Buck / Boost converter proposed in one embodiment of this application. Figure 10 (a) is a simulation waveform diagram of a conventional bidirectional Buck / Boost converter when the pulse frequency is 10Hz according to an embodiment of this application; Figure 10 (b) is a simulation waveform diagram of a conventional bidirectional Buck / Boost converter when the pulse frequency is 20Hz, according to an embodiment of this application.

[0037] Table 2 shows a comparison of simulation data under various operating conditions. The simulation results clearly demonstrate that the pulse power suppression circuit proposed in this invention can effectively suppress input current pulsation while significantly reducing the required capacitance value by increasing the voltage fluctuation range of the energy storage capacitor, thereby improving the power density of the pulse load power supply system, reducing costs, and ensuring system stability.

[0038] Table 2 Simulation Experiment Data

[0039] This disclosure also provides an electronic device, please refer to... Figure 11 , Figure 11 This is a schematic diagram of an electronic device illustrated in an embodiment of this disclosure. For example... Figure 11 As shown, the electronic device 100 includes a memory 110 and a processor 120. The memory 110 and the processor 120 are connected via a bus for communication. The memory 110 stores a computer program that can run on the processor 120 to implement the steps in the buck-boost pulse power suppression circuit for airborne high-voltage buses disclosed in this embodiment.

[0040] The disclosed embodiments also provide a computer-readable storage medium that, when executed by a processor of a computer device, enables the computer device to perform steps as described in the embodiments of this disclosure for a buck-boost pulse power suppression circuit applicable to an airborne high-voltage bus.

[0041] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, electronic devices, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0042] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0043] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0044] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0045] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0046] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0047] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0048] The above provides a detailed description of a step-up / step-down pulse power suppression circuit suitable for airborne high-voltage busbars provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A step-up / step-down pulse power suppression circuit suitable for airborne high-voltage busbars, characterized in that, include: High-voltage DC bus output module, phase-shifted full-bridge DC / DC converter module, bidirectional Sepic converter module, and pulse load module; The high-voltage DC bus output module is connected to the input terminal of the phase-shifted full-bridge DC / DC converter module and the bidirectional Sepic converter module, respectively. The output terminal of the phase-shifted full-bridge DC / DC converter module is connected to the pulse load module.

2. The step-up / step-down pulse power suppression circuit for airborne high-voltage buses according to claim 1, characterized in that, The phase-shifted full-bridge DC / DC converter module includes switching transistors S1, S2, S3, and S4, inductor L3, diodes D1, D2, D3, and D4, and transformer T1. The drains of both switching transistors S1 and S2 are connected to the high-voltage DC bus output module. The source of switching transistor S1 is connected to one end of inductor L3 and the drain of switching transistor S3. The source of switching transistor S2 is connected to one end of the primary winding of transformer T1 and the drain of switching transistor S4. The other end of inductor L3 is connected to the other end of the primary winding of transformer T1. The source of switching transistor S4 is connected to the source of switching transistor S3 and the high-voltage DC bus output module. One end of the secondary winding of transformer T1 is connected to the anode of diode D1 and the cathode of diode D3. The cathode of diode D1 is connected to the cathode of diode D2 and the pulse load module. The anode of diode D2 is connected to the other end of the secondary winding of transformer T1 and the cathode of diode D4. The anode of diode D3 is connected to the anode of diode D4 and the pulse load module.

3. The step-up / step-down pulse power suppression circuit for airborne high-voltage buses according to claim 2, characterized in that, The control circuit of the phase-shifted full-bridge DC / DC converter module includes: a voltage loop comparator, a voltage loop PI regulator, a current loop comparator, a current loop PI regulator, and a phase-shift modulator; Used to transfer pulse load voltage v o and given voltage v o_ref The difference voltage is obtained by subtracting the values ​​using a voltage loop comparator. The compensation current reference value i is obtained through the voltage loop PI regulator. o_ref , will pulse load current i o With the compensation current reference quantity i o_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The switching control signal is obtained through the current loop PI regulator, and then driven by the phase-shift modulator to drive the switching transistors S1, S2, S3 and S4 of the phase-shift full-bridge converter module.

4. The step-up / step-down pulse power suppression circuit for airborne high-voltage buses according to claim 1, characterized in that, The bidirectional Sepic converter module includes: inductor L1, inductor L2, and switching transistor S. a Switch S b Intermediate capacitor C m and energy storage capacitor C s ; One end of the inductor L1 is connected to the high-voltage DC bus output module, and the other end of the inductor L1 is connected to the switching transistor S. a The drain and intermediate capacitor C m One end is connected to the intermediate capacitor C. m The other end is connected to one end of inductor L2 and the switch S respectively. b The source connection of the switch S b The drain and energy storage capacitor C s The positive terminal is connected to the energy storage capacitor C. s The negative terminals are respectively connected to the other end of inductor L2 and switch S. a The source and high-voltage DC bus output module are connected.

5. The step-up / step-down pulse power suppression circuit for airborne high-voltage buses according to claim 4, characterized in that, The control module of the bidirectional Sepic converter module includes: a voltage loop control unit and a current loop control unit; The voltage loop control unit includes a voltage loop comparator and a voltage loop PI regulator; used to convert the energy storage capacitor voltage v Cs and reference voltage v Cs_ref The difference voltage is obtained by performing a difference operation using a voltage loop comparator. The first compensation current reference quantity i is generated by adjusting the voltage loop PI regulator. b_ref1 ; The current loop control unit includes a second-order low-pass filter, a current loop comparator, a current loop PI regulator, and a PWM modulator; it is used to input the phase-shifted full-bridge converter module's input current i in The input current i is obtained through a second-order low-pass filter. in The continuous value of the input current i in The continuous value and reference current i in_ref The second compensation current reference value i is obtained by subtraction using a current loop comparator. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtracting the current through a current loop comparator. b_ref The bidirectional Sepic converter module will compensate for the current i b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The current loop PI regulator generates a switching control signal, which is then used by a PWM modulator to control the switching transistor S of the bidirectional Sepic converter module. a and switching transistor S b Drive it.

6. The step-up / step-down pulse power suppression circuit for airborne high-voltage buses according to claim 4, characterized in that, The operating modes of the bidirectional Sepic converter module include: Light load mode: Part of the energy from the high-voltage DC bus output module is transmitted through inductors L1 and L2 and the intermediate capacitor C. m To the energy storage capacitor C s Charge; Heavy load mode: Energy storage capacitor C s Discharge occurs, and the bidirectional Sepic converter module charges the high-voltage DC bus output module.

7. The method for suppressing step-up / step-down pulse power applicable to airborne high-voltage buses according to any one of claims 1-6, characterized in that, Includes the following steps: S1. Real-time acquisition of energy storage capacitor voltage v Cs Phase-shifted full-bridge DC / DC converter module input current i in Bidirectional Sepic converter module compensation current i b Pulse load voltage v o and pulse load current i o ; S2, Extract the input current i of the phase-shifted full-bridge converter module in Continuous values; S3, change the voltage v of the energy storage capacitor Cs and reference voltage v Cs_ref Perform the subtraction to generate the difference voltage. The difference voltage PI regulation is performed to generate the first compensation current reference quantity i b_ref1 ; S4, Input current i in The continuous value and reference current i in_ref The second compensation current reference quantity i is obtained by performing the difference operation. b_ref2 The second compensation current reference quantity i b_ref2 and the first compensation current reference quantity i b_ref1 The reference current i is obtained by subtraction. b_ref ; Compensate current i of the bidirectional Sepic converter module b and reference current i b_ref The deviation is obtained by subtracting the values ​​using a current loop comparator. The PI controller generates a switch control signal. S5. Control the switching transistor S of the bidirectional Sepic converter module via a PWM modulator. a and switching transistor S b On and off; S6, the pulse load voltage v o and given voltage v o_ref The difference voltage is obtained by performing subtraction. The reference quantity i for generating the compensation current is obtained through PI regulation. o_ref ; S7, the pulse load current i o With the compensation current reference quantity i o_ref The difference is used to obtain the deviation. The PI controller generates a switch control signal. S8. The phase-shifting full-bridge converter module switches S1, S2, S3 and S4 are controlled by the phase-shifting modulator. S9. When the pulse load is in a light load state, control the switching transistor S. a / Switching transistor S b This allows energy to flow from the high-voltage DC bus output module to the energy storage capacitor C. s ; S10. When the pulse load is under heavy load, control the switching transistor S10. a / Switching transistor S b Energy is transferred from the energy storage capacitor C s The flow is directed to the high-voltage DC bus output module.

8. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the buck-boost pulse power suppression circuit suitable for airborne high-voltage buses as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the buck-boost pulse power suppression circuit for airborne high-voltage buses as described in any one of claims 1 to 7.

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