A dynamic reconfigurable signal processing platform based on ZYNQ architecture

Abstract

The application discloses a dynamic reconfigurable signal processing platform based on a ZYNQ architecture, and belongs to the technical field of digital signal processing.The dynamic reconfigurable signal processing platform comprises a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit.After radio frequency signals are fed in from an antenna end, the radio frequency signals enter the channel preprocessing unit, a balun circuit and a filter group are adopted, preselected filtering, amplification and conditioning are performed on the radio frequency signals, and the signals are extracted and sent to the high-speed AD sampling unit.The high-speed AD sampling unit converts accepted analog signals into digital signals and transmits the digital signals to the ZYNQ-PL logic unit, and the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are connected through an AXI bus.The ZYNQ-PL logic unit is composed of a static area and three dynamic areas, mainly realizes the logic part of a functional waveform, and completes the reconstruction and loading of the functional waveform.The ZYNQ-PS algorithm processing unit completes algorithm processing, and realizes the modulation, demodulation and functional algorithm implementation of the functional waveform.

Description

Technical Field

[0001] This application belongs to the field of digital signal processing technology, and in particular relates to a dynamically reconfigurable signal processing platform based on the ZYNQ architecture. Background Technology

[0002] The integrated radio frequency system is an important component of the aircraft avionics system. It adopts an integrated and modular design concept, integrating voice communication, radio navigation, surveillance and other functions to complete specific flight missions. It is an important system to ensure aircraft safety and perform aircraft take-off and landing missions.

[0003] The signal processing platform is the information processing center of the integrated radio frequency system, responsible for the real-time response and processing of a large amount of flight data and commands. The platform's technical level and processing capabilities are crucial to aircraft safety and mission execution efficiency. Traditional signal processing platforms adopt a multi-channel FPGA+DSP design architecture, with different functional threads running on each independent channel. The cross-channel function reconstruction process is complex, and functions must be deconstructed on the original channel before execution on the new channel. This results in a certain period of interruption, typically around 2-5 seconds, which can significantly impact the implementation and execution of critical tasks.

[0004] Traditional platform functions are complex to reconfigure across channels, which cannot meet the system's requirements for dynamic, real-time and uninterrupted function reconfiguration. In addition, they are relatively large in size, weight and power consumption, which cannot meet the requirements of highly integrated RF system, real-time task performance and reliability. Summary of the Invention

[0005] The purpose of this application is to overcome the problems of existing technologies by disclosing a dynamically reconfigurable signal processing platform based on the ZYNQ architecture. This application utilizes the partially reconfigurable characteristics of ZYNQ-PL to perform time-division multiplexing of limited logic resources. This improves the reliability and robustness of integrated radio frequency system tasks while reducing system power consumption and size, meeting the rapid response requirements of modern aircraft missions.

[0006] The objective of this application is achieved through the following technical solution:

[0007] A dynamically reconfigurable signal processing platform based on the ZYNQ architecture, the dynamically reconfigurable signal processing platform comprising: a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit, and a ZYNQ-PS algorithm processing unit;

[0008] In this process, after the radio frequency signal is fed in from the antenna end, it enters the channel preprocessing unit. The balun circuit and filter bank are used to pre-filter, amplify and condition the radio frequency signal, and the extracted signal is sent to the high-speed AD sampling unit.

[0009] The high-speed AD acquisition unit converts the received analog signal into a digital signal and transmits it to the ZYNQ-PL logic unit via the JESD204B bus. The ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are connected via the AXI bus.

[0010] The ZYNQ-PL logic unit consists of one static area and three dynamic areas. It mainly implements the logic part of the functional waveform, including AD data framing, digital and data exchange, and external RF component control, and completes the reconstruction and loading of the functional waveform. The ZYNQ-PS algorithm processing unit completes the algorithm processing and realizes the modulation, demodulation, and functional algorithm implementation of the functional waveform.

[0011] According to a preferred embodiment, the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are implemented by a ZYNQ chip, which is divided into a ZYNQ-PL logic unit part and a ZYNQ-PS algorithm processing part.

[0012] According to a preferred embodiment, the ZYNQ-PL logic unit portion is arranged with a dynamic region 1, a dynamic region 2, and a static region.

[0013] The static area contains fixed basic resources, including underlying interfaces, clock configurations, and system reset resources. During functional refactoring, the static area program remains unchanged, while different functional programs are dynamically loaded and refactored in dynamic area 1 and dynamic area 2.

[0014] According to a preferred embodiment, the ZYNQ-PS algorithm processing unit includes ARM1 and ARM2.

[0015] The ZYNQ-PS algorithm processing unit utilizes the multi-tasking capabilities of the ARM53 dual-core processor. It implements C-level telemetry and control (T / C) and ATC functions on ARM1, and L-level T / C and Ka-level satellite communication functions on ARM2. Furthermore, based on the functional program requirements of different mission phases, it dynamically loads the corresponding logic resources for different functional programs into the dynamic area of ​​the ZYNQ-PL logic unit.

[0016] If dynamic zone 1 is reconstructed, it will be reconstructed from the default C measurement and control to ATC. During the reconstruction, the normal use of the L measurement and control function in dynamic zone 2 will not be affected. If dynamic zone 2 is reconstructed, it will be reconstructed from the default L measurement and control to Ka satellite communication.

[0017] According to a preferred embodiment, the functional reconfiguration process of the ZYNQ chip includes:

[0018] Upon power-up, initialization is performed first, and the board-level management program is run to reset the hardware components such as the ZYNQ unit, phase-locked loop unit, and memory unit.

[0019] Then the ZYNQ-PS algorithm processing unit waits to receive the reconstruction instruction. If it does not receive it, it continues to wait. After receiving the reconstruction instruction, it starts the reconstruction of the ZYNQ-PS algorithm processing unit program. First, it runs the Golden program of the Flash sector. After the Golden program starts, it guides the loading of the reconstruction function program. Then it determines whether the ZYNQ-PL logic unit loading completion flag is 1. If it is not 1, it reloads the function program. If it is 1, it proceeds to the next step to start loading the ZYNQ-PS program.

[0020] The ZYNQ-PS algorithm processing unit executes its internal BootLoader program, which guides the functional program stored in the external FLASH to be loaded onto the PS end. Then, it checks whether the PS program loading completion flag is 1. If the flag is not 1, the functional program is reloaded. If the flag is 1, it means that the loading is complete, and the program jumps to the PS program entry point to start program execution. It then jumps back to the functional waveform entry address to start executing the newly loaded waveform program. The signal processing channel completes the functional waveform reconstruction.

[0021] According to a preferred embodiment, the high-speed AD sampling unit adopts a time interleaving algorithm to complete platform sampling by stacking the number of moving blades; and adopts an adaptive clock mismatch calibration algorithm to perform error calibration on the multi-channel AD sampling data.

[0022] According to a preferred embodiment, the error calibration process for multi-channel AD sampling data using an adaptive clock mismatch calibration algorithm includes:

[0023] X(t) is the analog input signal to be sampled, which is sampled by two ADC channels, ADC1 and ADC2, respectively. The digital signal is output after ADC sampling. digital signals As the reference input of the LMS algorithm module, the output is calculated by the LMS algorithm module. Compared to clock error and the corresponding error and digital signal The signals are fed together into the reconstruction filter H to calculate the calibrated digital signal. Then, it is time-division multiplexed by a digital multiplexer MUX, and finally outputs the calibrated and synthesized AD sampling signal X(K).

[0024] According to a preferred embodiment, the LMS algorithm module employs the following improved LMS algorithm for clock error correction. Calculations, including:

[0025] Step 1: Calculate the channel sampling clock: First, initialize the clock error of the objective function. According to the formula Calculate the sampling clock ,in The current clock error is j, and the number of algorithm iterations is j.

[0026] Step 2: Calculate the objective function and gradient. Define the objective function, V, as follows:

[0027]

[0028] in, It is the signal after being processed by the reconstruction filter H. It is a reference signal;

[0029] Calculate the gradient; calculate the gradient value of the objective function.

[0030]

[0031] Step 3: Update the clock error and adaptively adjust the learning rate based on the magnitude of the gradient.

[0032]

[0033] in, It is a preset threshold;

[0034] Calculate the update clock error:

[0035]

[0036] By iteratively calculating the above three steps, the current value can be obtained. Used for subsequent reconstruction filter H to calibrate digital signals Clock error.

[0037] According to a preferred embodiment, the frequency response of the reconstruction filter H is:

[0038]

[0039] in Angular frequency, For clock error, The sampling period.

[0040] According to a preferred embodiment, the balun circuit uses a JBL2012-2-06 / 28 broadband balun chip with a frequency range from 5MHz to 6000MHz;

[0041] The high-speed AD sampling unit uses the B9361NY ADC chip, and the sampled signal is sent to the ZYNQ-PL logic unit via JESD204B.

[0042] The data processing section consists of ZYNQ-PL logic units and ZYNQ-PS algorithm processing units, and uses the FMQL architecture processor JFMQL100T900-N as the control chip.

[0043] The aforementioned main solution and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed in this application. Those skilled in the art, after understanding the solution of this application, will realize that there are many combinations based on the prior art and common general knowledge, all of which are technical solutions to be protected in this application, and will not be exhaustively listed here.

[0044] The beneficial effects of this application are:

[0045] The advantages of the dynamically reconfigurable signal processing platform based on the ZYNQ architecture in this application are mainly as follows: 1) Resource saving: Functional waveforms can be dynamically reconfigured locally in real time in the dynamic area, realizing time-sharing reconstruction of multiple functional waveforms on the same chip, which is suitable for resource-constrained scenarios; 2) Improved real-time performance and response speed: The reconstruction time is usually in the microsecond or millisecond range, meeting the requirements of integrated RF systems for rapid task switching, and other functions can continue to work normally without being affected when one function is reconfigured; 3) Dynamic upgrade and reduced power consumption: The FPGA logic can be updated or switched without downtime, supporting online system upgrades. Power consumption optimization allows for dynamic activation of required functional modules and shutdown of idle logic according to task requirements, reducing ineffective power consumption.

[0046] The dynamically reconfigurable signal processing platform based on the ZYNQ architecture improves the reliability and robustness of integrated radio frequency system missions, while reducing system power consumption and size, meeting the rapid response requirements of modern aircraft missions. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of the dynamically reconfigurable signal processing platform of this application;

[0048] Figure 2 This is a block diagram of the AD sampling algorithm in this application;

[0049] Figure 3 This is a schematic diagram of the hardware architecture of the signal processing platform of this application;

[0050] Figure 4 This is a schematic diagram of the signal processing platform software initialization process of this application;

[0051] Figure 5 This application relates to the SCA software architecture;

[0052] Figure 6 This is a schematic diagram of the functional distribution of the dynamic region of the ZYNQ chip in this application;

[0053] Figure 7This is the functional restructuring strategy and process of this application. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0055] It should be noted that, in order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0056] refer to Figure 1 As shown, this application discloses a dynamic reconfigurable signal processing platform based on the ZYNQ architecture. The dynamic reconfigurable signal processing platform includes: a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit, and a ZYNQ-PS algorithm processing unit.

[0057] The radio frequency signal (frequency range 30MHz~6GHz) is fed into the antenna and enters the channel preprocessing unit. The balun circuit and filter bank are used to pre-filter, amplify and condition the radio frequency signal, and the extracted signal is sent to the high-speed AD sampling unit.

[0058] The high-speed AD acquisition unit can achieve a sampling frequency of up to 6Gbps and a sampling accuracy of 12 bits. It converts the analog signal into a digital signal and transmits it to the ZYNQ-PL logic unit through the JESD204B bus. By utilizing the fixed delay and phase consistency characteristics of the JESD204B bus, it ensures that the three AD signals arrive at the back end with phase consistency and data synchronization.

[0059] The information processing section mainly comprises the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit. The ZYNQ-PL logic unit consists of one static area and three dynamic areas, primarily implementing the logic of the functional waveform, including AD data framing, digital and data exchange, and external RF component control, completing the reconstruction and loading of the functional waveform. The ZYNQ-PS algorithm processing unit performs algorithm processing, implementing the modulation, demodulation, and functional algorithm implementation of the functional waveform.

[0060] Preferably, refer to Figure 2As shown, the high-speed AD sampling unit adopts a time interleaving algorithm and completes platform sampling by stacking the number of moving blades; and adopts an adaptive clock mismatch calibration algorithm to perform error calibration on the multi-channel AD sampling data.

[0061] Furthermore, the error calibration process for multi-channel AD sampling data, employing an adaptive clock mismatch calibration algorithm, includes:

[0062] X(t) is the analog input signal to be sampled, which is sampled by two ADC channels, ADC1 and ADC2, respectively. The digital signal is output after ADC sampling. digital signals As the reference input of the LMS algorithm module, the output is calculated by the LMS algorithm module. Compared to clock error and the corresponding error and digital signal The signals are fed together into the reconstruction filter H to calculate the calibrated digital signal. Then, it is time-division multiplexed by a digital multiplexer MUX, and finally outputs the calibrated and synthesized AD sampling signal X(K).

[0063] Preferably, the LMS algorithm module employs the following improved LMS algorithm for clock error correction. Calculations, including:

[0064] Step 1: Calculate the channel sampling clock: First, initialize the clock error of the objective function. According to the formula Calculate the sampling clock ,in The current clock error is j, and the number of algorithm iterations is j.

[0065] Step 2: Calculate the objective function and gradient. Define the objective function, V, as follows:

[0066]

[0067] in, It is the signal after being processed by the reconstruction filter H. It is a reference signal;

[0068] Calculate the gradient; calculate the gradient value of the objective function.

[0069]

[0070] Step 3: Update the clock error and adaptively adjust the learning rate based on the magnitude of the gradient.

[0071]

[0072] in, It is a preset threshold;

[0073] Calculate the update clock error:

[0074]

[0075] By iteratively calculating the above three steps, the current value can be obtained. Used for subsequent reconstruction filter H to calibrate digital signals Clock error.

[0076] Preferably, the frequency response of the reconstruction filter H is: ,in Angular frequency, For clock error, The sampling period.

[0077] refer to Figure 3 As shown, the hardware design of the signal processing platform is disclosed. The radio frequency signal is processed by a balun circuit and then enters an ADC sampling circuit for AD conversion. The converted digital signal is transmitted to the FPGA minimum system via a JESD204B bus. The FPGA minimum system has an external 4Gbit DDR3 memory and a 1Gbit BPI FLASH unit for FPGA program loading and data storage. The FPGA minimum system interacts with the DSP minimum system via the EMIF bus. The DSP minimum system has external DDR3 memory and NOR FLASH memory for function algorithm processing and data caching. The management unit circuit manages the board's health status, voltage monitoring, and temperature monitoring. The power management unit controls low-power modes. The memory management circuit controls and allocates the board's memory resources. The management unit circuit interacts with the DSP minimum system via the SPI bus. The power management circuit converts the primary power supply (voltage +12VDC) to the secondary power supply (voltage +5V / 3.3V / 2.5V / 1.8V / 1.0V / 0.75VDC) and controls the power-on sequence of each secondary power supply. The clock divider / multiplier circuit divides and multiplies the input clock, dividing / multiplying the input 100MHz clock to the frequency required by the system.

[0078] Because the AD input frequency range requirement is wide (30MHz-6GHz), an ultra-low insertion loss balun circuit was selected in the hardware design to preprocess, match and filter the input single-ended RF signal. The JBL2012-2-06 / 28 broadband balun chip from Shenzhen Zhenhua Fu Company was selected, with a frequency range from 5MHz to 6000MHz to meet the design requirements.

[0079] The preprocessed RF signal is fed into the ADC sampling circuit for AD conversion. The ADC chip used is the B9361NYB from the Beijing Institute of Microelectronics Technology. The B9361NYB is a high-performance, highly integrated wideband programmable RF transceiver with dual transmit and receive capabilities, designed for integrated RF systems. It operates at frequencies from 70MHz to 6GHz, supports channel bandwidths from less than 200kHz to 56MHz, and integrates a 12-bit DAC and ADC. It is a wideband RF 2x2 transceiver capable of zero-IF sampling of RF signals. The sampled signal is sent to the ZYNQ-PL logic unit via a JESD204B. The JESD204B's high-speed serial bus output parameters are matched to the receiving channel rate, and the SYSREF and SYNCB inputs provide management and control, enabling synchronous design of sampling data from the three AD devices.

[0080] The data processing section consists of the ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit, using the Fudan Microelectronics FMQL architecture processor JFMQL100T900-N as the core control chip. The internal structure of the JFMQL100T900-N chip is divided into two parts: the programmable logic ZYNQ-PL and the processor ZYNQ-PS. The ZYNQ-PL part is the programmable logic processing unit, providing 350K of logic resources, 19.2Mb of block RAM, 900 DSP processor resources, and 16 pairs of GTX high-speed interfaces. The PL and PS communicate via the AXI bus, following the standard AXI protocol, supporting a data bit width of 32bit or 64bit, and the main port capacity is: 8 reads and 8 writes. The ZYNQ-PS contains a quad-core high-performance ARM53 processor, each with a high-performance, low-power core and a single-core computing power of 1.9 DMIPS / MHz. It has an independent 32K L1 cache and 256K L2 cache. The PS part can be connected to external memory such as DDR3 and SPI-FLASH to complete the program burning and loading.

[0081] The ZYNQ-PL section mainly completes functions such as AD data framing, digital preprocessing, and RF front-end control, and completes the JESD204B interface adaptation and data buffering with B9361NYB; the ZYNQ-PS processor section completes the processing of functional waveform algorithms, including algorithms for measurement and control functions, navigation functions, approach guidance, and other functions.

[0082] The power supply circuit completes the conversion from the primary power supply of 28VDC to the secondary power supply. It uses an isolated DC-DC converter (DPX30-28T5-6V5-12FM from Beijing Xinle Energy Technology Co., Ltd.) to perform voltage conversion, surge suppression, overvoltage / overcurrent protection and other functions.

[0083] The phase-locked loop circuit completes the conversion and distribution of the board-level clock. It uses the GM4526CN from Chengdu Zhenxin Technology to convert and distribute the 100MHz input clock signal. It outputs the sampling clock and synchronous sampling clock of B9361NYB to provide the clock source for the JESD204B dedicated chip. At the same time, it outputs 156.25MHz, 100MHz, 66MHz, and 33MHz to provide the clock source for the ZYNQ processor of the signal processing platform.

[0084] The management unit circuit uses the JFM7K325T8-AS chip from Fudan Microelectronics, which communicates with the DSP via the SPI interface to complete functions such as health status management and multi-version program switching control of the board.

[0085] The signal processing platform software initialization process is as follows: Figure 4 As shown. After the module is powered on, it first completes the initialization of the underlying hardware. After initialization, the management unit program runs. The management unit program controls each power supply to start in a preset power-on sequence. To ensure the normal operation of the platform, the FPGA minimum system circuit is started first. After the FPGA starts, the DSP minimum system circuit and AD circuit are started, completing the initial default AD sampling rate and DSP operating mode configuration. After the module starts, the management unit controls the FPGA and DSP to load the default version. After the program loads successfully, the management unit controls the initialization of the clock phase-locked loop chip, outputting the required sampling rate clock; the AD chip is initialized, configuring the default sampling rate and accuracy; the FPGA registers and DSP registers are initialized, including the initialization operations of the external interface, DDR controller, GTH interface, SRIO interface, and JESE204B interface. After all chips are initialized, the power-on BIT self-test is automatically executed, and the self-test result is reported. At this point, the module initialization and startup are complete.

[0086] The signal processing platform adopts the SCA software architecture, constructing a micro-standard software system through a hierarchical approach. It achieves software and hardware decoupling through the open architecture of SCA, abstracts and encapsulates domain knowledge through domain models and framework technologies, provides numerous reusable software components and supporting tool software, and accelerates the development, configuration, and deployment of its software platform by establishing a system model and employing a model-driven approach. This constitutes a standardized platform container environment for waveform operation, promoting the portability and reusability of waveform components. The software architecture is as follows: Figure 5 As shown.

[0087] The SCA software architecture consists of the following parts: a) Hardware platform: Composed of three ZYNQ compute nodes, storage nodes, system management nodes, and IO control nodes. Nodes exchange data via high-speed interconnect buses (such as RIO / PCIE / AS5643 / Ethernet); b) Platform basic software: Provides the basic operating environment for the software, including embedded operating systems and hardware drivers, enabling hardware access and online updates; c) SCA general technology software: The core software of the SCA architecture, decoupling the upper-layer software from the lower-layer hardware through MHAL and MOCB communication middleware, constructing and deconstructing waveforms on the platform through core control software, and establishing network topology and managing logical relationships through network configuration software; d) Platform management software: Implements health management, resource scheduling, and refactoring management through business framework software, providing the operating foundation for AD configuration, clock configuration, platform control management services, and platform BIT management software; e) Waveform application software: Provides the operating platform for multiple waveform application software, providing control interfaces for the RF front-end, a functional algorithm running platform, and realizing the functions of various sensors in the integrated RF system.

[0088] This application's partitioned dynamic loading technology re-divides the on-chip resources of the ZYNQ chip, differentiating them into several small regions for specific program layout and routing, thereby achieving time-sharing loading of different functions on a single chip. By dynamically and locally reconfiguring the logic within the reconstructed regions, it meets the needs of multi-functional, large-scale applications. For example... Figure 6 As shown, the ZYNQ chip is divided into the logic unit ZYNQ-PL and the processor ZYNQ-PS. The ZYNQ-PL is laid out with dynamic area 1, dynamic area 2, and static area. The static area contains fixed basic resources, including low-level interfaces, clock configurations, system reset resources, etc. The program in the static area remains unchanged during function reconfiguration. Different function programs are dynamically loaded and reconfigured in dynamic area 1 and dynamic area 2. The ZYNQ-PS fully utilizes the multi-tasking performance of the ARM53 dual-core processor, running function C measurement and control (default function) and ATC function on ARM1, and running L on ARM2. The telemetry, tracking, and command (TT&C) function (default function) and Ka-band satellite communication function are dynamically loaded with the corresponding logical resources of different function programs in the dynamic area of ​​the ZYNQ-PL section according to the functional program requirements of different mission stages of the aircraft. If dynamic area 1 is reconstructed from the default function C TT&C to the ATC function, the normal use of the L TT&C function in dynamic area 2 will not be affected during the reconstruction. Similarly, if the L TT&C function in dynamic area 2 is reconstructed, the normal use of the C TT&C function in dynamic area 1 will not be affected. The advantage of this is that the TT&C functions related to aircraft safety are not affected during the reconstruction of the dynamic area, which increases the stability and reliability of the integrated radio frequency system.

[0089] Dynamic loading of partitions allows for reconfiguration of designated areas of the ZYNQ-PL using new programs, while also allowing the current functions to continue running in the remaining space of the device. The advantage of this is that when the functions of dynamic area 1 are reconfigured, the normal operation of dynamic area 2 is not affected, ensuring the continuity of critical system functions and further expanding the inherent flexibility of ZYNQ-PL.

[0090] Dynamic reconfiguration refers to the time-division multiplexing of resources with different functional waveforms under system control and scheduling during different flight missions. Reconfiguration design is divided into two types: mission reconfiguration and fault reconfiguration. Mission reconfiguration refers to the reconfiguration of different functions based on the different general signal processing waveform requirements of the system during different flight phases, such as takeoff, cruise, and approach / landing. Fault reconfiguration refers to the system reconstructing the waveform of a high-priority function using existing resources when that function fails, thereby ensuring the execution of critical missions during flight.

[0091] The dynamic reconfiguration process is shown in Figure 7. After power-on, initialization is completed first, and the board-level management program is run to reset the hardware components such as the ZYNQ unit, phase-locked loop unit, and storage unit. Then, the ZYNQ-PS algorithm processing unit waits for a reconfiguration command. If no reconfiguration command is received, it continues to wait. Upon receiving the reconfiguration command, the ZYNQ-PL program reconfiguration is initiated. First, the Golden program in the Flash sector is run. After the Golden program starts, it bootstraps the reconfiguration function program. Then, it checks whether the ZYNQ-PL loading completion flag is 1. If it is not 1, the function program is reloaded. If it is 1, it proceeds to the next step to load the ZYNQ-PS program. The ZYNQ-PS executes the internal BootLoader program, which bootstraps the function program stored in the external FLASH to the PS end for loading. Then, it checks whether the PS program loading completion flag is 1. If the flag is not 1, the function program is reloaded. If the flag is 1, it indicates that loading is complete, and the program jumps to the PS program entry point to start program execution. It then jumps back to the function waveform entry address to start executing the newly loaded waveform program. The signal processing channel completes the function waveform reconfiguration.

[0092] To address the real-time and uninterrupted requirements for reconfiguration of critical functions in integrated radio frequency (RF) systems, this application proposes a dynamically reconfigurable signal processing platform based on the ZYNQ platform. Utilizing ZYNQ-PL partially reconfigurable technology, time-division multiplexing of limited on-chip resources enables chip-level reconstruction and real-time updating of multiple functional waveforms, achieving a balance between resource sharing and flexible function reconfiguration in integrated RF systems. This platform can be widely applied in aerospace, shipbuilding, and weaponry fields.

[0093] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A dynamically reconfigurable signal processing system based on the ZYNQ architecture, characterized in that, The dynamically reconfigurable signal processing system includes: a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit, and a ZYNQ-PS algorithm processing unit; In this process, after the radio frequency signal is fed in from the antenna end, it enters the channel preprocessing unit. The balun circuit and filter bank are used to pre-filter, amplify and condition the radio frequency signal, and the extracted signal is sent to the high-speed AD sampling unit. The high-speed AD acquisition unit converts the received analog signal into a digital signal and transmits it to the ZYNQ-PL logic unit via the JESD204B bus. The ZYNQ-PL logic unit and the ZYNQ-PS algorithm processing unit are connected via the AXI bus. The ZYNQ-PL logic unit consists of one static area and three dynamic areas, which realize the logic part of the functional waveform, including AD data framing, digital and data exchange, and external RF component control, and complete the reconstruction and loading of the functional waveform; the ZYNQ-PS algorithm processing unit completes the algorithm processing, realizing the modulation, demodulation, and functional algorithm implementation of the functional waveform; The ZYNQ-PL logic unit and ZYNQ-PS algorithm processing unit are implemented by a ZYNQ chip. The ZYNQ chip is divided into a ZYNQ-PL logic unit part and a ZYNQ-PS algorithm processing part. The ZYNQ-PL logic unit layout includes dynamic area 1, dynamic area 2, and static area. The static area contains fixed basic resources, including underlying interfaces, clock configurations, and system reset resources. During functional refactoring, the static area program remains unchanged, while different functional programs are dynamically loaded and refactored in dynamic area 1 and dynamic area 2. The ZYNQ-PS algorithm processing unit includes ARM1 and ARM2. The ZYNQ-PS algorithm processing unit utilizes the multi-tasking capabilities of the ARM53 dual-core processor. It implements C-level telemetry and control (T / C) and ATC functions on ARM1, and L-level T / C and Ka-level satellite communication functions on ARM2. Furthermore, based on the functional program requirements of different mission phases, it dynamically loads the corresponding logic resources for different functional programs into the dynamic area of ​​the ZYNQ-PL logic unit. If dynamic zone 1 is reconstructed, it will be reconstructed from the default C measurement and control to ATC. During the reconstruction, the normal use of the L measurement and control function in dynamic zone 2 will not be affected. If dynamic zone 2 is reconstructed, it will be reconstructed from the default L measurement and control to Ka satellite communication. The functional reconfiguration process of the ZYNQ chip includes: Upon power-up, initialization is performed first, and the board-level management program is run to reset the hardware components such as the ZYNQ unit, phase-locked loop unit, and memory unit. Then the ZYNQ-PS algorithm processing unit waits to receive the reconstruction instruction. If it does not receive it, it continues to wait. After receiving the reconstruction instruction, it starts the reconstruction of the ZYNQ-PS algorithm processing unit program. First, it runs the Golden program of the Flash sector. After the Golden program starts, it guides the loading of the reconstruction function program. Then it determines whether the ZYNQ-PL logic unit loading completion flag is 1. If it is not 1, it reloads the function program. If it is 1, it proceeds to the next step to start loading the ZYNQ-PS program. The ZYNQ-PS algorithm processing unit executes its internal BootLoader program, which guides the functional program stored in the external FLASH to be loaded onto the PS end. Then, it checks whether the PS program loading completion flag is 1. If the flag is not 1, the functional program is reloaded. If the flag is 1, it means that the loading is complete, and the program jumps to the PS program entry point to start program execution. It then jumps back to the functional waveform entry address to start executing the newly loaded waveform program. The signal processing channel completes the functional waveform reconstruction.

2. The dynamically reconfigurable signal processing system based on the ZYNQ architecture as described in claim 1, characterized in that, The high-speed AD sampling unit adopts a time interleaving algorithm and completes platform sampling by stacking the number of moving blades; and adopts an adaptive clock mismatch calibration algorithm to perform error calibration on multi-channel AD sampling data.

3. The dynamically reconfigurable signal processing system based on the ZYNQ architecture as described in claim 2, characterized in that, The error calibration process for multi-channel AD sampling data using an adaptive clock mismatch calibration algorithm includes: X(t) is the analog input signal to be sampled, which is sampled by two ADC channels, ADC1 and ADC2, respectively. The digital signal is output after ADC sampling. digital signals As the reference input of the LMS algorithm module, the output is calculated by the LMS algorithm module. Compared to clock error and the corresponding error and digital signal The signals are fed together into the reconstruction filter H to calculate the calibrated digital signal. Then, it is time-division multiplexed by a digital multiplexer MUX, and finally outputs the calibrated and synthesized AD sampling signal X(K).

4. The dynamically reconfigurable signal processing system based on the ZYNQ architecture as described in claim 3, characterized in that, The LMS algorithm module employs the following improved LMS algorithm to address clock errors. Calculations, including: Step 1: Calculate the channel sampling clock: First, initialize the clock error of the objective function. According to the formula Calculate the sampling clock ,in The current clock error is j, and the number of algorithm iterations is j. Step 2: Calculate the objective function and gradient. Define the objective function, V, as follows: in, It is the signal after being processed by the reconstruction filter H. It is a reference signal; Calculate the gradient; calculate the gradient value of the objective function. Step 3: Update the clock error and adaptively adjust the learning rate based on the magnitude of the gradient. in, It is a preset threshold; Calculate the update clock error: By iteratively calculating the above three steps, the current value can be obtained. Used for subsequent reconstruction filter H to calibrate digital signals Clock error.

5. The dynamically reconfigurable signal processing system based on the ZYNQ architecture as described in claim 3, characterized in that, The frequency response of the reconstruction filter H is: in Angular frequency, For clock error, The sampling period.

6. The dynamically reconfigurable signal processing system based on the ZYNQ architecture as described in claim 1, characterized in that, The balun circuit uses the JBL2012-2-06 / 28 broadband balun chip, with a frequency range from 5MHz to 6000MHz; The high-speed AD sampling unit uses the B9361NY ADC chip, and the sampled signal is sent to the ZYNQ-PL logic unit via JESD204B. The data processing section consists of ZYNQ-PL logic units and ZYNQ-PS algorithm processing units, and uses the FMQL architecture processor JFMQL100T900-N as the control chip.

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