Semiconductor structure and forming method thereof
By forming low-dielectric sidewalls after forming source-drain epitaxial layers, the performance degradation problem in P-type silicon-germanium trench structures is solved, the morphology and capacitance are optimized, and the DC and AC performance of semiconductor devices is improved.
Patent Information
- Application Number
- CN202410614932.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-16
- Publication Date
- 2025-11-21
AI Technical Summary
The morphology of existing P-type silicon-germanium trench structures leads to a decrease in the DC and AC performance of semiconductor devices, especially due to insufficient overlap area between the source/drain epitaxial layers and the gate structure and increased capacitance.
Anisotropic etching is used to form source and drain openings, and low-dielectric sidewalls are formed after the source and drain epitaxial layers are formed to avoid loss of the low-dielectric sidewalls during the etching process. At the same time, the low-dielectric sidewalls isolate the source and drain epitaxial layers from the gate structure, thereby optimizing the morphology and reducing capacitance.
It improves the DC and AC performance of semiconductor devices, increases the overlap area between the source/drain epitaxial layers and the gate structure, reduces capacitance, and enhances overall performance.
Smart Images
Figure CN121001391A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, higher requirements are placed on the feature size and morphology of devices in integrated circuits. When the cross-sectional morphology of the P-type silicon germanium recess (PMOS Silicon Recess, or PSR) is U-shaped, the distance between the top of the PMOS silicon recess and the gate, and the distance between the bottom of the PMOS silicon germanium recess and the gate are both small. This results in a larger overlap area between the source / drain epitaxial layer formed in the PMOS silicon germanium recess and the gate, thereby increasing the DC performance of the semiconductor device.
[0003] However, the current P-type silicon-germanium groove structure needs to be optimized. Summary of the Invention
[0004] The problem solved by this invention is to provide a method for forming a semiconductor structure to improve the morphology of the P-type groove structure and enhance the performance of semiconductor devices.
[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a fin located on the substrate, and a gate structure located on the fin; forming an initial first sidewall on the fin, the sidewall of the gate structure, and the gate structure; after forming the initial first sidewall, etching the fin on both sides of the gate structure to form source / drain openings and a first sidewall located on the sidewall of the gate structure; forming a source / drain epitaxial layer within the source / drain openings; and after forming the source / drain epitaxial layer, forming a low-dielectric sidewall located on the first sidewall.
[0006] Optionally, the thickness of the first sidewall is in the range of 2nm to 12nm.
[0007] Optionally, in the step of etching the fins on both sides of the gate structure, the etching is anisotropic etching.
[0008] Optionally, the process parameters for the anisotropic etching are as follows: the process time range is 10 seconds to 100 seconds; the process gas includes gaseous hydrocarbons, halogen gases, and inert gases; the process gas flow rate range is 10 sccm to 500 sccm; and the electric field parameters include: the voltage range is 50V to 1000V; and the power range is 50W to 1000W.
[0009] Optionally, the sidewalls of the source / drain openings are perpendicular to the substrate surface.
[0010] Optionally, the step of etching the fins on both sides of the gate structure includes: using the mask layer above the gate structure as a mask, etching the fins on both sides of the gate structure to form source / drain openings located within the fins.
[0011] Optionally, in the step of forming the source-drain opening, the distance between the first sidewalls on the adjacent gate structure sidewalls is in the range of 10nm to 100nm.
[0012] Optionally, the low-dielectric sidewall includes a low-dielectric layer and a protective layer located on the low-dielectric layer.
[0013] Optionally, after forming the source / drain epitaxial layer but before forming the low-dielectric sidewall, the method further includes: forming an initial isolation layer on the source / drain epitaxial layer.
[0014] Optionally, the step of forming the low-dielectric sidewall includes: after forming the initial isolation layer, forming an initial low-dielectric sidewall on the first sidewall and the initial isolation layer; etching the initial low-dielectric sidewall and the initial isolation layer until the source-drain epitaxial layer is exposed, forming a low-dielectric sidewall on the first sidewall and an isolation layer between the source-drain epitaxial layer and the low-dielectric sidewall.
[0015] Optionally, in the step of forming an initial isolation layer on the source / drain epitaxial layer, the material of the initial isolation layer is silicon nitride, and the thickness of the initial isolation layer ranges from 2 nm to 10 nm.
[0016] Optionally, the thickness of the low-dielectric sidewall near the source / drain epitaxial layer is equal to the thickness of the side away from the source / drain epitaxial layer.
[0017] Optionally, the material of the source / drain epitaxial layer includes silicon-germanium.
[0018] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate; a fin located on the substrate and a gate structure located on the fin; a first sidewall located on the sidewall of the gate structure; source and drain epitaxial layers located in the fins on both sides of the gate structure; and a low-dielectric sidewall located on the first sidewall.
[0019] Optionally, the thickness of the first sidewall is in the range of 2nm to 12nm.
[0020] Optionally, the sidewalls of the source / drain epitaxial layer are perpendicular to the substrate surface.
[0021] Optionally, the low-dielectric sidewall includes a low-dielectric layer and a protective layer located on the low-dielectric layer.
[0022] Optionally, it may also include an isolation layer located between the source / drain epitaxial layer and the low-dielectric sidewall.
[0023] Optionally, the thickness of the low-dielectric sidewall near the source / drain epitaxial layer is equal to the thickness of the side away from the source / drain epitaxial layer.
[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0025] In the semiconductor structure formation method of the present invention, after forming the source / drain epitaxial layer, a low-dielectric sidewall is formed on the first sidewall. The low-dielectric sidewall is formed after etching the source / drain opening, which effectively prevents damage to the low-dielectric sidewall during the etching process and improves its performance. Furthermore, before forming the low-dielectric sidewall, the fin is etched to form the source / drain opening. During the formation of the source / drain opening, the fin sidewall does not have a low-dielectric sidewall, resulting in a larger etching space, which effectively reduces etching difficulty and improves the morphology of the formed source / drain opening.
[0026] In an optional embodiment of the present invention, the etching step of etching the fins on both sides of the gate structure is anisotropic etching. Etching the fins to form source / drain openings before the formation of low-dielectric sidewalls allows for a larger etching space. Anisotropic etching can form the required source / drain openings, avoiding the use of isotropic etching processes. It also ensures that the sidewalls of the source / drain openings are as perpendicular as possible to the substrate surface, effectively improving the morphology of the formed source / drain epitaxial layer. Increasing the overlap area between the gate structure and the source / drain epitaxial layer improves the DC performance of the semiconductor device.
[0027] In an optional embodiment of the present invention, the process parameters for the anisotropic etching are as follows: process time range: 10 seconds to 100 seconds; process gas includes gaseous hydrocarbons, halogen gases, and inert gases; process gas flow rate range: 10 sccm to 500 sccm; electric field parameters include: voltage range: 50V to 1000V; power range: 50W to 1000W. This anisotropic etching of the fins on both sides of the gate structure can achieve a significant improvement in the performance of the semiconductor device without changing the etching process parameters, thus improving the performance of the semiconductor device without increasing process costs.
[0028] In the semiconductor structure of the present invention, the source and drain epitaxial layers in the fins on both sides of the gate structure are separated from the gate structure by a first sidewall and a low-dielectric sidewall located on the first sidewall, which reduces the capacitance between the source and drain epitaxial layers and the gate structure and improves the AC performance of the semiconductor device.
[0029] In an optional embodiment of the present invention, the sidewalls of the source / drain epitaxial layer are perpendicular to the substrate surface. The difference between the distance from the bottom of the source / drain epitaxial layer to the adjacent sidewall of the gate structure and the distance from the top of the source / drain epitaxial layer to the adjacent sidewall of the gate structure is small, which optimizes the morphology of the source / drain epitaxial layer, increases the overlap area between the gate structure and the source / drain epitaxial layer, and improves the DC performance of the semiconductor device.
[0030] In an optional embodiment of the present invention, the thickness of the low-dielectric sidewall near the source / drain epitaxial layer is equal to the thickness of the side away from the source / drain epitaxial layer. The low-dielectric sidewall uniformly covers the first sidewall, and the low-dielectric sidewall has low loss, reducing the capacitance between the source / drain epitaxial layer and the gate structure, and improving the AC performance of the semiconductor device. Attached Figure Description
[0031] Figures 1 to 7 This is a cross-sectional schematic diagram of the various steps in the formation process of a semiconductor structure according to an embodiment.
[0032] Figures 8 to 14 This is a cross-sectional structural schematic diagram of each step in the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0033] As can be seen from the background art, there are problems with the morphology of P-type silicon-germanium trenches in the existing technology. The reasons for these problems will now be analyzed in conjunction with a semiconductor structure formation method:
[0034] Please refer to Figure 1 The system provides a substrate 100, a fin 101 located on the substrate 100, and a gate structure 102 located on the fin 101.
[0035] Please refer to Figure 2 An initial first sidewall 103 is formed on the fin 101, the sidewall of the gate structure 102, and the gate structure 102.
[0036] Please refer to Figure 3 After the initial first sidewall 103 is formed, an initial low dielectric sidewall 104 is formed on the initial first sidewall 103.
[0037] Please refer to Figures 4 to 6 After forming the initial low-dielectric sidewall 104, the fins 101 on both sides of the gate structure 102 are etched to form source / drain openings 106, a first sidewall 107 located on the sidewall of the gate structure 102, and a low-dielectric sidewall 108 located on the first sidewall 107. Figure 4 As shown, the initial first sidewalls 103 on the fins 101 on both sides of the gate structure 102 are etched until the fins 101 are exposed; as Figure 5As shown, the exposed fin 101 undergoes a first etching process to form an initial source / drain opening 105; as Figure 6 As shown, after the initial source / drain opening 105 is formed, the fin 101 exposed by the initial source / drain opening 105 is subjected to a second etching process to form the source / drain opening 106, the first sidewall 107 located on the sidewall of the gate structure 102, and the low-dielectric sidewall 108 located on the first sidewall 107.
[0038] Please refer to Figure 7 A source / drain epitaxial layer 109 is formed within the source / drain opening 106.
[0039] The first etching process is anisotropic etching; the second etching process is isotropic etching.
[0040] In the semiconductor structure formation method, a low-dielectric sidewall 108 is formed before forming the source / drain epitaxial layer 109. This results in a small initial source / drain opening 105 when the fin 101 is etched to form the initial source / drain opening 105. If the initial source / drain opening 105 is then subjected to isotropic etching, the isotropic etching will cause the cross-section of the formed source / drain opening 106 to be V-shaped. This results in the distance from the bottom of the source / drain epitaxial layer 109 formed in the source / drain opening 106 to the sidewall of the adjacent gate structure 102 being different from the distance from the top of the source / drain epitaxial layer 109 to the sidewall of the gate structure 102. The large difference in distance between the sidewalls of the adjacent gate structure 102 reduces the overlap area between the gate structure 102 and the source / drain epitaxial layer 109, thus reducing the DC performance of the semiconductor structure. Furthermore, the semiconductor structure formation method forms a low-dielectric sidewall 108 before forming the source / drain epitaxial layer 109. During the etching process of the initial low-dielectric sidewall 104 to form the source / drain opening 106, the initial low-dielectric sidewall 104 at the top corner of the fin 101 is excessively damaged, resulting in an increase in the capacitance between the source / drain epitaxial layer 109 and the gate structure 102, and simultaneously reducing the AC performance of the semiconductor device.
[0041] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a fin located on the substrate, and a gate structure located on the fin; forming an initial first sidewall on the fin, the sidewall of the gate structure, and the gate structure; after forming the initial first sidewall, etching the fin on both sides of the gate structure to form source / drain openings and a first sidewall located on the sidewall of the gate structure; forming a source / drain epitaxial layer within the source / drain openings; and after forming the source / drain epitaxial layer, forming a low-dielectric sidewall located on the first sidewall.
[0042] The present invention forms a low-dielectric sidewall on the first sidewall after forming the source / drain epitaxial layer, avoiding the process of etching the low-dielectric sidewall to form the source / drain opening. This reduces the loss of the low-dielectric sidewall at the top corner of the fin, lowers the capacitance between the source / drain epitaxial layer and the gate structure, and improves the AC performance of the semiconductor device. In the step of etching the fins on both sides of the gate structure, the etching is anisotropic. This anisotropic etching ensures that the sidewalls of the formed source / drain openings are as perpendicular as possible to the substrate surface. This minimizes the difference between the distance from the bottom of the source / drain epitaxial layer within the opening to the adjacent gate structure sidewall and the distance from the top of the source / drain epitaxial layer to the adjacent gate structure sidewall, optimizing the morphology of the source / drain epitaxial layer, increasing the overlap area between the gate structure and the source / drain epitaxial layer, and improving the DC performance of the semiconductor device.
[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0044] Please refer to Figure 8 The system provides a substrate 200, a fin 201 located on the substrate 200, and a gate structure 202 located on the fin 201.
[0045] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in this embodiment, the substrate 200 is made of silicon.
[0046] The fins 201 are partially exposed on both sides of the gate structure 202. In some embodiments, the fins have at least two gate structures 202, with adjacent gate structures 202 exposing a portion of the fins 201, and the extending direction of the fins 201 is perpendicular to the extending direction of the gate structures 202.
[0047] Specifically, in this embodiment, the semiconductor structure further includes a mask layer located on the gate structure 202. The mask layer is not removed after the gate structure 202 is formed, and serves to protect the gate structure 202. In this embodiment, the mask layer includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer. In other embodiments, the mask layer may be made of other materials.
[0048] Please refer to Figure 9 An initial first sidewall 203 is formed on the fin 201, the sidewall of the gate structure 202, and the gate structure 202.
[0049] The initial first sidewall 203 is formed by deposition. The material of the initial first sidewall 203 includes silicon nitride.
[0050] The initial first sidewall 203 has a thickness ranging from 2 nm to 12 nm. The thickness of the initial first sidewall 203 defines the thickness of the subsequently formed first sidewall 205. The thickness of the initial first sidewall 203 determines the distance from the sidewall of the subsequently formed source / drain epitaxial layer 206 to the sidewall of its adjacent gate structure 202.
[0051] Please refer to Figure 10 After the initial first sidewall 203 is formed (e.g.) Figure 9 As shown, the fins 201 on both sides of the gate structure 202 are etched to form source / drain openings 204 and a first sidewall 205 located on the sidewall of the gate structure 202.
[0052] The source / drain opening 204 provides a structural basis for forming the source / drain epitaxial layer 206.
[0053] The step of etching the fins 201 on both sides of the gate structure 202 includes: using the gate structure 202 as a mask, etching the fins 201 on both sides of the gate structure 202 to form source / drain openings 204 located in the fins 201.
[0054] like Figure 10 In some embodiments shown, the fin 201 has at least two gate structures 202. In the step of etching the fins 201 on both sides of the gate structure 202, the fins 201 between adjacent gate structures 202 are etched using the gate structure 202 as a mask, and the source / drain openings 204 are formed in the fins between adjacent fins 201.
[0055] In the step of etching the fins 201 on both sides of the gate structure 202, the etching is anisotropic etching. The process parameters for the anisotropic etching are: process time ranging from 10 to 100 seconds; process gases including gaseous hydrocarbons, halogen gases, and inert gases; process gas flow rate ranging from 10 sccm to 500 sccm; and electric field parameters including: voltage ranging from 50V to 1000V; and power ranging from 50W to 1000W. In some embodiments of the present invention, the process gas further includes nitrogen; and the inert gas includes helium. This anisotropic etching can achieve significant performance improvements in semiconductor devices without changing the etching process parameters, improving semiconductor device performance without increasing process costs.
[0056] In the step of forming the source / drain opening 204, the distance between the first sidewalls 205 on the sidewalls of adjacent gate structures 202 is in the range of 10 nm to 100 nm. The distance between the first sidewalls 205 on the sidewalls of adjacent gate structures 202 determines the size of the source / drain opening 204 in the extension direction of the fin 201.
[0057] The thickness of the first sidewall 205 is in the range of 2nm to 12nm. The function of the first sidewall 205 is to separate the gate structure 202 from the subsequently formed source / drain epitaxial layer 206 within the source / drain opening 204. The thickness of the first sidewall 205 is the distance between the sidewall of the source / drain opening 204 and the sidewall of the adjacent gate structure 202 along the extension direction of the fin 201. The thickness of the first sidewall 205 determines the distance between the sidewall of the subsequently formed source / drain epitaxial layer 206 and the adjacent gate structure 202.
[0058] Since only the first sidewall 205 is formed on the sidewall of the gate structure 202, the distance between adjacent gate structures 202 is the distance between the surfaces of the first sidewall 205 on the adjacent gate structures 202. The distance between adjacent gate structures 202 is large, and the space between adjacent gate structures 202 is large. In the step of etching the fins 201 on both sides of the gate structure 202, the source and drain openings 204 can be formed by anisotropic etching, without the need to use an isotropic etching process.
[0059] The sidewalls of the source / drain opening 204 are perpendicular to the surface of the substrate 200, such that the source / drain epitaxial layer 206 subsequently formed within the source / drain opening 204 (e.g., Figure 11 The difference between the distance from the bottom of the source / drain epitaxial layer 206 to the sidewall of the adjacent gate structure 202 and the distance from the top of the source / drain epitaxial layer 206 to the sidewall of the adjacent gate structure 202 is small, which optimizes the morphology of the source / drain epitaxial layer 206, increases the overlap area between the gate structure 202 and the source / drain epitaxial layer 206, and improves the DC performance of the semiconductor device.
[0060] Please refer to Figure 11 A source / drain epitaxial layer 206 is formed within the source / drain opening 204.
[0061] The source / drain epitaxial layer 206 is made of silicon-germanium. The formation process of the source / drain epitaxial layer 206 includes epitaxial growth.
[0062] Please refer to Figure 12 After the source / drain epitaxial layer 206 is formed, an initial isolation layer 207 is formed on the source / drain epitaxial layer 206.
[0063] The function of the initial isolation layer 207 is to separate the source / drain epitaxial layer 206 from the subsequently formed initial low-dielectric sidewall 208. The material of the initial low-dielectric sidewall 208 is not easy to grow on the material of the source / drain epitaxial layer 206, but is easier to grow on the material of the initial isolation layer 207. The presence of the initial isolation layer 207 improves the growth quality of the initial low-dielectric sidewall 208.
[0064] In the step of forming an initial isolation layer 207 located on the source / drain epitaxial layer 206, the material of the initial isolation layer 207 is silicon nitride, and the thickness of the initial isolation layer 207 ranges from 2 nm to 12 nm. The process for forming the initial isolation layer 207 includes deposition.
[0065] Please refer to Figures 13 to 14 After the source-drain epitaxial layer 206 is formed, a low-dielectric sidewall 211 is formed on the first sidewall 205.
[0066] The steps for forming the low-dielectric sidewall 211 include: as follows Figure 13 As shown, after the initial isolation layer 207 is formed, an initial low-dielectric sidewall 208 is formed on the first sidewall 205 and the initial isolation layer 207; as Figure 14 As shown, the initial low-dielectric sidewall 208 and the initial isolation layer 207 are etched until the source-drain epitaxial layer 206 is exposed, forming a low-dielectric sidewall 211 on the first sidewall 205 and an isolation layer 214 between the source-drain epitaxial layer 206 and the low-dielectric sidewall 211.
[0067] The function of the low-dielectric sidewall 211 is to reduce the capacitance between the source / drain epitaxial layer 206 and the gate structure 202, thereby improving the AC performance of the semiconductor device.
[0068] Compared to the process of first forming a low-dielectric sidewall and then etching it to form the source / drain opening, forming a low-dielectric sidewall 211 on the first sidewall 205 after forming the source / drain epitaxial layer 206 avoids the loss of the low-dielectric sidewall at the top corner of the fin during the process of etching the low-dielectric sidewall to form the source / drain opening, reduces the capacitance between the source / drain epitaxial layer 206 and the gate structure 202, and improves the AC performance of the semiconductor device.
[0069] The thickness of the low-dielectric sidewall 211 on the side near the source / drain epitaxial layer 206 is equal to the thickness on the side away from the source / drain epitaxial layer 206. The low-dielectric sidewall 211 uniformly covers the first sidewall 205. The low-dielectric sidewall 211 has low loss, reduces the capacitance between the source / drain epitaxial layer 206 and the gate structure 202, and improves the AC performance of the semiconductor device.
[0070] The initial low-dielectric sidewall 208 includes an initial low-dielectric layer 209 and an initial protective layer 210 located on the initial low-dielectric layer 209. The initial protective layer 210 is used to protect the initial low-dielectric layer 209. Specifically, in this embodiment, the initial protective layer 210 is a multilayer stacked structure, and the initial protective layer 210 includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer.
[0071] The process for forming the initial low-dielectric sidewall 208 includes deposition.
[0072] During the etching of the initial low-dielectric sidewall 208 and the initial isolation layer 207 until the source / drain epitaxial layer 206 is exposed, the etching is anisotropic etching, which reduces the loss of the low-dielectric sidewall 211 at the top corner of the fin 201.
[0073] The low-dielectric sidewall 211 includes a low-dielectric layer 212 and a protective layer 213 located on the low-dielectric layer 212. The protective layer 213 is used to protect the low-dielectric layer 212. Specifically, in this embodiment, the protective layer 213 is a multilayer stacked structure, and the protective layer 213 includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer.
[0074] The isolation layer 214 is made of silicon nitride. The thickness of the isolation layer 214 ranges from 2 nm to 12 nm.
[0075] Accordingly, embodiments of the present invention also provide a semiconductor structure, which can be formed by the above-described semiconductor structure formation method. The semiconductor structure includes: a substrate 200; a fin 201 located on the substrate 200 and a gate structure 202 located on the fin 201; a first sidewall 205 located on the sidewall of the gate structure 202; source / drain epitaxial layers 206 located within the fins 201 on both sides of the gate structure 202; and a low-dielectric sidewall 211 located on the first sidewall 205.
[0076] The semiconductor structure includes: substrate 200.
[0077] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in this embodiment, the substrate 200 is made of silicon.
[0078] The semiconductor structure includes a fin 201 located on the substrate 200 and a gate structure 202 located on the fin 201.
[0079] The adjacent gate structure 202 exposes a portion of the fin 201, and the extending direction of the fin 201 is perpendicular to the extending direction of the gate structure 202.
[0080] The semiconductor structure includes a first sidewall 205 located on the sidewall of the gate structure 202.
[0081] The semiconductor structure includes: source / drain epitaxial layers 206 located in the fins 201 on both sides of the gate structure 202.
[0082] The sidewalls of the source / drain epitaxial layer 206 are perpendicular to the surface of the substrate 200.
[0083] The distance between the first sidewalls 205 on the sidewalls of adjacent gate structures 202 is in the range of 10nm to 100nm. The distance between the first sidewalls 205 on the sidewalls of adjacent gate structures 202 determines the size of the source / drain epitaxial layer 206 in the extension direction of the fin 201.
[0084] The thickness of the first sidewall 205 is in the range of 2nm to 12nm. The thickness of the first sidewall 205 is the distance between the sidewall of the source / drain epitaxial layer 206 and the sidewall of the adjacent gate structure 202 along the extension direction of the fin 201.
[0085] The semiconductor structure includes a low-dielectric sidewall 211 located on the first sidewall 205.
[0086] The thickness of the low-dielectric sidewall 211 on the side closer to the source / drain epitaxial layer 206 is equal to the thickness on the side farther from the source / drain epitaxial layer 206.
[0087] The low-dielectric sidewall 211 includes a low-dielectric layer 212 and a protective layer 213 located on the low-dielectric layer 212.
[0088] Specifically, in this embodiment, the protective layer 213 is a multilayer stacked structure, and the protective layer 213 includes a silicon nitride layer and a silicon oxide layer located on the silicon nitride layer.
[0089] The semiconductor structure further includes an isolation layer 214 located between the source / drain epitaxial layer 206 and the low-dielectric sidewall 211.
[0090] The isolation layer 214 is made of silicon nitride. The thickness of the isolation layer 214 ranges from 2 nm to 12 nm.
[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate, a fin located on the substrate, and a gate structure located on the fin are provided; An initial first sidewall is formed on the fin, the sidewall of the gate structure, and the gate structure; After forming the initial first sidewall, the fins on both sides of the gate structure are etched to form source / drain openings and the first sidewall located on the sidewall of the gate structure. A source / drain epitaxial layer is formed within the source / drain opening; After the source-drain epitaxial layer is formed, a low-dielectric sidewall is formed on the first sidewall.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first sidewall is in the range of 2nm to 12nm.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the fins on both sides of the gate structure, the etching is anisotropic etching.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process parameters for the anisotropic etching are as follows: the process time ranges from 10 seconds to 100 seconds; the process gas includes gaseous hydrocarbons, halogen gases, and inert gases; the process gas flow rate ranges from 10 sccm to 500 sccm; and the electric field parameters include: a voltage range of 50V to 1000V and a power range of 50W to 1000W.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewalls of the source / drain openings are perpendicular to the substrate surface.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of etching the fins on both sides of the gate structure includes: using the mask layer above the gate structure as a mask, etching the fins on both sides of the gate structure to form source / drain openings located in the fins.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of forming the source-drain opening, the distance between the first sidewalls on the sidewalls of adjacent gate structures is in the range of 10nm to 100nm.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The low-dielectric sidewall includes a low-dielectric layer and a protective layer located on the low-dielectric layer.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the source / drain epitaxial layer and before forming the low-dielectric sidewall, the method further includes: forming an initial isolation layer located on the source / drain epitaxial layer.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The steps for forming the low-dielectric sidewall include: after forming the initial isolation layer, forming an initial low-dielectric sidewall on the first sidewall and the initial isolation layer; etching the initial low-dielectric sidewall and the initial isolation layer until the source / drain epitaxial layer is exposed, forming a low-dielectric sidewall on the first sidewall and an isolation layer between the source / drain epitaxial layer and the low-dielectric sidewall.
11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming an initial isolation layer on the source / drain epitaxial layer, the material of the initial isolation layer is silicon nitride, and the thickness of the initial isolation layer ranges from 2 nm to 10 nm.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the low-dielectric sidewall near the source / drain epitaxial layer is equal to the thickness of the side away from the source / drain epitaxial layer.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The source / drain epitaxial layer is made of silicon-germanium.
14. A semiconductor structure, characterized in that, include: Substrate; A fin located on the substrate and a gate structure located on the fin; The first sidewall is located on the sidewall of the gate structure; Source and drain epitaxial layers located in the fins on both sides of the gate structure; The low-dielectric sidewall located on the first sidewall.
15. The semiconductor structure as described in claim 14, characterized in that, The thickness of the first sidewall is in the range of 2nm to 12nm.
16. The semiconductor structure as claimed in claim 14, characterized in that, The sidewalls of the source / drain epitaxial layer are perpendicular to the substrate surface.
17. The semiconductor structure as claimed in claim 14, characterized in that, The low-dielectric sidewall includes a low-dielectric layer and a protective layer located on the low-dielectric layer.
18. The semiconductor structure as described in claim 14, characterized in that, Also includes: An isolation layer located between the source / drain epitaxial layer and the low-dielectric sidewall.
19. The semiconductor structure as described in claim 14 or 16, characterized in that, The thickness of the low-dielectric sidewall near the source / drain epitaxial layer is equal to the thickness of the side away from the source / drain epitaxial layer.