Back contact solar cell, method of manufacturing the same, and photovoltaic module

Abstract

The embodiment of the present application relates to the photovoltaic field, and provides a back contact solar cell, a preparation method thereof and a photovoltaic module, the method comprising: providing a substrate, the substrate comprising opposite front and back surfaces, the back surface comprising a first region and a non-first region; sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate, and removing the first mask layer corresponding to the non-first region by laser; removing at least the first doped conductive layer corresponding to the non-first region, and the remaining first doped conductive layer forming a first emitter; sequentially stacking a second doped conductive layer and a second mask layer on the side of the remaining first mask layer away from the first emitter and the non-first region, the materials of the first mask layer and the second mask layer independently comprising at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; removing at least the second mask layer corresponding to the first region by laser; removing at least the second doped conductive layer corresponding to the first region, and the remaining second doped conductive layer forming a second emitter.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaics, and in particular to a back contact solar cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] In the conventional preparation process of a back contact (BC) solar cell, laser patterning technology is widely used in the film opening process, aiming to accurately remove the thin film in a specific area to form a current path, connecting the positive and negative poles of the cell. However, the current laser film opening technology has a series of challenges, especially when processing silicon solar cells. In the laser film opening process, the mask layer is ablated under the action of laser to form the required pattern, but this process is often accompanied by the side effect of thermal effect, causing micro-cracks and lattice defects in the edge area of the cell, thereby affecting the performance and reliability of the cell. SUMMARY

[0003] The embodiments of the present application provide a back contact solar cell, a preparation method thereof and a photovoltaic module, which at least help to improve the performance of the back contact solar cell.

[0004] According to some embodiments of the present application, the embodiments of the present application provide a preparation method of a back contact solar cell, comprising: providing a substrate, the substrate comprising opposite front and back surfaces, the back surface comprising a first area and a non-first area; sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate, and removing the first mask layer corresponding to the non-first area by laser; removing at least the first doped conductive layer corresponding to the non-first area, and the remaining first doped conductive layer forming a first emitter; sequentially stacking a second doped conductive layer and a second mask layer on the side of the remaining first mask layer away from the first emitter and the non-first area, the materials of the first mask layer and the second mask layer independently comprising at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; removing at least the second mask layer corresponding to the first area by laser; removing at least the second doped conductive layer corresponding to the first area, and the remaining second doped conductive layer forming a second emitter.

[0005] In some embodiments, sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate comprises: forming the first doped conductive layer on the back surface of the substrate; forming a first silicate glass layer on the side of the first doped conductive layer away from the substrate; and forming a first buffer layer on the side of the first silicate glass layer away from the first doped conductive layer, the first buffer layer comprising at least one of an amorphous silicon layer, a nanocrystalline silicon layer and a silicon carbide layer.

[0006] In some embodiments, forming a first silicate glass layer on a side of the first doped conductive layer away from the substrate comprises: forming the first silicate glass layer with a thickness of 30-100 nm and a doping concentration of 1e19-1e21cm-3 on the side of the first doped conductive layer away from the substrate by a low pressure chemical vapor deposition process; and forming a first buffer layer on a side of the first silicate glass layer away from the first doped conductive layer comprises: forming the first buffer layer with a thickness of 0.1-5 nm and a hydrogen content of 5%-10% on the side of the first silicate glass layer away from the first doped conductive layer by a low pressure chemical vapor deposition process. -3

[0007] In some embodiments, before forming the first doped conductive layer on a back surface of the substrate, the method further comprises: forming a first tunneling oxide layer on the back surface of the substrate, the first doped conductive layer being located on a surface of the first tunneling oxide layer away from the substrate; and removing at least the first doped conductive layer corresponding to the non-first region comprises: removing the first buffer layer corresponding to the first region, the first doped conductive layer corresponding to the non-first region, and the first tunneling oxide layer by a pre-cleaning and an alkali etching process, so that the non-first region and the first silicate glass layer are exposed on a surface away from the substrate.

[0008] In some embodiments, sequentially stacking a second doped conductive layer and a second mask layer on a side of the remaining first mask layer away from the first emitter and on the non-first region comprises: forming the second doped conductive layer on a side of the remaining first mask layer away from the first emitter, on a side of the remaining first mask layer, and on the non-first region; forming a second silicate glass layer on a side of the second doped conductive layer away from the substrate; and forming a second buffer layer on a side of the second silicate glass layer away from the second doped conductive layer, the second buffer layer comprising at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer.

[0009] ​In some embodiments, before forming the second doped conductive layer on the side of the remaining first mask layer away from the first emitter, on the side surface of the remaining first mask layer, and on the non-first region, the method further includes: forming a second tunneling oxide layer on the side of the remaining first mask layer away from the first emitter, on the side surface of the remaining first mask layer, and on the non-first region, the second doped conductive layer being located on the surface of the second tunneling oxide layer away from the substrate; the non-first region includes a spacer region and a second region, the spacer region being located between the first region and the second region; at least the second doped conductive layer corresponding to the first region is removed, including: removing the second buffer layer corresponding to the second region, the second doped conductive layer corresponding to the first region and the spacer region, and the second tunneling oxide layer by an alkaline etching process, so that the spacer region, the remaining first silicate glass layer, and the remaining second silicate glass layer are exposed; texturing the spacer region and the front side of the substrate; and removing the remaining first silicate glass layer and the remaining second silicate glass layer by acid etching.

[0010] In some embodiments, removing at least the second mask layer corresponding to the first region by laser includes: removing the second mask layer corresponding to the first region and the interval region by laser.

[0011] In some embodiments, the method further includes: stacking a passivation layer and an anti-reflection layer on the surfaces of the first emitter and the second emitter away from the substrate, on the spacer region, and on the front side of the substrate; forming a first electrode on the side of the anti-reflection layer away from the first emitter, and forming a second electrode on the side of the anti-reflection layer away from the second emitter, wherein the first electrode is electrically connected to the first emitter, and the second electrode is electrically connected to the second emitter; and performing photo-annealing on the battery structure having the first electrode and the second electrode formed thereon.

[0012] According to some embodiments of this application, another aspect of this application provides a back-contact solar cell, wherein the back-contact solar cell is prepared using any of the back-contact solar cell preparation methods described above.

[0013] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, formed by connecting a plurality of back-contact solar cells; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film away from the battery string.

[0014] The technical solution provided in this application has at least the following advantages: By introducing a first mask layer and a second mask layer including at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide, since amorphous silicon, nanocrystalline silicon, or silicon carbide materials have good thermal conductivity and thermal stability, during the process of removing the first mask layer and the second mask layer by laser, at least part of the energy of the laser acting on the opening edge region will be absorbed by these materials, thereby reducing the thermal stress in the opening edge region and significantly reducing the degree of lattice damage and lattice defect density in the opening edge region during the laser opening process. This improves both the battery manufacturing yield and the battery open-circuit voltage, thereby improving the battery conversion efficiency. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a method for fabricating a back-contact solar cell according to an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the structure obtained after providing a substrate in the fabrication method of a back contact solar cell provided in one embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the structure obtained after forming the first doped conductive layer in the fabrication method of the back contact solar cell provided in one embodiment of this application;

[0019] Figure 4 This is a schematic diagram of the structure obtained after forming the first mask layer in the method for fabricating a back contact solar cell provided in one embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the structure obtained after removing the first mask layer corresponding to the non-first region in the fabrication method of the back contact solar cell provided in one embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the structure obtained after at least removing the first doped conductive layer corresponding to the non-first region in the fabrication method of the back contact solar cell provided in one embodiment of this application.

[0022] Figure 7 This is a schematic diagram of the structure obtained after forming the second doped conductive layer in the fabrication method of the back contact solar cell provided in one embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the structure obtained after forming the second mask layer in the method for fabricating a back contact solar cell provided in one embodiment of this application;

[0024] Figure 9 This is a schematic diagram of the structure obtained after at least removing the second mask layer corresponding to the first region in the fabrication method of the back contact solar cell provided in one embodiment of this application.

[0025] Figure 10 This is a schematic diagram of the structure obtained after at least removing the second doped conductive layer corresponding to the first region in the fabrication method of the back contact solar cell provided in one embodiment of this application.

[0026] Figure 11 This is a schematic diagram of the structure obtained after forming a passivation layer in the method for fabricating a back contact solar cell provided in one embodiment of this application;

[0027] Figure 12 This is a schematic diagram of the structure obtained after forming the anti-reflection layer in the method for fabricating a back-contact solar cell provided in one embodiment of this application;

[0028] Figure 13 This is a schematic diagram of the structure obtained after forming the first electrode and the second electrode in the fabrication method of the back contact solar cell provided in one embodiment of this application.

[0029] The above figures include the following reference numerals:

[0030] 10. Substrate; 11. First doped conductive layer; 12. First mask layer; 13. First emitter; 14. Second doped conductive layer; 15. Second mask layer; 16. Second emitter; 17. First silicate glass layer; 18. First buffer layer; 19. First tunneling oxide layer; 20. Second silicate glass layer; 21. Second buffer layer; 22. Second tunneling oxide layer; 23. Passivation layer; 24. Anti-reflection layer; 25. First final oxide layer; 26. First intermediate glass layer; 27. First intermediate buffer layer; 28. Second intermediate buffer layer; 29. ​​Second intermediate glass layer; 30. Second final oxide layer; 31. First electrode; 32. Second electrode. Detailed Implementation

[0031] As is known from the background technology, in the fabrication process of back contact solar cells, when a laser is used to pattern mask layers such as BSG (borosilicate glass) or PSG (phosphosilicate glass), the thermal radiation effect in the edge region will cause the local temperature to rise sharply, which will induce lattice defects or microcracks such as nonradiative recombination centers inside the silicon wafer. These defects will cause the carrier recombination in the edge region to be intensified, resulting in a high loss of cell efficiency.

[0032] To address the above problems, this application provides a method for fabricating a back-contact solar cell, comprising: providing a substrate, the substrate including a front side and a back side, the back side including a first region and a non-first region; sequentially stacking a first doped conductive layer and a first mask layer on the back side of the substrate, and removing the first mask layer corresponding to the non-first region by laser; removing at least the first doped conductive layer corresponding to the non-first region, the remaining first doped conductive layer forming a first emitter; sequentially stacking a second doped conductive layer and a second mask layer on the side of the remaining first mask layer away from the first emitter and on the non-first region, wherein the materials of the first mask layer and the second mask layer independently include at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide; removing at least the second mask layer corresponding to the first region by laser; removing at least the second doped conductive layer corresponding to the first region, the remaining second doped conductive layer forming a second emitter.

[0033] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0036] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0037] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0038] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the terms in the embodiments of this application can be understood according to the specific circumstances.

[0039] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, thin film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0040] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0041] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "part" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0042] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] This application provides a method for fabricating a back-contact solar cell. Figure 1 This is a flowchart illustrating a method for fabricating a back-contact solar cell according to an embodiment of this application. Figures 2 to 13 This is a schematic diagram of the structure after each process step in a method for fabricating a back-contact solar cell according to an embodiment of this application. Figures 1 to 13 As shown, the method includes the following steps:

[0044] Step S201: As Figure 2 As shown, a substrate 10 is provided, the substrate 10 including opposing front and back sides, the back side including a first region and a non-first region;

[0045] Optionally, the first region and the non-first region can be arranged adjacent to each other or spaced apart. The substrate 10 can be a double-sided polished silicon substrate.

[0046] Step S202: As Figure 4 and Figure 5 As shown, a first doped conductive layer 11 and a first mask layer 12 are sequentially stacked on the back side of the substrate 10, and the first mask layer 12 corresponding to the non-first region is removed by laser.

[0047] Specifically, the first mask layer 12 corresponding to the non-first region refers to the portion of the first mask layer 12 that overlaps with the non-first region in the stacking direction of the substrate 10, the first doped conductive layer 11, and the first mask layer 12. The first mask layer 12 corresponding to the non-first region is removed by laser, thus exposing the first doped conductive layer 11 corresponding to the non-first region.

[0048] Step S203: As Figure 5 and Figure 6 As shown, at least the first doped conductive layer 11 corresponding to the non-first region is removed, and the remaining first doped conductive layer 11 forms the first emitter 13, resulting in the following: Figure 6 The structure shown;

[0049] Specifically, step S203 at least exposes the non-first region. The first emitter 13 is located in the first region.

[0050] Step S204: As Figure 7 and Figure 8 As shown, in the remaining first mask layer 12 (i.e. Figure 8 A second doped conductive layer 14 and a second mask layer 15 are sequentially stacked on the side of the first intermediate glass layer 26 away from the first emitter 13 and on the non-first region. The materials of the first mask layer 12 and the second mask layer 15 independently include at least one of amorphous silicon, nanocrystalline silicon and silicon carbide.

[0051] Optionally, the materials of the first mask layer 12 and the second mask layer 15 can be the same or different.

[0052] Step S205: As Figure 8 and Figure 9 As shown, the second mask layer 15 corresponding to the first region is removed at least by laser.

[0053] Specifically, the second mask layer 15 corresponding to the first region refers to the portion of the second mask layer 15 that overlaps with the first region in the stacking direction. By removing the second mask layer 15 corresponding to the first region, the second doped conductive layer 14 corresponding to the first region can be exposed.

[0054] Step S206: As Figure 9 and Figure 10 As shown, at least the second doped conductive layer 14 corresponding to the first region is removed, and the remaining second doped conductive layer 14 forms the second emitter 16.

[0055] Specifically, the second emitter 16 is located in the non-first region.

[0056] In the above embodiment, a substrate with a back side including a first region and a non-first region is first provided. Then, a first doped conductive layer and a first mask layer are stacked on the back side of the substrate. The material of the first mask layer includes at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. The first mask layer corresponding to the non-first region is removed by laser, exposing the first doped conductive layer corresponding to the non-first region. Then, at least the first doped conductive layer corresponding to the non-first region is removed, and the remaining first doped conductive layer forms the first emitter. Afterward, a second doped conductive layer and a second mask layer are stacked on the side of the remaining first mask layer away from the first emitter and on the non-first region. The material of the second mask layer includes at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. The second mask layer corresponding to the first region is removed by laser, exposing the second doped conductive layer corresponding to the first region. Finally, at least the second doped conductive layer corresponding to the first region is removed, and the remaining second doped conductive layer forms the second emitter. This application introduces a first mask layer and a second mask layer comprising at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. Since amorphous silicon, nanocrystalline silicon, or silicon carbide have good thermal conductivity and thermal stability, during the laser removal of the first and second mask layers, at least a portion of the energy of the laser acting on the opening edge region is absorbed by these materials, reducing the thermal stress in the opening edge region. This significantly reduces the degree of lattice damage and lattice defect density in the opening edge region during the laser opening process, thereby improving both the battery manufacturing yield and the open-circuit voltage of the battery, and thus enhancing the battery conversion efficiency.

[0057] Furthermore, the introduction of amorphous silicon, nanocrystalline silicon, and silicon carbide materials minimizes residual damage after laser film opening, eliminating the need for complex post-processing repair steps such as additional thermal annealing or chemical treatment. This simplifies the overall manufacturing process and reduces process complexity and time costs.

[0058] Specifically, the opening edge region refers to the edge region formed after laser patterning. This edge region includes at least the edges of the first mask layer 12 and the second mask layer 15 that are removed under laser action, as well as the first doped conductive layer 11 and the second doped conductive layer 14.

[0059] In some embodiments, such as Figures 2 to 4As shown, a first doped conductive layer 11 and a first mask layer 12 are sequentially stacked on the back side of the substrate 10, including: forming the first doped conductive layer 11 on the back side of the substrate 10; forming a first silicate glass layer 17 on the side of the first doped conductive layer 11 away from the substrate 10; and forming a first buffer layer 18 on the side of the first silicate glass layer 17 away from the first doped conductive layer 11, wherein the first buffer layer 18 includes at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer. That is, the first silicate glass layer 17 and the first buffer layer 18 constitute the first mask layer 12. This embodiment introduces a first buffer layer 18, comprising at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer, in the fabrication process of the back contact battery. This layer is located on the first silicate glass layer 17. During the laser ablation process, these materials can absorb part of the laser energy, reducing the impact of thermal radiation on the substrate 10 and the first doped conductive layer 11, significantly reducing microcracks and lattice defects in the ablation edge region, thereby reducing the nonradiative recombination rate of charge carriers and improving the open-circuit voltage and overall conversion efficiency of the battery. Moreover, the amorphous silicon layer, nanocrystalline silicon layer, and silicon carbide layer can all serve as effective passivation layers, reducing the defect density on the silicon surface and further improving the photoelectric conversion efficiency of the battery. This application further reduces the adverse effects caused by process inconsistencies by effectively managing the thermal effects during the laser ablation process, thereby further improving the yield of battery production. In addition, the first silicate glass layer 17, due to its good light absorption characteristics, can effectively absorb the energy of the laser beam, thereby achieving precise mask layer ablation and contact hole formation. This helps improve the accuracy of laser patterning and ensures the accurate layout of the electrodes on the back of the battery.

[0060] According to some alternative embodiments of this application, a first silicate glass layer 17 is formed on the side of the first doped conductive layer 11 away from the substrate 10, including: forming a first silicate glass layer 17 with a thickness of 30~100nm and a doping concentration of 1e19~1e21cm on the side of the first doped conductive layer 11 away from the substrate 10 using a low-pressure chemical vapor deposition process. -3 The first silicate glass layer 17. Through low-pressure chemical vapor deposition, the first silicate glass layer 17 can be grown at lower pressures, which helps reduce the inclusion of impurities and defects, thereby depositing a high-quality, highly uniform, and low-defect-density first silicate glass layer 17. This results in the first silicate glass layer 17 possessing excellent electrical and optical properties, thus contributing to improved battery performance. A thickness of 30~100nm provides sufficient material to absorb laser energy, forming a clear contact hole pattern, while avoiding the laser penetration difficulties and energy waste problems associated with excessively thick mask layers. 1e19~1e21cm -3The appropriate doping concentration ensures good electrical properties and laser absorption characteristics, which is beneficial for precise control of the laser action area.

[0061] In the embodiment described, the temperature of the low-pressure chemical vapor deposition process can be 1000℃, and the radio frequency excitation frequency can be 13.56MHz.

[0062] Optionally, the thickness of the first silicate glass layer 17 can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any other value between 30 nm and 100 nm. The doping concentration of the first silicate glass layer 17 can be 1e19 cm⁻¹. -3 3e19cm -3 5e19cm -3 7e19cm -3 ,9e19cm -3 1e20cm -3 3e20cm -3 5e20cm -3 7e20cm -3 9e20cm -3 ,1e21cm -3 Or located at 1e19cm -3 and 1e21cm -3 Any other value between these two values.

[0063] In some alternative embodiments, a first buffer layer 18 is formed on the side of the first silicate glass layer 17 away from the first doped conductive layer 11. This includes forming the first buffer layer 18 with a thickness of 0.1~5 nm and a hydrogen content of 5%~10% on the side of the first silicate glass layer 17 away from the first doped conductive layer 11 using a low-pressure chemical vapor deposition process. The low-pressure chemical vapor deposition process allows the first buffer layer 18 to be grown at a lower pressure, which helps reduce the inclusion of impurities and defects, thereby depositing a high-quality, highly uniform, and low-defect-density first buffer layer 18. This results in the first buffer layer 18 having good electrical and optical properties, thus contributing to improved battery performance. Furthermore, the thickness of the first buffer layer 18 and the amount of hydrogen doping can be precisely controlled through low-pressure chemical vapor deposition (LPCVD). The ultrathin first buffer layer 18, as thin as 0.1–5 nm, reduces the absorption of sunlight, ensuring more photons reach the substrate 10 and are converted into photogenerated carriers. This improves the short-circuit current and overall photoelectric conversion efficiency of the battery. It also significantly passivates dangling bonds on the crystalline silicon surface, reducing surface recombination centers and thus enhancing the photogenerated carrier lifetime and open-circuit voltage. Because the first buffer layer 18 is very thin, a hydrogen content of 5%–10% helps alleviate stress through diffusion during laser film-forming, further preventing microcrack formation and improving battery stability and yield. Hydrogen atoms can also fill dangling bonds in silicon, reducing surface defects such as dangling bonds and micropores, thereby significantly improving the passivation effect on the silicon surface.

[0064] In the embodiment described, the temperature of the low-pressure chemical vapor deposition process can be 570°C, and the radio frequency excitation frequency can be 13.56MHz.

[0065] Optionally, the thickness of the first buffer layer 18 can be 0.1 nm, 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or any other value between 0.1 nm and 5 nm. The hydrogen content of the first buffer layer 18 can be 5%, 6%, 7%, 8%, 9%, 10%, or any other value between 5% and 10%.

[0066] In some embodiments, before forming the first doped conductive layer 11 on the back side of the substrate 10, the method further includes: Figure 2 and Figure 3As shown, a first tunneling oxide layer 19 is formed on the back side of the substrate 10, and the first doped conductive layer 11 is located on the surface of the first tunneling oxide layer 19 away from the substrate 10. In this embodiment, the first tunneling oxide layer 19 is formed on the back side of the substrate 10. This layer serves as a medium for charge tunneling, allowing charge carriers (electrons or holes) to pass through this layer via quantum tunneling, thus achieving effective charge transfer from the substrate 10 to the conductive layer above. The first tunneling oxide layer 19 also acts as a surface passivation layer, reducing recombination centers on the silicon surface and improving the photoelectric conversion efficiency of the battery.

[0067] For example, forming a first tunneling oxide layer 19 on the back side of the substrate 10 includes: in a low-pressure chemical vapor deposition apparatus, controlling the reaction temperature to be 570°C and the radio frequency excitation frequency to be 13.56MHz, forming the first tunneling oxide layer 19 of 1~2nm on the back side of the substrate 10 using a thermal oxidation process.

[0068] Specifically, such as Figure 4 and Figure 5 As shown, removing the first mask layer 12 corresponding to the non-first region by laser includes: sequentially removing the first buffer layer 18 and the first silicate glass layer 17 corresponding to the non-first region by laser, with the remaining first silicate glass layer 17 forming the first intermediate glass layer 26 and the remaining first buffer layer 18 forming the first intermediate buffer layer 27.

[0069] For example, forming the first doped conductive layer 11 on the back side of the substrate 10 includes: introducing silane into a low-pressure chemical vapor deposition apparatus to deposit an intrinsic amorphous silicon layer on the back side of the substrate 10; controlling the temperature in the low-pressure chemical vapor deposition apparatus to 900~1050°C and the radio frequency excitation frequency to 13.56MHz; introducing a boron source (such as BBr3 or BCl3) into the low-pressure chemical vapor deposition apparatus to perform high-temperature diffusion; and forming a uniformly doped P-type polycrystalline silicon layer on the back side of the substrate 10 to obtain the first doped conductive layer 11.

[0070] Based on this, such as Figure 5 and Figure 6 As shown, at least the first doped conductive layer 11 corresponding to the non-first region is removed, including: removing the first buffer layer (i.e., the first buffer layer corresponding to the first region) through pre-cleaning and alkaline etching processes. Figure 5The first intermediate buffer layer 27, the first doped conductive layer 11 corresponding to the non-first region, and the first tunneling oxide layer 19, as shown, expose the non-first region and the remaining first silicate glass layer (i.e., the first intermediate glass layer 26) away from the surface of the substrate 10. The remaining first tunneling oxide layer 19 forms the first final oxide layer 25, and the remaining first doped conductive layer 11 forms the first emitter 13. The pre-cleaning and alkaline etching processes can precisely remove material from the designated areas, achieving precise isolation between the first emitter 13 and the non-first region. Furthermore, the pre-cleaning and alkaline etching expose the non-first region, facilitating the subsequent deposition of film structures on the non-first region.

[0071] For example, removing the first buffer layer 18 corresponding to the first region, the first doped conductive layer 11 corresponding to the non-first region, and the first tunneling oxide layer 19 by pre-cleaning and alkaline etching includes: pre-cleaning the substrate 10 on which the first doped conductive layer 11 and the first mask layer 12 are formed using a cleaning solution including KOH and H2O2, and alkaline polishing the substrate 10 on which the first doped conductive layer 11 and the first mask layer 12 are formed using a solution including KOH and alkaline polishing additive, so as to remove the first buffer layer 18 corresponding to the first region, the first doped conductive layer 11 corresponding to the non-first region, and the first tunneling oxide layer 19.

[0072] Specifically, in the solution containing KOH and alkaline polishing additives, the percentage of KOH is 0.1-20 wt%, the alkaline polishing temperature is 30-80℃, and the alkaline polishing time is 10-500s.

[0073] In one alternative, the first mask layer 12 corresponding to the non-first region is removed by laser, including: using a green picosecond laser with a frequency of 800 kHz, a wavelength of 532 nm, and a spot diameter of 150 μm, at a speed of 0.276 J / cm². 2 The single-spot energy density is used to ablate the first mask layer 12 corresponding to the non-first region to form a patterned structure.

[0074] In another alternative, the removal of the first mask layer 12 corresponding to the non-first region by laser includes: using an ultraviolet picosecond laser with a wavelength of 355nm and a pulse width of 10ps to ablate the first mask layer 12 corresponding to the non-first region at a single spot energy density of 0.5~1.5J / cm² to form a patterned structure.

[0075] In another alternative, the removal of the first mask layer 12 corresponding to the non-first region by laser includes: using an infrared picosecond laser with a wavelength of 1030nm and a pulse width of 10ps to ablate the first mask layer 12 corresponding to the non-first region with a single spot energy density of 2~3J / cm² to form a patterned structure.

[0076] In other embodiments, in the remaining first mask layer 12 (i.e. Figure 8 The first intermediate glass layer 26) in the first region is stacked with a second doped conductive layer 14 and a second mask layer 15 on the side away from the first emitter 13 and the non-first region, including: Figure 7 and Figure 8 As shown, a second doped conductive layer 14 is formed on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region. That is, the second doped conductive layer 14 covers the exposed back surface of the substrate 10 on which the first intermediate glass layer 26 is formed. A second silicate glass layer 20 is formed on the side of the second doped conductive layer 14 away from the substrate 10. A second buffer layer 21 is formed on the side of the second silicate glass layer 20 away from the second doped conductive layer 14. The second buffer layer 21 includes at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer. In other words, the second silicate glass layer 20 and the second buffer layer 21 constitute the second mask layer 15. This embodiment introduces a second buffer layer 21, comprising at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer, in the fabrication process of the back contact battery. This layer is located on the second silicate glass layer 20. During the laser ablation process, these materials can absorb part of the laser energy, reducing the impact of thermal radiation on the substrate 10 and the second doped conductive layer 14, significantly reducing microcracks and lattice defects in the ablation edge region, thereby reducing the nonradiative recombination rate of charge carriers and improving the open-circuit voltage and overall conversion efficiency of the battery. Moreover, the amorphous silicon layer, nanocrystalline silicon layer, and silicon carbide layer can all serve as effective passivation layers, reducing the defect density on the silicon surface and further improving the photoelectric conversion efficiency of the battery. This application further reduces the adverse effects of process inconsistencies by effectively managing the thermal effects during the laser ablation process, thereby further improving the yield of battery production. In addition, the second silicate glass layer 20, due to its excellent light absorption characteristics, can effectively absorb the energy of the laser beam, thereby achieving precise mask layer ablation and contact hole formation. This helps improve the accuracy of laser patterning and ensures the accurate layout of the electrodes on the back of the battery.

[0077] Specifically, a second doped conductive layer 14 is formed on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region, including: as follows Figure 7 As shown, the second doped conductive layer 14 is formed on the side of the first intermediate glass layer 26 away from the substrate 10 and on the non-first region.

[0078] In some embodiments, forming a second silicate glass layer 20 on the side of the second doped conductive layer 14 away from the substrate 10 includes: forming a layer with a thickness of 30-100 nm and a doping concentration of 1e19-1e21 cm⁻¹ on the side of the second doped conductive layer 14 away from the substrate 10 using a low-pressure chemical vapor deposition process. -3 The second silicate glass layer 20 is formed using a low-pressure chemical vapor deposition process. This allows for the growth of the second silicate glass layer 20 at lower pressures, which helps reduce the incorporation of impurities and defects, resulting in a high-quality, highly uniform second silicate glass layer 20 with low defect density. This gives the second silicate glass layer 20 excellent electrical and optical properties, thus contributing to improved battery performance. A thickness of 30–100 nm provides sufficient material to absorb laser energy, forming a clear contact hole pattern, while avoiding the difficulties in laser penetration and energy waste associated with excessively thick mask layers. (1e19–1e21 cm) -3 The appropriate doping concentration ensures good electrical properties and laser absorption characteristics, which is beneficial for precise control of the laser action area.

[0079] In the embodiment described, the temperature of the low-pressure chemical vapor deposition process can be 1000℃, and the radio frequency excitation frequency can be 13.56MHz.

[0080] Optionally, the thickness of the second silicate glass layer 20 can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any other value between 30 nm and 100 nm. The doping concentration of the second silicate glass layer 20 can be 1e19 cm⁻¹. -3 3e19cm -3 5e19cm -3 7e19cm -3 ,9e19cm -3 1e20cm -3 3e20cm -3 5e20cm -3 7e20cm -3 9e20cm -3 ,1e21cm -3 Or located at 1e19cm -3and 1e21cm -3 Any other value between these two values.

[0081] In other embodiments, a second buffer layer 21 is formed on the side of the second silicate glass layer 20 away from the second doped conductive layer 14. This includes forming a second buffer layer 21 with a thickness of 0.1~5 nm and a hydrogen content of 5%~10% on the side of the second silicate glass layer 20 away from the second doped conductive layer 14 using a low-pressure chemical vapor deposition process. The low-pressure chemical vapor deposition process allows the growth of the second buffer layer 21 at a lower pressure, which helps reduce the inclusion of impurities and defects, thereby depositing a high-quality, highly uniform, and low-defect-density second buffer layer 21. This results in the second buffer layer 21 having good electrical and optical properties, thus contributing to improved battery performance. Furthermore, the thickness of the second buffer layer 21 and the amount of hydrogen doping can be precisely controlled through low-pressure chemical vapor deposition (LPCVD). The ultrathin second buffer layer 21, as thin as 0.1–5 nm, reduces the absorption of sunlight, ensuring more photons reach the substrate 10 and are converted into photogenerated carriers. This improves the short-circuit current and overall photoelectric conversion efficiency of the battery. It also significantly passivates dangling bonds on the crystalline silicon surface, reducing surface recombination centers and thus enhancing the photogenerated carrier lifetime and open-circuit voltage. Because the second buffer layer 21 is very thin, a hydrogen content of 5%–10% helps alleviate stress through diffusion during laser film-forming, further preventing microcrack formation and improving battery stability and yield. Hydrogen atoms can also fill dangling bonds in silicon, reducing surface defects such as dangling bonds and micropores, thereby significantly improving the passivation effect on the silicon surface.

[0082] In the embodiment described, the temperature of the low-pressure chemical vapor deposition process can be 570°C, and the radio frequency excitation frequency can be 13.56MHz.

[0083] Optionally, the thickness of the second buffer layer 21 can be 0.1 nm, 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or any other value between 0.1 nm and 5 nm. The hydrogen content of the second buffer layer 21 can be 5%, 6%, 7%, 8%, 9%, 10%, or any other value between 5% and 10%.

[0084] Optionally, the first silicate glass layer 17 is one of BSG and PSG, and the second silicate glass layer 20 is the other of BSG and PSG. For example, the first silicate glass layer 17 is BSG, and the second silicate glass layer 20 is PSG.

[0085] In some embodiments, before forming the second doped conductive layer 14 on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region, the method further includes: Figure 6 and Figure 7 As shown, in the remaining first mask layer 12 (i.e. Figure 7 A second tunneling oxide layer 22 is formed on the side of the first intermediate glass layer 26 away from the first emitter 13, on the remaining side of the first mask layer 12, and on the non-first region. The second doped conductive layer 14 is located on the surface of the second tunneling oxide layer 22 away from the substrate 10. In this embodiment, the second tunneling oxide layer 22 is formed on the exposed surface of the first mask layer 12 and on the non-first region. This layer serves as a medium for charge tunneling, allowing charge carriers (electrons or holes) to pass through it via quantum tunneling, thus achieving effective charge transfer from the substrate 10 to the upper conductive layer. The second tunneling oxide layer 22 also acts as a surface passivation layer, reducing recombination centers on the silicon surface and improving the photoelectric conversion efficiency of the battery.

[0086] For example, forming a second tunneling oxide layer 22 on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region includes: in a low-pressure chemical vapor deposition apparatus, controlling the reaction temperature to 570°C and the radio frequency excitation frequency to 13.56MHz, and using a thermal oxidation process to form a first tunneling oxide layer 19 of 1~2nm on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region.

[0087] In one embodiment of this application, a second doped conductive layer 14 is formed on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region, including: as follows Figure 7 As shown, the second doped conductive layer 14 is formed on the exposed surface of the second tunneling oxide layer 22 away from the substrate 10.

[0088] For example, forming the second doped conductive layer 14 on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region includes: introducing silane into a low-pressure chemical vapor deposition apparatus to deposit an intrinsic amorphous silicon layer on the back surface of the substrate 10; controlling the temperature in the low-pressure chemical vapor deposition apparatus to 900~1050°C and the radio frequency excitation frequency to 13.56MHz, introducing phosphorus oxychloride into the low-pressure chemical vapor deposition apparatus to perform high-temperature diffusion, so as to form a uniformly doped N-type polycrystalline silicon layer on the side of the remaining first mask layer 12 away from the first emitter 13, on the side surface of the remaining first mask layer 12, and on the non-first region, thereby obtaining the second doped conductive layer 14.

[0089] According to some alternative solutions, the second mask layer 15 corresponding to the first region is at least removed by laser, including: such as Figure 8 and Figure 9 As shown, the laser sequentially removes the second buffer layer 21 and the second silicate glass layer 20 from the first region and the spaced region, exposing the second doped conductive layer 14 in the first region and the spaced region. The remaining second buffer layer 21 (i.e., the second buffer layer 21 in the second region) forms the second intermediate buffer layer 28, and the remaining second silicate glass layer 20 (i.e., the second silicate glass layer 20 in the second region) forms the second intermediate glass layer 29.

[0090] In embodiments of this application, the non-first region includes a spacer region and a second region, the spacer region being located between the first region and the second region, and at least the second doped conductive layer 14 corresponding to the first region is removed, including: Figure 9 and Figure 10As shown, the second buffer layer 21 (i.e., the second intermediate buffer layer 28) corresponding to the second region, the second doped conductive layer 14 and the second tunneling oxide layer 22 corresponding to the first region and the spacer region are removed by alkaline etching, exposing the spacer region, the remaining first silicate glass layer 17 (i.e., the first intermediate glass layer 26), and the remaining second silicate glass layer 20 (i.e., the second intermediate glass layer 29). The remaining second tunneling oxide layer 22 forms the second final oxide layer 30, and the remaining second doped conductive layer forms the second emitter 16. The spacer region and the front side of the substrate 10 are texturized. The remaining first silicate glass layer 17 (i.e., the first intermediate glass layer 26) and the remaining second silicate glass layer 20 (i.e., the second intermediate glass layer 29) are removed by acid etching. In this embodiment, a pyramidal textured surface is formed on the spacer region and the front side of the substrate 10 through a one-step texturing process, which increases the path length of light on the surface of the battery, improves the light absorption rate and the short-circuit current of the battery, simplifies the fabrication steps, and helps to reduce production costs. In this embodiment, only the second tunneling oxide layer 22 and the second doped conductive layer 14 located in the second region are retained, so that the first emitter 13 and the second emitter 16 are electrically isolated in the spacer region, thus ensuring the normal electrical performance of the battery.

[0091] For example, removing the second buffer layer 21 corresponding to the second region, the second doped conductive layer 14 corresponding to the first region and the spacer region, and the second tunneling oxide layer 22 by alkaline etching includes: alkaline washing the second buffer layer 21 corresponding to the second region, the second doped conductive layer 14 corresponding to the first region and the spacer region, and the second tunneling oxide layer 22 by an alkaline solution containing KOH. Texturing the spacer region and the front side of the substrate 10 includes: immersing the alkaline-washed battery structure in a low-concentration KOH solution to form a micron-scale textured structure on the spacer region and the front side of the substrate 10. Removing the remaining first silicate glass layer 17 and the remaining second silicate glass layer 20 by acid etching includes: removing the remaining first silicate glass layer 17 and the remaining second silicate glass layer 20 by an HF solution.

[0092] In some embodiments, removing at least the second mask layer 15 corresponding to the first region by laser includes: such as Figure 8 and Figure 9As shown, the second mask layer 15 corresponding to the first region and the interval region is removed by laser. In this embodiment, during the removal of the second mask layer 15 by laser, at least a portion of the energy of the laser acting on the edge region of the open film is absorbed by materials such as amorphous silicon, nanocrystalline silicon, and silicon carbide in the second mask layer 15, reducing the impact of thermal radiation on the substrate 10 and the second doped conductive layer 14, significantly reducing microcracks and lattice defects in the edge region of the open film, thereby reducing the nonradiative recombination rate of charge carriers and improving the open-circuit voltage and overall conversion efficiency of the battery. Removing the second mask layer 15 by laser facilitates subsequent precise control of the second emitter 16.

[0093] In one alternative, the second mask layer 15 corresponding to the first region is at least removed by laser, including: using a green picosecond laser with a frequency of 800 kHz, a wavelength of 532 nm, and a spot diameter of 150 μm, at a speed of 0.210 J / cm². 2 The single-spot energy density ablates at least the first mask layer 12 corresponding to the first region, forming a patterned structure.

[0094] In another alternative, the second mask layer 15 corresponding to the first region is removed by laser, including: using an ultraviolet picosecond laser with a wavelength of 355nm and a pulse width of 10ps to ablate the first mask layer 12 corresponding to the first region at a single spot energy density of 0.5~1.5J / cm² to form a patterned structure.

[0095] In another alternative, the second mask layer 15 corresponding to the first region is removed by laser, including: using an infrared picosecond laser with a wavelength of 1030nm and a pulse width of 10ps to ablate the first mask layer 12 corresponding to the first region at a single spot energy density of 2~3J / cm² to form a patterned structure.

[0096] According to further embodiments of this application, the method further includes: Figure 10 , Figure 11 , Figure 12 as well as Figure 13As shown, a passivation layer 23 and an anti-reflection layer 24 are stacked on the surfaces of the first emitter 13 and the second emitter 16 away from the substrate 10, on the spacer region, and on the front side of the substrate 10. A first electrode 31 is formed on the side of the anti-reflection layer 24 away from the first emitter 13, and a second electrode 32 is formed on the side of the anti-reflection layer 24 away from the second emitter 16. The first electrode is electrically connected to the first emitter 13, and the second electrode is electrically connected to the second emitter 16. The battery structure with the first electrode and the second electrode formed is subjected to photo-annealing. In this embodiment, by depositing a passivation layer 23 and an anti-reflection layer 24 on the front and back sides of the battery structure, the passivation layer 23 reduces interfacial recombination, and the anti-reflection layer 24 increases the light incident rate, thereby improving the light absorption efficiency and carrier lifetime of the battery. Photo-annealing of the metallized battery structure accelerates the regeneration and diffusion of carriers inside the battery through high-intensity light and appropriate temperature, which helps to eliminate surface defects that may be introduced during the metallization process, promotes good contact between the electrode and the silicon surface, and reduces contact resistance. Meanwhile, photoannealing can also activate dopants, optimize the doping distribution of the battery, and enhance the performance stability of the battery.

[0097] Optionally, the passivation layer 23 may include an aluminum oxide layer, and the antireflection layer 24 may include a nitride layer. The passivation layer 23 and the antireflection layer 24 are stacked on the surfaces of the first emitter 13 and the second emitter 16 away from the substrate 10, on the spacer region, and on the front side of the substrate 10, comprising: forming the aluminum oxide layer on the surfaces of the first emitter 13 and the second emitter 16 away from the substrate 10, on the spacer region, and on the front side of the substrate 10 using an atomic layer deposition process at a reaction temperature of 270°C to obtain the passivation layer 23; and forming the silicon nitride layer on the surfaces of the passivation layer 23 away from the front and back sides of the substrate 10 using a low-pressure chemical vapor deposition process at a reaction temperature of 590°C to obtain the antireflection layer 24.

[0098] Exemplarily, a first electrode is formed on the side of the antireflective layer 24 away from the first emitter 13, and a second electrode is formed on the side of the antireflective layer 24 away from the second emitter 16, including: Figure 12 and Figure 13 As shown, silver paste is screen-printed onto the side of the anti-reflective layer 24 away from the first emitter 13 and the second emitter 16 using a screen printing process; the silver paste is then sintered in a ventilated environment at 170°C to form the first electrode and the second electrode.

[0099] For example, photo-annealing of a battery structure having the first electrode and the second electrode includes: providing illumination with an LED light source matrix (wavelength 400-800nm), and subjecting the battery structure to 90-second high-intensity photo-annealing at a light intensity of 60kW / m² and a temperature of 200°C.

[0100] In one embodiment, the substrate of this application is a phosphorus-doped n-type Czochralski single-crystal silicon wafer with dimensions of (183×183mm±0.25mm), a crystal orientation of (100), and a resistivity of 0.8~10Ω·cm. Performance testing shows that the silicon ingot, with a carrier injection concentration of 5×10⁻⁶... 14 cm -3 The lifespan of the body exceeds 8ms.

[0101] The technical solution of this application, by introducing an ultra-thin first and second buffer layer, allows the energy of the laser-induced thermal effect region at the edge to be absorbed by the first and second buffer layers, thus reducing the degree of edge damage caused by laser-induced film opening. Compared with the existing technology that uses BSG (borosilicate glass) or PSG (phosphosilicate glass) as the laser-induced film opening layer, which causes increased carrier recombination in the edge region and a battery efficiency loss of 0.5%-1%, the back-contact solar cell of this application reduces the lattice defect density in the laser-induced edge region by more than 60%, increases the cell open-circuit voltage (Voc) by 15-25mV, improves the cell conversion efficiency by 0.3%-1.2%, and increases the mass production yield to over 98%. Furthermore, using the method of this application to fabricate back-contact solar cells eliminates the traditional post-laser repair step, reducing battery production costs by approximately 20%.

[0102] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the back contact solar cell fabrication method of this application will be described in detail below with reference to specific embodiments and comparative examples.

[0103] Example

[0104] The present application discloses a method for fabricating a back-contact solar cell, comprising the following steps:

[0105] 1) First, prepare an N-type crystalline silicon substrate, clean the substrate and polish both sides;

[0106] 2) A tunneling silicon oxide layer with a thickness of 1.5 nm was deposited on the surface of the silicon substrate using LPCVD. An amorphous silicon layer with a thickness of 200 nm was then deposited on the surface of the tunneling silicon oxide layer using LPCVD. High-temperature annealing was performed using LPCVD, and boron atoms were doped into the amorphous silicon at a temperature of 1000 °C for 60 min, so that the amorphous silicon layer crystallized into a polycrystalline silicon layer.

[0107] 3) A 50nm BSG layer and a 5nm amorphous silicon protective layer are formed on the surface of the polycrystalline silicon layer using LPCVD;

[0108] 4) Laser patterning was performed on the second region using the following laser opening parameters: wavelength: 532nm, frequency: 1200KHz, pulse width: 10ps, scanning speed: 6.5m / s, single pulse energy density: 0.267J / cm².

[0109] 5) Wet etching, which is carried out by the following wet process: Alkali etching: 6wt% KOH solution + alkaline polishing additive, 78℃, 180s;

[0110] 6) A tunneling silicon oxide layer with a thickness of 1.5 nm was deposited on the surface of the silicon substrate using LPCVD. An amorphous silicon layer with a thickness of 200 nm was then deposited on the surface of the tunneling silicon oxide layer using LPCVD. High-temperature annealing was performed using LPCVD, and phosphorus atoms were doped into the amorphous silicon at a temperature of 950 °C for 60 min, so that the amorphous silicon layer crystallized into a polycrystalline silicon layer.

[0111] 7) Simultaneously, LPCVD is used to form a 30nm PSG layer and a 5nm amorphous silicon protective layer on the polycrystalline silicon surface;

[0112] 8) Laser patterning is performed on the first region using the following laser film opening parameters: wavelength: 532nm, frequency: 1200KHz, pulse width: 10ps, scanning speed: 6.5m / s, single pulse energy density: 0.210J / cm².

[0113] 9) Wet etching and texturing: Etching is performed using the following wet process: Alkali washing: 6wt% KOH solution, 65℃, 20s; Texturing: Immersion in 2wt% KOH solution to prepare micron-sized textured surfaces for the GAP area and the front of the battery.

[0114] 10) Passivation layer preparation: Alumina films were deposited on the front and back sides of the battery using an ALD device (temperature 270°C);

[0115] 11) Preparation of anti-reflective layers on the front and back sides: Silicon nitride (SiNx) stacks were deposited on the front and back sides of the battery using a PECVD device (frequency 13.56MHz, temperature 590℃);

[0116] 12) Metallization: Silver paste is screen-printed onto the P / N contact area.

[0117] Comparative Example

[0118] A method for fabricating a back-contact solar cell includes the following steps:

[0119] 1) First, prepare an N-type crystalline silicon substrate, clean the substrate and polish both sides;

[0120] 2) A tunneling silicon oxide layer with a thickness of 1.5 nm was deposited on the surface of the silicon substrate using LPCVD. An amorphous silicon layer with a thickness of 200 nm was then deposited on the surface of the tunneling silicon oxide layer using LPCVD. High-temperature annealing was performed using LPCVD, and boron atoms were doped into the amorphous silicon at a temperature of 1000 °C for 60 min, so that the amorphous silicon layer crystallized into a polycrystalline silicon layer.

[0121] 3) A 50nm BSG layer was formed on the polycrystalline silicon surface using LPCVD;

[0122] 4) Laser patterning was performed on the second region using the following laser opening parameters: wavelength: 532nm, frequency: 1200KHz, pulse width: 10ps, scanning speed: 6.5m / s, single pulse energy density: 0.267J / cm².

[0123] 5) Wet etching, which is carried out by the following wet process: Alkali etching: 6wt% KOH solution + alkaline polishing additive, 78℃, 180s;

[0124] 6) A tunneling silicon oxide layer with a thickness of 1.5 nm was deposited on the surface of the silicon substrate using LPCVD. An amorphous silicon layer with a thickness of 200 nm was then deposited on the surface of the tunneling silicon oxide layer using LPCVD. High-temperature annealing was performed using LPCVD, and phosphorus atoms were doped into the amorphous silicon at a temperature of 950 °C for 60 min, so that the amorphous silicon layer crystallized into a polycrystalline silicon layer.

[0125] 7) A 30nm PSG layer was formed on the polycrystalline silicon surface using LPCVD;

[0126] 8) Laser patterning is performed on the first region using the following laser film opening parameters: wavelength: 532nm, frequency: 1200KHz, pulse width: 10ps, scanning speed: 6.5m / s, single pulse energy density: 0.210J / cm².

[0127] 9) Wet etching and texturing: Etching is performed using the following wet process: Alkali washing: 6wt% KOH solution, 65℃, 20s. Texturing: Immersion in 2wt% KOH solution to prepare micron-sized textured surfaces on the GAP area and the front of the battery;

[0128] 10) Passivation layer preparation: Alumina films were deposited on the front and back sides of the battery using an ALD device (temperature 270°C);

[0129] 11) Preparation of anti-reflective layers on the front and back sides: Silicon nitride (SiNx) stacks were deposited on the front and back sides of the battery using a PECVD device (frequency 13.56MHz, temperature 590℃);

[0130] 12) Metallization: Silver paste is screen-printed onto the P / N contact area.

[0131] The cell performance of the back-contact solar cells obtained from the test examples and comparative examples is shown in Table 1.

[0132] Table 1

[0133]

[0134] Based on the experimental results in Table 1, the experimental conclusion is that introducing an ultrathin amorphous silicon protective layer reduces edge damage from laser-induced film opening and can significantly improve the cell conversion efficiency of BC cells.

[0135] Another embodiment of this application provides a back-contact solar cell, wherein the back-contact solar cell is prepared by any of the back-contact solar cell preparation methods described above.

[0136] The back-contact solar cell is prepared by the aforementioned method. This method involves introducing a first mask layer and a second mask layer, which include at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. Since amorphous silicon, nanocrystalline silicon, or silicon carbide have good thermal conductivity and thermal stability, during the laser removal of the first and second mask layers, at least part of the energy of the laser acting on the edge region of the open film is absorbed by these materials, reducing the thermal stress in the edge region of the open film. This significantly reduces the degree of lattice damage and lattice defect density in the edge region of the open film during the laser opening process, thereby improving both the cell manufacturing yield and the open-circuit voltage of the cell, and thus improving the cell conversion efficiency.

[0137] In another aspect, this application provides a photovoltaic module, comprising: a battery string formed by connecting a plurality of back-contact solar cells; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0138] The photovoltaic module includes stacked cover plates, encapsulating films, and cell strings. The cell strings are formed by connecting multiple back-contact solar cells. The cell fabrication process introduces a first mask layer and a second mask layer, including at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. Since amorphous silicon, nanocrystalline silicon, or silicon carbide have good thermal conductivity and thermal stability, during the laser removal of the first and second mask layers, at least part of the energy of the laser acting on the opening edge region is absorbed by these materials, reducing the thermal stress in the opening edge region. This significantly reduces the degree of lattice damage and lattice defect density in the opening edge region during the laser opening process, ensuring high cell conversion efficiency and thus ensuring good overall performance of the photovoltaic module.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] As can be seen from the above description, the embodiments described in this application achieve the following technical effects:

[0141] The method for fabricating a back-contact solar cell of this application first provides a substrate with a back side including a first region and a non-first region. Then, a first doped conductive layer and a first mask layer are stacked on the back side of the substrate. The material of the first mask layer includes at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. The first mask layer corresponding to the non-first region is removed by laser, exposing the first doped conductive layer corresponding to the non-first region. Then, at least the first doped conductive layer corresponding to the non-first region is removed, and the remaining first doped conductive layer forms the first emitter. Afterward, a second doped conductive layer and a second mask layer are stacked on the side of the remaining first mask layer away from the first emitter and on the non-first region. The material of the second mask layer includes at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. The second mask layer corresponding to the first region is removed by laser, exposing the second doped conductive layer corresponding to the first region. Finally, at least the second doped conductive layer corresponding to the first region is removed, and the remaining second doped conductive layer forms the second emitter. This application introduces a first mask layer and a second mask layer comprising at least one of amorphous silicon, nanocrystalline silicon, and silicon carbide. Since amorphous silicon, nanocrystalline silicon, or silicon carbide have good thermal conductivity and thermal stability, during the laser removal of the first and second mask layers, at least a portion of the energy of the laser acting on the opening edge region is absorbed by these materials, reducing the thermal stress in the opening edge region. This significantly reduces the degree of lattice damage and lattice defect density in the opening edge region during the laser opening process, thereby improving both the battery manufacturing yield and the open-circuit voltage of the battery, and thus enhancing the battery conversion efficiency.

[0142] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a back-contact solar cell, characterized in that, include: A substrate is provided, the substrate including opposing front and back sides, the back side including a first region and a non-first region; A first doped conductive layer and a first mask layer are sequentially stacked on the back side of the substrate, and the first mask layer corresponding to the non-first region is removed by laser. At least the first doped conductive layer corresponding to the non-first region is removed, and the remaining first doped conductive layer forms the first emitter; A second doped conductive layer and a second mask layer are sequentially stacked on the side of the remaining first mask layer away from the first emitter and on the non-first region, wherein the materials of the first mask layer and the second mask layer independently include at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; At least the second mask layer corresponding to the first region is removed by laser; At least the second doped conductive layer corresponding to the first region is removed, and the remaining second doped conductive layer forms the second emitter. A first doped conductive layer and a first mask layer are sequentially stacked on the back side of the substrate, including: The first doped conductive layer is formed on the back side of the substrate; A first silicate glass layer is formed on the side of the first doped conductive layer away from the substrate; A first buffer layer is formed on the side of the first silicate glass layer away from the first doped conductive layer, and the first buffer layer includes at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer.

2. The method for preparing a back-contact solar cell according to claim 1, characterized in that, Forming a first silicate glass layer on the side of the first doped conductive layer away from the substrate includes: using a low-pressure chemical vapor deposition process to form a layer with a thickness of 30-100 nm and a doping concentration of 1e19-1e21 cm⁻¹ on the side of the first doped conductive layer away from the substrate. -3 The first silicate glass layer; Forming a first buffer layer on the side of the first silicate glass layer away from the first doped conductive layer includes: forming a first buffer layer with a thickness of 0.1~5nm and a hydrogen content of 5%~10% on the side of the first silicate glass layer away from the first doped conductive layer using a low-pressure chemical vapor deposition process.

3. The method for preparing a back-contact solar cell according to claim 1, characterized in that, Before forming the first doped conductive layer on the back side of the substrate, the method for fabricating the back contact solar cell further includes: forming a first tunneling oxide layer on the back side of the substrate, wherein the first doped conductive layer is located on the surface of the first tunneling oxide layer away from the substrate; At least the first doped conductive layer corresponding to the non-first region is removed, including: removing the first buffer layer corresponding to the first region, the first doped conductive layer corresponding to the non-first region, and the first tunneling oxide layer by pre-cleaning and alkaline etching processes, so that the non-first region and the first silicate glass layer are exposed on the surface away from the substrate.

4. The method for preparing a back-contact solar cell according to claim 1, characterized in that, A second doped conductive layer and a second mask layer are sequentially stacked on the remaining side of the first mask layer away from the first emitter and on the non-first region, including: A second doped conductive layer is formed on the side of the remaining first mask layer away from the first emitter, on the side surface of the remaining first mask layer, and on the non-first region. A second silicate glass layer is formed on the side of the second doped conductive layer away from the substrate; A second buffer layer is formed on the side of the second silicate glass layer away from the second doped conductive layer, the second buffer layer comprising at least one of an amorphous silicon layer, a nanocrystalline silicon layer, and a silicon carbide layer.

5. The method for fabricating a back-contact solar cell according to claim 4, characterized in that, Before forming the second doped conductive layer on the side of the remaining first mask layer away from the first emitter, on the side surface of the remaining first mask layer, and on the non-first region, the method for fabricating the back contact solar cell further includes: forming a second tunneling oxide layer on the side of the remaining first mask layer away from the first emitter, on the side surface of the remaining first mask layer, and on the non-first region, wherein the second doped conductive layer is located on the surface of the second tunneling oxide layer away from the substrate. The non-first region includes a spacer region and a second region. The spacer region is located between the first region and the second region. At least the second doped conductive layer corresponding to the first region is removed, including: removing the second buffer layer corresponding to the second region, the second doped conductive layer corresponding to the first region and the spacer region, and the second tunneling oxide layer by alkaline etching, so that the spacer region, the remaining first silicate glass layer and the remaining second silicate glass layer are exposed; texturing the spacer region and the front side of the substrate; and removing the remaining first silicate glass layer and the remaining second silicate glass layer by acid etching.

6. The method for fabricating a back-contact solar cell according to claim 5, characterized in that, Removing at least the second mask layer corresponding to the first region by laser, including: The second mask layer corresponding to the first region and the interval region is removed by laser.

7. The method for fabricating a back-contact solar cell according to claim 5, characterized in that, The method for preparing the back-contact solar cell further includes: A passivation layer and an anti-reflection layer are stacked on the surfaces of the first emitter and the second emitter away from the substrate, on the spacer region, and on the front side of the substrate; A first electrode is formed on the side of the antireflective layer away from the first emitter, and a second electrode is formed on the side of the antireflective layer away from the second emitter. The first electrode is electrically connected to the first emitter, and the second electrode is electrically connected to the second emitter. The battery structure having the first electrode and the second electrode is subjected to photo-annealing treatment.

8. A back-contact solar cell, characterized in that, The back-contact solar cell is prepared using the method for preparing a back-contact solar cell according to any one of claims 1 to 7.

9. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple back-contact solar cells as described in claim 8; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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