Semiconductor device with nitrogen-doped field release dielectric layer

Abstract

Semiconductor devices including a nitrogen-doped field release dielectric layer (130) are described. A microelectronic device (100) comprises: a substrate (103) comprising a body region (108) having a first conductivity type and a drain drift region (138) having a second conductivity type opposite the first conductivity type; a gate dielectric layer (150) on the substrate (103), the gate dielectric layer (150) extending over the body region (108) and the drain drift region (138); and a nitrogen doped field release dielectric layer (130) on the drain drift region (138).

Description

[0001] This disclosure relates to the field of microelectronic devices. More specifically, but not exclusively, this disclosure relates to microelectronic devices having a nitrogen-doped field-release dielectric layer. Background Technology

[0002] Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing semiconductor devices that offer increasingly higher performance while meeting reliability specifications is challenging. Summary of the Invention

[0003] This summary is provided to introduce a simplified series of disclosed concepts, which will be further described below in detail with reference to the accompanying drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0004] The disclosed examples include microelectronic devices having a nitrogen-doped field-release dielectric layer. The nitrogen-doped field-release dielectric layer is primarily a silicon dioxide layer having an atomic percentage nitrogen content that may be in the form of silicon oxynitride, silicon nitride, or interstitial nitrogen material, or any combination thereof. The microelectronic device includes: a substrate comprising a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type; a gate dielectric layer on the substrate extending above the intersection of the body region and the drift region; a field-release dielectric layer on the drift region laterally adjacent to the gate dielectric layer at a location within the drift region; and a gate electrode above the gate dielectric layer and the field-release dielectric layer.

[0005] By doping the field release dielectric layer with nitrogen, the dielectric constant of the field release dielectric is increased to a level higher than that of pure silicon dioxide. Compared to a microelectronic device of similar size with an undoped field release dielectric, increasing the dielectric constant of the field release dielectric layer improves channel hot carrier performance, improves breakdown resistance, and reduces the specific on-resistance of the microelectronic device. The microelectronic device further includes a source region disposed in the body region, the source region having the second conductivity type; and a drain region disposed in the drift region, the drain region having the second conductivity type. Attached Figure Description

[0006] Figures 1A to 1L The images show cross-sections of example microelectronic devices at various formation stages, the microelectronic devices comprising transistors having nitrogen-doped field-release dielectric layers.

[0007] Figure 2 This is a top view of an example microelectronic device that includes a transistor with a nitrogen-doped field-release dielectric layer.

[0008] Figure 3 The cross-section is an alternative example of a microelectronic device comprising a transistor having a nitrogen-doped field-release dielectric layer including shallow trench isolation. Detailed Implementation

[0009] This disclosure is described with reference to the accompanying drawings. The drawings are not to scale and are provided for illustrative purposes only. Several aspects of this disclosure are described below with reference to illustrative example applications. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order of the activities or events shown, as some activities may occur in a different order and / or simultaneously with other activities or events. Furthermore, not all of the described actions or events are required to implement the methods according to this disclosure.

[0010] Furthermore, although some embodiments described herein are shown in two-dimensional views of various regions having depth and width, it should be clearly understood that these regions are merely illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured in an actual device, these regions will have three dimensions, including length, width, and depth. Moreover, while this disclosure is described with respect to embodiments of active devices, these descriptions are not intended to limit the scope or applicability of this disclosure. The active devices of this disclosure are not intended to be limited to the physical structures described. These structures are included to demonstrate the utility and application of this disclosure with respect to the presently preferred embodiments.

[0011] It should be noted that terms such as top, bottom, above, above, and below are used in this disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to a plane corresponding to the surface of a layer (e.g., the top surface of a semiconductor substrate). Furthermore, the term "approximately" as used herein may refer to a variation of ±5% to ±10% of the stated value in some cases. In other cases, the term "approximately" may refer to a variation of ±10% to ±20% of the stated value.

[0012] Microelectronic devices are constantly being improved to operate reliably with smaller feature sizes. Fabricating such microelectronic devices that meet area scaling and reliability requirements is challenging. Some metal-oxide-semiconductor (MOS) transistors include features to support high-voltage operation, such as voltages applied to their drain (or drain structure) of about 20 V, 30 V, 40 V, or even higher. Such MOS transistors may include drain diffusion profiles (or drain junction profiles) designed to support high voltages applied to the drain, for example, having extended portions to distribute voltage drops across a wider region. Therefore, such MOS transistors may be referred to as drain-extended MOS transistors, such as drain-extended n-channel MOS (DENMOS) transistors, drain-extended p-channel MOS (DEPMOS) transistors, laterally diffused MOS (LDMOS) transistors, and groups of DENMOS and DEPMOS transistors (which may be referred to as complementary drain-extended MOS or DECMOS transistors).

[0013] The disclosed examples include microelectronic devices having a nitrogen-doped field-release dielectric layer. The nitrogen-doped field-release dielectric layer is primarily a silicon dioxide layer having an atomic percentage nitrogen content that may be in the form of silicon oxynitride, silicon nitride, or interstitial nitrogen material, or any combination thereof. The microelectronic device includes: a substrate comprising a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type; a gate dielectric layer on the substrate extending above the intersection of the body region and the drift region; a field-release dielectric layer on the drift region laterally adjacent to the gate dielectric layer at a location within the drift region; and a gate electrode above the gate dielectric layer and the field-release dielectric layer.

[0014] Nitrogen doping of the field release dielectric layer increases its dielectric constant to a level higher than that of pure silicon dioxide. Introducing nitrogen into the field release dielectric layer increases both permittivity and dielectric constant, resulting in a more uniform electric field distribution across the layer and reducing the peak electric field near the junction of the gate dielectric and the field release dielectric layer. This reduction in maximum electric field and more uniform field distribution compared to similar devices with silicon dioxide field release dielectric layers leads to a larger surface breakdown voltage in nitrogen-doped field release dielectric layer LDMOS microelectronic devices. The improved surface breakdown voltage with nitrogen-doped field release dielectric layers allows for increased doping in the body region, which improves the body breakdown voltage while simultaneously reducing the on-resistance of LDMOS microelectronic devices with nitrogen-doped field release dielectric layers. An additional benefit of the higher dielectric constant of nitrogen-doped field release dielectric layers compared to undoped field release dielectric layers in a given device is improved channel hot carrier (CHC) performance. The microelectronic device further includes a source region disposed in the body region, the source region having the second conductivity type; and a drain region disposed in the drift region, the drain region having the second conductivity type.

[0015] The described examples encompass doped regions of various semiconductor structures, which may be characterized as p-doped and / or n-doped regions or portions, and contain regions with a specific type of dominant dopant, such as an n-type dopant (providing electrons as charge carriers) or a p-type dopant (providing holes as charge carriers). For the purposes of this description, the first type of doping may be n-type doping (n-doping, first conductivity type), and the second type of doping may be p-type doping (p-doping, second conductivity type).

[0016] Figures 1A to 1L This is a cross-section of an example microelectronic device 100 that includes an LDMOS transistor 101 in a series of steps of an example fabrication method. The LDMOS transistor 101 may have the following characteristics as shown in the reference diagram. Figure 2 The described raceway layout (with gate electrodes in a closed-loop configuration). Although the LDMOS transistor 101 described herein is an n-channel type (or n-channel LDMOS), a p-channel type LDMOS transistor (or p-channel LDMOS) can be formed according to this disclosure when the n-doped region is replaced by a p-doped region and the p-doped region is replaced by an n-doped region.

[0017] Figure 1A A cross-section of a microelectronic device 100 is shown, the microelectronic device 100 comprising a substrate wafer 105 composed of a semiconductor material referred to herein as substrate 103. Substrate 103 has a top surface 104. Substrate wafer 105 may be, for example, a portion of a bulk semiconductor wafer, a portion of a semiconductor wafer having an epitaxial layer, a portion of a silicon-on-insulator (SOI) wafer, or other structures suitable for forming the microelectronic device 100.

[0018] The substrate wafer 105 may include an optional n-type buried layer (NBL) 106 on the substrate wafer 105. For example, the substrate wafer 105 may be p-type, wherein the dopant concentration is 1 × 10⁻⁶. 17 From atoms per cubic centimeter to 1 × 10⁻⁶ 18 Atoms per cubic centimeter. Alternatively, the substrate wafer 105 can be lightly doped, with an average dopant concentration of less than 1 × 10⁻⁶ atoms per cubic centimeter. 16 One atom per cubic centimeter. For example, NBL 106 can be 2 micrometers to 10 micrometers thick and can have 1 × 10⁻⁶ atoms per cubic centimeter. 17 From atoms per cubic centimeter to 1 × 10 18 The dopant concentration is atoms per cubic centimeter. The substrate wafer 105 may contain a silicon epitaxial layer 107 on the NBL 106. For example, the epitaxial layer 107 is part of the substrate 103 and may be 2 micrometers to 12 micrometers thick. For example, the epitaxial layer 107 may be p-type, with a dopant concentration of 1 × 10⁻⁶. 15 From atoms per cubic centimeter to 1 × 10⁻⁶ 16 Atoms per cubic centimeter. In this example version where the substrate wafer 105 lacks NBL 106, the epitaxial layer 107 may be located directly on the substrate wafer 105. As will become apparent in the discussion, the epitaxial layer 107 may serve as the body region 108 of the LDMOS transistor 101. The body region 108 has a first conductivity type.

[0019] A first pad oxide layer 110 of silicon dioxide may be formed on a substrate 103. The first pad oxide layer 110 may comprise silicon dioxide formed by a thermal oxidation process or a chemical vapor deposition (CVD) process. The first pad oxide layer 110 may provide stress relief between the substrate 103 and subsequent layers. For example, the first pad oxide layer 110 may be 5 nm to 50 nm thick. A first silicon nitride layer 112 may then be deposited and a photomask (not shown) may be formed. The photomask acts to mask the first silicon nitride layer 112, and the photomask may comprise a photosensitive organic material that is coated, exposed, and developed. A plasma etching process (not shown) removes the first silicon nitride layer 112, the first pad oxide layer 110, and the epitaxial layer 107 from the exposed areas of the photomask to define a trench 114 for a shallow trench isolation (STI) field oxide region 116. The trench 114 is then filled with a dielectric, such as high-density plasma (HDP) oxide (not specifically shown), followed by chemical mechanical planarization to form a field oxide region 116 in the trench 114. Subsequent wet cleaning (not specifically shown) removes the first silicon nitride layer 112 and the first pad oxide layer 110, leaving the dielectric-filled field oxide region 116. Alternatively, localized silicon oxide (LOCOS) isolation (not specifically shown) can be used instead of STI-based field oxide regions 116 to provide electrical isolation.

[0020] refer to Figure 1B A second pad oxide layer 118 is formed on the top surface 104, and a second silicon nitride layer 120 is formed on the second pad oxide layer 118. The thickness of the second silicon nitride layer 120 may be greater than 90 nm to provide for... Figure 1C The injection mask for the subsequent nitrogen-containing plasma 128 step discussed in the text. A photomask defining the open region 122 is formed (not specifically shown). Subsequent plasma etching is used to remove the second silicon nitride layer 120 and the second pad oxide layer 118 from the open region 122 exposing the top surface 104 of the microelectronic device 100. A field release dielectric layer 126 can be formed in the open region 122 using local oxidation of silicon (LOCOS) furnace oxidation 124. Subsequent wet chemical removal of the second silicon nitride layer 120 and the second pad oxide layer 118 is then performed (not shown). In various examples, the field release dielectric layer 126 has a thickness in the range of 50 nm to 150 nm. Dielectric layers derived from LOCOS-type processes, such as the field release dielectric layer 126, have tapered edges, become thinner near their periphery, and terminate in a "beak" shape at the junction of the field release dielectric layer 126 with the epitaxial layer 107. Alternatively, the field release dielectric layer 126 can use Figure 3 The field-release dielectric layer 126 was formed using the STI method referenced in the text. The grown field-release dielectric layer 126 is a high-purity form of silicon dioxide (>99.99% SiO2). The dielectric constant of the field-release dielectric layer 126 is approximately 3.9.

[0021] refer to Figure 1C Nitrogen-containing plasma 128 can be used, which binds nitrogen to... Figure 1B In the field release dielectric layer 126 to form Figure 1C The nitrogen-doped field-release dielectric layer 130 shown is illustrated. The nitrogen-containing plasma 128 may contain dinitrogen (N2), ammonia (NH3), or other nitrogen-containing precursors. The resulting nitrogen-doped field-release dielectric layer 130 may contain atomic percentage nitrogen as a component, exhibiting silicon nitride (Si). X N Y ), silicon oxynitride (Si) X O Y N z Various stoichiometry of nitrogen and interstitial nitrogen, as a single component or any combination thereof. The nitrogen doping depth in the nitrogen-doped field release dielectric layer 130 can range from 50 to 150 nm, and although the nitrogen-doped field release dielectric layer 130 is primarily silicon dioxide, it can have a nitrogen concentration greater than 20% atomic percentage, depending on the nitrogen-containing plasma 128 formation conditions. The nitrogen-containing plasma 128 can result in a nitrogen-doped field release dielectric layer 130 with a uniform concentration or a nitrogen doping gradient throughout the film, wherein there is a higher nitrogen doping concentration at the top surface of the nitrogen-doped field release dielectric layer 130 and a lower nitrogen concentration near the interface between the nitrogen-doped field release dielectric layer 130 and the substrate 103. The RF power of the nitrogen-containing plasma 128 is typically between 100 W and 2000 W, and can contain RF bias plasma power greater than 1000 W. While the dielectric constant of the undoped field release dielectric layer 126 is approximately 3.9, the dielectric constant of the nitrogen-doped field release dielectric layer 130 can be greater than 5.5. Advantageously, the dielectric constant is increased by forming the nitrogen-doped field release dielectric layer 130 because, compared to a similar LDMOS transistor 101 with an undoped field release dielectric layer 126, the higher dielectric constant of the nitrogen-doped field release dielectric layer 130 improves the breakdown voltage, reduces the specific on-resistance (when coupled with a higher doping concentration in the drain drift region 138), and improves the channel hot carrier (CHC) reliability performance of a given LDMOS transistor 101.

[0022] Figure 1D The image shows a cross-section after the deposition and patterning of n-drift resist 132 to form n-drift resist openings 134. One or more n-type implantations 136 are performed to form drain drift regions 138 (which may be referred to as n-drift regions) in exposed areas of the substrate 103. The n-type implantations 136 used to define the drain drift regions 138 can occur in multiple steps. For example, phosphorus can be 1 × 10⁻⁶. 12 cm -2 With 1×1013 cm -2 The total dose injected between these parameters has an energy suitable for forming the drain drift region 138 with or without subsequent thermal cycling. Arsenic can also be injected in a similar dose, with a relatively lower energy than phosphorus implants. Following n-type implantation 136, the n-drift resist 132 is removed.

[0023] Also refer to Figure 1D P-type doping can be added to epitaxial layer 107 using high-energy p-type implants (not specifically shown) to form an optional p-type buried layer (PBL) 140. The high-energy p-type implants may include doses of 1 × 10⁻⁶. 12 cm -2 Up to 1 × 10 13 cm -2 Boron with energies ranging from 400 keV to 3 MeV is used. Indium can also be used as the implant material. For the low-voltage (e.g., 20 V) version of the LDMOS transistor 101, the high-energy p-type implant can be a blanket implant, while for the higher-voltage (e.g., >30 V) version of the LDMOS transistor 101, the high-energy p-type implant can be a mask implant to allow selective placement. For mask implantation, a photomask (not specifically shown) is deposited and patterned with openings that expose the region of the epitaxial layer 107 to which the high-energy p-type implant is to be implanted. High-energy p-type implantation is followed by thermal drive (not specifically shown), which extends the high-energy p-type implant material below the drain drift region 138. Dedicated thermal drive is optional, as activation of the high-energy p-type implant material can also be achieved with... Figure 1H After the formation of the n-type dwelling zone 168 discussed in the middle and Figure 1E The same damage annealing process was used after the formation of the p-type shallow well region 148 discussed in the paper.

[0024] refer to Figure 1E A photomask 142 is deposited and patterned with a shallow p-well opening 144, which exposes a region for forming a shallow p-well implantation 146 in the substrate 103 for forming a p-well region 148. The p-well implantation 146 may include one or more implantation steps, each performed at a different energy. The body doping provided by the p-well region 148 increases the base doping level to suppress parasitic bipolar transistor formation within the LDMOS transistor 101 and increase the safe operating area (SOA).

[0025] refer to Figure 1FThe image shows a cross-section after the formation of the gate dielectric layer 150 and the gate polysilicon layer 152. The gate dielectric layer 150 can be formed in a high-temperature furnace operation or a rapid thermal process. Other methods for forming the gate dielectric layer 150 are within the scope of this disclosure. For silicon dioxide or silicon oxynitride (SiON) gate dielectrics, the thickness of the gate dielectric layer 150 can range from approximately 3 nm to 15 nm, and it can be slightly thinner but has a higher dielectric constant than silicon dioxide; for example, the dielectric constant of silicon dioxide is approximately 3.9. The gate polysilicon layer 152 is formed on the gate dielectric layer 150. In some instances, the gate polysilicon layer 152 is formed using a deposition process that deposits polysilicon (which may be referred to as polysilicon) using one or more silane-based precursors. In other instances, alternative gate processes can be used to form the gate polysilicon layer 152. In this example, the gate polysilicon layer 152 comprises polysilicon. The gate polysilicon layer 152 has a thickness that can range from approximately 50 nm to 300 nm. Furthermore, the gate polysilicon layer 152 can be undoped during deposition. Subsequently, the gate polysilicon layer 152 will be doped, as shown in the reference. Figure 1J To describe in more detail.

[0026] Figure 1G The diagram shows cross-sections after the formation of gate resist 154 and after gate plasma etching 156. Gate plasma etching 156 removes the previously formed gate dielectric layer 150 and gate polysilicon layer 152 in areas not covered by gate resist 154, wherein the region beneath gate resist 154 defines the gate electrode 158. Gate electrode 158 may have the following characteristics as shown in the reference diagram. Figure 2 The described raceway layout (closed-loop configuration). After gate plasma etching 156 is completed, the gate resist 154 is removed, and the wafer surface can be cleaned using either a wet or dry process. Figure 1G As shown, the gate electrode 158 extends over a portion of the body region 108, a portion of the drain drift region 138, and a portion of the nitrogen-doped field-release dielectric layer 130 of the LDMOS transistor 101. One end of the gate electrode 158 terminates over the nitrogen-doped field-release dielectric layer 130, while the opposite end of the gate electrode 158 terminates over the subsequently formed p-type well region 166 (see reference). Figure 1H - For example, terminating above a p-type well region 166 in body region 108, said body region being electrically connected to a source region 178 formed later, as... Figure 1J As depicted in the text.

[0027] Figure 1H The cross-section is shown after the p-trap resist 162 has been deposited and patterned to form the p-trap resist opening 164. Figure 1HThe experiment also demonstrates performing p-type implantation 165 to form a p-type well region 166 (which may be referred to as a p-well region). The p-type dopant implanted by p-type implantation 165 may contain boron and / or indium. For example, energies between 80 keV and 3 MeV and doses of 4.0 × 10⁻⁶ can be used. 12 cm -2 Up to 1.5×10 14 cm -2 A series of boron implants, with an angle of less than 10 degrees, are used to implant the p-type well region 166. The p-type well region 166 and the body region 108 form the body of the LDMOS transistor 101. After p-type implantation 165, the p-type well resist 162 is removed. Subsequently, a thermal process can be used to activate dopants, such as dopants in the drain drift region 138 and dopants in the p-type well region 166. Optionally, an n-type dopant, such as arsenic or antimony, can also be added to the source side of the LDMOS transistor 101 (resist pattern not shown) to form an n-type dwell region 168. For example, a dose of 5 × 10⁻⁶ is used. 13 cm -2 Up to 1.2×10 15 cm -2 (For example, 8×10) 14 cm -2 Arsenic with energies from 10 keV to 50 keV (e.g., 15 keV and a 15-degree ion implantation tilt angle) can be used in a particular instance for the n-type residence region 168 dopant, or some or all of this implantation can be at, for example, a 45-degree angle (2 or 4 rotations). The implantation angle can also be straight (at 0 degrees) or from 0 degrees to 45 degrees.

[0028] Figure 1I Sidewall 170 may be formed on the lateral surface of gate electrode 158. Sidewall 170 is formed by blanket formation of one or more conformal layers of dielectric material over substrate 103 and gate electrode 158. The dielectric material is then removed from the lateral surface, i.e., the surface generally parallel to the top surface 104 of substrate 103, by an anisotropic etching process, such as reactive ion etching (RIE), leaving the dielectric material on the lateral surface of gate electrode 158 as sidewall 170. Sidewall 170 may comprise a dielectric material, such as silicon dioxide, silicon nitride, or both. Sidewall 170 may extend from the lateral edge of gate electrode 582 by 50 nanometers to 200 nanometers.

[0029] Figure 1JThe image shows a cross-section after the deposition and patterning of source and drain resist 172. Source and drain implantation 176 implants n-type dopant into the substrate 103 through source and drain resist openings 174 to form source region 178, drain region 180, and to provide n-type doping for the gate electrode 158. Source and drain implantation 176 can occur in one or more steps, wherein the implanted material contains one or more of phosphorus and arsenic, with a total dose of 5 × 10⁻⁶. 13 cm -2 With 4.5×10 15 cm -2 The energy is between 2 keV and 80 keV. The source region 178 and drain region 180 contain at least twice the average dopant density of the drain drift region 138. After forming the source region 178 and drain region 180, the source and drain resist 172 is removed.

[0030] refer to Figure 1K The process involves depositing and patterning a second source and drain resist 182 to form second source and drain resist openings 184 for subsequent second source and drain implantation 186. Second source and drain implantation 186 implants p-type dopant to form the back gate region 188 of the LDMOS transistor 101. Second source and drain implantation 186 also implants p-type dopant in the source and drain regions of a p-channel transistor in the microelectronic device 100 (not specifically shown). Second source and drain implantation 186 may occur in one or more steps, wherein the implanted material contains boron (or indium), and the total dose and energy are suitable for providing degenerate doping to the back gate region 188, for example, greater than 1 × 10⁻⁶ near the solubility limit of the dopant atoms in the back gate region 188. 19 / cm 3 The active average dopant density. After implanting the second source and drain at 186, the second source / drain resist at 182 is removed.

[0031] Figure 1L This image shows a cross-section of the LDMOS transistor 101 after the first layer of interconnect 194 is completed. In some instances, a metal silicide layer (not specifically shown) may be formed on an exposed area of ​​the top surface 104 of the substrate 103. A metal front dielectric (PMD) layer 190 is formed above the top surface 104 of the substrate 103. The PMD layer 190 may comprise one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, etc. In some instances, the PMD layer 190 comprises a PMD liner (not specifically shown) and a primary dielectric sublayer formed on the PMD liner. Subsequently, the PMD layer 190 may be planarized using a chemical mechanical polishing (CMP) process.

[0032] Contacts 192 can be formed through the PMD layer 190. Contacts 192 can be formed by patterning and etching holes through the PMD layer 190. Contacts 192 can be formed by sputtering titanium to form a titanium adhesion layer, followed by filling with a titanium nitride diffusion barrier. The tungsten core can then be formed using a process employing tungsten hexafluoride (WF6). Subsequently, the tungsten, titanium nitride, and titanium are removed from the top surface of the PMD layer 190 by a plasma etching process, a tungsten CMP process, or a combination of both, leaving contacts 192 extending to the top surface of the PMD layer 190.

[0033] Interconnect 194 may be formed on contact 192. Contact 192 and interconnect 194 provide electrical contact between LDMOS transistor 101 and other components of microelectronic device 100. In this example version where interconnect 194 has an etched aluminum structure, interconnect 194 may be formed, for example, by depositing an adhesion layer, an aluminum layer, and an anti-reflective layer, and forming an etch mask (not explicitly shown), followed by a RIE process to etch the anti-reflective layer, aluminum layer, and adhesion layer exposed by the etch mask, and then removing the etch mask.

[0034] In this example version where interconnect 194 has a damascene structure, interconnect 194 can be formed by forming an intermetallic dielectric (IMD) layer (not specifically shown) on PMD layer 190 and etching interconnect trenches through the IMD layer to expose contacts 192. The interconnect trenches may be filled with a barrier liner and copper. The copper and barrier liner can then be removed from the top surface of the IMD layer using a copper CMP process.

[0035] Figure 2 This is a top view of a microelectronic device 200 including an LDMOS transistor 201 in a racetrack configuration, such as a racetrack layout (or a generally rounded rectangular layout) that is generally larger in a first orientation than in a second orientation perpendicular to the first orientation. The racetrack configuration may also be referred to as a closed-loop configuration. The LDMOS transistor 201 includes aspects of the LDMOS transistor 101 described with reference to 1A to 1L. The LDMOS transistor 201 includes a gate electrode 258 in a racetrack configuration.

[0036] like Figure 2 As shown, drain region 280 may be the single innermost element of LDMOS transistor 201, while the other elements shown form a series of concentric closed-loop elements surrounding drain region 280. Nitrogen-doped field-release dielectric layer 230 is adjacent to drain region 280. Other elements of LDMOS transistor 201 include gate electrode 258, sidewall 270, source region 278, field oxide region 216, and p-type body well 266.

[0037] Figure 3This is a cross-section of an alternative example microelectronic device 300, which includes an LDMOS transistor 301 having a nitrogen-doped field-release dielectric layer 330. The LDMOS transistor 301 includes references 1A to 1L and... Figure 2 Aspects of LDMOS transistors 101 and 201 are described. LDMOS transistor 301 differs from LDMOS transistor 101 in that its nitrogen-doped field-release dielectric layer 330 utilizes STI instead of LOCOS as a means of electrical isolation.

[0038] Figure 3 Both the nitrogen-doped field release dielectric layer 330 and the field oxide region 316 in the process use, for example, Figure 1A The STI process discussed in the section on the formation of the field oxide region 116 forms an undoped dielectric film. Both can be formed simultaneously. When formed, both films are undoped. (See reference...) Figure 1A Following the shallow trench isolation formation step, a patterning step can be used to open the region above the nitrogen-doped field release dielectric layer 330 for nitrogen doping, while leaving the region above the field oxide region 316 unexposed, thus allowing the field oxide region 316 to remain undoped. In an alternative embodiment, a nitrogen precursor source can be used during STI oxide deposition to form nitrogen doping. A nitrogen precursor source during STI deposition is a method to ensure uniform deposition of the nitrogen dopant in the nitrogen-doped field release dielectric layer 330, although the nitrogen precursor in the source during STI deposition prevents the bonding of the undoped field oxide region 316 with the nitrogen-doped field release dielectric layer 330.

[0039] Also refer to Figure 3 A p-well region 366 (which includes aspects of p-type well region 166) is shown adjacent to drain drift region 338 (which includes aspects of drain drift region 138), but this disclosure is not limited thereto. For example, p-well region 366 may be spaced apart from drain drift region 338 such that epitaxial layer 307 may extend between drain drift region 338 and p-well region 366 to the top surface 304 of substrate 303. Other components in LDMOS transistor 301 include substrate wafer 305, n-type buried layer 306, optional p-type buried layer (PBL) 340, body region 308, gate dielectric 350, gate polysilicon layer 352, gate electrode 358, n-type region 368, and sidewall 370. Additional layers include source region 378, drain region 380, back gate region 388, PMD layer 390, contact 392, and interconnect 394.

[0040] While various embodiments of this disclosure have been described above, it should be understood that they are presented by way of example only and not as limitations. Thus, although the foregoing examples of using various resist layers (e.g., photoresist or photomask layers) to perform various process steps (e.g., implantation or etching steps) have been described, this disclosure is not limited thereto. For example, one or more hard masks (comprising one or more layers) may be patterned to define various regions for subsequent process steps to be applied (e.g., regions for receiving dopant atoms, regions for blocking etchant). Furthermore, in some instances, the resist layer may comprise multiple layers of resist instead of a single layer. Many changes may be made to the disclosed embodiments herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the foregoing embodiments. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: The semiconductor material of the substrate includes a body region having a first conductivity type and a drain drift region having a second conductivity type; A doped field release dielectric layer above the drain drift region, the doped field release dielectric layer mainly comprising silicon dioxide and containing at least 5 atomic percent nitrogen, the doped field release dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than that of the gate dielectric layer; wherein the gate dielectric layer above the body region extends above the intersection point between the body region and the drain drift region; The gate electrode above the gate dielectric layer; as well as A drain region having the second conductivity type and contacting the drain drift region, wherein the average dopant density of the drain region is greater than the average dopant density of the drain drift region.

2. The semiconductor device of claim 1, wherein the doped field release dielectric layer comprises a localized silicon oxide (LOCOS) layer of silicon dioxide, the silicon dioxide comprising at least 5 atomic percent nitrogen and comprising tapered edges.

3. The semiconductor device of claim 1, wherein the doped field release dielectric layer comprises a shallow trench isolation (STI) layer of silicon dioxide, the silicon dioxide comprising at least 5 atomic percent nitrogen.

4. The semiconductor device of claim 1, wherein a portion of the atomic percentage nitrogen in the doped field release dielectric layer is a component of silicon nitride.

5. The semiconductor device of claim 1, wherein a portion of the atomic percentage nitrogen in the doped field release dielectric layer is a component of silicon oxynitride.

6. The semiconductor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

7. The semiconductor device of claim 1, wherein the atomic percentage nitrogen of the doped field release dielectric layer is more concentrated at the top surface of the doped field release dielectric layer than at the interface between the doped field release dielectric layer and the substrate.

8. The semiconductor device of claim 1, wherein the atomic percentage nitrogen of the doped field release dielectric layer has an approximately uniform concentration of atomic percentage nitrogen throughout the doped field release dielectric layer.

9. The semiconductor device of claim 1, wherein the gate electrode has a closed-loop configuration.

10. The semiconductor device of claim 1, wherein the doped field oxide comprises at least 5 atomic percent nitrogen.

11. A method of forming a microelectronic device, comprising: A body region and a drain drift region are formed in a semiconductor material of a substrate, wherein the body region has a first conductivity type and the drain drift region has a second conductivity type; A doped field release dielectric layer is formed above the drain drift region, the doped field release dielectric layer having a nitrogen atomic percentage greater than 5 and a thickness greater than that of the gate dielectric layer; The gate dielectric layer is formed above the body region, and the gate dielectric layer extends above the intersection point between the body region and the drain drift region; A gate electrode is formed above the gate dielectric layer; A source region of the second conductivity type is formed in contact with the body region, wherein the average dopant density of the source region is greater than the average dopant density of the body region; as well as A drain region of the second conductivity type is formed in contact with the drain drift region, wherein the average dopant density of the drain region is greater than the average dopant density of the drain drift region.

12. The method of claim 11, wherein the field release dielectric layer is formed by localized silicon oxide (LOCOS).

13. The method of claim 11, wherein the field release dielectric layer is formed by shallow trench isolation (STI).

14. The method of claim 11, wherein the doped field release dielectric layer is formed by a nitrogen-containing plasma comprising dinitrogen (N2), the nitrogen-containing plasma incorporating an atomic percentage of nitrogen into the field release dielectric layer.

15. The method of claim 11, wherein the doped field release dielectric layer is formed by a nitrogen-containing plasma comprising ammonia (NH3), the nitrogen-containing plasma incorporating an atomic percentage of nitrogen into the field release dielectric layer.

16. The method of claim 11, wherein the doped field release dielectric layer is formed by a dielectric deposition process comprising at least one nitrogen-containing precursor.

17. The method of claim 11, wherein the doped field release dielectric layer and the doped field oxide layer are formed simultaneously.

18. The method of claim 11, wherein a portion of the atomic percentage nitrogen in the doped field release dielectric layer is formed as silicon nitride by nitrogen-containing plasma.

19. The method of claim 11, wherein a portion of the atomic percentage nitrogen in the doped field release dielectric layer is formed as silicon oxynitride by nitrogen-containing plasma.

20. The method of claim 11, wherein the atomic percentage nitrogen of the doped field release dielectric layer is formed at a higher concentration of nitrogen at the top surface of the doped field release dielectric layer than at the interface between the doped field release dielectric layer and the substrate.

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