Data transmission skew calibration method, device and chip

Abstract

The invention relates to a data sending skew calibration method, a data sending skew calibration device and a chip, and the method comprises the following steps: a local core grain serving as a data sending end executes two-dimensional scanning based on data link skew coding and clock signal phase interpolation, the test data is sent to the data receiving end of the remote core particle serving as the data receiving end through any data channel; the local core particle receives an analysis result which is returned by the remote core particle and is associated with the test data, and a skew code-phase interval in which the test data can be correctly received by the remote core particle is obtained according to the analysis result; and according to the skew coding-phase interval, determining the optimal data link skew coding of the local core grain for any data channel. According to the invention, the problem that the real optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew coding of the transmitting end and the transmission line delay can be solved, and the robustness of data transmission can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a data transmission skew calibration method, apparatus and chip. Background Technology

[0002] UCIe (Universal Chiplet Interconnect Express) is an open and unified interconnect protocol for chips, designed to enable high-speed, low-latency, and high-bandwidth interconnect communication between chips manufactured by different manufacturers and using different processes within the same package, thereby improving system performance and reducing power consumption and cost.

[0003] UCIe uses multiple parallel data lanes for high-speed data transmission between chips. Due to differences in packaging, wiring length, or process variations, slight differences in data arrival times on different data lanes are inevitable. This difference is called skew, and skew can occur at the data transmitter, data receiver, and other points. To ensure that the receiver can correctly sample the data, these skews must be calibrated; this process is called deskew. Summary of the Invention

[0004] In view of this, this disclosure provides a data transmission skew calibration method, apparatus, and chip to help solve the problem that the true optimal line delay point is incorrectly ignored due to the nonlinearity between the data link skew coding at the transmitting end and the transmission line delay, thereby helping to improve the robustness of data transmission.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] According to one aspect of the embodiments of this disclosure, a data transmission skew calibration method is provided, comprising:

[0007] The local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, which acts as the data receiver, through any data channel.

[0008] The local chip receives the analysis results related to the test data returned by the remote chip, and obtains the skew coding-phase interval that can be correctly received by the remote chip based on the analysis results;

[0009] Based on the skew coding-phase interval, the optimal data link skew coding for any one data channel is determined for the local chip.

[0010] In one possible implementation, the local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to transmit test data to the data receiver of a remote chip, acting as the data receiver, via any data channel, including:

[0011] From the preset minimum data link skew code to the maximum data link skew code, the data link skew code is gradually increased with a set first step length to obtain multiple different values ​​of the data link skew code.

[0012] In each of the data link skew coding cases, the clock signal phase interpolation is gradually increased from the preset minimum clock signal phase interpolation to the maximum clock signal phase interpolation with a set second step size to obtain multiple clock signal phase interpolation values ​​with different values.

[0013] The local chip transmits the test data to the remote chip through any one of the data channels, under the conditions of each of the multiple different values ​​of the data link skew coding and each of the multiple different values ​​of the clock signal phase interpolation.

[0014] In one possible implementation, the analysis result is the bit error rate;

[0015] The skew coding-phase interval includes the data link skew coding and the clock signal phase interpolation when the local chip transmits test data that can be correctly received;

[0016] Among them, the test data that can be correctly received refers to the test data that is determined to be correctly received by the remote chip based on the bit error rate.

[0017] In one possible implementation, the analysis results are obtained by comparing the test data received by the remote chip with the reference data stored locally by the remote chip.

[0018] In one possible implementation, obtaining the skew-coded-phase interval that allows the remote chip to correctly receive the test data based on the analysis results includes:

[0019] The bit error rate is compared with a preset bit error rate threshold.

[0020] The range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold is defined as the skew coding-phase interval.

[0021] In one possible implementation, determining the optimal data link skew code for any one data channel for the local chip based on the skew code-phase interval includes:

[0022] Obtain the phase value of the reference clock signal;

[0023] Within the skew coding-phase interval, at least one data link skew code associated with the phase value of the reference clock signal is determined;

[0024] The optimal data link skew code is obtained based on at least one data link skew code determined by the phase value associated with the reference clock signal.

[0025] In one possible implementation, determining at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval includes:

[0026] Within the skew coding-phase interval, the range of continuous clock signal phase interpolation associated with each data link skew code is obtained;

[0027] Based on the range of consecutive clock signal phase interpolations associated with each data link skew code, the median clock phase associated with each data link skew code is obtained, wherein the median clock phase is the midpoint between the maximum and minimum values ​​of the range of consecutive clock signal phase interpolations.

[0028] At least one data link skew code associated with the optimal clock median is determined as at least one data link skew code associated with the phase value of the reference clock signal, wherein the optimal clock median is the clock phase median that is equal to the phase value of the reference clock signal.

[0029] In one possible implementation, obtaining the optimal data link skew code based on at least one data link skew code determined to be associated with the phase value of the reference clock signal includes obtaining the optimal data link skew code using any one of the following first to fourth methods:

[0030] First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code;

[0031] The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code.

[0032] Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code;

[0033] Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

[0034] According to another aspect of the embodiments of this disclosure, a data transmission skew calibration apparatus is provided, comprising:

[0035] The two-dimensional scanning module, located in the local chip that serves as the data transmitter, is used to perform two-dimensional scanning based on data link skew coding and clock signal phase interpolation.

[0036] The test data transmission module, located in the local chip and coupled to the two-dimensional scanning module, is used to transmit test data to the remote chip, which is the data receiving end, through any data channel based on the two-dimensional scanning.

[0037] An analysis result receiving module, located in the local chip, is used to receive analysis results related to the test data returned by the remote chip;

[0038] An interval determination module, located in the local chip and coupled to the analysis result receiving module, is used to obtain the skew coding-phase interval that can be correctly received by the remote chip based on the analysis result;

[0039] An optimal skew coding determination module, located in the local core and coupled to the interval determination module, is used to determine the optimal data link skew coding of the local core for any one data channel based on the skew coding-phase interval.

[0040] In one possible implementation, the two-dimensional scanning module includes:

[0041] The skew coding scanning submodule is used to gradually increase the data link skew coding from the preset minimum data link skew coding to the maximum data link skew coding with a set first step length, and scan the data link skew coding with multiple different values ​​obtained sequentially.

[0042] The phase interpolation scanning submodule is used to scan the clock signal phase interpolation values ​​of multiple different values ​​one by one in each case of data link skew coding, from the preset minimum clock signal phase interpolation value to the maximum clock signal phase interpolation value, with a set second step size.

[0043] The test data transmission module is coupled to the skew coding scanning submodule and the phase interpolation scanning submodule, and is used to transmit the test data to the remote chip through any one of the data channels, under the conditions of each data link skew coding scanned by the skew coding scanning submodule and each clock signal phase interpolation scanned by the phase interpolation scanning submodule.

[0044] In one possible implementation, the analysis result is the bit error rate, and the interval determination module includes:

[0045] The bit error rate comparison submodule is used to compare the bit error rate with a preset bit error rate threshold value;

[0046] The interval determination submodule, coupled to the bit error rate comparison submodule, is used to determine the interval range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

[0047] In one possible implementation, the optimal skew coding determination module includes:

[0048] The clock phase acquisition submodule is used to acquire the phase value of the reference clock signal;

[0049] The skew coding range determination submodule, coupled to the clock phase acquisition submodule, is used to determine at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval.

[0050] An optimal skew code determination submodule, coupled to the skew code range determination submodule, is used to obtain the optimal data link skew code based on at least one data link skew code determined by the phase value associated with the reference clock signal.

[0051] In one possible implementation, the skew coding range determination submodule includes:

[0052] The phase interpolation range determination unit is used to obtain the range of continuous clock signal phase interpolation associated with each data link skew code within the skew code-phase interval.

[0053] A clock phase median determination unit, coupled to the phase interpolation range determination unit, is used to obtain the clock phase median associated with each data link skew code based on the range of continuous clock signal phase interpolation associated with each data link skew code, wherein the clock phase median is the intermediate value between the maximum and minimum values ​​of the range of continuous clock signal phase interpolation.

[0054] An optimal clock median determination unit, coupled to the clock phase median determination unit and the clock phase acquisition submodule, is used to compare the clock phase median associated with each data link skew code with the phase value of the reference clock signal to select the optimal clock median from the clock phase medians, wherein the optimal clock median is equal to the phase value of the reference clock signal;

[0055] A skew coding determination unit, coupled to the optimal clock median determination unit, is used to determine at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal.

[0056] In one possible implementation, the optimal skew coding determination submodule is used to obtain the optimal data link skew coding through any one of the following first to fourth methods:

[0057] First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code;

[0058] The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code.

[0059] Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code;

[0060] Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

[0061] According to another aspect of the present disclosure, a chip is provided, including a data transmission skew calibration device as described in any of the preceding claims.

[0062] As can be seen from the above scheme, the data transmission skew calibration method, device, and chip disclosed herein combine data link skew coding and clock signal phase interpolation for two-dimensional scanning. This allows the determined skew coding-phase interval, which can be correctly received by the remote chip, to reflect not only the relationship between the data link skew coding interval and the correctly received test data, but also the relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correctly received test data. This introduces a fine-tuning of the data link skew coding based on the reference clock signal using the clock signal phase interpolation interval. Based on this, the correlation between the finally determined data link skew coding and the reference clock signal can be optimized. This helps to solve the problem that the true optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew coding and the transmission line delay at the transmitting end, and helps to improve the robustness of data transmission. Attached Figure Description

[0063] Figure 1 This is a schematic diagram illustrating the relationship between data link skew coding and line delay.

[0064] Figure 2 This is a schematic flowchart illustrating a data transmission skew calibration method according to an illustrative embodiment;

[0065] Figure 3 This is a schematic diagram of a two-dimensional scanning process according to an illustrative embodiment;

[0066] Figure 4 This is a schematic diagram illustrating the process of obtaining the skew code-phase interval according to an illustrative embodiment;

[0067] Figure 5 This is a schematic diagram illustrating a two-dimensional skew coding-phase interval obtained based on a two-dimensional scan, according to an illustrative embodiment.

[0068] Figure 6 This is a schematic diagram illustrating a specific application scenario of a two-dimensional scanning process according to an illustrative embodiment;

[0069] Figure 7 This is a schematic diagram illustrating the steps for obtaining optimal data link skew coding according to an illustrative embodiment;

[0070] Figure 8 This is a schematic diagram illustrating the steps of determining the phase value associated with a reference clock signal according to an illustrative embodiment;

[0071] Figure 9 This is a schematic diagram of a data transmission skew calibration device according to an illustrative embodiment;

[0072] Figure 10 This is a schematic diagram of the circuit framework after incorporating the data transmission skew calibration method of the present disclosure into UCIe;

[0073] Figure 11 This is a schematic diagram of the state of the first built-in state machine in the phase interpolation scan control module, according to an illustrative embodiment.

[0074] Figure 12 This is a schematic diagram of the state of the second built-in state machine in the algorithm flow control module, according to an illustrative embodiment.

[0075] In the attached diagram, the component names represented by each number are as follows:

[0076] 100. Locally produced chips,

[0077] 110. Two-dimensional scanning module,

[0078] 111. Skew coding scanning submodule,

[0079] 112. Phase interpolation scanning submodule,

[0080] 120. Test data sending module,

[0081] 130. Analysis Result Receiving Module

[0082] 140. Interval Determination Module

[0083] 141. Bit error rate comparison submodule,

[0084] 142. Interval Determination Submodule

[0085] 150. Optimal skew coding determination module.

[0086] 151. Clock Phase Acquisition Submodule

[0087] 152. Skew coding range determination submodule,

[0088] 1521. Phase interpolation range determination unit.

[0089] 1522. Clock phase median determination unit.

[0090] 1523. Optimal Clock Median Determination Unit

[0091] 1524 skew coding determination unit,

[0092] 153. Optimal skew coding determination submodule. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0094] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0095] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0096] In relevant UCIe technologies, the deskewing process at the transmitter involves initiating an eye diagram scan to scan the skew codes of each data channel on the data link between the transmitter and receiver. Each data channel is scanned independently, and the scan identifies two boundary values ​​for the skew code that allow each channel to transmit data normally. The average of these two boundary values ​​is taken as the optimal skew code for the data channel. The skew code reflects the phase relationship between the data signal and the clock signal; changing the skew code while keeping the clock phase constant is equivalent to changing the phase of the data signal relative to the clock signal.

[0097] Figure 1 This is a schematic diagram illustrating the relationship between data link skew coding and line delay, such as... Figure 1 As shown, there is a significant non-linearity between data link skew coding and line delay. This is because related techniques determine the optimal value of the data link skew coding by scanning to find the left and right boundary values ​​of the data link skew coding that allow normal data transmission, and then taking the average of the left and right boundary values ​​as the optimal value. This involves combining... Figure 1 As shown, the left boundary value corresponds to the first line delay 'a', and the right boundary value corresponds to the second line delay 'b'. The first line delay 'a' is less than the second line delay 'b'. Because there is a large non-linearity between data link skew coding and line delay, the line delay corresponding to the optimal value of data link skew coding is not the midpoint between the first line delay 'a' and the second line delay 'b' corresponding to the left and right boundary values, respectively. The truly optimal line delay should be the midpoint between the first line delay 'a' and the second line delay 'b'. Therefore, in related technologies, simply taking the average of the two boundary values ​​will lead to the true optimal line delay point being incorrectly ignored, thereby reducing the robustness of data transmission.

[0098] In view of this, embodiments of this disclosure provide a data transmission skew calibration method, apparatus, and chip. Based on scanning the data link skew code, a clock signal phase interpolation (PI) scan is further introduced. Based on the two-dimensional scan of scanning the data link skew code and clock signal phase interpolation, the optimal data link skew code with reference to the clock signal phase is determined through the two-dimensional scan. Since there is a certain linear relationship between clock signal phase interpolation and link skew, the introduction of clock signal phase interpolation achieves the purpose of fine-tuning the data link skew code according to the clock signal phase interpolation. This can optimize the finally determined data link skew code, which helps to solve the problem that the true optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew code and the transmission line delay at the transmitting end, and helps to improve the robustness of data transmission.

[0099] Figure 2 This is a schematic flowchart illustrating a data transmission skew calibration method according to an illustrative embodiment, such as... Figure 2 As shown, the data transmission skew calibration method of this disclosure mainly includes the following steps 201 to 203.

[0100] Step 201: The local chip, acting as the data transmitter (TX), performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, acting as the data receiver (RX), through any data channel.

[0101] Step 202: The local chip receives the analysis results related to the test data returned by the remote chip, and obtains the skew coding-phase interval that can be correctly received by the remote chip based on the analysis results;

[0102] Step 203: Based on the skew coding-phase interval, determine the optimal data link skew coding for any data channel for the local core.

[0103] In an illustrative embodiment, the scanning range of the clock signal phase interpolation covers the phase value of the determined reference clock signal, that is, the phase value of the clock signal that has been aligned with the valid signal. The reference clock signal refers to the clock signal aligned with the valid signal, or in other words, the reference clock signal refers to the clock signal ultimately used by the local chip to send data to the remote chip.

[0104] The data transmission skew calibration method of this disclosure combines data link skew coding and clock signal phase interpolation for two-dimensional scanning. This allows the determined skew coding-phase interval, which can be correctly received by remote cores, to reflect not only the relationship between the data link skew coding interval and the correctly received test data, but also the relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correctly received test data. This introduces a fine-tuning of the data link skew coding based on the reference clock signal using the clock signal phase interpolation interval. Based on this, the correlation between the finally determined data link skew coding and the reference clock signal can be optimized. This helps to solve the problem that the true optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew coding and the transmission line delay at the transmitting end, and helps to improve the robustness of data transmission.

[0105] The data transmission skew calibration method of this disclosure is compatible with the UCIe protocol and can be executed in the LTSM_DATATRAINCENTER1 (link training state machine data training center 1) stage of the UCIe link training process.

[0106] Based on UCIe, the data channel is in the mainband, and the analysis results are transmitted through the sideband.

[0107] Figure 3 This is a schematic diagram of a two-dimensional scanning process according to an illustrative embodiment, such as... Figure 3 As shown in the illustrative embodiment, the two-dimensional scanning in this embodiment of the present disclosure, i.e., step 201, may include the following steps 301 to 303.

[0108] Step 301: Gradually increase the data link skew code from the preset minimum data link skew code to the maximum data link skew code, with a set first step length, to obtain multiple data link skew codes with different values.

[0109] Step 302: In each data link skew coding case, the clock signal phase interpolation is gradually increased from the preset minimum clock signal phase interpolation to the maximum clock signal phase interpolation with a set second step size to obtain multiple clock signal phase interpolation values ​​with different values.

[0110] Step 303: The local chip sends test data to the remote chip through any data channel, under the conditions of each data link skew code in multiple different values ​​of data link skew coding and each clock signal phase interpolation in multiple different values ​​of clock signal phase interpolation.

[0111] In an illustrative embodiment, the range between the minimum clock signal phase interpolation and the maximum clock signal phase interpolation covers the phase value of the determined reference clock signal.

[0112] In this illustrative embodiment, the analysis result is the bit error rate (BER). The skew coding-phase interval includes the data link skew coding and clock signal phase interpolation when the local chip transmits test data that can be correctly received. The test data that can be correctly received refers to the test data determined, based on the BER, to be correctly received by the remote chip.

[0113] In an illustrative embodiment, the analysis results are obtained by comparing the test data received by the remote chip with the reference data stored locally on the remote chip.

[0114] In the data transmission skew calibration method of this disclosure, when applied to the UCIe protocol, no modification to the remote core is required. The remote core simply performs bit error rate analysis in conjunction with the test data transmitted by the local core, which is already used in the link training process of UCIe. Based on UCIe, in the illustrative embodiment, the test data can be an LFSR (Linear Feedback Shift Register) Training Pattern.

[0115] Figure 4 This is a schematic diagram illustrating the process of obtaining the skew coding-phase interval according to an illustrative embodiment, as shown below. Figure 4 As shown in the illustrative embodiment, the process of obtaining the skew coding-phase interval in step 202 may include the following steps 401 to 402.

[0116] Step 401: Compare the bit error rate with the preset bit error rate threshold;

[0117] Step 402: Determine the range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

[0118] In the illustrative embodiment, when applied to UCIe, the bit error rate threshold can be directly adopted from the bit error rate threshold specified by UCIe, such as 10. -15 .

[0119] Figure 5 This is a schematic diagram illustrating a two-dimensional skew coding-phase interval obtained based on a two-dimensional scan, according to an illustrative embodiment. For example... Figure 5In the two-dimensional diagram shown, the horizontal direction represents the scanning direction of the data link skew coding, and the vertical direction represents the scanning direction of the clock signal phase interpolation. Horizontally, the data link skew coding value increases gradually from its minimum value c1 to its maximum value cN, following a preset step size. The number of data link skew codes N can be set as needed. Vertically, the clock signal phase interpolation value increases gradually from its minimum value φ1 to its maximum value φM, following a preset step size. The number of clock signal phase interpolation values ​​M can be set as needed. Figure 5 Each square in the diagram represents whether the test data corresponding to a certain data link skew code and clock signal phase interpolation was correctly received. A square marked with "P" indicates that the test data corresponding to that square was correctly received, while a square without "P" indicates that the test data corresponding to that square was not correctly received. For example, a square corresponding to data link skew code c1 and clock signal phase interpolation φ1 without "P" indicates that the test data corresponding to data link skew code c1 and clock signal phase interpolation φ1 was not correctly received. Conversely, a square corresponding to data link skew code cn1 and clock signal phase interpolation φm1 with "P" indicates that the test data corresponding to data link skew code cn1 and clock signal phase interpolation φm1 was correctly received.

[0120] See Figure 5 and combined Figure 3 As shown, in step 301, the preset minimum data link skew coding is, for example... Figure 5 c1, as shown, is the maximum data link skew coding, for example... Figure 5 The cN shown has a first step length that increases with each step from c1 to cN. This first step length can be, for example, the difference between c2 and c1, or the differences between cn2 and cn1, cn3 and cn2, cn4 and cn3, cn5 and cn4, and cn6 and cn5. Here, cn1, cn2, cn3, cn4, cn5, and cn6 are four data link skew codes that are sequentially spaced one first step length apart from c1 to cN. Based on this, step 301 can be to gradually increase the data link skew code from c1 to cN with a set first step length, obtaining multiple data link skew codes with different values ​​for c1, c2, ..., cn1, cn2, cn3, cn4, cn5, cn6, ..., cN.

[0121] See Figure 5 and combined Figure 3 As shown, in step 302, the preset minimum clock signal phase interpolation is, for example... Figure 5 As shown, φ1 represents the maximum clock signal phase interpolation, for example... Figure 5As shown in the diagram, the second step size is the step size that increases from φ1 to φM each time. The second step size can be, for example, the difference between φ2 and φ1, or the difference between φm2 and φm1, φm3 and φm2, φm4 and φm3, and φm5 and φm4. Here, φm1, φm2, φm3, φm4, and φm5 are five clock signal phase interpolations that are sequentially spaced one second step size apart from φ1 to φM. Based on this, step 302 can be a data link skew coding process that gradually increases the clock signal phase interpolation from φ1 to φM with a set second step size, obtaining multiple different values ​​for φ1, φ2, ..., φm1, φm2, φm3, φm4, φm5, ..., φM.

[0122] See Figure 5 and combined Figure 3 As shown, the conditions for each data link skew code in the multiple different values ​​of data link skew coding and each clock signal phase interpolation in the multiple different values ​​of clock signal phase interpolation in step 303 correspond to... Figure 5 Each square in the grid.

[0123] based on Figure 5 As shown, the bit error rate (analysis result) associated with the test data corresponding to each square, i.e., the bit error rate corresponding to each square, is compared with the bit error rate threshold in step 401. The skew coding-phase interval determined in step 402 is... Figure 5 The diagram shows all the squares containing the letter "P".

[0124] Figure 6 This is a schematic diagram illustrating a specific application scenario of a two-dimensional scanning process according to an illustrative embodiment. This specific application scenario process is based on... Figure 3 The two-dimensional scanning process shown is implemented as follows: Figure 6 And refer to Figure 5 As shown, the process of this specific application scenario mainly includes the following steps 601 to 607.

[0125] Step 601: Determine the preset minimum data link skew code as the current data link skew code, and determine the preset minimum clock signal phase interpolation as the current clock signal phase interpolation, then execute step 602.

[0126] Step 602: Using the current data link skew coding and the current clock signal phase interpolation, send test data to the remote chip through any data channel, and then execute step 603.

[0127] Step 603: Increase the current clock signal phase difference by the second step to obtain the updated current clock signal phase difference, and then execute step 604.

[0128] Step 604: Determine whether the current clock signal phase difference is greater than the preset maximum clock signal phase interpolation value. If yes, proceed to step 605; otherwise, proceed to step 602.

[0129] Step 605: Increase the current data link skew code by the first step length to obtain the updated current data link skew code, and then execute step 606.

[0130] Step 606: Determine whether the current data link skew code is greater than the preset maximum data link skew code. If so, end the process; otherwise, proceed to step 607.

[0131] Step 607: Determine the preset minimum clock signal phase interpolation as the current clock signal phase interpolation, and then execute step 602.

[0132] By looping through the specific application scenarios of steps 601 to 607, test data can be sent to a remote chip through any data channel under the conditions of each data link skew code in multiple different values ​​of data link skew coding and each clock signal phase interpolation in multiple different values ​​of clock signal phase interpolation.

[0133] Figure 7 This is a schematic diagram illustrating the steps for obtaining optimal data link skew coding according to an illustrative embodiment, as shown below. Figure 7 As shown, in an illustrative embodiment, step 203 may include steps 701 to 703 as follows.

[0134] Step 701: Obtain the phase value of the reference clock signal;

[0135] Step 702: Within the skew coding-phase interval, determine at least one data link skew code associated with the phase value of the reference clock signal;

[0136] Step 703: Obtain the optimal data link skew code based on at least one data link skew code determined to be associated with the phase value of the reference clock signal.

[0137] In the illustrative embodiment, the phase value of the reference clock signal is determined before de-skewing is performed. Based on the UCIe protocol, during link training, when the local chip (as the transmitter) sends test data to the remote chip (as the receiver), it is necessary to ensure the alignment between the clock signal and the valid signal sent by the local chip to the remote chip. The clock signal is sent by the local chip to the remote chip through the clock channel, and the valid signal is sent by the local chip to the remote chip through the valid signal channel. The valid signal is used by the remote chip to verify the received test data to ensure its validity. Therefore, when sending test data, only when the valid signal is aligned with the clock signal and the test data signal is aligned with the valid signal can the validity of the test data received by the remote chip be ensured, and bit error rate analysis can be performed based on this.

[0138] Figure 8 This is a schematic diagram illustrating the steps of determining the data link skew coding associated with a reference clock signal, according to an illustrative embodiment. Figure 8 As shown, in an illustrative embodiment, step 702 may include steps 801 to 803 as follows.

[0139] Step 801: Within the skew coding-phase interval, obtain the range of continuous clock signal phase interpolation associated with each data link skew code;

[0140] Step 802: Based on the range of continuous clock signal phase interpolation associated with each data link skew code, obtain the median of the clock phase associated with each data link skew code, where the median of the clock phase is the midpoint between the maximum and minimum values ​​of the range of continuous clock signal phase interpolation.

[0141] Step 803: Determine at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal, wherein the optimal clock median is the clock phase median that is equal to the phase value of the reference clock signal.

[0142] Combination Figure 5 As shown, the phase value at the location of the dashed line, i.e., "Ф", represents the phase value of the reference clock signal. Figure 5 In the illustrated embodiment, "Ф" is equal to "φm3".

[0143] like Figure 5 and combined Figure 8As shown, in step 801: within the skew coding-phase interval, the range of continuous clock signal phase interpolation associated with cn1 is φm2 to φm5, the range of continuous clock signal phase interpolation associated with cn2 is φm1 to φm5, the range of continuous clock signal phase interpolation associated with cn3 is φm1 to φm5, the range of continuous clock signal phase interpolation associated with cn4 is φm1 to φm5, the range of continuous clock signal phase interpolation associated with cn5 is φm1 to φm5, and the range of continuous clock signal phase interpolation associated with cn6 is φm1 to φm3. Wherein, for each data link skew coding test data is correctly received ( Figure 5 The phase interpolation of discontinuous clock signals containing "P" can be considered as an unstable result caused by factors such as temperature and noise, and can be disregarded.

[0144] like Figure 5 and combined Figure 8 As shown, in step 802: based on the interpolation range φm2 to φm5 of the continuous clock signal phases associated with cn1, the median value of the clock phase associated with cn1 is obtained as (φm2 + φm5) / 2, which is the midpoint between φm3 and φm4; based on the interpolation range φm1 to φm5 of the continuous clock signal phases associated with cn2, the median value of the clock phase associated with cn2 is obtained as (φm1 + φm5) / 2, which is φm3; based on the interpolation range φm1 to φm5 of the continuous clock signal phases associated with cn3, the median value of the clock phase associated with cn3 is obtained as (φm1 + φm5) / 2. ) / 2, i.e. φm3; Based on the interpolation range of continuous clock signal phases associated with cn4 from φm1 to φm5, the median value of the clock phase associated with cn4 is (φm1+φm5) / 2, i.e. φm3; Based on the interpolation range of continuous clock signal phases associated with cn5 from φm1 to φm5, the median value of the clock phase associated with cn5 is (φm1+φm5) / 2, i.e. φm3; Based on the interpolation range of continuous clock signal phases associated with cn6 from φm1 to φm5, the median value of the clock phase associated with cn6 is (φm1+φm3) / 2, i.e. φm2.

[0145] like Figure 5 and combined Figure 8 As shown, in step 803: the phase value of the reference clock signal is Ф, and Ф is equal to φm3, so the data link skew codes associated with the clock phase value of φm3, i.e., the phase value of the reference clock signal Ф, can be determined as c2, c3, c4 and c5.

[0146] After determining at least one data link skew code associated with the phase value of the reference clock signal, the optimal data link skew code can be selected from among various methods. In an illustrative embodiment, step 703 may include obtaining the optimal data link skew code using any one of the following first to fourth methods:

[0147] First method: Determine the smallest data link skew code among at least one data link skew code as the optimal data link skew code;

[0148] The second approach is to determine the largest data link skew code among at least one data link skew code as the optimal data link skew code.

[0149] The third approach: determine the intermediate data link skew code in at least one data link skew code as the optimal data link skew code;

[0150] The fourth method is to determine any one of the data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

[0151] Preferably, the optimal data link skew coding can be obtained using the first method.

[0152] like Figure 5 As shown, after determining the data link skew codes c2, c3, c4, and c5 associated with the phase value Ф of the reference clock signal, in step 703, c2 can be determined as the optimal data link skew code using the first method, c5 can be determined as the optimal data link skew code using the second method in step 703, and either c3 or c4 can be determined as the optimal data link skew code using the third or fourth method in step 703.

[0153] The data transmission skew calibration method of this disclosure combines data link skew coding and clock signal phase interpolation for two-dimensional scanning. This allows the determined skew coding-phase interval, which can be correctly received by remote cores, to reflect not only the relationship between the data link skew coding interval and the correctly received test data, but also the relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correctly received test data. This introduces a fine-tuning of the data link skew coding based on the reference clock signal using the clock signal phase interpolation interval. Based on this, the correlation between the finally determined data link skew coding and the reference clock signal can be optimized. This helps to solve the problem that the true optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew coding and the transmission line delay at the transmitting end, and helps to improve the robustness of data transmission.

[0154] This disclosure also provides a data transmission skew calibration device. Figure 9 This is a schematic diagram of the data transmission skew calibration device according to an illustrative embodiment, as shown below. Figure 9 As shown, the data transmission skew calibration device mainly includes a two-dimensional scanning module 110, a test data transmission module 120, an analysis result receiving module 130, an interval determination module 140, and an optimal skew code determination module 150. The two-dimensional scanning module 110, located in the local core 100 (the data transmission end), performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation. The test data transmission module 120, located in the local core 100 and coupled to the two-dimensional scanning module 110, transmits test data to a remote core (the data receiving end) through any data channel based on the two-dimensional scan. In the illustrative embodiment, when combined with UCIe, the data channel is located in the main band. The analysis result receiving module 130, located in the local core 100, receives analysis results related to the test data returned by the remote core. In the illustrative embodiment, when combined with UCIe, the analysis result receiving module 130 receives the analysis results from the sideband. The interval determination module 140, located in the local core 100 and coupled to the analysis result receiving module 130, is used to obtain the skew coding-phase interval that can correctly receive test data from the remote core based on the analysis results. The optimal skew coding determination module 150, located in the local core 100 and coupled to the interval determination module 140, is used to determine the optimal data link skew coding for any data channel of the local core 100 based on the skew coding-phase interval.

[0155] In illustrative embodiments, such as Figure 9 As shown, the two-dimensional scanning module 110 includes a skew coding scanning submodule 111 and a phase interpolation scanning submodule 112. The skew coding scanning submodule 111 is used to scan the data link skew codes of multiple different values ​​sequentially, from a preset minimum data link skew code to a preset maximum data link skew code, gradually increasing the skew code by a set first step size. The phase interpolation scanning submodule 112 is used to scan the clock signal phase interpolation values ​​of multiple different values ​​sequentially, from a preset minimum clock signal phase interpolation to a preset maximum clock signal phase interpolation, gradually increasing the clock signal phase interpolation by a set second step size, under each data link skew code scanned by the skew coding scanning submodule 111 and each clock signal phase interpolation value scanned by the phase interpolation scanning submodule 112. The test data transmission module 120 is coupled to the skew coding scanning submodule 111 and the phase interpolation scanning submodule 112, and is used to transmit test data to the remote chip through any data channel under each data link skew code scanned by the skew coding scanning submodule 111 and each clock signal phase interpolation value scanned by the phase interpolation scanning submodule 112.

[0156] In this illustrative embodiment, the analysis result is the bit error rate. For example... Figure 9 As shown, the interval determination module 140 includes a bit error rate comparison submodule 141 and an interval determination submodule 142. The bit error rate comparison submodule 141, coupled to the analysis result receiving module 130, is used to compare the bit error rate with a preset bit error rate threshold. The interval determination submodule 142, coupled to the bit error rate comparison submodule 141, is used to determine the interval range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

[0157] In illustrative embodiments, such as Figure 9 As shown, the optimal skew code determination module 150 includes a clock phase acquisition submodule 151, a skew code range determination submodule 152, and an optimal skew code determination submodule 153. The clock phase acquisition submodule 151 is used to acquire the phase value of the reference clock signal. The skew code range determination submodule 152, coupled to the clock phase acquisition submodule 151 and the interval determination module 140, is used to determine at least one data link skew code associated with the phase value of the reference clock signal within the skew code-phase interval. The optimal skew code determination unit 1524, coupled to the skew code range determination submodule 152, is used to obtain the optimal data link skew code based on the determined at least one data link skew code associated with the phase value of the reference clock signal.

[0158] In illustrative embodiments, such as Figure 9As shown, the skew coding range determination submodule 152 includes a phase interpolation range determination unit 1521, a clock phase median determination unit 1522, an optimal clock median determination unit 1523, and a skew coding determination unit 1524. The phase interpolation range determination unit 1521, coupled to the interval determination module 140, is used to obtain the range of continuous clock signal phase interpolations associated with each data link skew code within the skew coding-phase interval. The clock phase median determination unit 1522, coupled to the phase interpolation range determination unit 1521, is used to obtain the clock phase median associated with each data link skew code based on the range of continuous clock signal phase interpolations associated with each data link skew code, wherein the clock phase median is the midpoint between the maximum and minimum values ​​of the range of continuous clock signal phase interpolations. The optimal clock median determination unit 1523, coupled to the clock phase median determination unit 1522 and the clock phase acquisition submodule 151, is used to compare the clock phase median associated with each data link skew code with the phase value of the reference clock signal to select the optimal clock median from the clock phase medians, wherein the optimal clock median is equal to the phase value of the reference clock signal. The skew code determination unit 1524, coupled to the optimal clock median determination unit 1523 and the optimal skew code determination submodule 153, is used to determine at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal.

[0159] In an illustrative embodiment, the optimal skew coding determination unit 1524 is used to obtain the optimal data link skew coding through any one of the following first to fourth methods: First method: determining the minimum data link skew coding among at least one data link skew coding as the optimal data link skew coding; Second method: determining the maximum data link skew coding among at least one data link skew coding as the optimal data link skew coding; Third method: determining the intermediate data link skew coding among at least one data link skew coding as the optimal data link skew coding; Fourth method: determining any data link skew coding among at least one data link skew coding other than the minimum data link skew coding, the maximum data link skew coding, and the intermediate data link skew coding as the optimal data link skew coding.

[0160] Regarding the data transmission skew calibration device in the above embodiments, the specific manner in which each module and unit performs its operation has been described in detail in the embodiments related to the data transmission skew calibration method, and will not be elaborated here.

[0161] It should be noted that the above embodiments are only examples of the division of the above functional modules and units. In actual applications, the above functions can be assigned to different functional modules and units as needed, that is, the internal structure of the device can be divided into different functional modules and units to complete all or part of the functions described above.

[0162] In the illustrative embodiments, depending on the design, at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew coding determination module 150 can be implemented in a combination of multiple hardware, firmware, and software (i.e., programs).

[0163] In terms of hardware, at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew code determination module 150 can be implemented as logic circuits on an integrated circuit. For example, the related functions of at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew code determination module 150 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The related functions of at least one of the two-dimensional scanning module 110, test data sending module 120, analysis result receiving module 130, interval determination module 140, and optimal skew coding determination module 150 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0164] In software or firmware form, at least one of the related functions of the 2D scanning module 110, test data transmission module 120, analysis result receiving module 130, interval determination module 140, and optimal skew code determination module 150 can be implemented as programming codes. For example, at least one of the 2D scanning module 110, test data transmission module 120, analysis result receiving module 130, interval determination module 140, and optimal skew code determination module 150 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. Electronic devices (such as CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute programming code from a non-transient machine-readable storage medium to realize at least one of the related functions of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew coding determination module 150.

[0165] In an illustrative embodiment, this disclosure also provides a chip that includes a data transmission skew calibration device as described in any of the preceding embodiments.

[0166] In the illustrative embodiments, the data transmission skew calibration method and data transmission skew calibration device of the present disclosure are applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0167] The data transmission skew calibration method of this disclosure can be incorporated into UCIe. Figure 10 This is a schematic diagram of the circuit framework after incorporating the data transmission skew calibration method of this disclosure into UCIe. This circuit framework has its own scan control module for each of the 64 data channels, for example... Figure 10 The channel 0 scan control module, channel 1 scan control module, ..., channel 63 scan control module shown in the diagram, each data channel's scan control module includes a phase interpolation scan control module, a link skew value scan control module, and a scan result processing module. The circuit framework also includes an algorithm flow control module for controlling the scan control modules of each data channel.

[0168] The phase interpolation scan control module initiates multiple rounds of clock signal phase interpolation scans for this data channel based on the input scan boundary values, and calculates the optimal clock signal phase interpolation (i.e., the median clock phase in the above embodiment) under the current data link skew coding of this data channel based on the analysis results returned by the remote chip.

[0169] The phase interpolation scanning control module includes a first built-in state machine. Figure 11 This is a schematic diagram of the state of the first built-in state machine in the phase interpolation scan control module, as shown in an illustrative embodiment. Figure 11 As shown, the first built-in state machine includes six states: idle state, waiting for valid result state, scan state, waiting for adjustment completion state, end state, and error state. In the idle state, i.e., the phase interpolation scan is not enabled, the internal related functional circuit units are in the off state to reduce circuit power consumption. In the waiting for valid result state, the scan is enabled, the internal related functional circuit units are enabled, and they wait to receive relevant information. In the scan state, the internal related functional circuits process the result of the clock signal phase interpolation of the previous scan and determine the clock signal phase interpolation for the next scan. In the waiting for adjustment completion state, the next clock signal phase interpolation has been triggered, and it is necessary to wait for the clock signal phase interpolation to stabilize for a period of time at the digital-to-analog interface of the data channel from the local chip to the remote chip before switching to the next state. In the end state, it indicates that all related functions of clock signal phase interpolation have been completed and the relevant calculation results have been obtained. If no phase interpolation that allows the data channel to transmit and receive data normally is found during the entire clock signal phase interpolation process, the system enters the error state; that is, in the error state, no phase interpolation that allows the data channel to transmit and receive data normally is found during the entire clock signal phase interpolation process.

[0170] The link skew value scanning control module is used to send the data link skew code to the digital-to-analog interface, wherein the data link skew code is controlled by the algorithm flow control module.

[0171] The scan result processing module determines the optimal data link skew coding based on the analysis results obtained from the 2D scan, ensuring that the data signal transmitted by the data channel has the largest possible skew margin and improving the reliability of the data channel. See [link to data processing method] for details. Figure 5 That is, the description of the relevant embodiments above.

[0172] The algorithm flow control module controls the entire two-dimensional scanning process of the algorithm across all data channels and generates a completion flag. This module includes a second built-in state machine. Figure 12 This is a schematic diagram of the state of the second built-in state machine in the algorithm flow control module, as shown in an illustrative embodiment. Figure 12 As shown, the first built-in state machine includes five states: idle state, two-dimensional scan start state, two-dimensional scan end state, phase interpolation write-back state, and end state.

[0173] Idle state, meaning the state where 2D scanning is not activated. In the idle state, the relevant internal functional circuit units are turned off to reduce circuit power consumption.

[0174] In the 2D scanning start state, the upper layer control module used for control link training has received the start signal, and the relevant internal functional circuit units are turned on to start the 2D scanning.

[0175] At the end of the two-dimensional scan, the internal related functional circuit units have completed the two-dimensional scan process, and the clock signal phase interpolation and data link skew encoding have both reached the set maximum boundary values.

[0176] In the phase interpolation write-back state, since the phase interpolation of the clock signal of the digital-analog interface is changed multiple times during the two-dimensional scanning process, the phase interpolation of the reference clock signal (i.e., the phase value of the reference clock signal) needs to be fed back to the digital-analog interface after the calculation is completed. In this disclosure, adjusting the phase interpolation of the clock signal is only a means to obtain the optimal data link skew coding and not to change the phase of the clock signal.

[0177] In the final state, the two-dimensional scan has completed all relevant functions and obtained the optimal data link skew coding.

[0178] The data transmission skew calibration method, apparatus, and chip of this disclosure, through joint optimization of two-dimensional parameters, can effectively decouple the nonlinear coupling relationship between data link skew coding and data link delay. Experiments show that the data transmission skew calibration method of this disclosure improves calibration accuracy compared to related single-dimensional scanning methods in UCIe. The data transmission skew calibration method of this disclosure can be widely applied to related high-speed serial communication, clock data recovery (CDR) and other scenarios, helping to improve system timing stability and signal integrity.

[0179] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data transmission skew calibration method, comprising: The local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, which acts as the data receiver, through any data channel. The local chip receives the analysis results related to the test data returned by the remote chip, and obtains the skew coding-phase interval that can be correctly received by the remote chip based on the analysis results; Based on the skew coding-phase interval, the optimal data link skew coding for any one data channel is determined for the local chip.

2. The data transmission skew calibration method according to claim 1, characterized in that, The local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, acting as the data receiver, through any data channel, including: From the preset minimum data link skew code to the maximum data link skew code, the data link skew code is gradually increased with a set first step length to obtain multiple different values ​​of the data link skew code. In each of the data link skew coding cases, the clock signal phase interpolation is gradually increased from the preset minimum clock signal phase interpolation to the maximum clock signal phase interpolation with a set second step size to obtain multiple clock signal phase interpolation values ​​with different values. The local chip transmits the test data to the remote chip through any one of the data channels, under the conditions of each of the multiple different values ​​of the data link skew coding and each of the multiple different values ​​of the clock signal phase interpolation.

3. The data transmission skew calibration method according to claim 1, characterized in that: The analysis result is the bit error rate; The skew coding-phase interval includes the data link skew coding and the clock signal phase interpolation when the local chip transmits test data that can be correctly received; Among them, the test data that can be correctly received refers to the test data that is determined to be correctly received by the remote chip based on the bit error rate.

4. The data transmission skew calibration method according to claim 3, characterized in that: The analysis results are obtained by comparing the test data received by the remote core with the reference data stored locally by the remote core.

5. The data transmission skew calibration method according to claim 3, characterized in that, The step of obtaining the skew coding-phase interval that allows the remote chip to correctly receive the test data based on the analysis results includes: The bit error rate is compared with a preset bit error rate threshold. The range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold is defined as the skew coding-phase interval.

6. The data transmission skew calibration method according to claim 1, characterized in that, The step of determining the optimal data link skew coding for any data channel by the local chip based on the skew coding-phase interval includes: Obtain the phase value of the reference clock signal; Within the skew coding-phase interval, at least one data link skew code associated with the phase value of the reference clock signal is determined; The optimal data link skew code is obtained based on at least one data link skew code determined by the phase value associated with the reference clock signal.

7. The data transmission skew calibration method according to claim 6, characterized in that, The step of determining at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval includes: Within the skew coding-phase interval, the range of continuous clock signal phase interpolation associated with each data link skew code is obtained; Based on the range of consecutive clock signal phase interpolations associated with each data link skew code, the median clock phase associated with each data link skew code is obtained, wherein the median clock phase is the midpoint between the maximum and minimum values ​​of the range of consecutive clock signal phase interpolations. At least one data link skew code associated with the optimal clock median is determined as at least one data link skew code associated with the phase value of the reference clock signal, wherein the optimal clock median is the clock phase median that is equal to the phase value of the reference clock signal.

8. The data transmission skew calibration method according to claim 6, characterized in that, The step of obtaining the optimal data link skew code based on at least one data link skew code determined in relation to the phase value of the reference clock signal includes obtaining the optimal data link skew code using any one of the following first to fourth methods: First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code; The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code. Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code; Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

9. A data transmission skew calibration device, characterized in that, include: The two-dimensional scanning module, located in the local chip that serves as the data transmitter, is used to perform two-dimensional scanning based on data link skew coding and clock signal phase interpolation. The test data transmission module, located in the local chip and coupled to the two-dimensional scanning module, is used to transmit test data to the remote chip, which is the data receiving end, through any data channel based on the two-dimensional scanning. An analysis result receiving module, located in the local chip, is used to receive analysis results related to the test data returned by the remote chip; An interval determination module, located in the local chip and coupled to the analysis result receiving module, is used to obtain the skew coding-phase interval that can be correctly received by the remote chip based on the analysis result; An optimal skew coding determination module, located in the local core and coupled to the interval determination module, is used to determine the optimal data link skew coding of the local core for any one data channel based on the skew coding-phase interval.

10. The data transmission skew calibration device according to claim 9, characterized in that, The two-dimensional scanning module includes: The skew coding scanning submodule is used to gradually increase the data link skew coding from the preset minimum data link skew coding to the maximum data link skew coding with a set first step length, and scan the data link skew coding with multiple different values ​​obtained sequentially. The phase interpolation scanning submodule is used to scan the clock signal phase interpolation values ​​of multiple different values ​​one by one in each case of data link skew coding, from the preset minimum clock signal phase interpolation value to the maximum clock signal phase interpolation value, with a set second step size. The test data transmission module is coupled to the skew coding scanning submodule and the phase interpolation scanning submodule, and is used to transmit the test data to the remote chip through any one of the data channels, under the conditions of each data link skew coding scanned by the skew coding scanning submodule and each clock signal phase interpolation scanned by the phase interpolation scanning submodule.

11. The data transmission skew calibration device according to claim 9, characterized in that: The analysis result is the bit error rate, and the interval determination module includes: The bit error rate comparison submodule is used to compare the bit error rate with a preset bit error rate threshold value; The interval determination submodule, coupled to the bit error rate comparison submodule, is used to determine the interval range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

12. The data transmission skew calibration device according to claim 9, characterized in that, The optimal skew coding determination module includes: The clock phase acquisition submodule is used to acquire the phase value of the reference clock signal; The skew coding range determination submodule, coupled to the clock phase acquisition submodule, is used to determine at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval. An optimal skew code determination submodule, coupled to the skew code range determination submodule, is used to obtain the optimal data link skew code based on at least one data link skew code determined by the phase value associated with the reference clock signal.

13. The data transmission skew calibration device according to claim 12, characterized in that, The skew coding range determination submodule includes: The phase interpolation range determination unit is used to obtain the range of continuous clock signal phase interpolation associated with each data link skew code within the skew code-phase interval. A clock phase median determination unit, coupled to the phase interpolation range determination unit, is used to obtain the clock phase median associated with each data link skew code based on the range of continuous clock signal phase interpolation associated with each data link skew code, wherein the clock phase median is the intermediate value between the maximum and minimum values ​​of the range of continuous clock signal phase interpolation. An optimal clock median determination unit, coupled to the clock phase median determination unit and the clock phase acquisition submodule, is used to compare the clock phase median associated with each data link skew code with the phase value of the reference clock signal to select the optimal clock median from the clock phase medians, wherein the optimal clock median is equal to the phase value of the reference clock signal; A skew coding determination unit, coupled to the optimal clock median determination unit, is used to determine at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal.

14. The data transmission skew calibration device according to claim 12, characterized in that, The optimal skew coding determination submodule is used to obtain the optimal data link skew coding through any one of the following first to fourth methods: First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code; The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code. Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code; Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

15. A chip, characterized in that, Includes the data transmission skew calibration device as described in any one of claims 9 to 14.

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