Data transmission skew calibration method, device and chip

Abstract

The present disclosure relates to a data transmission skew calibration method, device and chip, the method comprising: performing two-dimensional scanning based on data link skew encoding and clock signal phase interpolation by a local chip particle as a data transmission end to transmit test data to a data receiving end of a remote chip particle as a data receiving end through any data channel; the local chip particle receives the analysis result returned by the remote chip particle in association with the test data, and obtains a skew encoding-phase interval in which the test data can be correctly received by the remote chip particle according to the analysis result; and the local chip particle determines the optimal data link skew encoding for any data channel according to the skew encoding-phase interval. The present disclosure is advantageous in solving the problem that the real optimal line delay point is ignored due to the nonlinearity between the data link skew encoding of the transmission end and the transmission line delay, and is helpful to improve the robustness of data transmission.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chips, and in particular to a data transmission skew calibration method, device and chip. BACKGROUND

[0002] UCIe (Universal Chiplet Interconnect Express) is an open and unified interconnection protocol for chips, aiming to enable chiplets manufactured by different manufacturers and different processes to realize high-speed, low-latency and high-bandwidth interconnection communication within the same package, thereby improving system performance, reducing power consumption and cost.

[0003] UCIe uses multiple parallel data lanes for high-speed transmission between chiplets. Due to differences in packaging, wiring length or process changes, the arrival times of data on different data lanes inevitably have slight differences. This difference is called skew, which can occur at the data sending end, the data receiving end, etc. In order to ensure that the receiving end can correctly sample data, these skews must be calibrated, which is called deskewing. SUMMARY

[0004] Therefore, the present disclosure provides a data transmission skew calibration method, device and chip to help solve the problem that the true optimal line delay point is ignored due to the nonlinearity between the data link skew encoding and the transmission line delay at the sending end, and to help improve the robustness of data transmission.

[0005] The technical solution of the present disclosure is implemented as follows:

[0006] According to an aspect of an embodiment of the present disclosure, a data transmission skew calibration method is provided, comprising:

[0007] The local chiplet as the data sending end performs two-dimensional scanning based on data link skew encoding and clock signal phase interpolation to send test data to the data receiving end of the remote chiplet as the data receiving end through any one data lane;

[0008] The local chiplet receives the analysis results associated with the test data returned by the remote chiplet, and obtains a skew encoding-phase interval in which the test data can be correctly received by the remote chiplet according to the analysis results;

[0009] According to the skew encoding-phase interval, the optimal data link skew encoding of the local chiplet for the any one data lane is determined.

[0010] In a possible implementation, the local chip as the data sending end performs two-dimensional scanning based on data link skew encoding and clock signal phase interpolation to send test data to the data receiving end of the remote chip as the data receiving end through any one data channel, comprising:

[0011] gradually increasing the data link skew encoding at a preset first step size from a preset minimum data link skew encoding to a maximum data link skew encoding, to obtain a plurality of different values of the data link skew encoding;

[0012] gradually increasing the clock signal phase interpolation at a preset second step size from a preset minimum clock signal phase interpolation to a maximum clock signal phase interpolation, to obtain a plurality of different values of the clock signal phase interpolation, under each of the data link skew encoding;

[0013] the local chip sends the test data to the remote chip through the any one data channel under each of the plurality of different values of the data link skew encoding and each of the plurality of different values of the clock signal phase interpolation.

[0014] In a possible implementation, the analysis result is a bit error rate;

[0015] the skew encoding-phase interval includes the data link skew encoding and the clock signal phase interpolation when the local chip sends test data that can be correctly received;

[0016] wherein the test data that can be correctly received refers to test data determined to be correctly received by the remote chip based on the bit error rate.

[0017] In a possible implementation, the analysis result is obtained by the remote chip comparing the received test data with reference data stored locally by the remote chip.

[0018] In a possible implementation, the skew encoding-phase interval in which the test data can be correctly received by the remote chip according to the analysis result comprises:

[0019] comparing the bit error rate with a preset bit error rate threshold value;

[0020] determining the interval range of the two-dimensional scanning corresponding to all test data whose bit error rate does not exceed the bit error rate threshold value as the skew encoding-phase interval.

[0021] In a possible implementation, the determining the optimal data link skew encoding of the local chip for the arbitrary data lane according to the skew encoding-phase interval comprises:

[0022] obtaining a phase value of a reference clock signal;

[0023] determining at least one data link skew encoding associated with the phase value of the reference clock signal within the skew encoding-phase interval;

[0024] obtaining the optimal data link skew encoding according to the at least one data link skew encoding associated with the phase value of the reference clock signal.

[0025] In a possible implementation, the determining the at least one data link skew encoding associated with the phase value of the reference clock signal within the skew encoding-phase interval comprises:

[0026] obtaining a range of continuous clock signal phase interpolations respectively associated with each data link skew encoding within the skew encoding-phase interval;

[0027] obtaining a clock phase median respectively associated with each data link skew encoding according to the range of continuous clock signal phase interpolations respectively associated with each data link skew encoding, wherein the clock phase median is an intermediate value between a maximum value and a minimum value of the range of continuous clock signal phase interpolations;

[0028] determining the at least one data link skew encoding associated with the optimal clock median as the at least one data link skew encoding associated with the phase value of the reference clock signal, wherein the optimal clock median is the clock phase median equal to the phase value of the reference clock signal.

[0029] In a possible implementation, the obtaining the optimal data link skew encoding according to the at least one data link skew encoding associated with the phase value of the reference clock signal comprises obtaining the optimal data link skew encoding in any one of the following first mode to fourth mode:

[0030] the first mode: determining a minimum data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0031] the second mode: determining a maximum data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0032] The third mode is to determine the middle data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0033] The fourth mode is to determine any one data link skew encoding in the at least one data link skew encoding except the minimum data link skew encoding, the maximum data link skew encoding and the middle data link skew encoding as the optimal data link skew encoding.

[0034] According to another aspect of the embodiments of the present disclosure, a data sending skew calibration device is provided, comprising:

[0035] A two-dimensional scanning module is located in a local kernel as a data sending end, and is configured to perform two-dimensional scanning based on data link skew encoding and clock signal phase interpolation;

[0036] A test data sending module is located in the local kernel and coupled to the two-dimensional scanning module, and is configured to send test data to a remote kernel as a data receiving end through any one data channel based on the two-dimensional scanning;

[0037] An analysis result receiving module is located in the local kernel, and is configured to receive analysis results associated with the test data returned by the remote kernel;

[0038] An interval determining module is located in the local kernel and coupled to the analysis result receiving module, and is configured to obtain a skew encoding-phase interval in which the test data can be correctly received by the remote kernel according to the analysis results;

[0039] An optimal skew encoding determining module is located in the local kernel and coupled to the interval determining module, and is configured to determine an optimal data link skew encoding of the local kernel for the any one data channel according to the skew encoding-phase interval.

[0040] In a possible implementation, the two-dimensional scanning module comprises:

[0041] A skew encoding scanning sub-module is configured to gradually increase the data link skew encoding from a preset minimum data link skew encoding to a maximum data link skew encoding with a set first step size, and sequentially scan each of a plurality of different values of the data link skew encoding obtained;

[0042] A phase interpolation scanning sub-module is configured to gradually increase the clock signal phase interpolation from a preset minimum clock signal phase interpolation to a maximum clock signal phase interpolation with a set second step size in each of the data link skew encodings, and sequentially scan each of a plurality of different values of the clock signal phase interpolation obtained;

[0043] The test data sending module is coupled to the skew encoding scanning submodule and the phase interpolation scanning submodule, and is configured to send the test data to the remote chip via the arbitrary data channel under the condition that each data link skew encoding scanned by the skew encoding scanning submodule and each clock signal phase interpolation scanned by the phase interpolation scanning submodule.

[0044] In a possible implementation, the analysis result is a bit error rate, and the interval determining module comprises:

[0045] a bit error rate comparing submodule configured to compare the bit error rate with a preset bit error rate threshold value;

[0046] an interval determining submodule coupled to the bit error rate comparing submodule and configured to determine the interval range of the two-dimensional scanning corresponding to all test data whose bit error rate does not exceed the bit error rate threshold value as the skew-encoding-phase interval.

[0047] In a possible implementation, the optimal skew encoding determining module comprises:

[0048] a clock phase acquiring submodule configured to acquire a phase value of a reference clock signal;

[0049] a skew encoding range determining submodule coupled to the clock phase acquiring submodule and configured to determine at least one data link skew encoding associated with the phase value of the reference clock signal within the skew-encoding-phase interval;

[0050] an optimal skew encoding determining submodule coupled to the skew encoding range determining submodule and configured to obtain the optimal data link skew encoding according to the at least one data link skew encoding associated with the phase value of the reference clock signal.

[0051] In a possible implementation, the skew encoding range determining submodule comprises:

[0052] a phase interpolation range determining unit configured to obtain a range of continuous clock signal phase interpolations respectively associated with each data link skew encoding within the skew-encoding-phase interval;

[0053] a clock phase median value determining unit coupled to the phase interpolation range determining unit and configured to obtain a clock phase median value respectively associated with each data link skew encoding according to the range of continuous clock signal phase interpolations respectively associated with each data link skew encoding, wherein the clock phase median value is an intermediate value between a maximum value and a minimum value of the range of continuous clock signal phase interpolations;

[0054] The optimal clock median value determination unit is coupled to the clock phase median value determination unit and the clock phase acquisition submodule, configured to compare the clock phase median values respectively associated with each data link skew encoding with the phase value of the reference clock signal, so as to select an optimal clock median value from the clock phase median values, wherein the optimal clock median value is equal to the phase value of the reference clock signal.

[0055] The skew encoding determination unit is coupled to the optimal clock median value determination unit, configured to determine at least one data link skew encoding associated with the optimal clock median value as the at least one data link skew encoding associated with the phase value of the reference clock signal.

[0056] In a possible implementation, the optimal skew encoding determination submodule is configured to obtain the optimal data link skew encoding by any one of the following first to fourth manners:

[0057] The first manner: determining the minimum data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0058] The second manner: determining the maximum data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0059] The third manner: determining the intermediate data link skew encoding in the at least one data link skew encoding as the optimal data link skew encoding;

[0060] The fourth manner: determining any one of the at least one data link skew encoding except the minimum data link skew encoding, the maximum data link skew encoding and the intermediate data link skew encoding as the optimal data link skew encoding.

[0061] According to another aspect of the embodiments of the present disclosure, a chip is provided, which comprises the data transmission skew calibration apparatus as any one of the above.

[0062] It can be seen from the above scheme that the data transmission skew calibration method, device and chip of the present disclosure combine data link skew encoding and clock signal phase interpolation for two-dimensional scanning, so that the skew encoding-phase interval determined to be able to correctly receive test data by the remote chip is not only related to the data link skew encoding interval and the corresponding relationship between the correct reception of test data, but also reflects the corresponding relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correct reception of test data, thereby introducing the fine tuning of the data link skew encoding based on the reference clock signal by using the clock signal phase interpolation interval. Based on this, the association between the finally determined data link skew encoding and the reference clock signal can be optimized, which is helpful to solve the problem that the real optimal line delay point is ignored due to the nonlinearity between the data link skew encoding and the transmission line delay at the sending end, and is helpful to improve the robustness of data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 is a schematic diagram of the curve relationship between data link skew encoding and line delay;

[0064] Figure 2 is a flowchart of a data transmission skew calibration method according to an illustrative embodiment;

[0065] Figure 3 is a two-dimensional scanning process schematic diagram according to an illustrative embodiment;

[0066] Figure 4 is a process schematic diagram for obtaining a skew encoding-phase interval according to an illustrative embodiment;

[0067] Figure 5 is a two-dimensional diagram schematic diagram for obtaining a skew encoding-phase interval based on two-dimensional scanning according to an illustrative embodiment;

[0068] Figure 6 is a flowchart of a specific application scenario of a two-dimensional scanning process according to an illustrative embodiment;

[0069] Figure 7 is a step schematic diagram for obtaining an optimal data link skew encoding according to an illustrative embodiment;

[0070] Figure 8 is a step schematic diagram for determining a data link skew encoding associated with a phase value of a reference clock signal according to an illustrative embodiment;

[0071] Figure 9 is a structure schematic diagram of a data transmission skew calibration device according to an illustrative embodiment;

[0072] Figure 10 is a circuit framework schematic diagram after combining the data transmission skew calibration method of the embodiments of the present disclosure to UCIe;

[0073] Figure 11 is a state schematic diagram of a first built-in state machine in a phase interpolation scanning control module according to an illustrative embodiment;

[0074] Figure 12 is a state schematic diagram of a second built-in state machine in an algorithm flow control module according to an illustrative embodiment.

[0075] In the drawings, the component names represented by each reference numeral are as follows:

[0076] 100, local core,

[0077] 110, two-dimensional scanning module,

[0078] 111, skew encoding scanning sub-module,

[0079] 112, phase interpolation scanning sub-module,

[0080] 120, test data transmission module,

[0081] 130, analysis result receiving module,

[0082] 140, interval determination module,

[0083] 141, bit error rate comparison sub-module,

[0084] 142, interval determination sub-module,

[0085] 150, optimal skew encoding determination module,

[0086] 151, clock phase acquisition sub-module,

[0087] 152, skew encoding range determination sub-module,

[0088] 1521, phase interpolation range determination unit,

[0089] 1522, clock phase median value determination unit,

[0090] 1523, optimal clock median value determination unit,

[0091] 1524 skew encoding determination unit,

[0092] 153, optimal skew encoding determination sub-module. DETAILED DESCRIPTION

[0093] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0094] It should be noted that the terms "first", "second" and the like in the description and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0095] The "coupling (or connection)" used in the description and claims of the present disclosure can refer to any direct or indirect connection means, for example, the first device is coupled (or connected) to the second device, which should be interpreted as that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means.

[0096] In the related UCIe technology, the deskewing process of the sending end is to initiate an eye scan by the sending end to scan the data link skew code of each data channel on the data link between the sending end and the receiving end, and each data channel is scanned independently. The two boundary values of the data link skew code of each data channel at which the data can be normally transmitted are found through the scanning, and the average value of the two boundary values is taken as the optimal data link skew code of the data channel. The data link skew code reflects the phase relationship between the data signal and the clock signal. In the case of keeping the clock phase unchanged, changing the data link skew code is equivalent to changing the phase of the data signal relative to the clock signal.

[0097] Figure 1 is a schematic diagram of the curve relationship between the data link skew code and the line delay, as shown in Figure 1 The data link skew code and the line delay have a great degree of nonlinearity. Because the optimal value of the data link skew code is determined by scanning the left boundary value and the right boundary value of the data link skew code at which the data can be normally transmitted in the related art, and the average value of the left boundary value and the right boundary value is taken as the optimal value of the data link skew code, as shown in Figure 1 The left boundary value corresponds to the first line delay a, and the right boundary value corresponds to the second line delay b. The first line delay a is smaller than the second line delay b. Because the data link skew code and the line delay have a great degree of nonlinearity, the line delay corresponding to the optimal value of the data link skew code is not the middle value of the first line delay a and the second line delay b corresponding to the left boundary value and the right boundary value respectively. The truly optimal line delay should be the middle value of the first line delay a and the second line delay b. Therefore, in the related art, the method of simply taking the average value of the two boundary values will cause the truly optimal line delay point to be ignored, thereby reducing the robustness of data transmission.

[0098] Therefore, the data sending skew calibration method, device and chip are provided in the embodiments of the present disclosure. On the basis of scanning data link skew encoding, clock signal phase interpolation (PI) scanning is further introduced. Based on two-dimensional scanning of the data link skew encoding and the clock signal phase interpolation, the optimal data link skew encoding referring to the clock signal phase is determined. Because the clock signal phase interpolation and the link skew present a certain linear relationship, after the clock signal phase interpolation is introduced, the purpose of fine-tuning the data link skew encoding according to the clock signal phase interpolation is achieved, and the finally determined data link skew encoding can be optimized, which is beneficial to solve the problem that the truly optimal line delay point is ignored due to the nonlinearity between the data link skew encoding of the sending end and the sending line delay, and helps to improve the robustness of data transmission.

[0099] Figure 2 is a flowchart of a data sending skew calibration method according to an illustrative embodiment. As shown in Figure 2 The data sending skew calibration method of the embodiments of the present disclosure mainly includes the following steps 201 to 203.

[0100] Step 201, performing two-dimensional scanning based on data link skew encoding and clock signal phase interpolation by a local chip as a data sending end (TX), to send test data to a data receiving end of a remote chip as a data receiving end (RX) through any data channel;

[0101] Step 202, the local chip receives the analysis result associated with the test data returned by the remote chip, and obtains a skew encoding-phase interval in which the test data can be correctly received by the remote chip according to the analysis result;

[0102] Step 203, determining the optimal data link skew encoding of the local chip for any data channel according to the skew encoding-phase interval.

[0103] In the illustrative embodiment, the scanning range of the clock signal phase interpolation covers the phase value of the reference clock signal that has been determined, that is, the phase value of the clock signal that has been aligned with the effective signal. The reference clock signal refers to the clock signal aligned with the effective signal, or in other words, the reference clock signal refers to the clock signal finally used by the local chip to send data to the remote chip.

[0104] The data transmission skew calibration method of the embodiment of the present disclosure combines data link skew encoding and clock signal phase interpolation for two-dimensional scanning, so that the determined skew encoding-phase interval in which the test data can be correctly received by the remote die reflects not only the corresponding relationship between the data link skew encoding interval and the correctly received test data, but also the corresponding relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correctly received test data, thereby introducing fine tuning of the data link skew encoding based on the reference clock signal by using the clock signal phase interpolation interval. Based on this, the association between the finally determined data link skew encoding and the reference clock signal can be optimized, which is helpful to solve the problem that the real optimal line delay point is ignored due to the nonlinearity between the data link skew encoding of the sending end and the transmission line delay, and is helpful to improve the robustness of data transmission.

[0105] The data transmission skew calibration method of the embodiment of the present disclosure is compatible with the UCIe protocol and can be executed in the LTSM_DATATRAINCENTER1 (link training state machine data training center 1) stage of the link training process of UCIe.

[0106] Based on UCIe, the data channel is in the main band, and the analysis result is transmitted through the side band.

[0107] Figure 3 is a schematic diagram of a two-dimensional scanning process according to an illustrative embodiment. As shown in Figure 3 In the illustrative embodiment, the two-dimensional scanning in the embodiment of the present disclosure, i.e., step 201, can include steps 301 to 303 as follows.

[0108] Step 301, gradually increase the data link skew encoding with a set first step size from a preset minimum data link skew encoding to a maximum data link skew encoding, to obtain a plurality of data link skew encodings with different values;

[0109] Step 302, under each data link skew encoding, gradually increase the clock signal phase interpolation with a set second step size from a preset minimum clock signal phase interpolation to a maximum clock signal phase interpolation, to obtain a plurality of clock signal phase interpolations with different values;

[0110] Step 303, the local die transmits test data to the remote die through any one data channel under the condition of each data link skew encoding in the plurality of data link skew encodings with different values and each clock signal phase interpolation in the plurality of clock signal phase interpolations with different values.

[0111] In an illustrative embodiment, the phase of the maximum clock signal is interpolated into the range between the phase values of the determined phase of the reference clock signal and the phase of the minimum clock signal.

[0112] In an illustrative embodiment, the analysis result is a bit error rate. The skew encoding-phase interval includes the data link skew encoding and the clock signal phase interpolation when the test data transmitted by the local chip can be correctly received by the remote chip. Here, the test data that can be correctly received by the remote chip refers to the test data determined to be correctly received by the remote chip based on the bit error rate.

[0113] In an illustrative embodiment, the analysis result is obtained by comparing the received test data by the remote chip with reference data stored locally by the remote chip.

[0114] In the data transmission skew calibration method of the embodiments of the present disclosure, when applied to the UCIe protocol, no modification is required for the remote chip, and the remote chip only performs bit error rate analysis on the test data transmitted by the local chip, which is already adopted in the link training process of UCIe. Based on UCIe, in an illustrative embodiment, the test data can be a LFSR (Linear Feedback Shift Register) Training Pattern (LFSR training code).

[0115] Figure 4 FIG. 2 is a schematic diagram of a process for obtaining a skew encoding-phase interval according to an illustrative embodiment. As shown in FIG. 2, in an illustrative embodiment, the process for obtaining the skew encoding-phase interval in step 202 can include the following steps 401 to 402. Figure 4

[0116] Step 401, compare the bit error rate with a preset bit error rate threshold value.

[0117] Step 402, determine the interval range of the two-dimensional scanning corresponding to all the test data whose bit error rate does not exceed the bit error rate threshold value as the skew encoding-phase interval.

[0118] In an illustrative embodiment, when applied to UCIe, the bit error rate threshold value can directly use the bit error rate threshold value specified by UCIe, for example, 10 -15 .

[0119] Figure 5 FIG. 3 is a two-dimensional diagram of obtaining a skew encoding-phase interval based on two-dimensional scanning according to an illustrative embodiment. As shown in FIG. 3, in an illustrative embodiment, the two-dimensional scanning can include the following steps 301 to 302. Figure 5 ​In the two-dimensional diagram shown, the horizontal direction represents the scanning direction of the data link skew coding, and the vertical direction represents the scanning direction of the clock signal phase interpolation. Horizontally, the data link skew coding value increases gradually from its minimum value c1 to its maximum value cN, following a preset step size. The number of data link skew codes N can be set as needed. Vertically, the clock signal phase interpolation value increases gradually from its minimum value φ1 to its maximum value φM, following a preset step size. The number of clock signal phase interpolation values ​​M can be set as needed. Figure 5 Each square in the diagram represents whether the test data corresponding to a certain data link skew code and clock signal phase interpolation was correctly received. A square marked with "P" indicates that the test data corresponding to that square was correctly received, while a square without "P" indicates that the test data corresponding to that square was not correctly received. For example, a square corresponding to data link skew code c1 and clock signal phase interpolation φ1 without "P" indicates that the test data corresponding to data link skew code c1 and clock signal phase interpolation φ1 was not correctly received. Conversely, a square corresponding to data link skew code cn1 and clock signal phase interpolation φm1 with "P" indicates that the test data corresponding to data link skew code cn1 and clock signal phase interpolation φm1 was correctly received.

[0120] See Figure 5 and combined Figure 3 As shown, in step 301, the preset minimum data link skew coding is, for example... Figure 5 c1, as shown, is the maximum data link skew coding, for example... Figure 5 The cN shown has a first step length that increases with each step from c1 to cN. This first step length can be, for example, the difference between c2 and c1, or the differences between cn2 and cn1, cn3 and cn2, cn4 and cn3, cn5 and cn4, and cn6 and cn5. Here, cn1, cn2, cn3, cn4, cn5, and cn6 are four data link skew codes that are sequentially spaced one first step length apart from c1 to cN. Based on this, step 301 can be to gradually increase the data link skew code from c1 to cN with a set first step length, obtaining multiple data link skew codes with different values ​​for c1, c2, ..., cn1, cn2, cn3, cn4, cn5, cn6, ..., cN.

[0121] See Figure 5 and combined Figure 3 As shown, in step 302, the preset minimum clock signal phase interpolation is, for example... Figure 5 As shown, φ1 represents the maximum clock signal phase interpolation, for example... Figure 5The second step length is, for example, the difference between φ2 and φ1, or the difference between φm2 and φm1, the difference between φm3 and φm2, the difference between φm4 and φm3, the difference between φm5 and φm4, where φm1, φm2, φm3, φm4, φm5 are five clock signal phase interpolations between φ1 and φM with a second step length. Based on this, step 302 can be gradually increasing the clock signal phase interpolation from φ1 to φM with a set second step length, obtaining the data link skew encoding of multiple different values of φ1, φ2, …, φm1, φm2, φm3, φm4, φm5, …, φM.

[0122] Referring to Figure 5 and in combination with Figure 3 It is shown that the condition of the local seed in step 303 in each of the multiple different values of the data link skew encoding and each of the multiple different values of the clock signal phase interpolation corresponds to Figure 5 each square in the table.

[0123] Based on Figure 5 It is shown that the bit error rate (analysis result) associated with the test data corresponding to each square, i.e. the bit error rate corresponding to each square, is compared with the bit error rate threshold value in step 401, and the skew encoding-phase interval determined in step 402 is the one containing "P" in the table shown in Figure 5 .

[0124] Figure 6 is a specific application scenario flowchart of a two-dimensional scanning process according to an illustrative embodiment, which is implemented based on the two-dimensional scanning process shown in Figure 3 , as shown in Figure 6 and referring to Figure 5 , the specific application scenario flowchart mainly includes the following steps 601 to 607.

[0125] Step 601, determine the preset minimum data link skew encoding as the current data link skew encoding, and determine the preset minimum clock signal phase interpolation as the current clock signal phase interpolation, and then perform step 602.

[0126] Step 602, under the condition of using the current data link skew encoding and the current clock signal phase interpolation, send test data to the remote seed through any data channel, and then perform step 603.

[0127] Step 603, increase the current clock signal phase difference value by a second step length to obtain an updated current clock signal phase difference value, and then perform step 604.

[0128] Step 604, judge whether the current clock signal phase difference value is greater than the preset maximum clock signal phase interpolation value, if yes, execute step 605, otherwise execute step 602.

[0129] Step 605, increase the current data link skew encoding by a first step size to obtain an updated current data link skew encoding, and then execute step 606.

[0130] Step 606, judge whether the current data link skew encoding is greater than the preset maximum data link skew encoding, if yes, end the flow, otherwise execute step 607.

[0131] Step 607, determine the preset minimum clock signal phase interpolation value as the current clock signal phase interpolation value, and then execute step 602.

[0132] Through the loop control of the specific application scenario flow of steps 601 to 607, it can be realized that under the condition of each data link skew encoding of a plurality of different values and each clock signal phase interpolation value of a plurality of different values, test data is sent to the remote chip through any data channel.

[0133] Figure 7 is a step diagram for obtaining an optimal data link skew encoding according to an illustrative embodiment, as shown in Figure 7 In the illustrative embodiment, step 203 can include steps 701 to 703 as follows.

[0134] Step 701, obtain the phase value of the reference clock signal;

[0135] Step 702, determine at least one data link skew encoding associated with the phase value of the reference clock signal in the skew encoding-phase interval;

[0136] Step 703, obtain the optimal data link skew encoding according to the at least one data link skew encoding associated with the phase value of the reference clock signal.

[0137] In the illustrative embodiment, the phase value of the reference clock signal is determined before performing deskewing. According to the UCIe protocol, during link training, the local die as the sending end sends test data to the remote die as the receiving end, and the alignment between the clock signal sent by the local die to the remote die through the clock channel and the valid signal sent by the local die to the remote die through the valid signal channel needs to be ensured, wherein the valid signal is used by the remote die to check the received test data to ensure the validity of the received test data. Therefore, only when the valid signal is aligned with the clock signal and the test data signal is aligned with the valid signal during sending of the test data, can it be ensured that the test data received by the remote die is valid, and on this basis, the bit error rate is analyzed.

[0138] Figure 8 is a schematic diagram of the step of determining the data link skew code associated with the phase value of the reference clock signal according to an illustrative embodiment, as shown in Figure 8 In the illustrative embodiment, step 702 can include steps 801 to 803 as follows.

[0139] Step 801, obtaining a range of continuous clock signal phase interpolations respectively associated with each data link skew code in the skew code-phase interval;

[0140] Step 802, obtaining a clock phase median respectively associated with each data link skew code according to the range of continuous clock signal phase interpolations respectively associated with each data link skew code, wherein the clock phase median is an intermediate value between the maximum value and the minimum value of the range of continuous clock signal phase interpolations;

[0141] Step 803, determining at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal, wherein the optimal clock median is a clock phase median equal to the phase value of the reference clock signal.

[0142] In combination with Figure 5 As shown, the phase value at the position of the dashed line, i.e. “Ф”, represents the phase value of the reference clock signal, and in the embodiment shown in Figure 5 “Ф” is equal to “φm3”.

[0143] As shown in Figure 5 and in combination with Figure 8As shown, in step 801, in the skew encoding-phase interval, the range of the continuous clock signal phase interpolation associated with cn1 is φm2 to φm5, the range of the continuous clock signal phase interpolation associated with cn2 is φm1 to φm5, the range of the continuous clock signal phase interpolation associated with cn3 is φm1 to φm5, the range of the continuous clock signal phase interpolation associated with cn4 is φm1 to φm5, the range of the continuous clock signal phase interpolation associated with cn5 is φm1 to φm5, and the range of the continuous clock signal phase interpolation associated with cn6 is φm1 to φm3. Among them, for each data link skew encoding test data is correctly received (φm1 to φm5) (with "P") discontinuous clock signal phase interpolation, which can be considered as the result of instability caused by temperature, noise and other factors, can not be considered. Figure 5

[0144] As shown in FIG. 8, in step 802, according to the range of the continuous clock signal phase interpolation associated with cn1 φm2 to φm5, the clock phase median associated with cn1 is obtained as (φm2+φm5) / 2, that is, the intermediate value of φm3 and φm4; according to the range of the continuous clock signal phase interpolation associated with cn2 φm1 to φm5, the clock phase median associated with cn2 is obtained as (φm1+φm5) / 2, that is, φm3; according to the range of the continuous clock signal phase interpolation associated with cn3 φm1 to φm5, the clock phase median associated with cn3 is obtained as (φm1+φm5) / 2, that is, φm3; according to the range of the continuous clock signal phase interpolation associated with cn4 φm1 to φm5, the clock phase median associated with cn4 is obtained as (φm1+φm5) / 2, that is, φm3; according to the range of the continuous clock signal phase interpolation associated with cn5 φm1 to φm5, the clock phase median associated with cn5 is obtained as (φm1+φm5) / 2, that is, φm3; according to the range of the continuous clock signal phase interpolation associated with cn6 φm1 to φm5, the clock phase median associated with cn6 is obtained as (φm1+φm3) / 2, that is, φm2. Figure 5 Figure 8 As shown in FIG. 8, in step 803, the phase value of the reference clock signal is Ф, and Ф is equal to φm3, so it can be determined that the data link skew encoding associated with the clock phase median φm3, that is, associated with the phase value Ф of the reference clock signal, is c2, c3, c4 and c5.

[0145] As shown in FIG. 8, in step 804, the phase value of the reference clock signal is Ф, and Ф is equal to φm2, so it can be determined that the data link skew encoding associated with the clock phase median φm2, that is, associated with the phase value Ф of the reference clock signal, is c1. Figure 5 Figure 8 As shown in FIG. 8, in step 805, the phase value of the reference clock signal is Ф, and Ф is equal to φm4, so it can be determined that the data link skew encoding associated with the clock phase median φm4, that is, associated with the phase value Ф of the reference clock signal, is c6.

[0146] ​​​After determining at least one data link skew code associated with the phase value of the reference clock signal, the optimal data link skew code can be selected from among various methods. In an illustrative embodiment, step 703 may include obtaining the optimal data link skew code using any one of the following first to fourth methods:

[0147] First method: Determine the smallest data link skew code among at least one data link skew code as the optimal data link skew code;

[0148] The second approach is to determine the largest data link skew code among at least one data link skew code as the optimal data link skew code.

[0149] The third approach: determine the intermediate data link skew code in at least one data link skew code as the optimal data link skew code;

[0150] The fourth method is to determine any one of the data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

[0151] Preferably, the optimal data link skew coding can be obtained using the first method.

[0152] like Figure 5 As shown, after determining the data link skew codes c2, c3, c4, and c5 associated with the phase value Ф of the reference clock signal, in step 703, c2 can be determined as the optimal data link skew code using the first method, c5 can be determined as the optimal data link skew code using the second method in step 703, and either c3 or c4 can be determined as the optimal data link skew code using the third or fourth method in step 703.

[0153] The data transmission skew calibration method of this disclosure combines data link skew coding and clock signal phase interpolation for two-dimensional scanning. This allows the determined skew coding-phase interval, which can be correctly received by remote cores, to reflect not only the relationship between the data link skew coding interval and the correctly received test data, but also the relationship between the clock signal phase interpolation interval before and after the phase value of the reference clock signal and the correctly received test data. This introduces a fine-tuning of the data link skew coding based on the reference clock signal using the clock signal phase interpolation interval. Based on this, the correlation between the finally determined data link skew coding and the reference clock signal can be optimized. This helps to solve the problem that the true optimal line delay point is mistakenly ignored due to the nonlinearity between the data link skew coding and the transmission line delay at the transmitting end, and helps to improve the robustness of data transmission.

[0154] The present disclosure also provides a data transmission skew calibration device, Figure 9 is a structural schematic diagram of the data transmission skew calibration device according to an exemplary embodiment, as Figure 9 shown, the data transmission skew calibration device mainly comprises a two-dimensional scanning module 110, a test data transmission module 120, an analysis result receiving module 130, an interval determination module 140, and an optimal skew encoding determination module 150. The two-dimensional scanning module 110 is located in a local kernel 100 as a data transmission end, and is used to perform two-dimensional scanning based on data link skew encoding and clock signal phase interpolation. The test data transmission module 120 is located in the local kernel 100 and is coupled to the two-dimensional scanning module 110, and is used to transmit test data to a remote kernel as a data receiving end through any data channel based on two-dimensional scanning. In an exemplary embodiment, in the case of being combined with UCIe, the data channel is located in the main band. The analysis result receiving module 130 is located in the local kernel 100, and is used to receive analysis results associated with the test data returned by the remote kernel. In an exemplary embodiment, in the case of being combined with UCIe, the analysis result receiving module 130 receives the analysis results from the sideband. The interval determination module 140 is located in the local kernel 100 and is coupled to the analysis result receiving module 130, and is used to obtain a skew encoding-phase interval in which the test data can be correctly received by the remote kernel according to the analysis results. The optimal skew encoding determination module 150 is located in the local kernel 100 and is coupled to the interval determination module 140, and is used to determine the optimal data link skew encoding of the local kernel 100 for any data channel according to the skew encoding-phase interval.

[0155] In an exemplary embodiment, as Figure 9 shown, the two-dimensional scanning module 110 comprises a skew encoding scanning sub-module 111 and a phase interpolation scanning sub-module 112. The skew encoding scanning sub-module 111 is used to gradually increase the data link skew encoding from a preset minimum data link skew encoding to a maximum data link skew encoding at a set first step, and sequentially scans each of the obtained multiple different values of the data link skew encoding. The phase interpolation scanning sub-module 112 is used to gradually increase the clock signal phase interpolation from a preset minimum clock signal phase interpolation to a maximum clock signal phase interpolation at a set second step under each data link skew encoding, and sequentially scans each of the obtained multiple different values of the clock signal phase interpolation. The test data transmission module 120 is coupled to the skew encoding scanning sub-module 111 and the phase interpolation scanning sub-module 112, and is used to transmit test data to the remote kernel through any data channel under the condition of each data link skew encoding scanned by the skew encoding scanning sub-module 111 and each clock signal phase interpolation scanned by the phase interpolation scanning sub-module 112, respectively.

[0156] In an illustrative embodiment, the analysis result is a bit error rate. As shown in Figure 9 The interval determining module 140 includes a bit error rate comparing sub-module 141 and an interval determining sub-module 142. The bit error rate comparing sub-module 141 is coupled to the analysis result receiving module 130 and configured to compare the bit error rate with a preset bit error rate threshold. The interval determining sub-module 142 is coupled to the bit error rate comparing sub-module 141 and configured to determine the interval range of the two-dimensional scan corresponding to all the test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

[0157] In an illustrative embodiment, as shown in Figure 9 The optimal skew coding determining module 150 includes a clock phase obtaining sub-module 151, a skew coding range determining sub-module 152, and an optimal skew coding determining sub-module 153. The clock phase obtaining sub-module 151 is configured to obtain the phase value of the reference clock signal. The skew coding range determining sub-module 152 is coupled to the clock phase obtaining sub-module 151 and the interval determining module 140 and configured to determine at least one data link skew coding associated with the phase value of the reference clock signal within the skew coding-phase interval. The optimal skew coding determining sub-module 153 is coupled to the skew coding range determining sub-module 152 and configured to obtain the optimal data link skew coding according to the at least one data link skew coding associated with the phase value of the reference clock signal.

[0158] In an illustrative embodiment, as shown in Figure 9As shown, the skew coding range determining sub-module 152 comprises a phase interpolation range determining unit 1521, a clock phase median value determining unit 1522, an optimal clock median value determining unit 1523, and a skew coding determining unit 1524. The phase interpolation range determining unit 1521 is coupled to the interval determining module 140, and is configured to obtain a range of continuous clock signal phase interpolations respectively associated with each data link skew coding within the skew coding-phase interval. The clock phase median value determining unit 1522 is coupled to the phase interpolation range determining unit 1521, and is configured to obtain clock phase median values respectively associated with each data link skew coding according to the range of continuous clock signal phase interpolations respectively associated with each data link skew coding, wherein the clock phase median value is an intermediate value between the maximum value and the minimum value of the range of continuous clock signal phase interpolations. The optimal clock median value determining unit 1523 is coupled to the clock phase median value determining unit 1522 and the clock phase obtaining sub-module 151, and is configured to compare the clock phase median values respectively associated with each data link skew coding with the phase value of the reference clock signal, so as to select an optimal clock median value from the clock phase median values, wherein the optimal clock median value is equal to the phase value of the reference clock signal. The skew coding determining unit 1524 is coupled to the optimal clock median value determining unit 1523 and the optimal skew coding determining sub-module 153, and is configured to determine at least one data link skew coding associated with the optimal clock median value as at least one data link skew coding associated with the phase value of the reference clock signal.

[0159] In an illustrative embodiment, the optimal skew coding determining unit 1524 is configured to obtain the optimal data link skew coding by any one of the following first to fourth manners: the first manner is to determine the minimum data link skew coding among the at least one data link skew coding as the optimal data link skew coding; the second manner is to determine the maximum data link skew coding among the at least one data link skew coding as the optimal data link skew coding; the third manner is to determine the intermediate data link skew coding among the at least one data link skew coding as the optimal data link skew coding; and the fourth manner is to determine any one of the at least one data link skew coding other than the minimum data link skew coding, the maximum data link skew coding, and the intermediate data link skew coding as the optimal data link skew coding.

[0160] As to the data transmission skew calibration apparatus in the above-mentioned embodiments, the specific manners in which the respective modules and units perform operations have been described in detail in the embodiments of the data transmission skew calibration method, and thus will not be described in detail here.

[0161] It should be noted that the above examples are only used to illustrate the division of the above functional modules and units, and in actual applications, the above functions can be completed by different functional modules and units according to needs, that is, the internal structure of the device is divided into different functional modules and units to complete all or part of the above described functions.

[0162] In the illustrative embodiments, according to different designs, the implementation of at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew encoding determination module 150 can be a combination of multiple of hardware, firmware, and software (i.e., programs).

[0163] In terms of hardware, at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew encoding determination module 150 can be implemented on a logic circuit on an integrated circuit, for example, the related functions of at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew encoding determination module 150 can be implemented in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. Various logic blocks, modules, and circuits in the at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determination module 140, and the optimal skew encoding determination module 150 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0164] In software or firmware form, the functions of at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determining module 140, and the optimal skew encoding determining module 150 can be implemented as programming codes. For example, at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determining module 140, and the optimal skew encoding determining module 150 is implemented by using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded, stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage device. An electronic device (such as a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the two-dimensional scanning module 110, the test data sending module 120, the analysis result receiving module 130, the interval determining module 140, and the optimal skew encoding determining module 150.

[0165] In an illustrative embodiment, the present disclosure also provides a chip comprising the data sending skew calibration apparatus according to any one of the preceding embodiments.

[0166] In an illustrative embodiment, the data sending skew calibration method and the data sending skew calibration apparatus of the present disclosure are applicable to SoC chips and the like, where the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0167] The data transmission skew calibration method of the embodiments of the present disclosure can be combined in UCIe, Figure 10 is a schematic diagram of a circuit framework after the data transmission skew calibration method of the embodiments of the present disclosure is combined in UCIe, the circuit framework is respectively provided with a scanning control module for each of 64 data channels, for example Figure 10 The scanning control module of each data channel includes a phase interpolation scanning control module, a link skew value scanning control module, and a scanning result processing module.

[0168] The phase interpolation scanning control module initiates multiple rounds of clock signal phase interpolation scanning of the data channel according to the input scanning boundary value, and calculates the optimal clock signal phase interpolation (i.e., the clock phase median in the above embodiment) of the data channel under the current data link skew encoding according to the analysis result returned by the remote chip.

[0169] The phase interpolation scanning control module includes a first built-in state machine, Figure 11 is a state diagram of the first built-in state machine in the phase interpolation scanning control module according to an illustrative embodiment, as shown in Figure 11 The first built-in state machine includes six states, namely an idle state, a result valid state, a scanning state, an adjustment completion state, an end state, and an error state. In the idle state, the internal related functional circuit units are in a closed state, reducing the power consumption of the circuit. In the result valid state, the scanning has been started, the internal related functional circuit units are turned on, and the relevant information is waiting to be received. In the scanning state, the internal related functional circuit processes the result of the clock signal phase interpolation of the previous scanning, and judges the clock signal phase interpolation of the next scanning. In the adjustment completion state, the next clock signal phase interpolation has been triggered, and needs to wait for the clock signal phase interpolation to be stable for a period of time at the digital-analog interface of the data channel from the local chip to the remote chip before switching to the next state. In the end state, it indicates that the clock signal phase interpolation has been completed, and the relevant calculation result has been obtained. If no phase interpolation can be found to allow the data channel to normally transmit and receive data during the entire clock signal phase interpolation process, the error state is entered, that is, in the error state, no phase interpolation can be found to allow the data channel to normally transmit and receive data during the entire clock signal phase interpolation process.

[0170] The link skew value scanning control module is used to send the data link skew encoding to the digital-analog interface, wherein the data link skew encoding is controlled by the algorithm flow control module.

[0171] The scanning result processing module is configured to determine the optimal data link skew coding according to the analysis result obtained by the two-dimensional scanning, so that the data signal transmitted by the data channel can have the largest skew margin, thereby improving the reliability of the data channel. The data processing manner can be referred to Figure 5 The above-mentioned related embodiments are described.

[0172] The algorithm flow control module is configured to control the two-dimensional scanning process of the entire algorithm of each data channel and generate an algorithm completion flag. The algorithm flow control module is provided with a second built-in state machine. Figure 12 The second built-in state machine in the algorithm flow control module is shown in the state diagram of the second built-in state machine in the algorithm flow control module according to an illustrative embodiment. Figure 12 The first built-in state machine includes five states, namely, an idle state, a two-dimensional scanning start state, a two-dimensional scanning end state, a phase interpolation write-back state, and an end state.

[0173] The idle state is a state in which the two-dimensional scanning is not started. In the idle state, the internal related functional circuit unit is in a closed state, thereby reducing the power consumption of the circuit.

[0174] In the two-dimensional scanning start state, the internal related functional circuit unit is started and the two-dimensional scanning is started after receiving the start signal of the control module for controlling the link training from the upper layer.

[0175] In the two-dimensional scanning end state, the internal related functional circuit unit completes the two-dimensional scanning process, and the clock signal phase interpolation and the data link skew coding both reach the maximum boundary value.

[0176] In the phase interpolation write-back state, the clock signal phase interpolation of the digital-analog interface is changed multiple times during the two-dimensional scanning process. Therefore, after the calculation is completed, the phase interpolation of the reference clock signal (i.e., the phase value of the reference clock signal) needs to be fed back to the digital-analog interface. In the present disclosure, adjusting the clock signal phase interpolation is only a means to obtain the optimal data link skew coding, but not to change the phase of the clock signal.

[0177] In the end state, the two-dimensional scanning has completed all related functions, and the optimal data link skew coding has been obtained.

[0178] The data sending skew calibration method, device and chip provided by the embodiments of the present disclosure can effectively decouple the nonlinear coupling relationship between data link skew encoding and data link delay through two-dimensional parameter joint optimization. Experiments show that the data sending skew calibration method provided by the embodiments of the present disclosure improves the accuracy of calibration compared with the related single-dimensional scanning method of UCIe. The data sending skew calibration method provided by the embodiments of the present disclosure can be widely applied to related high-speed serial communication, clock data recovery (CDR) and the like, and can help to improve the stability of system timing and the integrity of signals.

[0179] The above merely describes preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data transmission skew calibration method, comprising: The local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, which acts as the data receiver, through any data channel. The local chip receives the analysis results related to the test data returned by the remote chip, and obtains the skew coding-phase interval that can be correctly received by the remote chip based on the analysis results; Based on the skew coding-phase interval, the optimal data link skew coding for any one data channel is determined for the local chip.

2. The data transmission skew calibration method according to claim 1, characterized in that, The local chip, acting as the data transmitter, performs a two-dimensional scan based on data link skew coding and clock signal phase interpolation to send test data to the data receiver of the remote chip, acting as the data receiver, through any data channel, including: From the preset minimum data link skew code to the maximum data link skew code, the data link skew code is gradually increased with a set first step length to obtain multiple different values ​​of the data link skew code. In each of the data link skew coding cases, the clock signal phase interpolation is gradually increased from the preset minimum clock signal phase interpolation to the maximum clock signal phase interpolation with a set second step size to obtain multiple clock signal phase interpolation values ​​with different values. The local chip transmits the test data to the remote chip through any one of the data channels, under the conditions of each of the multiple different values ​​of the data link skew coding and each of the multiple different values ​​of the clock signal phase interpolation.

3. The data transmission skew calibration method according to claim 1, characterized in that: The analysis result is the bit error rate; The skew coding-phase interval includes the data link skew coding and the clock signal phase interpolation when the local chip transmits test data that can be correctly received; Among them, the test data that can be correctly received refers to the test data that is determined to be correctly received by the remote chip based on the bit error rate.

4. The data transmission skew calibration method according to claim 3, characterized in that: The analysis results are obtained by comparing the test data received by the remote core with the reference data stored locally by the remote core.

5. The data transmission skew calibration method according to claim 3, characterized in that, The step of obtaining the skew coding-phase interval that allows the remote chip to correctly receive the test data based on the analysis results includes: The bit error rate is compared with a preset bit error rate threshold. The range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold is defined as the skew coding-phase interval.

6. The data transmission skew calibration method according to claim 1, characterized in that, The step of determining the optimal data link skew coding for any data channel by the local chip based on the skew coding-phase interval includes: Obtain the phase value of the reference clock signal; Within the skew coding-phase interval, at least one data link skew code associated with the phase value of the reference clock signal is determined; The optimal data link skew code is obtained based on at least one data link skew code determined by the phase value associated with the reference clock signal.

7. The data transmission skew calibration method according to claim 6, characterized in that, The step of determining at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval includes: Within the skew coding-phase interval, the range of continuous clock signal phase interpolation associated with each data link skew code is obtained; Based on the range of consecutive clock signal phase interpolations associated with each data link skew code, the median clock phase associated with each data link skew code is obtained, wherein the median clock phase is the midpoint between the maximum and minimum values ​​of the range of consecutive clock signal phase interpolations. At least one data link skew code associated with the optimal clock median is determined as at least one data link skew code associated with the phase value of the reference clock signal, wherein the optimal clock median is the clock phase median that is equal to the phase value of the reference clock signal.

8. The data transmission skew calibration method according to claim 6, characterized in that, The step of obtaining the optimal data link skew code based on at least one data link skew code determined in relation to the phase value of the reference clock signal includes obtaining the optimal data link skew code using any one of the following first to fourth methods: First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code; The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code. Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code; Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

9. A data transmission skew calibration device, characterized in that, include: The two-dimensional scanning module, located in the local chip that serves as the data transmitter, is used to perform two-dimensional scanning based on data link skew coding and clock signal phase interpolation. The test data transmission module, located in the local chip and coupled to the two-dimensional scanning module, is used to transmit test data to the remote chip, which is the data receiving end, through any data channel based on the two-dimensional scanning. An analysis result receiving module, located in the local chip, is used to receive analysis results related to the test data returned by the remote chip; An interval determination module, located in the local chip and coupled to the analysis result receiving module, is used to obtain the skew coding-phase interval that can be correctly received by the remote chip based on the analysis result; An optimal skew coding determination module, located in the local core and coupled to the interval determination module, is used to determine the optimal data link skew coding of the local core for any one data channel based on the skew coding-phase interval.

10. The data transmission skew calibration device according to claim 9, characterized in that, The two-dimensional scanning module includes: The skew coding scanning submodule is used to gradually increase the data link skew coding from the preset minimum data link skew coding to the maximum data link skew coding with a set first step length, and scan the data link skew coding with multiple different values ​​obtained sequentially. The phase interpolation scanning submodule is used to scan the clock signal phase interpolation values ​​of multiple different values ​​one by one in each case of data link skew coding, from the preset minimum clock signal phase interpolation value to the maximum clock signal phase interpolation value, with a set second step size. The test data transmission module is coupled to the skew coding scanning submodule and the phase interpolation scanning submodule, and is used to transmit the test data to the remote chip through any one of the data channels, under the conditions of each data link skew coding scanned by the skew coding scanning submodule and each clock signal phase interpolation scanned by the phase interpolation scanning submodule.

11. The data transmission skew calibration device according to claim 9, characterized in that: The analysis result is the bit error rate, and the interval determination module includes: The bit error rate comparison submodule is used to compare the bit error rate with a preset bit error rate threshold value; The interval determination submodule, coupled to the bit error rate comparison submodule, is used to determine the interval range of the two-dimensional scan corresponding to all test data whose bit error rate does not exceed the bit error rate threshold as the skew coding-phase interval.

12. The data transmission skew calibration device according to claim 9, characterized in that, The optimal skew coding determination module includes: The clock phase acquisition submodule is used to acquire the phase value of the reference clock signal; The skew coding range determination submodule, coupled to the clock phase acquisition submodule, is used to determine at least one data link skew code associated with the phase value of the reference clock signal within the skew coding-phase interval. An optimal skew code determination submodule, coupled to the skew code range determination submodule, is used to obtain the optimal data link skew code based on at least one data link skew code determined by the phase value associated with the reference clock signal.

13. The data transmission skew calibration device according to claim 12, characterized in that, The skew coding range determination submodule includes: The phase interpolation range determination unit is used to obtain the range of continuous clock signal phase interpolation associated with each data link skew code within the skew code-phase interval. A clock phase median determination unit, coupled to the phase interpolation range determination unit, is used to obtain the clock phase median associated with each data link skew code based on the range of continuous clock signal phase interpolation associated with each data link skew code, wherein the clock phase median is the intermediate value between the maximum and minimum values ​​of the range of continuous clock signal phase interpolation. An optimal clock median determination unit, coupled to the clock phase median determination unit and the clock phase acquisition submodule, is used to compare the clock phase median associated with each data link skew code with the phase value of the reference clock signal to select the optimal clock median from the clock phase medians, wherein the optimal clock median is equal to the phase value of the reference clock signal; A skew coding determination unit, coupled to the optimal clock median determination unit, is used to determine at least one data link skew code associated with the optimal clock median as at least one data link skew code associated with the phase value of the reference clock signal.

14. The data transmission skew calibration device according to claim 12, characterized in that, The optimal skew coding determination submodule is used to obtain the optimal data link skew coding through any one of the following first to fourth methods: First method: Determine the minimum data link skew code among the at least one data link skew codes as the optimal data link skew code; The second method is to determine the largest data link skew code among the at least one data link skew codes as the optimal data link skew code. Third method: Determine the intermediate data link skew code in the at least one data link skew code as the optimal data link skew code; Fourth method: Determine any one of the at least one data link skew codes, excluding the minimum data link skew code, the maximum data link skew code, and the intermediate data link skew code, as the optimal data link skew code.

15. A chip, characterized in that, Includes the data transmission skew calibration device as described in any one of claims 9 to 14.

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