Access request processing device, access request processing method, processor and equipment

Abstract

The invention discloses an access request processing device, an access request processing method, a processor and equipment, and belongs to the technical field of storage. The access request processing device comprises a merging unit and a sending unit, the merging unit is used for merging the at least one group of first access requests meeting the merging condition to obtain at least one second access request, any group of first access requests meeting the merging condition carries discrete access addresses, and storage spaces corresponding to the discrete access addresses are located in the same candidate storage space; the candidate storage space is a storage space supporting access through a request in the memory; and the sending unit is used for sending at least one second access request to the memory. Based on the device, the method, the processor and the equipment, the sending times of the access request can be reduced, and the utilization rate of the bus on which the access request is sent is improved. The access request processing device is suitable for an artificial intelligence processor.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an access request processing apparatus, access request processing method, processor, and device. Background Technology

[0002] In the field of storage technology, a processor can generate an access request carrying an access address. This access request is used to access the storage space in memory corresponding to the access address, so as to read or write data in the storage space corresponding to the access address.

[0003] In some cases, a processor can generate multiple access requests carrying discrete access addresses, and the processor includes an access request processing device for processing these multiple access requests. In related technologies, the access request processing device includes a sending unit for sequentially sending multiple access requests to the memory in a predetermined order.

[0004] In related technologies, if the memory space corresponding to the access address carried by multiple access requests is accessed, all access requests need to be sent to the memory in sequence, resulting in a large number of access requests being sent. This leads to a small average amount of memory space accessed by each access request and low utilization of the bus on which the access requests depend. Summary of the Invention

[0005] This application provides an access request processing apparatus, an access request processing method, a processor, and a device, which can be used to reduce the number of access request transmissions, thereby improving the utilization rate of the bus on which access requests depend. The technical solutions provided by this application include the following aspects.

[0006] On the one hand, embodiments of this application provide an access request processing apparatus, which includes a merging unit and a sending unit;

[0007] The merging unit is used to merge at least one set of first access requests that meet the merging conditions to obtain at least one second access request. Any set of first access requests that meet the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is a storage space in the memory that supports access through a single request.

[0008] The sending unit is used to send the at least one second access request to the memory.

[0009] On the other hand, embodiments of this application provide an access request processing method, which is applied to an access request processing apparatus, the access request processing apparatus including a merging unit and a sending unit; the method includes:

[0010] The merging unit merges at least one set of first access requests that meet the merging conditions to obtain at least one second access request. Each set of first access requests that meets the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is a storage space in the memory that supports access through a single request.

[0011] The at least one second access request is sent to the memory via the sending unit.

[0012] On the other hand, embodiments of this application provide a processor, which includes the access request processing apparatus provided in embodiments of this application.

[0013] On the other hand, embodiments of this application provide a computer device, which includes a processor and a memory, wherein the processor is the processor provided in embodiments of this application.

[0014] The technical solution provided in this application has at least the following beneficial effects:

[0015] The technical solution provided in this application embodiment includes an access request processing device including a merging unit. Based on this structure, the access request processing device can merge at least one set of first access requests that meet the merging conditions, and then send the merged second access request to the memory.

[0016] Since the second access request is obtained by merging at least one set of first access requests that meet the merging conditions, the number of second access requests is small. Sending the second access request to the memory can reduce the number of access request transmissions, increase the average storage space accessed by each transmitted access request, and thus improve the utilization of the bus on which the transmission of access requests depends. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a memory access system for an artificial intelligence processor provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the structure of an access request processing device provided in an embodiment of this application;

[0020] Figure 3This is a schematic diagram illustrating the correspondence between the representation information of the access address carried in the first access request and the access address carried in the first access request, as provided in an embodiment of this application.

[0021] Figure 4 This is a schematic diagram illustrating a process of merging two first access requests provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of another access request processing device provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of another access request processing device provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of another access request processing device provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram illustrating the update process of a priority indicator provided in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram illustrating a process for determining the fourth access request with the highest priority index using a pairwise comparison strategy, as provided in an embodiment of this application.

[0027] Figure 10 This is a schematic diagram illustrating a process of accessing memory based on an access request processing device, as provided in an embodiment of this application.

[0028] Figure 11 This is a flowchart of an access request processing method provided in an embodiment of this application;

[0029] Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application;

[0030] Figure 13 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application;

[0031] Figure 14 This is a schematic diagram of the structure of a server provided in an embodiment of this application.

[0032] Figure label:

[0033] 1-Merging unit; 2-Transmitting unit; 3-Comparison unit; 11-Merging sub-unit; 21-Allocation sub-unit; 22-Selection sub-unit; 23-Transmitting sub-unit. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] The access request processing apparatus provided in this application embodiment is a type of processor used for processing access requests. Processors include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), and TPUs (Tensor Processing Units). In some embodiments, the processor can be a processor used for processing AI (Artificial Intelligence) tasks; such a processor can be called an AI processor. Artificial intelligence will be described below.

[0036] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0037] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, pre-trained model technology, operating / interactive systems, and mechatronics. Among these, pre-trained models, also known as large models or foundational models, can be widely applied to downstream tasks across various AI fields after fine-tuning. AI software technologies primarily include computer vision, speech recognition, natural language processing, and machine learning / deep learning.

[0038] Computer vision (CV) is a science that studies how to enable machines to "see." More specifically, it refers to machine vision, which uses cameras and computers to replace human eyes in recognizing and measuring targets, and then performs image processing to create images more suitable for human observation or transmission to instruments for detection. As a scientific discipline, computer vision researches related theories and technologies, attempting to build artificial intelligence systems capable of extracting information from images or multidimensional data.

[0039] Large-scale modeling has brought about significant changes to the development of computer vision technology. Pre-trained models in the vision field, such as shifted-window transformers (swin-transformers), vision transformers (ViT), vision mixture of experts (V-MOE) models, and masked autoencoders (MAE), can be fine-tuned and quickly and widely applied to specific downstream tasks. Computer vision technology typically includes image processing, image recognition, image semantic understanding, image retrieval, optical character recognition (OCR), video processing, video semantic understanding, video content / behavior recognition, 3D object reconstruction, 3D technology, virtual reality, augmented reality, simultaneous localization and mapping (SLAM), and common biometric recognition technologies such as facial recognition and fingerprint recognition.

[0040] Key technologies in speech technology include Automatic Speech Recognition (ASR), Text-to-Speech (TTS), and Voiceprint Recognition. Enabling computers to hear, see, speak, and feel is the future direction of human-computer interaction, with speech emerging as one of the most promising methods. Large-scale modeling has revolutionized speech technology. Pre-trained models using the Transformer architecture, such as WavLM (a model name) and Unified Speech (UniSpeech), possess strong generalization and versatility, enabling them to excel in various speech processing tasks.

[0041] Natural Language Processing (NLP) is an important field within computer science and artificial intelligence. It studies the theories and methods for enabling effective communication between humans and computers using natural language. NLP deals with natural language, the language people use in daily life, and is closely related to linguistics, involving computer science and mathematics. Pre-trained models, a crucial technique for model training in artificial intelligence, evolved from Large Language Models (LLMs) in NLP. After fine-tuning, LLMs can be widely applied to downstream tasks. NLP techniques typically include text processing, semantic understanding, machine translation, question answering, and knowledge graphs.

[0042] Machine learning (ML) is a multidisciplinary field involving probability theory, statistics, approximation theory, convex analysis, and algorithm complexity theory. It specifically studies how computers can simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to endow computers with intelligence; its applications span all areas of artificial intelligence. Machine learning and deep learning typically include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and instruction-based learning. Pre-trained models are the latest development in deep learning, integrating all of these techniques.

[0043] Autonomous driving technology refers to vehicles driving themselves without driver intervention. It typically includes technologies such as high-precision mapping, environmental perception, computer vision, behavioral decision-making, path planning, and motion control. Autonomous driving encompasses various development paths, including single-vehicle intelligence, vehicle-to-infrastructure (V2I) communication, and networked cloud control. Autonomous driving technology has broad application prospects, currently focusing on logistics, public transportation, taxis, and intelligent transportation systems, and is expected to see further development in the future.

[0044] With the research and advancement of artificial intelligence (AI) technology, AI is being studied and applied in various fields, such as smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, autonomous driving, drones, digital twins, virtual humans, robots, AI-generated content (AIGC), conversational interaction, smart healthcare, smart customer service, and game AI. It is believed that with the development of technology, AI will be applied in more fields and play an increasingly important role.

[0045] This application uses an AI processor as an example for illustration.

[0046] AI processors need to process large amounts of data, involving numerous memory access operations. The data to be processed is generally stored in external memory of the AI ​​processor. The access request processing device built into the AI ​​processor is responsible for processing access requests to complete the transfer of external data to the AI ​​processor and the transfer of data from the AI ​​processor to external memory.

[0047] As AI processors become increasingly complex, memory access operations (also known as memory access requests) also become more complex. Memory access operations can be sequential, meaning they access a contiguous block of addresses. Such access requests are relatively easy to translate into final memory access requests. Memory access operations can also be discrete, meaning they access non-contiguous addresses. Optimizing memory access performance in these scenarios is a key technology in AI processor design. The access request processing apparatus provided in this application can be used to improve the performance of memory access requests based on discrete access operations.

[0048] For example, the external memory of the AI ​​processor can be any type of memory capable of storing data. For instance, the external memory of the AI ​​processor can refer to DDR (Double Data Rate SDRAM). The access request processing device built into the AI ​​processor can be any device capable of processing access requests to access memory using those requests. For instance, the access request processing device built into the AI ​​processor can refer to DMA (Direct Memory Access).

[0049] For example, the memory access system (also known as the AI ​​processor memory access system) in which the AI ​​processor resides can be as follows: Figure 1 As shown, the memory access system of the AI ​​processor includes the AI ​​processor and memory. The AI ​​processor includes a vector scalar unit in the vector processing engine, a matrix scalar unit in the matrix operation engine, and an access request processing device. The vector scalar unit sends external memory read / write commands (i.e., access requests) required by the vector processing engine to the access request processing device, and the matrix operation engine also sends external memory read / write commands (i.e., access requests) to the access request processing device. Upon receiving an access request, the access request processing device processes it to send an access request to the memory, thereby initiating a read / write access operation to the memory. The vector processing engine handles the vectors involved in the AI ​​task; the matrix operation engine handles the vectors involved in the AI ​​task.

[0050] For example, sending an access request to the memory by the access request processing device can refer to the access request processing device sending an access request to the memory based on a protocol. The protocol here can be selected based on experience or flexibly adjusted according to the application scenario. Under different protocols, the form of the access request sent by the access request processing device to the memory may be different.

[0051] In some embodiments, the access request processing device sends an access request to the memory based on the AXI (Advanced eXtensible Interface) protocol. The AXI protocol is a bus protocol used for communication between high-performance processors and external devices (such as memory). In the AXI protocol, the burst transfer mechanism is a special data transfer method that can transfer multiple data items in a single transfer transaction, thereby reducing transfer management overhead and increasing data transfer speed.

[0052] When the access request processing device sends an access request to the memory based on the AXI protocol, the access request sent by the access request processing device to the memory is called a burst request. The burst request includes the following two important parameters:

[0053] (1) Burst Length: Burst length refers to the number of data transmission operations to be performed in a single transmission transaction. Burst length defines how many cycles the data transmission will continue after the burst begins. For example, if the burst length is 4, then 4 data transmissions will be performed consecutively in the same burst transaction. Burst length directly affects the total amount of data and the duration of the transmission transaction.

[0054] (2) Burst Size: Burst size refers to the size of the data (usually in bytes) in each individual data transfer operation. The burst size determines how many bytes of data each transfer operation will process. For example, if the burst size is 8 bytes, then each data transfer operation will transfer 8 bytes of data. The burst size affects the amount of data in a single transfer operation.

[0055] In short, burst length focuses on the total number of transmission operations in a transmission transaction, while burst size focuses on the amount of data in each transmission operation. Using them together, a transmission transaction can be described in detail. For example, a transmission transaction can be defined as a burst transaction with a length of 4 and a size of 8 bytes, meaning that four consecutive transmission operations, each transmitting 8 bytes of data, will be performed. By properly configuring these two parameters, data transmission performance can be optimized to meet different system requirements.

[0056] It should be noted that the above description only uses an AI processor as an example, but the embodiments of this application are not limited thereto. In some embodiments, the processor may also be a processor suitable for scenarios other than AI scenarios.

[0057] This application provides an access request processing apparatus, such as... Figure 2As shown, the access request processing apparatus includes a merging unit 1 and a sending unit 2. Exemplarily, both the merging unit 1 and the sending unit 2 are hardware modules; for example, both are circuits. The merging unit 1 and the sending unit 2 are described below.

[0058] Merging unit 1 is used to merge at least one set of first access requests that meet the merging conditions to obtain at least one second access request. Each set of first access requests that meets the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is a storage space in the memory that supports access through a single request.

[0059] The processor includes an access source capable of generating a first access request for reading data from or writing data to memory. An access source refers to a device with memory access needs (e.g., needing to read data from or write data to memory). For example, taking an AI processor as an example, the access source may include, but is not limited to, an AI processor. Figure 1 The control unit in the vector processing engine and the control unit in the matrix operation engine are shown in the figure.

[0060] Among the first access requests generated by the access source, there are at least one set of first access requests that meet the merging conditions. The merging unit 1 can merge the at least one set of first access requests that meet the merging conditions to reduce the number of access requests. For example, the number of first access requests generated by the access source is at least two, and the merging unit is used to merge at least one set of first access requests that meet the merging conditions from the at least two first access requests. The at least two first access requests are access requests generated by the access source at the same time or within the same time period. The at least two first access requests can be generated by one access source or by multiple access sources, and this embodiment of the application does not limit this.

[0061] For example, an access source can generate an access request vector at the same time, which may include multiple sub-requests, each of which can serve as a first access request.

[0062] Each of the at least two first access requests carries an access address, and the access address carried by each first access request corresponds to a portion of the storage space in the memory. This portion of the storage space is the storage space in the memory that the first access request needs to access.

[0063] For example, the storage space in the memory is composed of storage cells, which are consecutively numbered. The access address carried by the first access request can be represented using the numbers of the storage cells in the memory. For instance, the storage cells in the memory can be consecutively numbered 0, 1, 2, 3, ..., n. Then, the access address carried by the first access request can be represented using a consecutive number from 0, 1, 2, 3, ..., n. If the access address carried by the first access request is represented using consecutive numbers 0-3, it means that the storage space corresponding to the access address carried by the first access request is the storage space composed of storage cells numbered 0, 1, 2, and 3 in the memory.

[0064] For example, if the storage space corresponding to the access address carried by the first access request includes a certain storage unit in the memory, it means that the first access request needs to access that storage unit (e.g., write data to the storage unit, or read data from the storage unit). For instance, if the access address carried by the first access request includes address 1, it means that the first access request needs to access the storage unit numbered 1. The amount of data used to store in each storage unit can be determined by the type of storage unit. This application embodiment does not limit this. For example, the amount of data used to store in each storage unit can be one byte.

[0065] In this embodiment, the access addresses carried by at least two first access requests are discrete, meaning that the access addresses carried by any two of the at least two first access requests are not consecutive. That is, there is an address gap between the access addresses carried by different first access requests. For example, assuming that each first access request carries an address represented by consecutive numbers, assuming one first access request carries an address represented by numbers 0-10 (which can be called the address from address 0 to address 10), and another first access request carries an address represented by numbers 15-16 (which can be called the address from address 15 to address 16), then the access addresses carried by these two first access requests are discrete.

[0066] This application does not limit the representation of the access address carried in the first access request, as long as it can uniquely identify a portion of the storage space in the memory. For example, the type of the first access request can be a burst request. In this case, the access address carried in the first access request can be represented based on the starting address, burst size, and burst length.

[0067] For example, the correspondence between the access address representation information carried in the first access request and the access address carried in the first access request is as follows: Figure 3 As shown. See also Figure 3 In (1), if the access address carried by the first access request is represented by "address=0, burst_size=4byte, burst_length=4", it means that the storage space that the first access request needs to access is four consecutive storage spaces for storing 4 bytes of data, starting from storage unit number 0. Each storage unit is used to store 1 byte of data. Therefore, the storage space that the first access request needs to access is the storage space for storing 16 bytes of data, consisting of storage units numbered from storage unit number 0 to storage unit number 15.

[0068] See Figure 3 In (2), if the access address carried by the first access request is represented by "address=0, burst_size=4byte, burst_length=1", it means that the storage space that the first access request needs to access is a storage space for storing 4 bytes of data starting from the storage unit numbered 0. That is, the first access request needs to access the storage space for storing 4 bytes of data consisting of the storage unit numbered 0 to the storage unit numbered 3. The storage space for storing 4 bytes of data consisting of the storage unit numbered 0 to the storage unit numbered 3 can be called the storage space corresponding to burst_size.

[0069] It should be noted that, Figure 3 The example described uses the access address carried in the first access request as a continuous number, with each number corresponding to a storage unit in the memory for storing one byte of data. However, the embodiments of this application are not limited to this.

[0070] In this embodiment of the application, at least two first access requests include at least one set of first access requests that meet the merging conditions. After obtaining at least two first access requests with discrete access addresses, the merging unit 1 merges the at least one set of first access requests that meet the merging conditions from the at least two first access requests to obtain at least one second access request. It should be noted that each set of first access requests that meets the merging conditions includes two or more first access requests.

[0071] In an exemplary embodiment, the groups of first access requests that satisfy the merging condition among at least two first access requests may encompass all the first access requests. In this case, at least one second access request includes only the access request obtained by merging the groups of first access requests. The number of second access requests is the same as the number of groups of first access requests that satisfy the merging condition.

[0072] In an exemplary embodiment, each group of first access requests that meets the merging condition may cover a portion of the first access requests. In this case, at least one second access request includes not only the access request obtained after merging the groups of first access requests, but also the first access requests that do not meet the merging condition and are not covered by the groups of first access requests.

[0073] It should be noted that, regardless of the type of the at least one second access request, since the at least one second access request includes access requests obtained by merging the groups of first access requests, the number of second access requests is less than the number of first access requests. Furthermore, the average storage space corresponding to the access addresses carried by the second access requests is greater than the average storage space corresponding to the access addresses carried by the first access requests. For example, the size of the storage space can be measured by the number of storage units contained within it.

[0074] Since the access addresses carried by at least two first access requests are discrete, any set of first access requests that satisfies the merging condition carries discrete access addresses. Furthermore, the memory spaces corresponding to the discrete access addresses carried by any set of first access requests that satisfy the merging condition reside in the same candidate memory space. A candidate memory space is a memory space in the memory that supports access through a single request. In other words, the merging condition is determined by whether the memory spaces corresponding to the access addresses carried by at least two first access requests reside in the same candidate memory space. A set of first access requests whose memory spaces corresponding to their access addresses reside in the same candidate memory space is considered a set of first access requests that satisfies the merging condition.

[0075] Candidate memory space is memory space that supports access through a single request. Based on the above method, each group of first access requests that meets the merging conditions is determined. This ensures that the access request obtained after merging each group of first access requests is a request that can directly access the memory, thus ensuring the reliability of the access request merging, thereby ensuring the reliability of the second access request, improving the reliability of access request processing, and ultimately improving the reliability of memory access.

[0076] Candidate storage spaces can be obtained by pre-dividing the memory spaces that can be accessed in the memory. The number of candidate storage spaces is related to the memory spaces that can be accessed in the memory and the division method. This application does not limit this.

[0077] For example, taking a burst request as an example of a request used to access memory, the memory space that can be accessed can be divided based on the burst size threshold and burst length threshold of the burst request that can access memory. Each candidate memory space obtained after the division is a memory space for storing the number of bytes equal to the burst size threshold multiplied by the burst length threshold. In some embodiments, the burst size threshold and burst length threshold of the burst request that can access memory can also be referred to as the burst size threshold and burst length threshold that the AXI bus can access.

[0078] For example, the burst size threshold and burst length threshold can be set empirically or adjusted flexibly according to needs, and this application embodiment does not limit them. For example, the burst size threshold can be 128 bytes (represented as burst_size = 128 bytes), and the burst length threshold can be 16 (represented as burst_length = 16), then each candidate storage space is a storage space used to store 128 * 16 bytes. As another example, the burst size threshold can be 4 bytes (represented as burst_size = 4 bytes), and the burst length threshold can be 16 (represented as burst_length = 16), then each candidate storage space is a storage space used to store 4 * 16 bytes.

[0079] For example, the access request processing device may pre-record information about each candidate storage space, thereby enabling the merging of at least one group of first access requests that meet the merging conditions from at least two first access requests based on the information of each candidate storage space. For example, if the groups of first access requests that meet the merging conditions cover all first access requests, then the access request obtained after merging the groups of first access requests is directly used as at least one second access request; if the groups of first access requests that meet the merging conditions cover only a portion of the first access requests, then the access request obtained after merging the groups of first access requests and the first access requests not covered by the groups of first access requests that meet the merging conditions are used as at least one second access request.

[0080] It should be noted that the storage space corresponding to the access address carried by each first access request is located in a candidate storage space. If the storage space corresponding to the access address carried by different first access requests is in the same candidate storage space, it means that the storage space corresponding to the access address carried by different first access requests is in the same candidate storage space; if the storage space corresponding to the access address carried by different first access requests is in different candidate storage spaces, it means that the storage space corresponding to the access address carried by different first access requests is in different candidate storage spaces.

[0081] In some embodiments, the storage spaces corresponding to the access addresses carried by different first access requests being located in the same candidate storage space can also be referred to as the storage spaces corresponding to the access addresses carried by different first access requests falling within the range of a request (e.g., a burst request).

[0082] In one possible implementation, the access address carried by the merged access request corresponds to a first storage space, which is the smallest storage space containing the storage space corresponding to the access address carried by any group of first access requests. In other words, the process of merging any group of first access requests that meets the merging conditions includes: determining the smallest storage space (i.e., the first storage space) containing the storage space corresponding to the access address carried by the group of first access requests, and using the access request whose carried access address corresponds to the smallest storage space (i.e., the first storage space) as the access request obtained after merging the group of first access requests.

[0083] In this way, while ensuring that the access request obtained after merging any group of first access requests can successfully access all the storage space corresponding to the access address carried by the first access request, the storage space corresponding to the access address carried by the first access request is minimized as much as possible, thereby improving the access effectiveness of the access request obtained after merging any group of first access requests and thus improving the memory access performance.

[0084] For example, if a set of first access requests that meets the merging conditions includes two first access requests, the process of merging these two first access requests can be as follows: Figure 4 As shown. The first access request carries an access address represented by "address=0, burst_size=4byte, burst_length=1". The storage space corresponding to the access address carried by the first access request is a storage space for storing 4 bytes of data, starting from storage unit number 0 (that is, the storage space consisting of storage units numbered 0 to 3). The second access request carries an access address represented by "address=8, burst_size=4byte, burst_length=2". The storage space corresponding to the access address carried by the second access request is two consecutive storage spaces for storing 4 bytes of data, starting from storage unit number 8 (that is, the storage space consisting of storage units numbered 8 to 15).

[0085] Taking a burst size threshold of 4 bytes and a burst length threshold of 16 as an example, the access addresses carried by the two first access requests are discrete, and the storage spaces corresponding to the access addresses carried by the two first access requests are located in the same candidate storage space, that is, the two first access requests can be merged. Figure 4 As shown, the smallest storage space containing the storage space corresponding to the access address carried by the two first access requests is the storage space consisting of storage units numbered 0 to 15. Then, the access request carrying the access address corresponding to the access address of the storage space consisting of storage units numbered 0 to 15 is taken as the access request obtained after merging the two first access requests. The access address carried by the access request obtained after merging the two first access requests can be represented by "address=0, burst_size=4byte, burst_length=4". The storage space corresponding to this access address is four consecutive storage spaces starting from storage unit numbered 0, used to store 4 bytes of data.

[0086] By merging a group of first access requests that meet the merging conditions, two or more first access requests can be combined into one access request, reducing the overall number of memory access requests. In memory access systems based on the AXI bus, it is necessary to maximize the burst_length to the maximum value to maximize the system's bus utilization. An extreme example is 16 requests with a burst_length of 1 versus 1 request with a burst_length of 16; the latter has a much higher bus utilization than the former, and higher bus utilization leads to higher performance. Therefore, reducing the overall number of memory access requests is beneficial to improving bus utilization. For example, bus utilization can be represented by the total burst length of access requests sent to memory via the bus within a unit time period, or by the size of the memory space corresponding to the access address carried by the access request sent to memory via the bus within a unit time period.

[0087] In one possible implementation, see Figure 5 The access request processing apparatus further includes a comparison unit 3. The comparison unit 3 is connected to the merging unit 1. The comparison unit 3 is used to compare the access addresses carried in at least two first access requests to obtain a comparison result. The comparison result is used to indicate whether the storage spaces corresponding to the access addresses carried in the at least two first access requests are located in the same candidate storage space. When the access request processing apparatus further includes the comparison unit 3, the merging unit 1 is used to merge at least one group of first access requests that meet the merging conditions from the at least two first access requests based on the comparison result, to obtain at least one second access request.

[0088] Under this scheme, merging unit 1 only needs to run the calculation logic to merge at least one set of first access requests that meet the merging conditions, without having to run the calculation logic to compare the access addresses carried by at least two first access requests, which helps to reduce the computational pressure on merging unit 1.

[0089] In an exemplary embodiment, the process of comparison unit 3 comparing the access addresses carried by at least two first access requests can be implemented using a pairwise comparison method. For example, in the pairwise comparison method, comparison unit 3 has N*(N-1) / 2 comparison nodes, where N is the number of at least two first access requests. Each comparison node is used to compare the access addresses carried by two of the at least two first access requests. The comparison process of different comparison nodes depends on two different first access requests (either both first access requests are different, or one of the two first access requests is different). In some embodiments, comparison unit 3 can also be called a comparison array (cmp_array).

[0090] For example, at least two first access requests have different numbers, and any first access request needs to be compared with the access address of its preceding first access request, wherein the preceding first access request refers to the first access request with a number less than that of any first access request.

[0091] For example, assuming there are 4 first access requests, numbered 0, 1, 2, and 3 respectively, then comparison unit 3 has 6 comparison nodes. The first comparison node is used to compare the access addresses of req0 (the first access request numbered 0) and req1 (the first access request numbered 1), the second comparison node is used to compare the access addresses of req0 and req2 (the first access request numbered 2), the third comparison node is used to compare the access addresses of req0 and req3 (the first access request numbered 3), the fourth comparison node is used to compare the access addresses of req1 and req2, the fifth comparison node is used to compare the access addresses of req1 and req3, and the sixth comparison node is used to compare the access addresses of req2 and req3.

[0092] In the pairwise comparison method, the comparison result includes multiple sub-results. Each sub-result indicates whether the storage spaces corresponding to the access addresses carried by the two first access requests on which the sub-result depends are located in the same candidate storage space. By combining the various sub-results, it is possible to determine the groups of first access requests whose storage spaces corresponding to the carried access addresses are located in the same candidate storage space, that is, to determine at least one group of first access requests that meet the merging conditions among at least two first access requests.

[0093] For example, the sub-result obtained by the first comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req1 are in the same candidate storage space; the sub-result obtained by the second comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req2 are in the same candidate storage space; the sub-result obtained by the third comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req3 are in different candidate storage spaces; the sub-result obtained by the fourth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req1 and req2 are in the same candidate storage space; the sub-result obtained by the fifth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req1 and req3 are in different candidate storage spaces; and the sub-result obtained by the sixth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req2 and req3 are in different candidate storage spaces.

[0094] By analyzing the sub-results obtained from the above six comparison nodes, it can be determined that the storage spaces corresponding to the access addresses carried by req0, req1, and req2 are located in the same candidate storage space, that is, a set of first access requests (req0, req1, and req2) that meet the merging conditions are identified. In this case, at least one second access request includes the access request obtained by merging req0, req1, and req2, as well as req3.

[0095] For example, the sub-result obtained by the first comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req1 are in the same candidate storage space; the sub-result obtained by the second comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req2 are in different candidate storage spaces; the sub-result obtained by the third comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req0 and req3 are in different candidate storage spaces; the sub-result obtained by the fourth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req1 and req2 are in different candidate storage spaces; the sub-result obtained by the fifth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req1 and req3 are in different candidate storage spaces; and the sub-result obtained by the sixth comparison node is used to indicate that the storage spaces corresponding to the access addresses carried by req2 and req3 are in the same candidate storage space.

[0096] By analyzing the sub-results obtained from the above six comparison nodes, it can be determined that the storage spaces corresponding to the access addresses carried by req0 and req1 are in the same candidate storage space, and the storage spaces corresponding to the access addresses carried by req2 and req3 are in the same candidate storage space. Furthermore, the candidate storage spaces for the access addresses carried by req0 and req1 are different from those for the access addresses carried by req2 and req3. In other words, two sets of first access requests satisfying the merging condition are identified: one set of first access requests is req0 and req1, and the other set is req2 and req3. In this case, at least one second access request includes the access request obtained by merging req0 and req1, and the access request obtained by merging req2 and req3.

[0097] When the comparison result is obtained through comparison unit 3, merging unit 1 merges at least one set of first access requests that meet the merging conditions from at least two first access requests based on the comparison result, to obtain at least one second access request.

[0098] In one possible implementation, the merging unit 1 is a single unit. In this case, the process by which the merging unit 1 merges at least one group of first access requests that meet the merging conditions from at least two first access requests based on the comparison results to obtain at least one second access request is as follows: the comparison results are analyzed using the single unit to determine each group of first access requests that meet the merging conditions, and each group of first access requests that meets the merging conditions is merged separately; if each group of first access requests covers all first access requests, the access request obtained after merging each group of first access requests is taken as at least one second access request; if each group of first access requests covers some first access requests, the access request obtained after merging each group of first access requests and the first access requests not covered by each group of first access requests are taken as at least one second access request.

[0099] In this approach, only one unit needs to be placed in the access request processing device to realize the merging process, which helps to reduce the number of hardware components that need to be placed in the access request processing device, saves the area occupied by the access request processing device, and thus saves the area occupied by the processor.

[0100] In another possible implementation, see Figure 6 The merging unit 1 includes at least two merging subunits 11 corresponding to the first access requests respectively. In this case, at least one second access request includes the access requests output by each merging subunit 11.

[0101] Taking any one of at least two first access requests as an example, the merging subunit corresponding to any one first access request is used to output the access request obtained by merging any group of first access requests when any one first access request is in any group of first access requests and any one first access request meets the merging requirements; or, it is used to not output the access request when any one first access request is in any group of first access requests and any one first access request does not meet the merging requirements; or, it is used to output any one first access request when any one first access request is not in at least one group of first access requests.

[0102] It should be noted that although the merging subunit 11 corresponding to any first access request may or may not output an access request, at least one of the two first access requests will have a merging subunit 11 that outputs an access request, so as to ensure that at least one second access request is obtained.

[0103] In the case where the merging unit 1 includes at least two merging subunits 11 corresponding to the first access requests respectively, each merging subunit 11 only needs to focus on the merging of the first access requests corresponding to it. There is no conflict between the calculation logic of multiple merging subunits 11, which enables multiple merging subunits 11 to perform parallel calculations, improves the efficiency of obtaining at least one second access request, and thus improves memory access efficiency.

[0104] For any first access request to satisfy the merging requirement, it means that other first access requests in any group of first access requests need to be merged into that first access request. The method for determining whether any first access request satisfies the merging requirement can be set based on experience or flexibly adjusted according to the application scenario, and this application embodiment does not limit it in this way.

[0105] In an exemplary embodiment, at least two first access requests have different numbers; any first access request satisfying the merging requirement includes the number of any first access request satisfying a constraint condition within any group of first access request numbers. The constraint condition is a condition that restricts the numbers. The constraint condition can be set based on experience or flexibly adjusted according to the application scenario; this embodiment does not limit this. For example, the constraint condition being satisfied by the number of any first access request within any group of first access request numbers could mean that the number of any first access request is the maximum value among the numbers of any group of first access requests, or it could mean that the number of any first access request is the minimum value among the numbers of any group of first access requests, etc.

[0106] The merging requirement is determined by checking whether the number of any first access request is the maximum or minimum number among any group of first access requests. The logic for determining the number is relatively simple, which helps to simplify the calculation logic for determining whether any first access request meets the merging requirement and improves the efficiency of obtaining at least one second access request.

[0107] If any first access request does not meet the merging requirement, it means that any first access request needs to be merged into other first access requests in any group of first access requests. In an exemplary embodiment, if any first access request is located in any group of first access requests indicated by the comparison result, and any first access request does not meet the merging requirement, it can be considered that any first access request needs to be merged into (or has already been merged into) other first access requests. In this case, any first access request can be invalidated. If any first access request is invalidated, the merging subunit 11 corresponding to any first access request does not output any access request.

[0108] For example, if req1 is in a first access request group consisting of req0 and req1, and req1 does not meet the merging requirements, then req1 is considered to be merged into req0, forming a merged req0. After passing through the merging sub-unit 11 corresponding to req1, req1 is invalidated. It should be noted that for access requests that are burst requests, the burst_length of the merged req0 may increase or remain unchanged compared to req0. If the burst_length of the merged req0 remains unchanged, then the burst_size of the merged req0 increases; if the burst_length of the merged req0 increases, then the burst_size of the merged req0 may increase or remain unchanged.

[0109] For example, the process of invalidating any first access request can be called the process of masking any first access request. The merging subunit 11 corresponding to any first access request can also be called a mask unit.

[0110] After processing by merging unit 1, at least one second access request is obtained. This at least one second access request can also be referred to as the output result of merging unit 1 (which can be represented as merged_req). The output result of merging unit 1 needs to be output to sending unit 2, which is connected to merging unit 1. Next, sending unit 2 will be described.

[0111] Sending unit 2 is used to send at least one second access request to the memory.

[0112] In one possible implementation, see Figure 7 The transmitting unit 2 includes an allocation subunit 21, a selection subunit 22, and a transmitting subunit 23. Exemplarily, all three subunits are hardware modules, such as circuits. They are connected sequentially, with the allocation subunit 21 connected to the merging unit 1. The allocation subunit 21, selection subunit 22, and transmitting subunit 23 will be described below.

[0113] The allocation subunit 21 is used to allocate at least one second access request to the waiting queue, thereby obtaining an updated waiting queue.

[0114] A wait queue is a queue that waits for access requests to be sent to the memory. All access requests first enter the wait queue and wait until the appropriate time to be sent to the memory. In some embodiments, the allocation subunit 21 can be represented as an allocation unit. In an exemplary embodiment, the wait queue can be recorded by a table, which can be called a wait table. In an exemplary embodiment, the wait queue can have multiple entries, each entry recording information related to an access request.

[0115] For example, taking a burst request as an example, the relevant information of the access request may include, but is not limited to, the following five aspects: starting address (also known as the access start address), burst length, address identifier, request information, and priority index. For example, the starting address and burst length can be directly extracted from the access address carried in the access request.

[0116] For example, the address identifier is used to indicate the valid and invalid addresses in the access address carried by the access request. The valid address is the access address in the access request generated by the access source, and the invalid address is any address other than the valid address. It can also be understood as additional addresses added during the merging process besides the access address carried by the merged access request. For example, the address identifier includes a first number of bits, where the first number is the number of addresses covered by the access address carried by the access request (each address corresponds to a storage unit in memory, e.g., each address corresponds to a storage unit for storing 1 byte of data). Each bit corresponds one-to-one with the addresses covered by the access address carried by the access request. If a bit is 0, the address corresponding to that bit is an invalid address; if a bit is 1, the address corresponding to that bit is a valid address. Based on the address identifier, the number of valid addresses in the access address carried by the access request can be determined, as can the valid data in the data to be accessed by the access request.

[0117] For example, the request information is used to indicate information about the access request generated by the access source upon which the access request depends, such as the access address carried in the access request generated by the access source upon which the access request depends. Based on the request information, it is convenient to subsequently access the memory based on the access request to obtain data, and then match the data with the access request generated by the access source, thereby feeding back the corresponding data to the corresponding access source.

[0118] For example, a priority index is used to indicate the priority at which an access request is sent to the storage. The higher the priority index, the higher the priority at which the access request is sent to the storage.

[0119] In an exemplary embodiment, the priority index of any third access request in the waiting queue is determined based on at least one of the following: the number of valid addresses in the access address carried by any third access request; and the number of clock cycles that any third access request has been waiting for. The number of valid addresses in the access address carried by any third access request can be determined based on the number of 1s in the address identifier of that third access request. A clock cycle is the most basic and smallest unit of time in a computer device. The number of clock cycles that any third access request has been waiting for refers to the number of clock cycles that have elapsed between the time when any third access request was assigned to the waiting queue and the current time.

[0120] In some embodiments, where the priority index for any third access request is determined solely based on the number of valid addresses in the access addresses carried by any third access request, the number of valid addresses in the access addresses carried by any third access request can be used as the priority index for any third access request.

[0121] If the priority index of any third access request is determined solely based on the number of clock cycles that any third access request has been waiting for, then the number of clock cycles that any third access request has been waiting for can be used as the priority index of any third access request.

[0122] Given that the priority index for any third access request is determined based on the number of valid addresses in the access address carried by the third access request and the number of clock cycles that the third access request has been waiting for, the sum of the number of valid addresses in the access address carried by the third access request and the number of clock cycles that the third access request has been waiting for can be used as the priority index for any third access request.

[0123] For example, an entry used to record information related to an access request may have fields (also called domains) for recording information on the five aspects mentioned above, with each field recording information on one aspect. For instance, an entry may have five fields named addr, burst_len, strb, req_info, and priority. The field named addr records the starting address of the access request, the field named burst_len records the starting address of the access request, the field named strb records the starting address of the access request, the field named req_info records the starting address of the access request, and the field named priority records the priority index of the access request.

[0124] The allocation principle for each of the at least one second access requests is the same. Taking any one second access request as an example, the method by which the allocation subunit 21 allocates the any one second access request to the waiting queue is described. For example, the allocation subunit 21 is used to merge any one second access request into any one third access request if any one of the at least one second access requests and any one of the third access requests in the waiting queue meet the merging condition; or, it is used to add any one second access request as a new access request to the waiting queue if any one of the second access requests and none of the third access requests in the waiting queue meet the merging condition, and the number of third access requests in the waiting queue is less than a quantity threshold; or, it is used to allocate any one second access request to the waiting queue after any one of the third access requests in the waiting queue has been sent to the memory if any one of the second access requests and none of the third access requests in the waiting queue meet the merging condition, and the number of third access requests in the waiting queue is not less than a quantity threshold.

[0125] Access requests in the waiting queue are referred to as third access requests. If any second access request and any third access request satisfy the merging condition, it means that any second access request can be merged with any third access request. In this case, any second access request is assigned to the waiting queue by merging any second access request into any third access request.

[0126] For example, the merging condition for any second access request and any third access request can be that the storage space corresponding to the access address carried by any second access request and the storage space corresponding to the access address carried by any third access request are located in the same candidate storage space in the memory.

[0127] The quantity threshold can be set based on experience or adjusted flexibly according to the application scenario; this application embodiment does not limit this. For example, the process of adding any second access request as a new access request to the waiting queue can be as follows: select an idle entry in the waiting queue, and record the relevant information of the second access request in that idle entry.

[0128] In other words, the allocation logic for any second access request is as follows:

[0129] 1) First, determine whether any second access request and the access request in the current waiting queue can be merged. The merging logic is the same as the merging process in merging unit 1. If it can be merged with an access request in the waiting queue, then merge any second access request into that access request. Taking the access request as a burst request as an example, the burst_length of the resulting access request may become longer or may remain unchanged.

[0130] 2) If any second access request cannot be merged with any of the access requests in the current waiting queue, then select an idle entry and assign it to any second access request, that is, add the second access request as a new access request to the waiting queue.

[0131] 3) If the current waiting queue is full, that is, the number of access requests in the waiting queue is not less than the number threshold, then any second access request needs to be allocated after a free entry is released from the waiting queue. In other words, any second access request needs to be allocated to the waiting queue after an access request in the waiting queue is sent to the memory.

[0132] In the process of allocating the second access request to the waiting queue, it is necessary to fully consider whether the second access request can be merged with the third access request in the waiting queue, and whether the number of the third access requests in the waiting queue is less than the number threshold. By using different methods to allocate the second access request to the waiting queue under different circumstances, the matching between the method of allocating the second access request to the waiting queue and the actual situation can be improved, the reliability of allocating the second access request to the waiting queue can be improved, and thus the reliability of memory access can be improved.

[0133] After allocating each second access request to the waiting queue, an updated waiting queue is obtained. Then, the allocation subunit 21 outputs the updated waiting queue to the selection subunit 22 connected to it. The selection subunit 22 is used to select access requests that meet the sending conditions from the updated waiting queue.

[0134] In an exemplary embodiment, any fourth access request in the updated waiting queue has a priority index. In this case, the access request that meets the sending conditions can be the fourth access request with the highest priority index in the updated waiting queue. The higher the priority index, the greater the demand for the fourth access request to be sent to the memory. In some embodiments, the selection subunit 22 can be represented as a priority max cmp select unit.

[0135] By determining whether the priority index of the fourth access request is the highest, the calculation logic for determining whether the fourth access request meets the sending conditions is simplified, thus improving memory access efficiency. Furthermore, prioritizing higher-priority access requests sent to memory improves memory access reliability.

[0136] In an exemplary embodiment, the priority index of any fourth access request in the updated waiting queue is determined based on at least one of the following: the number of valid addresses in the access addresses carried by any fourth access request; and the number of clock cycles that any fourth access request has been waiting for. The number of valid addresses in the access addresses carried by any fourth access request can be determined based on the number of 1s recorded in the strb field of the entry recording that fourth access request.

[0137] In some embodiments, if the priority index of any fourth access request is determined solely based on the number of valid addresses in the access addresses carried by the fourth access request, then the number of valid addresses in the access addresses carried by the fourth access request can be used as the priority index of the fourth access request. If the priority index of any fourth access request is determined solely based on the number of clock cycles that the fourth access request has waited for, then the number of clock cycles that the fourth access request has waited for can be used as the priority index of the fourth access request. If the priority index of any fourth access request is determined based on both the number of valid addresses in the access addresses carried by the fourth access request and the number of clock cycles that the fourth access request has waited for, then the sum of the number of valid addresses in the access addresses carried by the fourth access request and the number of clock cycles that the fourth access request has waited for can be used as the priority index of the fourth access request.

[0138] By considering the number of valid addresses and / or the number of clock cycles to determine the priority index of access requests, it is possible to ensure that access requests with a large number of valid addresses and / or those that have been in the waiting queue for a long time are sent to the memory first. These access requests are the ones with greater demand for accessing the memory, and sending these access requests to the memory first is beneficial to improving memory access performance.

[0139] As time goes on, the waiting queue is constantly updated, and the priority indicators of the access requests in the waiting queue are also constantly updated. That is to say, the priority indicators of the same access request in the waiting queue before the update and the waiting queue after the update may be different. The reason for the change in priority indicators may be that new requests are merged into the access requests, or the number of clock cycles increases, or new requests are merged into the access requests and the number of clock cycles increases.

[0140] Taking the access request priority index as the sum of the number of valid addresses in the access address carried by the access request and the number of clock cycles the access request has waited for, the update process of the access request priority index can be as follows: Figure 8 As shown. Suppose that at a certain moment, the valid addresses in the access address carried by the access request are addresses 0-3, 8-9, and 14-15, then the address identifier of the access request at that moment can be represented as strb = 1100_0011_0000_1111. The number of 1s in strb is 8, which means that there are a total of 8 bytes of valid data in the access request. valid_clock = 5 indicates that the number of clock cycles that the access request has waited for is 5. At that moment, the priority index of the access request is the sum of these two, which is 13. Suppose that after 4 clock cycles, a new access request is merged into the access request, and the new access request carries the access address 6-7. Then the valid addresses in the access address carried by the new access request are updated to addresses 0-3, 6-9, and 14-15. At this time, the address identifier of the access request can be represented as strb = 1100_0011_1100_1111. The number of 1s in strb increases to 10, valid_clock increases to 9, and finally the priority index of the access request is updated to 19.

[0141] In an exemplary embodiment, the process of determining the fourth access request with the highest priority index in the updated waiting queue can employ a pairwise comparison strategy. For example, the fourth access requests in the updated waiting queue are grouped into pairs, and the priority indices of the two fourth access requests in each group are compared to determine the fourth access request with the higher priority index in each group, completing one comparison process. The fourth access requests determined in the first comparison process are then grouped into pairs again, and the priority indices of the two fourth access requests in each group are compared to determine the fourth access request with the higher priority index in each group, completing a second comparison process. This process continues until only one fourth access request is determined, at which point the currently determined fourth access request is taken as the fourth access request with the highest priority index. For example, the pairwise comparison strategy described above applies when the number of fourth access requests in the updated waiting queue is even.

[0142] For example, the process of determining the fourth access request with the highest priority index using a pairwise comparison strategy can be as follows: Figure 9 As shown in the diagram. Assume there are four fourth access requests in the updated waiting queue, represented as access request 1, access request 2, access request 3, and access request 4, with priority indices of 5, 10, 7, and 20 respectively. Comparing the priority indices of access request 1 and access request 2, access request 2 is determined to have the higher priority. Similarly, comparing the priority indices of access request 3 and access request 4, access request 4 is determined to have the higher priority. This completes one comparison process. Then, comparing the priority indices of access request 2 and access request 4, access request 4 is determined to have the higher priority. This completes the second comparison process. Since only one access request is identified, access request 4 is designated as the fourth access request with the highest priority.

[0143] It should be noted that the above-described method of determining the fourth access request with the highest priority index using a pairwise comparison strategy is merely illustrative, and the embodiments of this application are not limited thereto. In some embodiments, the fourth access request with the highest priority index can also be determined in other ways. For example, the priority index of the first fourth access request in the updated waiting queue can be set to the maximum value, and then compared with the priority index of each of the other fourth access requests. If a priority index larger than the current maximum value is found, the maximum value is updated, and so on, until all access requests are traversed. The fourth access request corresponding to the maximum value determined after traversing all access requests is taken as the fourth access request with the highest priority index.

[0144] A high priority indicator indicates that the current access request already includes a large number of merged requests, and that the current access request has been in the waiting queue for a long time, requiring it to be sent out as soon as possible. Access requests that have been in the waiting queue for a short time and contain little valid data can remain in the waiting queue and be merged with subsequent access requests.

[0145] The sending subunit 23 is used to send an access request that meets the sending conditions to the memory.

[0146] In the exemplary embodiment, there are two cases for access requests that meet the sending conditions:

[0147] Case 1: Any of the second access requests in at least one second access request matches an access request that satisfies the sending conditions.

[0148] For example, the matching of any second access request with an access request that meets the sending conditions may mean that the access request that meets the sending conditions is the second access request itself, or it may mean that the access request that meets the sending conditions includes the second access request.

[0149] In this case 1, sending an access request that meets the sending conditions to the memory by the sending subunit 23 means that the sending subunit 23 sends an access request that meets the sending conditions and matches any second access request to the memory, so as to send the any second access request to the memory.

[0150] Case 2: Each of the second access requests in at least one second access request does not match the access request that satisfies the sending conditions.

[0151] In this second scenario, sending an access request that meets the sending conditions to the memory by the sending subunit 23 means that the sending subunit 23 sends an access request that meets the sending conditions but does not match any of the second access requests.

[0152] For example, the process of sending an access request that meets the sending conditions to the memory by the sending subunit 23 includes: the sending subunit sending the access request that meets the sending conditions to the bus (e.g., an AXI bus), and sending the access request that meets the sending conditions to the memory via the bus. In some embodiments, the sending subunit 23 may be represented as req send (requestsend unit).

[0153] By implementing the process of first allocating, then selecting, and finally sending, the sending of the second access request can improve the standardization of the second access request sending, improve the standardization of memory access, and reduce the possibility of errors. In addition, the access requests sent to the memory are those that meet the sending conditions in the current waiting queue, which helps to ensure the reliability of memory access.

[0154] It should be noted that the above description only uses the example of the sending unit 2 including the allocation subunit 21, the selection subunit 22, and the sending subunit 23, but the embodiments of this application are not limited to this. The structure of the sending unit 2 can also be other cases, and under different structures, the process of the sending unit 2 sending at least one second access request to the memory may be different.

[0155] For example, the sending unit 2 may be a single, integrated unit. In this case, the process of sending at least one second access request to the memory by the sending unit 2 can be as follows: the sending unit 2 arranges the second access requests in a certain order, and after all the historical access requests have been sent to the memory, it sends each second access request to the memory in that order. The order can be set based on experience or flexibly adjusted according to the application scenario. For example, the order can refer to the order in which the memory spaces corresponding to the access addresses carried by each second access request are arranged from largest to smallest or smallest to largest.

[0156] This application proposes a discrete access request processing device to improve bus utilization. By comparing adjacent discrete addresses, multiple discrete requests that can be merged into a burst request are combined, reducing the total number of requests sent by the AI ​​processor to the bus (e.g., the AXI bus), increasing the effective burst length of each request, improving bus utilization, and thus enhancing the memory access performance of the AI ​​processor. In the field of AI processors, discrete memory access performance has a significant impact on the overall performance of the AI ​​processor. The discrete access request processing device to improve bus utilization proposed in this application has high performance and consumes less chip area, effectively enhancing the competitiveness of the product.

[0157] In this embodiment of the application, the access request processing device includes a merging unit. Based on this structure, the access request processing device can merge at least one set of first access requests that meet the merging conditions, and then send the merged second access request to the memory.

[0158] Since the second access request is obtained by merging at least one set of first access requests that meet the merging conditions, the number of second access requests is small. Sending the second access request to the memory can reduce the number of access request transmissions, increase the average storage space accessed by each transmitted access request, and thus improve the utilization of the bus on which the transmission of access requests depends.

[0159] For example, taking an access request processing device including a comparison unit 3, a merging subunit 11, an allocation subunit 21, a selection subunit 22, and a sending subunit 23 corresponding to at least two first access requests as an example, a specific process for accessing memory based on the access request processing device is described. This process can be as follows: Figure 10 As shown. In Figure 10In the access process shown, there are 8 initial access requests, represented as req0, req1, req2, req3, req4, req5, req6, and req7. Here, req0, req1, req2, and req3 are four sub-requests in request vector 0, and req4, req5, req6, and req7 are four sub-requests in request vector 1. For example, request vector 0 is the request vector generated by the control unit of the vector processing engine, and request vector 1 is the request vector generated by the control unit of the matrix operation engine.

[0160] Comparison unit 3 includes 28 comparison nodes. Eight first access requests enter comparison unit 3, and the 28 comparison nodes compare the access addresses carried by these eight first access requests. Figure 10 In comparison unit 3, each circle represents a comparison node, and the two numbers in the circle represent the numbers of the two first access requests for which the access addresses are compared. For example, the numbers 0 and 1 in the circle in the upper left corner represent the numbers of req0 and req1, which means that the access addresses carried by req0 and req1 are being compared.

[0161] The comparison unit 3 outputs the comparison results to the merging subunits 11 corresponding to the eight first access requests respectively. The merging subunits 11 corresponding to the eight first access requests respectively handle the merging of their respective first access requests according to the comparison results and output the merging result (merged_req) to the allocation subunit 21. The merging result is at least one second access request.

[0162] The allocation subunit 21 allocates at least one second access request to the waiting queue, resulting in an updated waiting queue. The updated waiting queue includes multiple entries (e.g., entry0, entry1, ..., entryn-1), each entry recording relevant information about an access request based on five fields: addr, burst_len, strb, req_info, and priority.

[0163] Selection subunit 22 selects the access request with the highest priority index from the updated waiting queue, and sending subunit 23 sends the access request with the highest priority index to the bus (AXI-BUS). The access request with the highest priority index is sent to the memory through the bus to access the memory space corresponding to the access address carried by the access request with the highest priority index.

[0164] This application also provides an access request processing method, which can be applied to the access request processing apparatus described above. The access request processing apparatus includes a merging unit and a sending unit. For example... Figure 11As shown, the method includes the following steps 1101 and 1102.

[0165] Step 1101: At least one set of first access requests that meet the merging conditions are merged by the merging unit to obtain at least one second access request. Any set of first access requests that meet the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is the storage space in the memory that supports access through a single request.

[0166] In one possible implementation, the access request processing apparatus further includes a comparison unit; the method further includes: comparing the access addresses carried by at least two first access requests through the comparison unit to obtain a comparison result, the comparison result being used to indicate whether the storage spaces corresponding to the access addresses carried by the at least two first access requests are located in the same candidate storage space, and the access addresses carried by the at least two first access requests are discrete. The merging unit merges at least one set of first access requests that meet the merging conditions to obtain at least one second access request, including: merging at least one set of first access requests that meet the merging conditions from at least two first access requests based on the comparison result through the merging unit to obtain at least one second access request.

[0167] In one possible implementation, the merging unit includes at least two merging sub-units corresponding to each of the first access requests, and at least one second access request includes access requests output by each merging sub-unit. The access addresses carried by the at least two first access requests are discrete. The merging unit merges at least one group of first access requests that meet the merging conditions to obtain at least one second access request, including: when any first access request is located in any group of first access requests and any first access request meets the merging requirements, the merging sub-unit corresponding to any first access request outputs the access request obtained by merging any group of first access requests; when any first access request is located in any group of first access requests and any first access request does not meet the merging requirements, no access request is output; when any first access request is not located in at least one group of first access requests, any first access request is output.

[0168] In an exemplary embodiment, at least two first access requests have different numbers; any first access request satisfying the merging requirement includes the number of any first access request being the maximum value among the numbers of any group of first access requests, or any first access request satisfying the merging requirement includes the number of any first access request being the minimum value among the numbers of any group of first access requests.

[0169] In one possible implementation, the access address carried by the access request obtained by merging any group of first access requests corresponds to a first storage space, and the first storage space is the smallest storage space containing the storage space corresponding to the access address carried by any group of first access requests.

[0170] Step 1102: Send at least one second access request to the memory via the sending unit.

[0171] In one possible implementation, the sending unit includes an allocation subunit, a selection subunit, and a sending subunit. Sending at least one second access request to the memory through the sending unit includes: allocating at least one second access request to a waiting queue through the allocation subunit to obtain an updated waiting queue; selecting an access request that meets the sending conditions from the updated waiting queue through the selection subunit; and sending any second access request to the memory through the sending subunit if any of the at least one second access request matches an access request that meets the sending conditions.

[0172] In one possible implementation, at least one second access request is allocated to a waiting queue by an allocation subunit to obtain an updated waiting queue. This includes: merging any second access request into any third access request if the allocation subunit meets a merging condition with any second access request in the at least one second access request; adding any second access request as a new access request to the waiting queue if the merging condition is not met with any third access requests in the waiting queue and the number of third access requests in the waiting queue is less than a quantity threshold; and allocating any second access request to the waiting queue after sending any third access request in the waiting queue to memory if the merging condition is not met with any second access request in the waiting queue and the number of third access requests in the waiting queue is not less than a quantity threshold.

[0173] In an exemplary embodiment, any fourth access request in the updated waiting queue has a priority index; the access request that meets the sending conditions is the fourth access request with the highest priority index in the updated waiting queue.

[0174] In an exemplary embodiment, the priority index of any fourth access request in the updated waiting queue is determined based on at least one of the following: the number of valid addresses in the access addresses carried by any fourth access request; and the number of clock cycles that any fourth access request has been waiting for.

[0175] The implementation methods and technical effects of steps 1101 and 1102 can be found in the above text. Figures 2 to 10The corresponding explanations will not be repeated here.

[0176] In an exemplary embodiment, this application provides a processor that includes the access request processing apparatus provided in this application. Exemplarily, the processor further includes an access source for generating at least two first access requests carrying discrete access addresses. Exemplarily, the processor belongs to a type of chip.

[0177] In an exemplary embodiment, such as Figure 12 As shown, this application embodiment provides a computer device, which includes a processor 1201 and a memory 1202. The processor 1201 is the processor provided in this application embodiment. An access request processing device in the processor 1201 is used to access the memory 1202. Exemplarily, this computer device can be a terminal or a server. The structures of the terminal and the server will be described below.

[0178] Figure 13 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. The terminal can be a smartphone, tablet computer, media player, laptop computer, or desktop computer. The terminal may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names.

[0179] Typically, a terminal includes a processor 1301 and a memory 1302. The processor 1301 includes the access request processing device provided in this application embodiment, which is used to access the memory 1302.

[0180] Processor 1301 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1301 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1301 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1301 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1301 may also include an AI (Artificial Intelligence) processor, which is used to handle AI-related computational operations.

[0181] The memory 1302 may include one or more computer-readable storage media, which may be non-transitory. The memory 1302 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0182] In some embodiments, the terminal may also optionally include: a peripheral device interface 1303 and at least one peripheral device. The processor 1301, memory 1302, and peripheral device interface 1303 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of: a radio frequency circuit 1304, a display screen 1305, a camera assembly 1306, an audio circuit 1307, and a power supply 1308.

[0183] Peripheral device interface 1303 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1301 and memory 1302. In some embodiments, processor 1301, memory 1302 and peripheral device interface 1303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1301, memory 1302 and peripheral device interface 1303 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0184] The radio frequency (RF) circuit 1304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1304 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1304 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1304 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1304 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: metropolitan area networks (MANs), various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks (WLANs), and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1304 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0185] Display screen 1305 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1305 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1301 for processing. In this case, display screen 1305 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, display screen 1305 can be a single screen, located on the front panel of the terminal; in other embodiments, display screen 1305 can be at least two screens, respectively located on different surfaces of the terminal or in a folded design; in other embodiments, display screen 1305 can be a flexible display screen, located on a curved or folded surface of the terminal. Furthermore, display screen 1305 can be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. Display screen 1305 can be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0186] The camera assembly 1306 is used to acquire images or videos. Optionally, the camera assembly 1306 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1306 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0187] The audio circuit 1307 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1301 for processing, or input to the radio frequency circuit 1304 to achieve voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1301 or the radio frequency circuit 1304 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1307 may also include a headphone jack.

[0188] Power supply 1308 is used to power the various components in the terminal. Power supply 1308 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1308 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0189] In some embodiments, the terminal further includes one or more sensors 1309. The one or more sensors 1309 include, but are not limited to: an acceleration sensor 1310, a gyroscope sensor 1311, a pressure sensor 1312, an optical sensor 1313, and a proximity sensor 1314.

[0190] Accelerometer 1310 can detect the magnitude of acceleration along the three coordinate axes of a coordinate system established by the terminal. For example, accelerometer 1310 can be used to detect the components of gravitational acceleration along the three coordinate axes. Processor 1301 can control display screen 1305 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 1310. Accelerometer 1310 can also be used for games or for acquiring user motion data.

[0191] The gyroscope sensor 1311 can detect the terminal's orientation and rotation angle. The gyroscope sensor 1311 can work in conjunction with the accelerometer sensor 1310 to collect the user's 3D movements on the terminal. Based on the data collected by the gyroscope sensor 1311, the processor 1301 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0192] The pressure sensor 1312 can be disposed on the side bezel of the terminal and / or the lower layer of the display screen 1305. When the pressure sensor 1312 is disposed on the side bezel of the terminal, it can detect the user's grip signal on the terminal, and the processor 1301 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 1312. When the pressure sensor 1312 is disposed on the lower layer of the display screen 1305, the processor 1301 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 1305. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0193] Optical sensor 1313 is used to collect ambient light intensity. In one embodiment, processor 1301 can control the display brightness of display screen 1305 based on the ambient light intensity collected by optical sensor 1313. Specifically, when the ambient light intensity is high, the display brightness of display screen 1305 is increased; when the ambient light intensity is low, the display brightness of display screen 1305 is decreased. In another embodiment, processor 1301 can also dynamically adjust the shooting parameters of camera assembly 1306 based on the ambient light intensity collected by optical sensor 1313.

[0194] The proximity sensor 1314, also known as a distance sensor, is typically installed on the front panel of the terminal. The proximity sensor 1314 is used to detect the distance between the user and the front of the terminal. In one embodiment, when the proximity sensor 1314 detects that the distance between the user and the front of the terminal is gradually decreasing, the processor 1301 controls the display screen 1305 to switch from a screen-on state to a screen-off state; when the proximity sensor 1314 detects that the distance between the user and the front of the terminal is gradually increasing, the processor 1301 controls the display screen 1305 to switch from a screen-off state to a screen-on state.

[0195] Those skilled in the art will understand that Figure 13 The structure shown does not constitute a limitation on the terminal and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0196] Figure 14This is a schematic diagram of a server structure provided in an embodiment of this application. The server can vary significantly due to differences in configuration or performance, and may include one or more processors 1401 and one or more memories 1402. At least one of the one or more processors 1401 includes the access request processing device provided in this embodiment, which is used to access at least one memory 1402 among the one or more memories 1402. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated here.

[0197] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the first access request involved in this application was obtained under fully authorized conditions.

[0198] The terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the above exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0199] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0200] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. An access request processing apparatus, characterized in that, The access request processing device includes a merging unit (1) and a sending unit (2); The merging unit (1) is used to merge at least one set of first access requests that meet the merging conditions to obtain at least one second access request. Any set of first access requests that meet the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is a storage space in the memory that supports access through a single request. The sending unit (2) is used to send the at least one second access request to the memory.

2. The apparatus according to claim 1, characterized in that, The access request processing device further includes a comparison unit (3); The comparison unit (3) is used to compare the access addresses carried by at least two first access requests to obtain a comparison result. The comparison result is used to indicate whether the storage spaces corresponding to the access addresses carried by the at least two first access requests are located in the same candidate storage space. The access addresses carried by the at least two first access requests are discrete. The merging unit (1) is used to merge at least one set of first access requests that meet the merging conditions among the at least two first access requests based on the comparison result, so as to obtain the at least one second access request.

3. The apparatus according to claim 1, characterized in that, The merging unit (1) includes at least two merging subunits (11) corresponding to the first access requests respectively, and the at least one second access request includes the access requests output by each merging subunit (11). The access addresses carried by the at least two first access requests are discrete. The merging subunit (11) corresponding to any first access request is used to output the access request obtained by merging the first access requests when the first access request is located in any group of first access requests and the first access request meets the merging requirements. Alternatively, it can be used to not output an access request if any of the first access requests is located in any group of first access requests and if any of the first access requests does not meet the merging requirement; Alternatively, it can be used to output any of the first access requests if any of the first access requests is not among the at least one set of first access requests.

4. The apparatus according to claim 3, characterized in that, The at least two first access requests have different numbers; any first access request satisfying the merging requirement includes the number of any first access request being the maximum value among the numbers of any group of first access requests, or the number of any first access request satisfying the merging requirement includes the number of any first access request being the minimum value among the numbers of any group of first access requests.

5. The apparatus according to any one of claims 1-4, characterized in that, The first storage space corresponds to the access address carried by the access request obtained by merging any group of first access requests. The first storage space is the smallest storage space that contains the storage space corresponding to the access address carried by any group of first access requests.

6. The apparatus according to any one of claims 1-4, characterized in that, The sending unit (2) includes an allocation subunit (21), a selection subunit (22), and a sending subunit (23); The allocation subunit (21) is used to allocate the at least one second access request to the waiting queue to obtain the updated waiting queue; The selection subunit (22) is used to select an access request that meets the sending conditions in the updated waiting queue; The sending subunit (23) is used to send any second access request to the memory if any second access request in the at least one second access request matches the access request that satisfies the sending conditions.

7. The apparatus according to claim 6, characterized in that, The allocation subunit (21) is used to merge any second access request into any third access request when any second access request in the at least one second access request and any third access request in the waiting queue meet the merging condition; Alternatively, if any second access request and each of the third access requests in the waiting queue do not meet the merging condition, and the number of third access requests in the waiting queue is less than a number threshold, then any second access request can be added as a new access request to the waiting queue. Alternatively, if neither the second access request nor any of the third access requests in the waiting queue satisfy the merging condition, and the number of third access requests in the waiting queue is not less than the number threshold, then after any third access request in the waiting queue is sent to the memory, the second access request is allocated to the waiting queue.

8. The apparatus according to claim 6 or 7, characterized in that, Any fourth access request in the updated waiting queue has a priority index; the access request that meets the sending conditions is the fourth access request with the highest priority index in the updated waiting queue.

9. The apparatus according to claim 8, characterized in that, The priority metric for any fourth access request in the updated waiting queue is determined based on at least one of the following: The number of valid addresses in the access address carried by any fourth access request; The number of clock cycles that any fourth access request has been waiting for.

10. An access request processing method, characterized in that, The method is applied to an access request processing apparatus, the access request processing apparatus including a merging unit and a sending unit; the method includes: The merging unit merges at least one set of first access requests that meet the merging conditions to obtain at least one second access request. Each set of first access requests that meets the merging conditions carries a discrete access address and the storage space corresponding to the discrete access address is located in the same candidate storage space. The candidate storage space is a storage space in the memory that supports access through a single request. The at least one second access request is sent to the memory via the sending unit.

11. The method according to claim 10, characterized in that, The access request processing apparatus further includes a comparison unit; the method further includes: The comparison unit compares the access addresses carried by at least two first access requests to obtain a comparison result. The comparison result is used to indicate whether the storage spaces corresponding to the access addresses carried by the at least two first access requests are located in the same candidate storage space. The access addresses carried by the at least two first access requests are discrete. The process of merging at least one set of first access requests that meet the merging conditions through the merging unit to obtain at least one second access request includes: The merging unit merges at least one set of first access requests that meet the merging conditions from the at least two first access requests based on the comparison results to obtain the at least one second access request.

12. The method according to claim 10, characterized in that, The merging unit includes at least two merging sub-units corresponding to the first access requests respectively, and the at least one second access request includes the access requests output by each merging sub-unit. The access addresses carried by the at least two first access requests are discrete. The process of merging at least one set of first access requests that meet the merging conditions through the merging unit to obtain at least one second access request includes: If any first access request is located in any group of first access requests and meets the merging requirements, the merging subunit corresponding to any first access request outputs the access request obtained by merging the group of first access requests; if any first access request is located in any group of first access requests and does not meet the merging requirements, no access request is output; if any first access request is not located in the at least one group of first access requests, the first access request is output.

13. The method according to claim 12, characterized in that, The at least two first access requests have different numbers; any first access request satisfying the merging requirement includes the number of any first access request being the maximum value among the numbers of any group of first access requests, or the number of any first access request satisfying the merging requirement includes the number of any first access request being the minimum value among the numbers of any group of first access requests.

14. The method according to any one of claims 10-13, characterized in that, The first storage space corresponds to the access address carried by the access request obtained by merging any group of first access requests. The first storage space is the smallest storage space that contains the storage space corresponding to the access address carried by any group of first access requests.

15. The method according to any one of claims 10-13, characterized in that, The sending unit includes an allocation subunit, a selection subunit, and a sending subunit; sending the at least one second access request to the memory through the sending unit includes: The allocation subunit allocates the at least one second access request to the waiting queue, resulting in an updated waiting queue; The selection subunit selects access requests that meet the sending conditions from the updated waiting queue. If any of the at least one second access requests matches the access request that satisfies the sending conditions, the sending subunit sends the second access request to the memory.

16. The method according to claim 15, characterized in that, The step of allocating the at least one second access request to the waiting queue through the allocation subunit to obtain the updated waiting queue includes: If any second access request in at least one second access request and any third access request in the waiting queue satisfy the merging condition, the allocation subunit merges the second access request into the third access request. If none of the second access requests and all the third access requests in the waiting queue meet the merging condition, and the number of third access requests in the waiting queue is less than the number threshold, then the second access request is added to the waiting queue as a new access request. If neither the second access request nor any of the third access requests in the waiting queue meets the merging condition, and the number of third access requests in the waiting queue is not less than the number threshold, then the second access request is allocated to the waiting queue after any third access request in the waiting queue is sent to the memory.

17. The method according to claim 15 or 16, characterized in that, Any fourth access request in the updated waiting queue has a priority index; the access request that meets the sending conditions is the fourth access request with the highest priority index in the updated waiting queue.

18. The method according to claim 17, characterized in that, The priority metric for any fourth access request in the updated waiting queue is determined based on at least one of the following: The number of valid addresses in the access address carried by any fourth access request; The number of clock cycles that any fourth access request has been waiting for.

19. A processor, characterized in that, The processor includes the access request processing apparatus as described in any one of claims 1-9.

20. A computer device, characterized in that, The computer device includes a processor and a memory, wherein the processor is the processor of claim 19.

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