Circuit and method for weight mapping for in-memory calculations

Abstract

The invention relates to a circuit and a method for weight mapping in memory body calculation. The circuit for weight mapping in memory body calculation comprises a memory body unit; first address lines, each of which is coupled to a corresponding one of the memory cells; and second address lines, each of which is coupled to a group of cells in the memory cells. One or more of the memory cells are configured to be accessed to one or more weight values when one or more of the first address lines and one or more of the second address lines corresponding to the one or more of the memory cells are asserted. The one or more cells accessed at a first time correspond to a first weight matrix, and the one or more cells accessed at a second time correspond to a second weight matrix, the second weight matrix being a transpose matrix of the first weight matrix.

Description

Technical Field

[0001] This disclosure relates to circuits and methods for weight mapping computation within a memory, and particularly to circuits and methods for weight mapping computation within a memory having logic gates. Background Technology

[0002] Computer artificial intelligence (AI) is built upon machine learning, such as the use of deep learning techniques. Machine learning utilizes computational systems organized as neural networks to calculate the statistical probability of a match between input data and previously calculated data. A neural network refers to multiple interconnected processing nodes that enable data analysis to compare inputs with “training” data. Training data refers to the computational analysis of the properties of known data to develop a model for comparing input data. An example of AI and data training applications can be found in object recognition, where a system analyzes the properties of many (e.g., thousands or more) images to determine patterns that can be used to perform statistical analysis to identify input objects. Summary of the Invention

[0003] In some embodiments, a circuit for calculating a weight mapping within a memory cell is provided, comprising: a plurality of memory cells; a plurality of first address lines, each of the first address lines being coupled to a corresponding memory cell among the memory cells; and a plurality of second address lines, each of the second address lines being coupled to a set of cells among the memory cells, wherein when one or more of the first address lines corresponding to one or more cells among the memory cells and one or more of the second address lines are asserted, one or more cells among the memory cells are used to access one or more weight values, and wherein one or more cells accessed at a first time correspond to a first weight matrix, and one or more cells accessed at a second time correspond to a second weight matrix, the second weight matrix being a transpose of the first weight matrix.

[0004] In some embodiments, a circuit for calculating a weight mapping within a memory is provided, comprising: a memory array; and a control circuit operatively coupled to the memory array, the control circuit being configured to: provide an enable signal and an address signal; and access at least one memory cell of the memory array based on the enable signal and the address signal, wherein the control circuit is configured to provide a first address signal at a first time to access the memory array based on a first weight matrix, and to provide a second address signal at a second time to access the memory array based on a second weight matrix, the second weight matrix being a transpose of the first weight matrix.

[0005] In some embodiments, a method for weight mapping computation within a memory is provided, comprising the following steps: providing a first address signal and a first enable signal at a first time; accessing a first group of memory cells in a memory array based on the first address signal and the first enable signal, wherein the first group of memory cells corresponds to a first weight matrix; providing a second address signal and a second enable signal at a second time; and accessing a second group of memory cells in the memory array based on the second address signal and the second enable signal, wherein the second group of memory cells corresponds to a second weight matrix, and the second weight matrix is ​​a transpose of the first weight matrix. Attached Figure Description

[0006] The various aspects of the disclosed embodiments can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 and Figure 2 A schematic diagram illustrating example circuits according to some embodiments of this disclosure;

[0008] Figure 3 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure;

[0009] Figures 4 to 7 A schematic diagram illustrating example circuits according to some embodiments of this disclosure;

[0010] Figures 8 to 10 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure;

[0011] Figure 11 A flowchart illustrating an example method of operating circuitry according to various embodiments.

[0012] [Symbol Explanation]

[0013] 100: Data Calculation Circuit

[0014] 102: Memory Circuit

[0015] 103: Storage element

[0016] 104: Input Circuit

[0017] 120, 220: Control circuit

[0018] 202: Memory Circuit

[0019] 203: Memory Unit

[0020] 250: First address line

[0021] 260: Second address line

[0022] 270: Logic Gates

[0023] 381, 382, ​​382T, 383, 383T, 581, 581T, 582: Matrix

[0024] 451A, 451B, 451C, 451D, 551A, 551B, 551C, 551D: Address signals

[0025] 461A, 461B, 461C, 461D, 561A, 561B, 561C, 561D: Enable signals

[0026] 551A: First Address Signal

[0027] 551B: Second Address Signal

[0028] 551C: Third Address Signal

[0029] 551D: Fourth Address Signal

[0030] 661A: First Enable Signal

[0031] 661B: Second Enable Signal

[0032] 661C: Third Enable Signal

[0033] 661D: Fourth Enabling Signal

[0034] 671A, 671B, 671C, 671D, 771A, 771B, 771C, 771D, 971, 1071

[0035] :enter

[0036] 690A, 690B, 690C, 690D, 790A, 790B, 790C, 790D, pMAC0, pMAC1, pMAC2, pMAC3: Output

[0037] 981, 990: Weight matrices

[0038] 1081: Transposed weight matrix

[0039] 1090: Transformation Matrix

[0040] 1100: Method

[0041] 1110, 1120, 1130, 1140: Operation

[0042] InDE: Input Data Element

[0043] WtDE: Weighted Data Element

[0044] MUL: Multiplication

[0045] W: Weight

[0046] WASEL0[3:0]-WASEL3[3:0]: Address lines

[0047] ap: value

[0048] WL: Character Line

[0049] RBL: Bitline

[0050] XIN: Input

[0051] XIN0: Input

[0052] XIN1: Input

[0053] XIN2: Input

[0054] XIN3: Input Detailed Implementation

[0055] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the embodiments disclosed herein. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0056] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0057] Neural networks compute “weights” to perform computations on new data (input data “characters”). Neural networks use multiple layers of computational nodes, where deeper layers perform computations based on the results of computations performed by higher layers. Machine learning currently relies on the calculation of dot products and absolute differences of vectors, typically computed using a multiply-accumulate (MAC) operation on the parameters, input data, and weights. The computations of large and deep neural networks often involve so many data elements that storing them in the processor cache is impractical. Therefore, these data elements are typically stored in memory.

[0058] Machine learning is typically computationally intensive, requiring the computation and comparison of many different data elements. The computation within the processor is orders of magnitude faster than the transfer of data elements between the processor and main memory resources. Due to the memory size required to store data elements, placing all data elements in a cache closer to the processor is very expensive for most practical systems. Therefore, the transfer of data elements becomes a major bottleneck in AI computation. As datasets increase, the time and power / energy spent by a computing system moving data elements can ultimately be multiples of the time and power spent on actually performing computations.

[0059] In this regard, computing-in-memory (CIM) circuits have been proposed to perform such MAC operations. CIM circuits perform data processing in situ within a suitable memory circuit. CIM circuits suppress the latency of data / program retrieval and uploading output results to the corresponding memory (e.g., memory arrays), thus overcoming the memory (or van Neumann) bottleneck of traditional computers. Another key advantage of CIM circuits is high computational parallelism, thanks to the specific architecture of the memory array, where computation can be performed simultaneously along several current paths. CIM circuits also benefit from the high density of multiple memory arrays with computing devices, which typically possess excellent scalability and 3D integration capabilities. As a non-limiting example, CIM circuits for various machine learning applications can perform MAC operations locally within memory (i.e., without sending data elements to the host processor), enabling higher-yield dot products of neuron activation and weight matrices, while still providing higher performance and lower energy consumption compared to host processor computation.

[0060] In machine learning applications, CIM circuits are often used to perform MAC operations on a large number of data elements (e.g., input character vectors and weight matrices) with rearranged weighted feature maps to process dot product multiplication. This can require additional loops and / or buffering, and therefore necessitates rearranging the weight matrix. Consequently, such methods can lead to additional costs.

[0061] This disclosure provides various embodiments of a CIM circuit that can perform MAC operations using a rearranged weighted feature map without performing additional loops and / or buffering. According to this disclosure, the CIM circuit can provide an enable signal and an address signal, and access a memory array based on the enable signal and the address signal. The CIM circuit can provide a first address signal at a first time to access the memory array based on a first weight matrix, and can provide a second address signal at a second time to access the memory array based on a second weight matrix, the second weight matrix being a transpose of the first weight matrix. By flexibly accessing the memory array based on the weight matrix and the transpose of the weight matrix, the CIM circuit disclosed herein can perform MAC operations using a rearranged weighted feature map without performing additional loops and / or buffering (e.g., within a single macro).

[0062] Figure 1 Schematic diagrams illustrating example circuits according to some embodiments of this disclosure are provided. More specifically, Figure 1 The diagram shows an example data calculation circuit 100 according to some embodiments of the present disclosure. Figure 1 In the illustrated embodiment depicted, the data computation circuit 100 (also referred to as (e.g., CIM) circuit 100 or memory circuit 100) includes various elements commonly used to perform in-memory computations (e.g., multiply-accumulate (MAC) operations) on the input character vector and the weight matrix. The input character vector may contain multiple input data elements InDE, and the weight matrix may contain multiple weight data elements WtDE.

[0063] As shown in the figure, circuit 100 includes memory circuit 102, input circuit 104, and control circuit 120. It should be understood that... Figure 1 The block diagram of the circuit depicted is simplified, and therefore, circuit 100 may include any of a variety of other elements while remaining within the scope of the embodiments disclosed herein.

[0064] The memory circuit 102 may include one or more memory arrays and one or more corresponding circuits. Each memory array is a storage device containing multiple storage elements (sometimes referred to as "memory array," "memory cell," etc.) 103. Each of the storage elements 103 includes electrical, electromechanical, electromagnetic, or other means for storing one or more data elements, and each data element includes one or more data bits represented by a logic state. In some embodiments, the logic state corresponds to a voltage level of charge stored in some or all of the storage element 103. In some embodiments, the logic state corresponds to some or all of the physical properties of the storage element 103, such as resistance or magnetic orientation.

[0065] In some embodiments, the storage element 103 includes one or more static random-access memory (SRAM) cells. In various embodiments, the SRAM cell includes multiple transistors, such as a five-transistor (5T) SRAM cell, a six-transistor (6T) SRAM cell, an eight-transistor (8T) SRAM cell, a nine-transistor (9T) SRAM cell, etc. In some embodiments, the SRAM cell includes a multi-track SRAM cell. In some embodiments, the SRAM cell has a length at least twice its width.

[0066] In some embodiments, the storage element 103 includes one or more dynamic random-access memory (DRAM) cells, resistive random-access memory (RRAM) cells, magnetoresistive random-access memory (MRAM) cells, ferroelectric random-access memory (FeRAM) cells, NOR flash memory cells, NAND flash memory cells, conductive-bridging random-access memory (CBRAM) cells, data registers, non-volatile memory (NVM) cells, 3D NVM cells, or other memory cell types capable of storing bit data.

[0067] In addition to the memory array, memory circuitry 102 may include multiple circuits for accessing or otherwise controlling the memory array. For example, memory circuitry 102 may include multiple (e.g., word line) drivers operatively coupled to the memory array. Drivers may apply signals (e.g., voltages) to corresponding storage elements 103 to allow those storage elements 103 to be accessed (e.g., programmed, read, etc.). As another example, memory circuitry 102 may include multiple programming and / or reading circuits operatively coupled to the memory array.

[0068] Each memory array of memory circuit 102 is used to store multiple weighted data elements WtDE. In some embodiments, program circuitry can write the weighted data elements WtDE into corresponding storage elements 103 of the memory array, and read circuitry can read the bits written into the storage elements 103 to verify or otherwise test whether the written weighted data elements WtDE are correct. The driver of memory circuit 102 may include or be operatively coupled to multiple input activation latches for receiving and temporarily storing input data elements InDE. In some other embodiments, such input activation latches may be part of input circuitry 104, which may further include multiple buffers for temporarily storing weighted data elements WtDE retrieved from the memory array of memory circuitry 102. Thus, input circuitry 104 can receive input data elements InDE and weighted data elements WtDE.

[0069] In various embodiments of this disclosure, circuit 100 (e.g., control circuit 120) can be used to perform MAC operations based on an input character vector (including, for example, input data element InDE) and a weight matrix (including, for example, weight data element WtDE).

[0070] Figure 2 The illustration shows a schematic diagram of an example memory circuit 202 according to some embodiments of the present disclosure. More specifically, memory circuit 202 is an example of memory circuit 102. Memory circuit 202 may substantially resemble and / or incorporate features of memory circuit 102. Memory circuit 202 may include a plurality of memory cells (sometimes referred to as a "memory array") 203, and memory cells 203 may substantially resemble and / or incorporate features of storage element 103. Figure 2 The illustration shows a non-limiting example of memory circuitry 202. In some embodiments, memory circuitry 202 may include more than Figure 2 As shown or about Figure 2 The more, fewer, or different elements described.

[0071] Memory circuitry 202 may include a plurality of first address lines 250. Each of the plurality of first address lines 250 may be coupled to a corresponding memory cell in a plurality of memory cells 203. In some embodiments, the plurality of address lines 250 may correspond to a plurality of memory cells in a plurality of memory cells 203. Each of the plurality of first address lines 250 may be configured to receive an address signal indicating a corresponding memory cell in a plurality of memory cells 203. In some embodiments, each of the plurality of first address lines 250 may be configured to assert access to a corresponding memory cell in a plurality of memory cells 203 using the address signal.

[0072] Memory circuitry 202 may include a plurality of second address lines 260. Each of the plurality of second address lines 260 may be coupled to a corresponding set of memory cells in a plurality of memory cells 203 (e.g., memory cells in a column of the plurality of memory cells 203). In some embodiments, the plurality of address lines 260 may correspond to a plurality of rows or columns in the plurality of memory cells 203. Each of the plurality of second address lines 260 may be configured to receive an enable signal (e.g., write enable, read enable, etc.) corresponding to a corresponding set of memory cells in the plurality of memory cells 203. In some embodiments, each of the plurality of second address lines 260 may be configured to assert access to a corresponding set of memory cells in the plurality of memory cells 203 using an enable signal.

[0073] Memory circuitry 202 may include control circuitry 220 operatively coupled to a plurality of memory cells 203. In some embodiments, control circuitry 220 may substantially resemble and / or incorporate features of control circuitry 120. In some embodiments, control circuitry 220 may include or be included within control circuitry 120. In some embodiments, control circuitry 220 may be operatively coupled to control circuitry 120.

[0074] In some embodiments, the control circuit 220 may be used to provide an enable signal and an address signal. For example, the control circuit 220 may provide an enable signal to a plurality of memory cells 203 via a second address line 260. The control circuit 220 may provide an address signal to a plurality of memory cells 203 via a first address line 250. In some embodiments, the control circuit 220 may access at least one of the plurality of memory cells 203 based on the enable signal and the address signal.

[0075] In some embodiments, the control circuit 220 can be configured to provide a first address signal at a first time to access a plurality of memory cells 203 based on a first weight matrix, and to provide a second address signal at a second time to access a plurality of memory cells 203 based on a second weight matrix. In some embodiments, the second weight matrix may be the transpose of the first weight matrix.

[0076] In some embodiments, when one or more of the plurality of first address lines 250 and one or more of the plurality of second address lines 260 corresponding to one or more of the plurality of memory cells 203 are asserted, one or more memory cells 203 can be accessed (e.g., written, read, etc.) for one or more weight values. In some embodiments, one or more cells accessed at a first time may correspond to a first weight matrix, and one or more cells accessed at a second time may correspond to a second weight matrix. In some embodiments, the second weight matrix may be a transpose of the first weight matrix.

[0077] In some embodiments, memory circuitry 202 may include a plurality of logic gates 270. For example, the plurality of logic gates 270 may be a plurality of AND gates. The plurality of logic gates 270 are operatively coupled between a corresponding first address line of a plurality of first address lines 250 and a corresponding second address line of a plurality of second address lines 260. In some embodiments, each of the plurality of logic gates 270 (e.g., AND gates) may include a first input for receiving an enable signal (e.g., via a corresponding first address line of the plurality of first address lines 250) and a second input for receiving an address signal (e.g., via a corresponding second address line of the plurality of second address lines 260). In some embodiments, each of the plurality of logic gates 270 may include an output operatively coupled to a corresponding memory cell of the plurality of memory cells 203. The plurality of logic gates 270 may provide logical operations (e.g., AND operations) via their outputs.

[0078] In some embodiments, memory circuitry 202 may include a multiplexer operatively coupled between a plurality of memory cells 203 and control circuitry 220. In some embodiments, a plurality of first address lines 250, a plurality of second address lines 260, and a plurality of logic gates 270 may define the multiplexer. In some embodiments, the multiplexer may be or include any logic elements and / or control circuitry for accessing the plurality of memory cells 203 based on a first weight matrix and a second weight matrix that is the transpose of the first weight matrix.

[0079] Figure 3 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure. Figure 3 The weight mapping process shown can be associated with memory circuit 102, memory circuit 202, etc. Figure 3 The image shows a non-restricted example of a weight mapping process.

[0080] In some embodiments, matrix 381 may correspond to (e.g., Figure 1 The input data element InDe. In some embodiments, matrix 382 may correspond to (e.g., Figure 1 The weighted data element WtDe is given, and matrix 382T may correspond to the transpose of matrix 382. Matrix 383 may correspond to the matrix generated by the first MAC operation of matrices 381 and 382. Matrix 383T may correspond to the matrix generated by the second MAC operation of matrices 381 and 382T. The memory circuitry (e.g., memory circuitry 202) disclosed herein may be used to perform the first MAC operation (e.g., based on the untransposed weighted matrix) and the second MAC operation (e.g., based on the transposed weighted matrix) without performing additional loops and / or buffering (e.g., within a single macro).

[0081] Figure 4Schematic diagrams illustrating example memory circuits according to some embodiments of this disclosure are provided. More specifically, Figure 4 The image shows the memory circuit 202 (control circuit 220 not shown) during the first moment of an instance write operation associated with the weight matrix 581. Figure 4 The write operation shown is a non-limiting example. In some embodiments, memory circuitry 202 may be compared to... Figure 4 As shown or about Figure 4 The described more, fewer, or different operations are used to operate.

[0082] In some embodiments, control circuitry 220 may be used to provide enable signal 461A and address signal 451A (e.g., WASEL0[3:0]) during a first cycle in a first time period. During the first cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on enable signal 461A and address signal 451A. For example, as shown, a first subset of address lines corresponding to a first row of the plurality of memory cells 203 may be asserted to provide address signal 451A, while enable signal 461A (e.g., “a”, “b”, “c”, and “d”) is asserted. This allows writing to memory cells in the first row of the plurality of memory cells 203. For example, in the first subset of address lines, address signal 451A includes a first address line signal coupled to the first memory cell via a corresponding logic gate among a plurality of logic gates 270. Enable signal 461A includes a first enable line signal (e.g., for "a" in the first column), which is coupled to a first memory cell via a corresponding logic gate among a plurality of logic gates 270. Based on the logical operation of the first address line signal and the first enable line signal, a logical value (e.g., "a") can be written to the first memory cell. Similarly, logical values ​​(e.g., "b", "c", and "d") can be written to other memory cells in the first row.

[0083] In some embodiments, control circuitry 220 may be used to provide enable signal 461B and address signal 451B (e.g., WASEL1[3:0]) during a second cycle in a first time period. During the second cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on enable signal 461B and address signal 451B. For example, as shown, a second subset of address lines corresponding to a second row of the plurality of memory cells 203 may be asserted to provide address signal 451B, while enable signal 461B (e.g., “e”, “f”, “g”, and “h”) is asserted. This allows writing to memory cells in the second row of the plurality of memory cells 203. For example, in the second subset of address lines, address signal 451B includes a second address line signal coupled to a second memory cell via a corresponding logic gate among a plurality of logic gates 270. Enable signal 461B includes a second enable line signal (e.g., for "e" in the first column), which is coupled to a second memory cell via a corresponding logic gate among a plurality of logic gates 270. Based on logical operations of the second address line signal and the second enable line signal, a logical value (e.g., "e") can be written to the second memory cell. Similarly, logical values ​​(e.g., "f", "g", and "h") can be written to other memory cells in the second row.

[0084] In some embodiments, control circuitry 220 may be used to provide enable signal 461C and address signal 451C (e.g., WASEL2[3:0]) during a third cycle in a first time period. During the third cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on enable signal 461C and address signal 451C. For example, as shown, a third subset of address lines corresponding to the third row of the plurality of memory cells 203 may be asserted to provide address signal 451C, while enable signal 461C (e.g., “i”, “j”, “k”, and “l”) is asserted. This allows writing to memory cells in the third row of the plurality of memory cells 203. For example, in the third subset of address lines, address signal 451C includes a third address line signal coupled to the third memory cell via a corresponding logic gate among a plurality of logic gates 270. Enable signal 461C includes a third enable line signal (e.g., for "i" in the first column), which is coupled to a third memory cell via corresponding logic gates among a plurality of logic gates 270. Based on logical operations of the third address line signal and the third enable line signal, a logical value (e.g., "i") can be written to the third memory cell. Similarly, logical values ​​(e.g., "j", "k", and "l") can be written to other memory cells in the third row.

[0085] In some embodiments, control circuitry 220 may be used to provide enable signal 461D and address signal 451D (e.g., WASEL3[3:0]) during a fourth cycle in a first time period. During the fourth cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on enable signal 461D and address signal 451D. For example, as shown, a fourth subset of address lines corresponding to the fourth row of the plurality of memory cells 203 may be asserted to provide address signal 451D, while enable signal 461D (e.g., “m”, “n”, “o”, and “p”) is asserted. This may be written to memory cells in the fourth row of the plurality of memory cells 203. Thus, in some embodiments, control circuitry 220 may access the plurality of memory cells 203 to write to weight matrix 581. For example, in the fourth subset of address lines, address signal 451D includes a fourth address line signal coupled to the fourth memory cell via a corresponding logic gate among a plurality of logic gates 270. Enable signal 461D includes a fourth enable line signal (e.g., for "m" in the first column), which is coupled to a fourth memory cell via corresponding logic gates in a plurality of logic gates 270. Based on logical operations of the fourth address line signal and the fourth enable line signal, a logical value (e.g., "m") can be written to the fourth memory cell. Similarly, logical values ​​(e.g., "n", "o", and "p") can be written to other memory cells in the fourth row.

[0086] Figure 5 Schematic diagrams illustrating example memory circuits according to some embodiments of this disclosure are provided. More specifically, Figure 5 The memory circuit 202 (control circuit 220 not shown) is shown at a second time during an instance write operation associated with the weight matrix 581T. Figure 5 The write operation shown is a non-limiting example. In some embodiments, memory circuitry 202 may be compared to... Figure 5 As shown or about Figure 5 The described operations may be more, fewer, or different. In some embodiments, memory circuitry 202 may be used to access a plurality of memory cells 203 based on shift matrix 582, wherein one or more rows in weight matrix 581T are shifted.

[0087] In some embodiments, control circuitry 220 may be used to provide address signals. The address signals include a first address signal 551A during a first cycle, a second address signal 551B during a second cycle, a third address signal 551C during a third cycle, and a fourth address signal 551D during a fourth cycle. The first address signal 551A includes a first address line signal (e.g., via a first row assertion in a first subset of the plurality of first address lines 250). The first address signal 551A includes a second address line signal (e.g., via a second row assertion in a second subset of the plurality of first address lines 250). The first address signal 551A includes a third address line signal (e.g., via a third row assertion in a third subset of the plurality of first address lines 250). The first address signal 551A includes a fourth address line signal (e.g., via a fourth row assertion in a fourth subset of the plurality of first address lines 250). Similarly, for each cycle, each address signal may include address line signals that are different for different subsets of the plurality of first address lines 250.

[0088] In some embodiments, control circuitry 220 may be used to provide an enable signal 561A and an address signal 551A during a first cycle of a second time period. During the first cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on the enable signal 561A and the address signal 551A. For example, as shown, different address line signals for different subsets of a plurality of first address lines 250 may be asserted, while the enable signal 561A (e.g., “a”, “b”, “c”, and “d”) is asserted. This allows writing to be performed on the memory cell accessed by the enable signal 561A and the address signal 551A. For example, a logical value (e.g., "a") can be written to the first column of memory cells in the first row of the plurality of memory cells 203, a logical value (e.g., "b") can be written to the second column of memory cells in the second row of the plurality of memory cells 203, a logical value (e.g., "c") can be written to the third column of memory cells in the third row of the plurality of memory cells 203, and a logical value (e.g., "d") can be written to the fourth column of memory cells in the fourth row of the plurality of memory cells 203.

[0089] In some embodiments, control circuitry 220 may be used to provide an enable signal 561B and an address signal 551B during a second cycle of a second time period. During the second cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on the enable signal 561B and the address signal 551B. For example, as shown, different address line signals for different subsets of a plurality of first address lines 250 may be asserted, while the enable signal 561B (e.g., “h”, “e”, “f”, and “g”) is asserted. This allows writing to be performed on the memory cell accessed by the enable signal 561B and the address signal 551B. For example, a logical value (e.g., "e") can be written to the second column of the first row of the plurality of memory cells 203, a logical value (e.g., "e") can be written to the third column of the second row of the plurality of memory cells 203, a logical value (e.g., "g") can be written to the fourth column of the third row of the plurality of memory cells 203, and a logical value (e.g., "h") can be written to the first column of the fourth row of the plurality of memory cells 203.

[0090] In some embodiments, control circuitry 220 may be used to provide an enable signal 561C and an address signal 551C during a third cycle of a second time period. During the third cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on the enable signal 561C and the address signal 551C. For example, as shown, different address line signals for different subsets of a plurality of first address lines 250 may be asserted, while the enable signal 561C (e.g., "k", "l", "i", and "j") is asserted. This allows writing to be performed on the memory cell accessed by the enable signal 561C and the address signal 551C. For example, a logical value (e.g., "i") can be written to the third column of the first row of the plurality of memory cells 203, a logical value (e.g., "j") can be written to the fourth column of the second row of the plurality of memory cells 203, a logical value (e.g., "k") can be written to the first column of the third row of the plurality of memory cells 203, and a logical value (e.g., "l") can be written to the second column of the fourth row of the plurality of memory cells 203.

[0091] In some embodiments, control circuitry 220 may be used to provide enable signal 561D and address signal 551D during a fourth cycle of a second time period. During a third cycle, control circuitry 220 may be used to access (e.g., write) at least one memory cell among a plurality of memory cells 203 based on enable signal 561D and address signal 551D. For example, as shown, different address line signals for different subsets of a plurality of first address lines 250 may be asserted, while enable signal 561D (e.g., "n", "o", "p", and "m") is asserted. This allows writing to be performed on the memory cell accessed by enable signal 561D and address signal 551D. For example, a logical value (e.g., "m") can be written to the fourth column of the first row of the plurality of memory cells 203, a logical value (e.g., "n") can be written to the first column of the second row of the plurality of memory cells 203, a logical value (e.g., "o") can be written to the second column of the third row of the plurality of memory cells 203, and a logical value (e.g., "p") can be written to the third column of the fourth row of the plurality of memory cells 203.

[0092] Such as about Figure 4 and Figure 5 The discussion and Figure 4 and Figure 5 As shown, control circuitry 220 can assert different address lines in various ways. In some embodiments, control circuitry 220 can be used to alternately assert different rows in a plurality of memory cells 203. In some embodiments, when control circuitry 220 asserts one row in a plurality of memory cells 203, control circuitry 220 can be used to access the entire memory cell coupled to that row at a time, alternating between different rows. In some embodiments, control circuitry 220 can be used to alternately assert different first address lines in a plurality of first address lines 250, alternating between multiple subsets or alternating within subsets. In some embodiments, control circuitry 220 can be used to assert a complete subset of a plurality of subsets in a plurality of memory cells 203, alternating between multiple subsets.

[0093] Figure 6 Schematic diagrams illustrating example memory circuits according to some embodiments of this disclosure are provided. More specifically, Figure 6 The image shows the memory circuit 202 (control circuit 220 not shown) during the instance read operation associated with the weight matrix 581 at the first moment. Figure 6 The read operation shown is a non-limiting example. In some embodiments, memory circuitry 202 may be compared to Figure 6 As shown or about Figure 6 The described more, fewer, or different operations are used to operate.

[0094] During a read operation, control circuitry 220 can be used to access (e.g., read) a plurality of memory cells 203. In some embodiments, control circuitry 220 can be used to read a plurality of memory cells 203 that have been written based on weight matrix 581. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to perform a MAC operation based on the read operation.

[0095] During the first cycle, control circuit 220 (and / or control circuit 120) can be used to provide input (e.g., input data element InDE) 671A, while simultaneously providing a first address signal and a first enable signal 661A. Since the first enable signal 661A asserts a read enable signal on the first column of the plurality of memory cells 203, the first column of the plurality of memory cells 203 (e.g., "a", "e", "i", and "m") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform a MAC operation based on the first column of the plurality of memory cells 203 (e.g., "a", "e", "i", and "m") and input 671A. Control circuit 220 (and / or control circuit 120) can be used to provide an output (e.g., 1*a+2*e+3*i+4*m) 690A based on the MAC operation.

[0096] During the second cycle, control circuit 220 (and / or control circuit 120) can be used to provide input (e.g., input data element InDE) 671B, while simultaneously providing a second address signal and a second enable signal 661B. In some embodiments, the second address signal may be the same as the first address signal provided during the first cycle. Since the second enable signal 661B asserts a read enable signal on the second column of the plurality of memory cells 203, the second column of the plurality of memory cells 203 (e.g., "b", "f", "j", and "n") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform a MAC operation based on the second column of the plurality of memory cells 203 (e.g., "b", "f", "j", and "n") and input 671B. Control circuit 220 (and / or control circuit 120) can be used to provide an output (e.g., 1*b+2*f+3*j+4*n) 690B based on the MAC operation.

[0097] During the third cycle, control circuit 220 (and / or control circuit 120) can be used to provide an input (e.g., an input data element InDE) 671C, while simultaneously providing a third address signal and a third enable signal 661C. In some embodiments, the third address signal may be the same as the first address signal provided during the first cycle. Since the third enable signal 661C asserts a read enable signal on the third column of the plurality of memory cells 203, the third column of the plurality of memory cells 203 (e.g., "c", "g", "k", and "o") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform a MAC operation based on the third column of the plurality of memory cells 203 (e.g., "c", "g", "k", and "o") and the input 671C. Control circuit 220 (and / or control circuit 120) can be used to provide an output (e.g., 1*c+2*g+3*k+4*o) 690C based on the MAC operation.

[0098] During the fourth cycle, control circuitry 220 (and / or control circuitry 120) can be used to provide an input (e.g., an input data element InDE) 671D, along with a fourth address signal and a fourth enable signal 661D. In some embodiments, the fourth address signal may be the same as the first address signal provided during the first cycle. Since the fourth enable signal 661D asserts a read enable signal on the fourth column of the plurality of memory cells 203, the fourth column of the plurality of memory cells 203 (e.g., "d", "h", "l", and "p") can be read. Control circuitry 220 (and / or control circuitry 120) can be used to perform a MAC operation based on the fourth column of the plurality of memory cells 203 (e.g., "d", "h", "l", and "p") and the input 671D. Control circuitry 220 (and / or control circuitry 120) can be used to provide an output (e.g., 1*d+2*h+3*l+4*p) 690D based on the MAC operation.

[0099] Figure 7 Schematic diagrams illustrating example memory circuits according to some embodiments of this disclosure are provided. More specifically, Figure 7 The memory circuit 202 (control circuit 220 not shown) is shown at a second time during an instance read operation associated with the weight matrix 581T. Figure 7 The read operation shown is a non-limiting example. In some embodiments, memory circuitry 202 may be compared to Figure 7 As shown or about Figure 7 The described operations may be more, fewer, or different. In some embodiments, memory circuitry 202 may be used to access a plurality of memory cells 203 based on shift matrix 582, wherein one or more rows in weight matrix 581T are shifted.

[0100] During a read operation, control circuitry 220 can be used to access (e.g., read) a plurality of memory cells 203. In some embodiments, control circuitry 220 can be used to read a plurality of memory cells 203 that have been written based on weight matrix 581T (or weight matrix 582). In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to perform a MAC operation based on the read operation.

[0101] During the first cycle, control circuit 220 (and / or control circuit 120) can be used to provide an input (e.g., an input data element InDE) 771A. Control circuit 220 (and / or control circuit 120) can be used to provide a first address signal and a first enable signal (e.g., as per the context of...). Figure 5 (As discussed). During the first cycle, memory cells in the first column of the first row of the plurality of memory cells 203 (e.g., "a"), memory cells in the second column of the second row of the plurality of memory cells 203 (e.g., "b"), memory cells in the third column of the third row of the plurality of memory cells 203 (e.g., "c"), and memory cells in the fourth column of the fourth row of the plurality of memory cells 203 (e.g., "a") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform MAC operations based on memory cells (e.g., "a", "b", "c", and "d") read based on a first address signal and a first enable signal and input 771A. Control circuit 220 (and / or control circuit 120) can be used to provide outputs (e.g., 1*a+2*b+3*c+4*d) 790A based on MAC operations.

[0102] During the second cycle, control circuit 220 (and / or control circuit 120) can be used to provide an input (e.g., an input data element InDE) 771B. Control circuit 220 (and / or control circuit 120) can be used to provide a second address signal and a second enable signal (e.g., as per the context of...). Figure 5 (As discussed). During the second cycle, memory cells in the second column of the first row of the plurality of memory cells 203 (e.g., “e”), memory cells in the third column of the second row of the plurality of memory cells 203 (e.g., “f”), memory cells in the fourth column of the third row of the plurality of memory cells 203 (e.g., “g”), and memory cells in the first column of the fourth row of the plurality of memory cells 203 (e.g., “h”) can be read. Control circuit 220 (and / or control circuit 120) can be used to perform MAC operations based on the memory cells (e.g., “e”, “f”, “g”, and “h”) read based on the second address signal and the second enable signal and input 771B. Control circuit 220 (and / or control circuit 120) can be used to provide outputs (e.g., 1*e+2*f+3*g+4*h) 790B based on the MAC operation.

[0103] During the third cycle, control circuit 220 (and / or control circuit 120) can be used to provide an input (e.g., an input data element InDE) 771C. Control circuit 220 (and / or control circuit 120) can be used to provide a third address signal and a third enable signal (e.g., as per the context of...). Figure 5 (As discussed). During the third cycle, memory cells in the third column of the first row of multiple memory cells 203 (e.g., "i"), memory cells in the fourth column of the second row of multiple memory cells 203 (e.g., "j"), memory cells in the first column of the third row of multiple memory cells 203 (e.g., "k"), and memory cells in the second column of the fourth row of multiple memory cells 203 (e.g., "l") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform MAC operations based on the memory cells (e.g., "i", "j", "k", and "l") read based on the third address signal and the third enable signal and input 771C. Control circuit 220 (and / or control circuit 120) can be used to provide outputs (e.g., 1*i+2*j+3*k+4*l) 790C based on the MAC operation.

[0104] During the fourth cycle, control circuit 220 (and / or control circuit 120) can be used to provide an input (e.g., an input data element InDE) 771D. Control circuit 220 (and / or control circuit 120) can be used to provide a fourth address signal and a fourth enable signal (e.g., as per the context of...). Figure 5 (As discussed). During the fourth cycle, memory cells in the fourth column of the first row of multiple memory cells 203 (e.g., "m"), memory cells in the first column of the second row of multiple memory cells 203 (e.g., "n"), memory cells in the second column of the third row of multiple memory cells 203 (e.g., "o"), and memory cells in the third column of the fourth row of multiple memory cells 203 (e.g., "p") can be read. Control circuit 220 (and / or control circuit 120) can be used to perform MAC operations based on the memory cells (e.g., "m", "n", "o", and "p") read based on the fourth address signal and the fourth enable signal and input 771D. Control circuit 220 (and / or control circuit 120) can be used to provide outputs (e.g., 1*m+2*n+3*o+4*p) 790D based on the MAC operation.

[0105] refer to Figures 4 to 7The control circuit 220 (and / or control circuit 120) can be used to perform MAC operations in a flexible manner. In some embodiments, the control circuit 220 (and / or control circuit 120) can be used to access a first group of memory cells in a plurality of memory cells 203 at a first time for a read operation using a first weight matrix. The control circuit 220 (and / or control circuit 120) can be used to access a second group of memory cells in a plurality of memory cells 203 at a second time for a write operation using a second weight matrix, which is a transpose (and / or shift) matrix of the first weight matrix. In some embodiments, the control circuit 220 (and / or control circuit 120) can be used to access a first group of memory cells in a plurality of memory cells 203 at a first time for a write operation using the first weight matrix. The control circuit 220 (and / or control circuit 120) can be used to access a second group of memory cells in a plurality of memory cells 203 at a second time for a read operation using a second weight matrix, which is a transpose (and / or shift) matrix of the first weight matrix.

[0106] Figure 8 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure. Figure 8 The weight mapping process shown can be associated with memory circuit 102, memory circuit 202, etc. Figure 8 The illustration shows a non-limiting example of a weight mapping process. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to reconfigure the weight matrix (e.g., weight matrix 581, weight matrix 581T, etc.). For example, when the weight matrix is ​​an n-by-n matrix, control circuitry 220 (and / or control circuitry 120) can be used to convert the weight matrix to a 1-by-n matrix. 2 Matrix. Control circuitry 220 (and / or control circuitry 120) can be used to access memory cells (e.g., multiple memory cells 203) and / or based on a transformed weight matrix (e.g., 1 x n). 2 (Matrix) performs MAC operations.

[0107] Figure 9 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure. Figure 9 The weight mapping process shown can be associated with memory circuit 102, memory circuit 202, etc. Figure 9 The illustration shows a non-limiting example of a weight mapping process. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to reconfigure the weight matrix (e.g., weight matrix 581, weight matrix 581T, etc.). For example, when the weight matrix is ​​an n-by-n matrix, control circuitry 220 (and / or control circuitry 120) can be used to convert the weight matrix to a 1-by-n matrix. 2Matrix. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to perform transformations on the (untransposed) weight matrix and the transposed weight matrix.

[0108] Control circuit 220 (and / or control circuit 120) can be used to convert the (untransposed) weight matrix 981 into a transformed weight matrix 990. Control circuit 220 (and / or control circuit 120) can be used to perform MAC operations based on the transformed weight matrix 990 and input 971. As shown, based on the MAC operation, control circuit 220 (and / or control circuit 120) can be used to provide outputs (pMAC0, pMAC1, pMAC2, pMAC3, etc.). For example, output pMAC0 can be 0*a+1*b+2*c+3*d. Output pMAC1 can be 0*e+1*f+2*g+3*h. Output pMAC2 can be 0*i+1*j+2*k+3*l. Output pMAC3 can be 0*m+1*n+2*o+3*p.

[0109] Figure 10 A schematic diagram illustrating an instance weight mapping process according to some embodiments of this disclosure. Figure 10 The weight mapping process shown can be associated with memory circuit 102, memory circuit 202, etc. Figure 10 The illustration shows a non-limiting example of a weight mapping process. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to reconfigure the weight matrix (e.g., weight matrix 581, weight matrix 581T, etc.). For example, when the weight matrix is ​​an n-by-n matrix, control circuitry 220 (and / or control circuitry 120) can be used to convert the weight matrix to a 1-by-n matrix. 2 Matrix. In some embodiments, control circuitry 220 (and / or control circuitry 120) can be used to perform transformations on the (untransposed) weight matrix and the transposed weight matrix.

[0110] Control circuit 220 (and / or control circuit 120) can be used to convert the transposed weight matrix 1081 into a transformation matrix 1090. Control circuit 220 (and / or control circuit 120) can be used to perform a MAC operation based on the transformation weight matrix 1090 and the input 1071. In some embodiments, control circuit 220 (and / or control circuit 120) can be used to switch at least one of the matrix elements to perform a MAC operation. As shown, based on the MAC operation, control circuit 220 (and / or control circuit 120) can be used to provide outputs (pMAC0, pMAC1, pMAC2, pMAC3, etc.). For example, output pMAC0 may be 0*a+1*e+2*i+3*m. Output pMAC1 may be 0*b+1*f+2*j+3*n. Output pMAC2 may be 0*c+1*g+2*k+3*o. Output pMAC3 may be 0*d+1*h+2*l+3*p.

[0111] Figure 11 A flowchart illustrating an example method 1100 with operating circuitry according to various embodiments is provided. Example method 1100 may be performed by control circuitry 120, control circuitry 220, etc., or one or more of these elements. Therefore, the following embodiments of method 1100 may be combined with, but are not limited to, other embodiments. Figures 1 to 10 The method 1100 is described using at least one of the following methods. The illustrated embodiments of method 1100 are provided as examples and do not limit the scope of the embodiments disclosed herein. Therefore, it should be understood that any of the various operations of method 1100 may be omitted, reordered, and / or added while remaining within the scope of the embodiments disclosed herein.

[0112] In short, method 1100 may begin with operation 1110: providing a first address signal and a first enable signal at a first time. Method 1100 may continue to operation 1120: accessing a first group of memory cells in the memory array based on the first address signal and the first enable signal, wherein the first group of memory cells corresponds to a first weight matrix. Method 1100 may continue to operation 1130: providing a second address signal and a second enable signal at a second time. Method 1100 may continue to operation 1140: accessing a second group of memory cells in the memory array based on the second address signal and the second enable signal, wherein the second group of memory cells corresponds to a second weight matrix, the second weight matrix being the transpose of the first weight matrix.

[0113] In operation 1110, the control circuit (e.g., control circuit 120, control circuit 220) can provide a first address signal (e.g., address signals 451A, 451B, 451C, 451D, etc.) at the first moment. Figure 6 The address signal described) and the first enable signal (e.g., enable signals 461A, 461B, 461C, 461D, 661A, 661B, 661C, 661D, etc.).

[0114] In operation 1120, the control circuitry can access a first group of memory cells (e.g., a plurality of memory cells 203) in the memory array based on a first address signal and a first enable signal. The first group of memory cells may correspond to a first weight matrix (e.g., weight matrix 581). In some embodiments, the control circuitry can be used to access the memory cells based on logic and operations of the first address signal and the first enable signal.

[0115] In operation 1130, the control circuit can provide a second address signal at a second time (e.g., address signals 551A, 551B, 551C, 551D, etc.). Figure 7 The address signal described) and the second enable signal (e.g., enable signals 561A, 561B, 561C, 561D, regarding...) Figure 7 (The enable signal described). In some embodiments, the control circuitry can be used to access memory cells based on the logic and operations of the first address signal and the first enable signal.

[0116] In operation 1140, the control circuit can access a second set of memory cells in the memory array based on a second address signal and a second enable signal. The second set of memory cells may correspond to a second weight matrix (e.g., weight matrix 581T). The second weight matrix may be the transpose of the first weight matrix.

[0117] In some embodiments, a circuit for calculating a weight mapping within a memory cell is provided, comprising: a plurality of memory cells; a plurality of first address lines, each of the first address lines being coupled to a corresponding memory cell among the memory cells; and a plurality of second address lines, each of the second address lines being coupled to a set of cells among the memory cells, wherein when one or more of the first address lines corresponding to one or more cells among the memory cells and one or more of the second address lines are asserted, one or more cells among the memory cells are used to access one or more weight values, and wherein one or more cells accessed at a first time correspond to a first weight matrix, and one or more cells accessed at a second time correspond to a second weight matrix, the second weight matrix being a transpose of the first weight matrix.

[0118] In some embodiments, the circuit further includes a plurality of AND gates, each of which is operatively coupled between a corresponding first address line among the first address lines and a corresponding second address line among the second address lines.

[0119] In some embodiments, each of these AND gates includes a first input for receiving an enable signal and a second input for receiving an address signal.

[0120] In some embodiments, each of these AND gates includes an output operatively coupled to a corresponding memory cell in these memory cells.

[0121] In some embodiments, the first weight matrix is ​​an n-by-n matrix, and these memory cells are based on 1-by-n 2 The matrix is ​​accessed.

[0122] In some embodiments, one or more of these memory units are used to access the memory using a first weight matrix at a first time to perform a read operation, and one or more of these memory units are used to access the memory using a second weight matrix at a second time to perform a write operation.

[0123] In some embodiments, these first address lines comprise multiple subsets, each of which is coupled to a corresponding row of these memory cells, and different first address lines are asserted alternately to alternate these subsets.

[0124] In some embodiments, these first address lines comprise a plurality of subsets, each of which is coupled to a corresponding row of these memory cells, and wherein a complete subset of these subsets is asserted to alternate between these subsets.

[0125] In some embodiments, the first number of address lines in the first address lines corresponds to the number of memory cells in the memory cells, and the second number of address lines in the second address lines corresponds to the number of rows or columns in the memory cells.

[0126] In some embodiments, a circuit for calculating a weight mapping within a memory is provided, comprising: a memory array; and a control circuit operatively coupled to the memory array, the control circuit being configured to: provide an enable signal and an address signal; and access at least one memory cell of the memory array based on the enable signal and the address signal, wherein the control circuit is configured to provide a first address signal at a first time to access the memory array based on a first weight matrix, and to provide a second address signal at a second time to access the memory array based on a second weight matrix, the second weight matrix being a transpose of the first weight matrix.

[0127] In some embodiments, the circuitry further includes a multiplexer operatively coupled between the memory array and the control circuitry.

[0128] In some embodiments, the multiplexer includes at least one logic gate and a plurality of address lines.

[0129] In some embodiments, at least one logic gate includes an AND gate, which includes a first input for receiving an enable signal and a second input for receiving an address signal.

[0130] In some embodiments, at least one logic gate includes an AND gate, which includes an output operatively coupled to a corresponding memory cell of the memory array.

[0131] In some embodiments, the first matrix is ​​an n-by-n matrix, and the control circuitry is used to base the matrix on a 1-by-n matrix. 2 Matrix access memory array.

[0132] In some embodiments, the control circuitry is used to write to the memory array based on a first weight matrix and to read from the memory array based on a second weight matrix.

[0133] In some embodiments, the control circuitry is used to alternately assert different rows of the memory array.

[0134] In some embodiments, when the control circuit asserts a row of the memory array, the control circuit is used to access a complete memory cell coupled to a row of the memory array at a time.

[0135] In some embodiments, a method for weight mapping computation within a memory is provided, comprising the following steps: providing a first address signal and a first enable signal at a first time; accessing a first group of memory cells in a memory array based on the first address signal and the first enable signal, wherein the first group of memory cells corresponds to a first weight matrix; providing a second address signal and a second enable signal at a second time; and accessing a second group of memory cells in the memory array based on the second address signal and the second enable signal, wherein the second group of memory cells corresponds to a second weight matrix, and the second weight matrix is ​​a transpose of the first weight matrix.

[0136] In some embodiments, the method further includes the following steps: accessing a first group of memory cells based on logic and operations of a first address signal and a first enable signal.

[0137] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of this subject. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0138] The foregoing overview of several embodiments provides a better understanding of the features of the embodiments disclosed herein. Those skilled in the art will appreciate that they can readily use the embodiments disclosed herein as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A circuit for calculating weight mapping within a memory, characterized in that, include: Multiple memory units; A plurality of first address lines, each of which is coupled to a corresponding memory cell among the plurality of memory cells; and A plurality of second address lines, each of which is coupled to a group of cells among the plurality of memory cells. Wherein, when one or more of the plurality of first address lines and one or more of the plurality of second address lines corresponding to one or more of the plurality of memory cells are asserted, one or more of the plurality of memory cells are used to access one or more weight values, and The one or more units accessed at a first time correspond to a first weight matrix, and the one or more units accessed at a second time correspond to a second weight matrix, which is a transpose of the first weight matrix.

2. The circuit as described in claim 1, characterized in that, It further includes a plurality of AND gates, each of which is operatively coupled between a corresponding first address line among the plurality of first address lines and a corresponding second address line among the plurality of second address lines.

3. The circuit as described in claim 2, characterized in that, Each of the plurality of AND gates includes a first input for receiving a consistency signal and a second input for receiving an address signal.

4. The circuit as described in claim 1, characterized in that, The first weight matrix is ​​an n-by-n matrix, and the plurality of memory cells are based on a 1-by-n matrix. 2 The matrix is ​​accessed.

5. The circuit as described in claim 1, characterized in that, The one or more of the plurality of memory units are used to access the first weight matrix at the first time to perform a read operation, and the one or more of the plurality of memory units are used to access the second weight matrix at the second time to perform a write operation.

6. The circuit as described in claim 1, characterized in that, The plurality of first address lines comprises a plurality of subsets, each of the subsets being coupled to a corresponding row of the plurality of memory cells, and wherein different first address lines are asserted alternately to alternate the plurality of subsets.

7. A circuit for calculating weight mapping within a memory, characterized in that, include: A memory array; and A control circuit, operatively coupled to the memory array, is used to: Provide a consistent energy signal and an address signal; and At least one memory cell of the memory array is accessed based on the enable signal and the address signal. The control circuit is used to provide a first address signal at a first time to access the memory array based on a first weight matrix, and to provide a second address signal at a second time to access the memory array based on a second weight matrix, wherein the second weight matrix is ​​a transpose of the first weight matrix.

8. The circuit as described in claim 7, characterized in that, The control circuit is used to alternately assert different rows of the memory array. When the control circuit asserts a row of the memory array, the control circuit is used to access the complete memory cell coupled to that row of the memory array in one go.

9. A method for weight mapping computation within a memory, characterized in that, Includes the following steps: Provide a first address signal and a first enable signal at the first moment; Based on the first address signal and the first enable signal, a first group of memory cells in a memory array is accessed, wherein the first group of memory cells corresponds to a first weight matrix; Provide a second address signal and a second enable signal at a second time; and Accessing a second group of memory cells in the memory array based on the second address signal and the second enable signal, wherein the second group of memory cells corresponds to a second weight matrix, and the second weight matrix is ​​a transpose of the first weight matrix.

10. The method as described in claim 9, characterized in that, Further steps include: The first set of memory cells is accessed based on a logic operation using the first address signal and the first enable signal.

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