A control circuit for airborne radar or a pilot switch

Abstract

The application provides a control circuit for an airborne radar or a pilot switch, belongs to the technical field of airborne computers, and specifically utilizes a heartbeat signal and a watchdog circuit of an FPGA to ensure that the system continues to output a stable signal only after the FPGA normally operates, and enables the bus driver to be timely cut off in an abnormal state. The uncertainty of the IO port output state of the FPGA is converted into a determinable safe output state through exclusive or logical combination operation of a judgment circuit, and the fault tolerance of the system is enhanced. The opening and closing states of a magnetic latching relay are read back by using the FPGA, and the state of the magnetic latching relay when powered on is confirmed. The safety state design of the application not only improves the reliability of the system, but also simplifies the circuit design, significantly reduces the risk of overall circuit failure caused by single-point failure, and thus ensures the high safety of the airborne radar or the pilot switch control.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of onboard computers, in particular to a control circuit for an onboard radar or a transponder switch. BACKGROUND

[0002] In high-complexity avionics systems, ensuring the reliable operation of each subsystem and the safe communication between them is a major challenge. During flight, the aircraft often faces extreme environmental conditions, including high and low temperatures and high vibrations, and these external factors pose a potential threat to the stable operation of the control system. For example, at high temperatures, some components may overheat and fail; at low temperatures, the system may be unstable due to cold start problems. The lack of effective protection mechanisms, the inability to ensure that control signals are in a determinable safe output state, and single failure points leading to the risk of overall circuit failure are all safety hazards in control systems. Therefore, in the control circuit of an onboard radar or a transponder switch, safety and stability are key to circuit design. SUMMARY

[0003] Therefore, the present application provides a control circuit for an onboard radar or a transponder switch, which solves the problems in the prior art, simplifies circuit design, reduces the risk of overall circuit failure caused by a single failure point, ensures the high safety of the onboard radar or the transponder switch control, and realizes the safe output of the control signal of the onboard radar or the transponder switch.

[0004] The control circuit for an onboard radar or a transponder switch provided by the present application adopts the following technical solution:

[0005] A control circuit for an onboard radar or a transponder switch, comprising an FPGA, a watchdog circuit, a bus driver, a judgment circuit, and a magnetic latching relay.

[0006] The FPGA sends an open signal or a close signal of the connection control to the bus driver through a connection control channel, and the FPGA sends an open signal or a close signal of the disconnection control signal to the bus driver through a disconnection control channel, while the FPGA outputs a first state signal and a second state signal to the bus driver, the first state signal indicating the open or close state of the connection control, and the second state signal indicating the open or close state of the disconnection control.

[0007] The bus driver sends the opening signal or the closing signal of the continuity control, the opening signal or the closing signal of the disconnection control, the first state signal and the second state signal to the judgment circuit, when the states of the first state signal and the second state signal are different, the judgment circuit judges that the bus driver sends the opening signal or the closing signal of the continuity control and the opening signal or the closing signal of the disconnection control is valid, and sends the continuity or disconnection signal to the magnetic latching relay, the magnetic latching relay performs the continuity or disconnection action according to the received signal to control the opening and closing of the radar or the guide.

[0008] The FPGA normally works to periodically send the heartbeat line to the watchdog circuit, the watchdog circuit normally receives the heartbeat line to output the low-level signal to the enable end of the bus driver, the bus driver normally works, the FPGA abnormally stops sending the heartbeat line to the watchdog circuit, and the watchdog circuit receives the heartbeat line abnormally to output the high-level signal to the enable end of the bus driver, and the bus driver stops working.

[0009] Optionally, the magnetic latching relay is a double-coil magnetic latching relay, the judgment circuit outputs two signals, the first signal is the voltage signal of the continuity control, and the second signal is the voltage signal of the disconnection control, the first signal is connected to the first coil of the double-coil magnetic latching relay, the second signal is connected to the second coil of the double-coil magnetic latching relay, the first switch in the double-coil magnetic latching relay is used to communicate with the power supply circuit of the radar or the guide, and the double-coil magnetic latching relay selects the continuity and disconnection state switching according to the voltage of the two signals output by the judgment circuit.

[0010] Optionally, the judgment circuit includes an XOR gate, a first AND gate and a second AND gate, the bus driver is used to send the opening signal or the closing signal of the continuity control to the first AND gate, the bus driver is used to send the opening signal or the closing signal of the disconnection control to the second AND gate, the first state signal and the second state signal output by the bus driver are sent to the XOR gate, the judgment result of the XOR gate is output to the first AND gate and the second AND gate, one end of the first coil of the double-coil magnetic latching relay is connected to the output end of the first AND gate, and one end of the second coil of the double-coil magnetic latching relay is connected to the output end of the second AND gate.

[0011] The communication control channel output 1 indicates that the communication control is open and the first state signal is 1, and the communication control channel output 0 indicates that the communication control is closed and the first state signal is 0; the disconnect control channel output 1 indicates that the communication control is open and the second state signal is 1, and the disconnect control channel output 0 indicates that the communication control is closed and the second state signal is 0; when the first state signal and the second state signal received by the XOR gate are consistent, the XOR gate outputs 0, and when the first state signal and the second state signal received by the XOR gate are inconsistent, the XOR gate outputs 1;

[0012] When the signals received by the first AND gate are both 1, the first coil generates an electromagnetic field and the double-coil magnetic latching relay is in a communication state, and when the signals received by the second AND gate are both 1, the second coil generates an electromagnetic field and the double-coil magnetic latching relay is in a closed state.

[0013] Optionally, the watchdog circuit comprises a monostable trigger and a NOT gate, the output end of the NOT gate is connected to the enable end of the bus driver, the FPGA periodically sends a heartbeat line to the monostable trigger, the monostable trigger sends a high-level signal to the NOT gate when normally receiving the heartbeat line, and the NOT gate outputs a low-level signal.

[0014] The monostable trigger sends a low-level signal to the NOT gate when abnormally receiving the heartbeat line, and the NOT gate outputs a high-level signal.

[0015] Optionally, the state back-reading circuit is further connected to the magnetic latching relay, for sending the communication or disconnection state information of the magnetic latching relay to the bus driver, and the bus driver sends the communication or disconnection state information of the magnetic latching relay to the FPGA.

[0016] Optionally, the back-reading circuit comprises an optoelectronic coupler, the input end of the optoelectronic coupler is connected to the second switch of the double-coil magnetic latching relay, one end of the second switch is connected to power supply, and the output end of the optoelectronic coupler is connected to the bus driver.

[0017] In summary, the present application has the following beneficial technical effects:

[0018] The heartbeat signal of the FPGA and the watchdog circuit are used to ensure that the system continues to output stable signals only after the FPGA normally operates, and the bus driver is enabled in time in an abnormal state.

[0019] Moreover, the uncertainty of the IO port output state of the FPGA is converted into a determinable safe output state through the XOR and logic combination operation of the judgment circuit, thereby enhancing the fault tolerance of the system.

[0020] Moreover, the open and closed states of the magnetic latching relay are read back by the FPGA to confirm the state when it is powered on.

[0021] The safety design of the application not only improves the reliability of the system, but also simplifies the circuit design, significantly reduces the risk of single point failure leading to overall circuit failure, thereby ensuring the high safety of the airborne radar or the control of the switch. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description only represent some of the embodiments of the application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0023] Figure 1 The circuit principle block diagram of the control circuit of the radar or the switch of the application. DETAILED DESCRIPTION

[0024] The embodiments of the application will be described in detail below with reference to the drawings.

[0025] The embodiments of the application will be described in detail below with reference to the drawings.

[0026] It should be noted that the various aspects described below in the context of the appended claims are illustrative. It should be apparent to those skilled in the art that the aspects described herein can be carried out in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the teachings provided herein one skilled in the art should be able to devise numerous alternative ways of implementing the aspects described herein without departing from the spirit of the application. For example, the various aspects described herein can be implemented across many devices, apparatuses, and systems. Any and all such variations are considered within the scope of the application. Other aspects of the application will become apparent to those skilled in the art from a review of the following description, which is provided by way of example of the application.

[0027] It is also need to be explained that the following provided figures are only to illustrate the basic idea of the present application in a schematic way, only the components relevant to the present application are shown in the figures, not the number, shape and size of the components when actually implemented, the shape, number and proportion of each component when actually implemented can be a random change, and the component layout pattern can also be more complex.

[0028] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, one skilled in the art will understand that the described aspects can be practiced without these specific details.

[0029] The embodiment of the present application provides a control circuit of an airborne radar or a transponder switch.

[0030] As shown in Figure 1 A control circuit of an airborne radar or a transponder switch, comprising an FPGA, a watchdog circuit, a bus driver, a judgment circuit and a magnetic latching relay.

[0031] The FPGA sends an open signal or a close signal of the on control to the bus driver through the on control channel, and the FPGA sends an open signal or a close signal of the off control signal to the bus driver through the off control channel, and the FPGA outputs a first state signal State A and a second state signal State B to the bus driver, the first state signal represents the open or close state of the on control, and the second state signal represents the open or close state of the off control. Wherein, the open signal of the on control represents starting on, that is, opening the radar or the transponder; the close signal of the on control represents closing on, that is, closing the radar or the transponder; the open signal of the off control represents starting off, that is, closing the radar or the transponder, and the close signal of the off control represents closing off, that is, opening the radar or the transponder. When the FPGA sends the open signal of the on control through the on control channel, the off control channel sends the close signal of the off control, which is used to make the magnetic latching relay in the on state to open the radar or the transponder. When the FPGA sends the open signal of the off control through the off control channel, the on control channel sends the close signal of the on control, which is used to make the magnetic latching relay in the off state to close the radar or the transponder. The open signal is high level, and the close signal is low level.

[0032] The bus driver sends the on / off signal for connection control, the on / off signal for disconnection control, a first state signal, and a second state signal to the judgment circuit. When the states of the first state signal and the second state signal are different, the judgment circuit determines that the on / off signal for connection control and the on / off signal for disconnection control sent by the bus driver are valid, and sends a connection or disconnection signal to the magnetic latching relay. The magnetic latching relay performs a connection or disconnection action according to the received signal to control the opening and closing of the radar or communication system. Since the radar or communication system is either in an open state or a closed state, during normal operation of the control circuit, one of the connection control channel and the disconnection control channel will definitely output an open signal, and the other will output a closed signal. The connection control channel and the disconnection control channel cannot simultaneously output open or closed signals. Therefore, the FPGA outputs the states of connection control and disconnection control while outputting the control signal. Only when the states of connection control and disconnection control are inconsistent are the connection control signal and disconnection control signal sent to the magnetic latching relay valid. This ensures the determinism of the signal in the fixed operation mode and allows for safe output to the magnetic latching relay, guaranteeing the safety and stability of the system.

[0033] When the FPGA is working normally, it periodically sends heartbeat signals to the watchdog circuit. When the watchdog circuit receives the heartbeat signal normally, it outputs a low-level signal to the enable terminal of the bus driver, indicating normal operation. When the FPGA malfunctions, it stops sending heartbeat signals to the watchdog circuit. If the watchdog circuit receives an abnormal heartbeat signal, it outputs a high-level signal to the enable terminal of the bus driver, causing the bus driver to stop working. The watchdog circuit ensures that the bus driver is automatically shut down in the event of an FPGA malfunction or fault. The bus driver can only transmit data normally when the FPGA is working properly. At this time, the control and status signals of the radar or communication system are converted by the bus driver and then transmitted to the judgment circuit. Once the FPGA malfunctions or malfunctions, the bus driver will also stop data transmission. This mechanism ensures that the circuit can automatically cut off data communication when the FPGA malfunctions, further guaranteeing the stability and reliability of the system.

[0034] In this application embodiment, a set of control circuits is used to control the radar to turn on or off, and another set of control circuits with the same structure is used to control the opening or closing of the conduction.

[0035] The magnetic holding relay is a double-coil magnetic holding relay, the judgment circuit outputs two signals, the first signal is a voltage signal for on control, the second signal is a voltage signal for off control, the first signal is connected to the first coil of the double-coil magnetic holding relay, the second signal is connected to the second coil of the double-coil magnetic holding relay, the first switch in the double-coil magnetic holding relay is used to connect with the power supply circuit of the radar or the through guide, and the double-coil magnetic holding relay switches between the on and off states according to the voltage of the two signals output by the judgment circuit. When the on control is an open signal and the first state signal and the second state signal are inconsistent, the first coil of the double-coil magnetic holding relay is powered to generate a magnetic field, the second coil is powered off without a magnetic field, the internal switch of the double-coil magnetic holding relay is closed, the double-coil magnetic holding relay is in the on state, and the radar or the through guide is in the open state. When the off control is an open signal and the first state signal and the second state signal are inconsistent, the first coil of the double-coil magnetic holding relay is powered off without a magnetic field, the second coil is powered on to generate a magnetic field, the internal switch of the double-coil magnetic holding relay is opened, the double-coil magnetic holding relay is in the off state, and the radar or the through guide is in the closed state.

[0036] The application adopts a magnetic holding relay to receive the final control signal generated by the judgment circuit, and drives the opening and closing operation of the internal switch contact through the pulse current triggered coil magnetic field. After receiving the final result of the judgment circuit, the magnetic holding relay generates a transient pulse current, which excites the coil to generate a magnetic field. The generated magnetic field is superimposed with the magnetic field of the built-in permanent magnet, and according to the principle of "like repels, unlike attracts", the contact is driven to open and close. After the pulse disappears, the relay can maintain the current switch state due to the action of the permanent magnet. The magnetic holding relay does not need continuous power to maintain its state. Once it is set to the on or off state, it will continue to maintain the state until a new instruction is received. This feature makes the magnetic holding relay have the advantages of high energy saving and long-term stability, meets the application requirements of airborne radar and through guide, and is especially suitable for use in airborne switch control circuits that require high reliability and stable performance.

[0037] The judging circuit comprises an exclusive-OR gate, a first AND gate and a second AND gate, the bus driver is configured to send the open signal or the close signal of the communication control to the first AND gate, the bus driver is configured to send the open signal or the close signal of the disconnection control to the second AND gate, the first state signal and the second state signal output by the bus driver are sent to the exclusive-OR gate, the judging result of the exclusive-OR gate is output to the first AND gate and the second AND gate, the output of the first AND gate is the first path signal of the judging circuit, the output end of the first AND gate is connected to one end of the first coil of the double-coil magnetic latching relay, the output of the second AND gate is the second path signal of the judging circuit, and the output end of the second AND gate is connected to one end of the second coil of the double-coil magnetic latching relay.

[0038] The output 1 of the communication control channel indicates that the communication control is open and the first state signal is 1, and the output 0 of the communication control channel indicates that the communication control is closed and the second state signal is 0; the output 1 of the disconnection control channel indicates that the communication control is open and the first state signal is 1, and the output 0 of the disconnection control channel indicates that the communication control is closed and the second state signal is 0; when the first state signal and the second state signal received by the exclusive-OR gate are consistent, the exclusive-OR gate outputs 0, and when the first state signal and the second state signal received by the exclusive-OR gate are inconsistent, the exclusive-OR gate outputs 1; when the signals received by the first AND gate are all 1, the signals received by the second AND gate are not all 1, the first coil generates an electromagnetic field, and the second coil does not generate an electromagnetic field, and the double-coil magnetic latching relay is in the communication state; when the signals received by the second AND gate are all 1, the signals received by the first AND gate are not all 1, the second coil generates an electromagnetic field, and the first coil does not generate an electromagnetic field, and the double-coil magnetic latching relay is in the closed state.

[0039] The watchdog circuit comprises a monostable trigger and a NOT gate, the output end of the NOT gate is connected to the enable end of the bus driver, the FPGA periodically sends a heartbeat line to the monostable trigger, the monostable trigger sends a high-level signal to the NOT gate when normally receiving the heartbeat line, and the NOT gate outputs a low-level signal; the monostable trigger sends a low-level signal to the NOT gate when abnormally receiving the heartbeat line, and the NOT gate outputs a high-level signal.

[0040] The control circuit further comprises a state reading-back circuit, the state reading-back circuit is connected to the magnetic latching relay and is configured to send the communication or disconnection state information of the magnetic latching relay to the bus driver, and the bus driver sends the communication or disconnection state information of the magnetic latching relay to the FPGA.

[0041] The reading-back circuit comprises an optoelectronic coupler, the input end of the optoelectronic coupler is connected to the second switch of the double-coil magnetic latching relay, one end of the second switch is connected to the power supply, and the output end of the optoelectronic coupler is connected to the bus driver.

[0042] The state feedback circuit is configured to feed back the switch state information of the magnetic latching relay to the FPGA, and the FPGA reads the opening and closing state of the magnetic latching relay when powered on. This process realizes the physical isolation of input and output signals by using an optocoupler, thereby effectively preventing the adverse effects of external interference and signal noise on the circuit. Through this feedback mechanism, when the FPGA is powered on again, the state signal is transmitted back to the FPGA through the bus driver. At this time, the opening and closing state before the relay is powered off can be read, ensuring that the system is in a determinable safe state.

[0043] In the embodiment of the application, the power supply design for the double-coil magnetic latching relay and the state feedback circuit is as follows:

[0044] The first transistor is connected between the first AND gate and the first end of the first coil of the double-coil magnetic latching relay, and the second transistor is connected between the second AND gate and the first end of the second coil of the double-coil magnetic latching relay. The second ends of the first coil and the second coil are connected to a +5V power supply, and one end of the second switch is connected to the +5V power supply. The optocoupler in the feedback circuit reflects the on-off state of the double-coil magnetic latching relay according to the different on-off conditions of the +5V power supply and the closed and open states of the second switch.

[0045] The base of the first transistor is connected to the first AND gate, the collector of the first transistor is connected to the first end of the first coil, and the emitter of the first transistor is grounded. The base of the second transistor is connected to the second AND gate, the collector of the second transistor is connected to the first end of the second coil, and the emitter of the second transistor is grounded.

[0046] When the continuous control is an open signal, the signals received by the first AND gate are all 1, the first AND gate outputs a 5V voltage, the first transistor is turned on, the first coil and the grounded emitter of the first transistor are turned on, the first end of the first coil is grounded at 0V, and the second end is +5V. The first coil is powered on to generate a magnetic field, driving the first switch and the second switch of the double-coil magnetic latching relay to be in a closed state, and the double-coil magnetic latching relay is in a continuous state. At this time, the second AND gate receives a closed control as a closed signal, i.e., one of the signals received by the second AND gate is 0 and the other is 1. The second AND gate has no voltage output, i.e., the voltage signal output by the second AND gate is 0V, and the second transistor is in an off state, and no current passes through the second coil.

[0047] Similarly, when the disconnect control is an open signal, the signals received by the second AND gate are both 1, the second AND gate outputs a 5V voltage, the second transistor is turned on, the second coil and the grounded emitter of the second transistor are turned on, the first end of the second coil is grounded at 0V, the second end is +5V, the second coil is energized to generate a magnetic field, driving the first switch and the second switch of the double-coil magnetic latching relay to be in the open state, and the double-coil magnetic latching relay is in the open state. At this time, the communication control received by the first AND gate is a close signal, that is, one of the signals received by the first AND gate is 0 and the other is 1, the first AND gate has no voltage output, that is, the voltage signal output by the first AND gate is 0V, and the first transistor is in the off state, and no current flows through the first coil.

[0048] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control circuit for airborne radar or conduction switch, characterized in that, This includes FPGA, watchdog circuit, bus driver, decision circuit, and magnetic latching relay; The FPGA sends a connection control open or close signal to the bus driver through the connection control channel, and sends a disconnect control open or close signal to the bus driver through the disconnect control channel. At the same time, the FPGA outputs a first status signal and a second status signal to the bus driver. The first status signal indicates the connection control open or close status, and the second status signal indicates the disconnect control open or close status. The bus driver sends the open or closed signal of the connection control, the open or closed signal of the disconnection control, the first state signal, and the second state signal to the judgment circuit. When the states of the first state signal and the second state signal are different, the judgment circuit determines that the open or closed signal of the connection control or the open or closed signal of the disconnection control sent by the bus driver is valid, and sends a connection or disconnection signal to the magnetic latching relay. The magnetic latching relay performs a connection or disconnection action according to the received signal to control the opening and closing of the radar or communication system. When the FPGA is working normally, it periodically sends a heartbeat signal to the watchdog circuit. When the watchdog circuit receives the heartbeat signal normally, it outputs a low-level signal to the enable terminal of the bus driver. When the bus driver is working normally, it stops sending heartbeat signals to the watchdog circuit when the FPGA is malfunctioning. When the watchdog circuit receives a heartbeat signal malfunctioning, it outputs a high-level signal to the enable terminal of the bus driver, and the bus driver stops working.

2. The control circuit for airborne radar or conduction switch according to claim 1, characterized in that, The magnetic latching relay is a dual-coil magnetic latching relay. The judgment circuit outputs two signals: a first signal is a voltage signal for connection control, and a second signal is a voltage signal for disconnection control. The first signal is connected to the first coil of the dual-coil magnetic latching relay, and the second signal is connected to the second coil of the dual-coil magnetic latching relay. The first switch in the dual-coil magnetic latching relay is used to connect to the power supply circuit of the radar or the conduction circuit. The dual-coil magnetic latching relay switches between connection and disconnection states according to the voltage of the two signals output by the judgment circuit.

3. The control circuit for airborne radar or conduction switch according to claim 2, characterized in that, The judgment circuit includes an XOR gate, a first AND gate, and a second AND gate. The bus driver is used to send an open or closed signal for connection control to the first AND gate, and the bus driver is used to send an open or closed signal for disconnection control to the second AND gate. The first and second status signals output by the bus driver are sent to the XOR gate. The judgment results of the XOR gate are both output to the first and second AND gates. The output terminal of the first AND gate is connected to one end of the first coil of the dual-coil magnetic latching relay, and the output terminal of the second AND gate is connected to one end of the second coil of the dual-coil magnetic latching relay. When the connection control channel outputs 1, it indicates that the connection control is open and the first state signal is 1; when the connection control channel outputs 0, it indicates that the connection control is closed and the first state signal is 0. When the disconnect control channel outputs 1, it indicates that the connection control is open and the second state signal is 1; when the disconnect control channel outputs 0, it indicates that the connection control is closed and the second state signal is 0. When the first state signal and the second state signal received by the XOR gate are the same, the XOR gate outputs 0; when the first state signal and the second state signal received by the XOR gate are not the same, the XOR gate outputs 1. When all signals received by the first AND gate are 1, the first coil generates an electromagnetic field and the dual-coil magnetic latching relay is in a connected state. When all signals received by the second AND gate are 1, the second coil generates an electromagnetic field and the dual-coil magnetic latching relay is in a closed state.

4. The control circuit for airborne radar or conduction switch according to claim 1, characterized in that, The watchdog circuit includes a monostable multivibrator and a NOT gate. The output of the NOT gate is connected to the enable terminal of the bus driver. The FPGA periodically sends a heartbeat line to the monostable multivibrator. When the monostable multivibrator receives the heartbeat line normally, it sends a high-level signal to the NOT gate, and the NOT gate outputs a low-level signal. When the monostable multivibrator receives a heartbeat line abnormality, it sends a low-level signal to the NOT gate, and the NOT gate outputs a high-level signal.

5. The control circuit for airborne radar or conduction switch according to claim 2, characterized in that, It also includes a status readback circuit, which is connected to the magnetic latching relay and is used to send the on or off status information of the magnetic latching relay to the bus driver. The bus driver then sends the on or off status information of the magnetic latching relay to the FPGA.

6. The control circuit for airborne radar or conduction switch according to claim 5, characterized in that, The readback circuit includes an optocoupler, the input of which is connected to the second switch of a dual-coil magnetic latching relay, and one end of the second switch is connected to a power supply. The output of the optocoupler is connected to the bus driver.

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