Test methods for wired controllers, wired controllers and wired controller test systems

Abstract

This application relates to the field of wired remote control technology, and discloses a testing method, a wired remote control, and a wired remote control testing system. The wired remote control includes: a button control chip configured to acquire simulated button signals during testing, the simulated button signals being used to simulate the signals generated when a physical button is pressed; and a main control chip connected to the button control chip, configured to receive the simulated button signals and use these signals to test the firmware under test in the main control chip. Through this method, the dependence on physical mechanical structures can be eliminated, and the testing of the firmware under test in the main control chip can be achieved through interaction between the button control chip and the main control chip within the wired remote control, thus verifying the robustness, fault tolerance, and stability of the firmware under test in the main control chip.

Description

Technical Field

[0001] This application relates to the field of wired controller technology, and in particular to a test method for wired controllers, a wired controller, and a wired controller test system. Background Technology

[0002] Stress testing of firmware for button-type wired controllers primarily relies on manual triggering or external mechanical fixtures simulating physical buttons. This method has significant limitations: it is costly and, constrained by the physical execution method, it struggles to rapidly replicate test cases and execute them in parallel on a large scale, failing to efficiently handle the synchronous testing needs of multiple wired controllers. Furthermore, purely physical button operations cannot accurately and reliably generate complex abnormal signal sequences (such as extremely high-frequency continuous clicks, simultaneous multi-button triggering at millisecond levels, and sliding operations with specific timing sequences), leading to many potential software defects, such as state machine errors, buffer overflows, or race conditions, that cannot be effectively exposed through traditional triggering methods. This hinders the deepening of test coverage and the verification of product reliability. Summary of the Invention

[0003] The testing method, controller, and system for the wired controller provided in this application can eliminate the dependence on physical mechanical structures and enable the interaction between the controller chip and the main control chip through buttons inside the controller to test the firmware under test in the main control chip, thereby verifying the robustness, fault tolerance, and stability of the firmware under test in the main control chip.

[0004] In a first aspect, this application provides a wired controller, which includes: a button control chip configured to: acquire simulated button signals during testing, the simulated button signals being used to simulate the signals generated when a physical button is pressed; and a main control chip connected to the button control chip, configured to: receive the simulated button signals and use the simulated button signals to test the firmware under test in the main control chip.

[0005] The button control chip is also configured to randomly acquire analog button signals from the set of analog button signals during the test.

[0006] The testing process includes a first testing phase and a second testing phase. The button control chip is also configured to: in the first testing phase, randomly acquire simulated button signals from the set of simulated button signals without repetition, until all simulated button signals in the set of simulated button signals have been acquired; in the second testing phase, randomly acquire simulated button signals again without restriction from the set of simulated button signals.

[0007] The set of simulated button signals includes a first type of simulated button signal and a second type of simulated button signal; the first type of simulated button signal is used to simulate the signal generated by pressing a physical button in a conventional way, and the second type of simulated button signal is used to simulate the signal generated by pressing a physical button in an unconventional way.

[0008] The first type of analog button signal includes: a first analog button signal, a second analog button signal, and a third analog button signal; wherein, the first analog button signal is used to simulate the signal generated when a single button is pressed for a first duration, the second analog button signal is used to simulate the signal generated when a single button is pressed for a second duration, and the third analog button signal is used to simulate the signal generated when two buttons are pressed simultaneously for a third duration, wherein the first duration is shorter than the second duration.

[0009] The second type of simulated button signals includes: a fourth simulated button signal, a fifth simulated button signal, a sixth simulated button signal, a seventh simulated button signal, and an eighth simulated button signal. The fourth simulated button signal is used to simulate the signal generated by pressing at least three buttons, the fifth simulated button signal is used to simulate the signal generated by pressing multiple buttons in succession, the sixth simulated button signal is used to simulate the signal generated by pressing a single button multiple times within a fourth time period, the seventh simulated button signal is used to simulate the signal generated by pressing a test button, and the eighth simulated button signal is used to simulate data boundary signals. The test button does not exist in the wire controller.

[0010] The main control chip is also configured to: when an abnormality is detected in the firmware under test in the main control chip when the current simulated button signal is used to test the firmware under test, mark the current simulated button signal and terminate the current process; and use the current simulated button signal to test the firmware under test in the main control chip again until the number of tests reaches the preset number.

[0011] The button control chip is also configured to disable its capacitance detection function during testing; the capacitance detection function is used to detect whether a physical button is pressed.

[0012] Secondly, this application provides a wired controller testing system, which includes: a wired controller, the wired controller being the same as the one provided in the first aspect; and an image recognition device for acquiring the display screen image of the wired controller during the testing process and determining whether the wired controller is abnormal by recognizing the display screen image.

[0013] Thirdly, this application provides a testing method for a wired controller, which includes a button control chip and a main control chip. The testing method includes: during the testing process, the button control chip acquires a simulated button signal, which is used to simulate the signal generated when a physical button is pressed; the simulated button signal is sent to the main control chip, and the simulated button signal is used to test the firmware under test in the main control chip.

[0014] The beneficial effects of the embodiments of this application are as follows: Unlike the prior art, the test method, wire controller, and wire controller test system provided in this application utilize a button control chip to generate simulated button signals and send the simulated button signals to the main control chip. The simulated button signals are used to test the firmware under test in the main control chip, thereby eliminating the dependence on physical mechanical structures. The test of the firmware under test in the main control chip is achieved through the interaction between the button control chip and the main control chip inside the wire controller. This verifies the robustness, fault tolerance, and stability of the firmware under test in the main control chip, reducing test costs and test cycles. Furthermore, the button control chip can simulate more types of simulated button signals, such as a series of button signals from normal operation to abnormal button signals, which can improve the test coverage, execution efficiency, and reliability during the test process. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the wired controller provided in this application;

[0017] Figure 2 This is a schematic diagram illustrating the interaction between the button control chip, the main control chip, and the display screen provided in this application;

[0018] Figure 3 This is a schematic diagram of the structure of an embodiment of the wire controller testing system provided in this application;

[0019] Figure 4 This is a flowchart illustrating an embodiment of the testing method for the wired controller provided in this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] Stress testing of firmware for button-type wired controllers primarily relies on manual triggering or external mechanical fixtures simulating physical buttons. This method has significant limitations: it is costly and, constrained by the physical execution method, it struggles to rapidly replicate test cases and execute them in parallel on a large scale, failing to efficiently handle the synchronous testing needs of multiple wired controllers. Furthermore, purely physical button operations cannot accurately and reliably generate complex abnormal signal sequences (such as extremely high-frequency continuous clicks, simultaneous multi-button triggering at millisecond levels, and sliding operations with specific timing sequences), leading to many potential software defects, such as state machine errors, buffer overflows, or race conditions, that cannot be effectively exposed through traditional triggering methods. This hinders the deepening of test coverage and the verification of product reliability.

[0023] Based on this, the wired controller testing method, wired controller, and wired controller testing system provided in this application utilize a button control chip to generate simulated button signals and send these simulated button signals to the main control chip. The simulated button signals are then used to test the firmware under test (DUT) in the main control chip. This eliminates the reliance on physical mechanical structures. The testing of the DUT in the main control chip is achieved through interaction between the button control chip and the main control chip within the wired controller. This verifies the robustness, fault tolerance, and stability of the DUT in the main control chip, reducing testing costs and time. Furthermore, the button control chip can simulate a wider range of simulated button signals, from normal operation signals to abnormal button signals, improving test coverage, execution efficiency, and reliability during the testing process. See any of the following embodiments for specific technical solutions.

[0024] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the wired controller provided in this application. The wired controller 100 includes: a button control chip 10, a main control chip 20, and a display screen 30. The button control chip 10 and the main control chip 20 are communicatively connected. For example, the button control chip 10 and the main control chip 20 are electrically connected. In some embodiments, the button control chip 10 and the main control chip 20 can communicate based on the I2C (Inter-Integrated Circuit) protocol. The main control chip 20 and the display screen 30 are electrically connected. Furthermore, the wired controller 100 is also provided with several buttons, such as... Figure 1Buttons A, B, and C are shown. The number of buttons in the wired controller 100 is set according to the actual situation, and will not be described here.

[0025] In some embodiments, the button control chip 10 is configured to acquire simulated button signals during testing, the simulated button signals being used to simulate the signals generated when a physical button is pressed.

[0026] In some embodiments, the simulated button signals can be simulated according to the type of physical buttons defined in the wired controller 100. For example, taking the wired controller 100 as an air conditioner wired controller as an example: the physical buttons in the wired controller 100 include: decrease button, increase button, on / off button, function button, mode button, sleep / confirm button, fan speed button, and timer button.

[0027] The functions of reducing and increasing buttons can include setting the indoor unit operating temperature, setting a timer, switching to silent mode, air exchange level, cleaning level, setting upper and lower limits for energy-saving temperature, parameter setting and querying, etc.

[0028] The function of the switch button can include turning the indoor unit on and off.

[0029] The functions of the buttons can include switching between strong airflow, vertical airflow, horizontal airflow, ventilation, silent mode, drying, cleaning, health mode, going out mode, and auxiliary heating.

[0030] The mode button can be used to switch between indoor unit automatic, cooling, dehumidification, ventilation, heating, underfloor heating, 3D heating, and heating operation modes.

[0031] The sleep / confirm button can be used to turn the sleep function on or off, select or cancel the function, etc.

[0032] The function of the fan speed button can include switching the fan speed status.

[0033] The timer button can be used to set a timer.

[0034] The two buttons can be used simultaneously to set the child lock function. For example, pressing the decrease and increase buttons at the same time will activate or deactivate the child lock function.

[0035] Based on this, simulated button signals can be used to simulate button signals according to the functions mentioned above.

[0036] In some embodiments, the button control chip 10 can construct simulated button signals according to functional setting requirements. For example, if the functional setting requirement is to set the heating temperature to 24 degrees Celsius, then based on the requirement of 24 degrees Celsius heating, it is determined which buttons need to participate. The simulated button signals for the corresponding buttons are first simulated, and then ordered in sequence to form a simulated button signal sequence. This sequence is then sent sequentially to the main control chip 20 to test the firmware under test in the main control chip 20 using the simulated button signals. This can be defined as a conventional button signal sequence.

[0037] In some embodiments, to verify the processing capability of the main control chip 20 for abnormal key signals, after the key control chip 10 constructs simulated key signals according to functional setting requirements, these simulated key signals can be randomly sorted to form an unconventional key signal sequence. The unconventional key signal sequence is then sent sequentially to the main control chip 20, thereby using simulated key signals to test the firmware under test in the main control chip 20.

[0038] In some embodiments, the analog key signal can be obtained by simulating a single key signal. For example, a long press or short press of a single key can be simulated.

[0039] In some embodiments, simulation can be performed based on multiple button signals to obtain simulated button signals corresponding to the multiple button signals within a preset time. For example, it can simulate simultaneous long press of two buttons, simultaneous short press of two buttons, or continuous pressing of three buttons.

[0040] That is, the button control chip 10 can simulate the button signal under normal operation, the button control chip 10 can simulate the button signal that the button can form under abnormal operation, and the button control chip 10 can simulate the button signal that a physical button cannot form. In this way, a more comprehensive set of button signals can be used to stress test the firmware under test in the test main control chip 20.

[0041] In some embodiments, the main control chip 20 is connected to the button control chip 10 and is configured to: receive simulated button signals and use the simulated button signals to test the firmware under test in the main control chip 20.

[0042] The firmware under test can be understood as the application program in the main control chip 20, which can process the corresponding key operations according to the preset logic.

[0043] In some embodiments, when the firmware under test in the main control chip 20 is normal, it can parse the simulated button signals to obtain screen switching data, and send the screen switching data to the display screen 30 of the wired controller 100 so that the display screen 30 can perform screen switching.

[0044] In some embodiments, when the firmware under test in the main control chip 20 has defects, the screen switching data is obtained by parsing the simulated button signals and then sent to the display screen 30 of the wired controller 100, causing the display screen 30 to exhibit corresponding anomalies during screen switching. Based on this, the firmware under test in the main control chip 20 can be tested by sending simulated button signals to the main control chip 20, eliminating the dependence on physical mechanical structures and thus significantly improving test coverage, execution efficiency, and reliability. In this way, each wired controller 100 can perform stress tests on the firmware under test of its internal main control chip 20. Multiple wired controllers 100 can perform the test simultaneously, without being limited by the number of physical mechanical structures. This not only enables large-scale parallel automated execution and efficient discovery of deep firmware defects (such as state machine race conditions, buffer processing errors, and abnormal input processing logic vulnerabilities) that are difficult to reach by other methods, but also reduces testing costs and time while providing unprecedented verification strength for the robustness of the firmware under test.

[0045] In some embodiments, the button control chip 10 is further configured to randomly acquire analog button signals from a set of analog button signals during testing.

[0046] In some embodiments, a simulated button signal generation program can be set in the button control chip 10 to generate a series of simulated button signals, which then constitute the simulated button signal set. For example, based on the function of the physical buttons of the wired controller 100, simulated button signals under various conditions can be generated for each physical button, such as simulating long press, short press, and multiple consecutive presses. It can also simulate button signals that would not normally occur under the current physical button conditions. In some embodiments, the button control chip 10 can randomly acquire simulated button signals from the simulated button signal set multiple times during testing. Therefore, the randomly acquired simulated button signals may or may not be repeated.

[0047] In some embodiments, the testing process includes a first testing phase and a second testing phase. The button control chip 10 is further configured to: in the first testing phase, randomly acquire simulated button signals from the set of simulated button signals without repetition, until all simulated button signals in the set of simulated button signals have been acquired; in the second testing phase, randomly acquire simulated button signals again without restriction from the set of simulated button signals. The second testing phase follows the first testing phase. For example, the second testing phase begins after the first testing phase is completed. In this way, in the first testing phase, all simulated button signals in the set of simulated button signals are acquired and tested, thereby simulating more real-world scenarios for the wired controller 100. In the second testing phase, simulated button signals are randomly acquired again without restriction from the set of simulated button signals, thereby meeting the requirements of stress testing. That is, comprehensive testing is performed first to avoid the omission of simulated button signals that cannot participate in the testing, resulting in incomplete testing, and then stress testing is performed.

[0048] In some embodiments, the set of analog key signals includes a first type of analog key signal and a second type of analog key signal; wherein the first type of analog key signal is used to simulate the signal generated by conventionally pressing a physical key, and the second type of analog key signal is used to simulate the signal generated by unconventional pressing of a physical key.

[0049] In some embodiments, the first type of simulated button signal includes: a first simulated button signal, a second simulated button signal, and a third simulated button signal; wherein, the first simulated button signal is used to simulate the signal generated by a single button being pressed for a first duration, the second simulated button signal is used to simulate the signal generated by a single button being pressed for a second duration, and the third simulated button signal is used to simulate the signal generated by two buttons being pressed simultaneously for a third duration, wherein the first duration is less than the second duration. In some embodiments, the third duration can be equal to the first duration. In some embodiments, the first duration, the second duration, and the third duration can be defined, such as the first duration being 100 milliseconds, the second duration being 1500 milliseconds, and the third duration being 100 milliseconds. The specific duration can be set according to the detection logic of the firmware in the main control chip of the wired controller.

[0050] In some embodiments, the first analog button signal is equivalent to simulating the signal generated by a single button being pressed briefly. The second analog button signal is equivalent to simulating the signal generated by a single button being pressed for a long time, and the third analog button signal is used to simulate the signal generated by two buttons being pressed simultaneously.

[0051] In some embodiments, the second type of simulated button signals includes: a fourth simulated button signal, a fifth simulated button signal, a sixth simulated button signal, a seventh simulated button signal, and an eighth simulated button signal; wherein, the fourth simulated button signal is used to simulate the signal generated by pressing at least three buttons, the fifth simulated button signal is used to simulate the signal generated by pressing multiple buttons in succession, the sixth simulated button signal is used to simulate the signal generated by pressing a single button multiple times within a fourth duration, the seventh simulated button signal is used to simulate the signal generated by pressing a test button, and the eighth simulated button signal is used to simulate a data boundary signal, wherein the test button does not exist in the wire controller 100.

[0052] In some embodiments, the fourth analog button signal is equivalent to simulating the signal generated by at least three buttons being pressed simultaneously, and the fifth analog button signal is equivalent to simulating the signal generated by multiple buttons being pressed in succession. For example... Figure 1 In the first simulation, if buttons A, B, and C are pressed in a very short time sequence, a continuous button signal is generated. The fifth simulated button signal can simulate this type of signal. The sixth simulated button signal is equivalent to simulating the signal generated by a single button being pressed multiple times within the fourth duration. The duration of each press is shorter than the first duration. For example, if pressed 5 times within 500 milliseconds, each press lasts 5 milliseconds; if pressed 10 times within 500 milliseconds, each press lasts 5 milliseconds. This simulates a single button being pressed at a very high frequency. The seventh simulated button signal is equivalent to simulating the signal generated by a test button being pressed. This test button does not exist in the wired controller 100. The eighth simulated button signal is used to simulate data boundary signals. Data boundary signals refer to data boundaries. For example, button signals are represented using data values, such as 0x01, 0x02, etc. Based on this, the data value has boundaries, such as 0xFF. Based on this, the data boundary signal can be used to test the firmware under test in the main control chip. Similarly, the data boundary signal can be understood as a special non-existent key.

[0053] In some embodiments, based on the communication protocol, the state of multiple buttons is represented by a single byte of data bits, 0x00 when no operation is performed and 0x1F when all buttons are pressed. Each test instruction (simulated button signal) consists of a data value and a duration (in milliseconds). The data value represents the button press. Common operation use cases include, but are not limited to: single button short press (0x01, 100), double button short press (0x03, 100), and single button long press (0x01, 1500). Abnormal test sequences are designed to break through the boundaries of normal logic, such as simulating multiple button presses simultaneously (0x1F), simulating rapid key value switching caused by sliding (0x01→0x03→0x07), extremely high frequency clicks (0x01, 5), triggering non-existent buttons (0x20) or data boundary values ​​(0xFF), etc. All these normal and abnormal use cases are integrated into a randomly selectable set of test vectors (simulated button signal set) for the button control chip 10 to call cyclically.

[0054] In some embodiments, the main control chip 20 is further configured to: when an anomaly is detected in the firmware under test in the main control chip 20 using the current simulated key signal, mark the current simulated key signal and terminate the current process; then test the firmware under test in the main control chip 20 again using the current simulated key signal until the number of tests reaches a preset number. In some embodiments, the preset test can be 2, 3, 5, 10, or 15 times, and there is no specific limitation. In some embodiments, if the firmware under test in the main control chip 20 tests normally again using the current simulated key signal during the test, the test ends. In some embodiments, if the firmware under test in the main control chip 20 tests normally again using the current simulated key signal during the test, it is determined whether the current number of tests has reached the preset number. If yes, the test ends; if no, the test continues using the current simulated key signal to test the firmware under test in the main control chip 20 until the number of tests reaches the preset number. The test results for each test can be statistically analyzed, and the final determination of whether the firmware under test in the main control chip 20 is abnormal can be made based on the test results. For example, the percentage of normal test results out of a preset number of tests is counted. If this percentage is greater than a threshold, the test of the current analog button signal is considered normal; if the percentage is less than or equal to the threshold, the test of the current analog button signal is considered abnormal. Based on this, when the firmware under test in the main control chip 20 is found to be abnormal during the current analog button signal test, to avoid sporadic abnormalities, the firmware under test in the main control chip 20 is tested again using the current analog button signal until the preset number of tests is reached. This verifies whether the abnormality is caused by an inherent malfunction in the firmware under test or by other problems with the wired controller 100, thus improving the accuracy of the firmware test.

[0055] In some embodiments, the button control chip 10 is further configured to disable its capacitance detection function during testing; wherein the capacitance detection function is used to detect whether a physical button is pressed. Therefore, disabling the capacitance detection function of the button control chip 10 during testing prevents the actual button signal generated by the physical button being pressed from affecting the test.

[0056] In one application scenario, combined Figure 2 Explanation:

[0057] Upon power-up, the button control chip 10 enters the initialization phase, disabling the actual capacitance detection function. After disabling the actual capacitance detection function, the button control chip 10 is configured in analog mode, and then initialized as an I2C slave.

[0058] At the same time, the main control chip 20 is powered on and enters the initialization stage. The main control chip 20 is initialized as an I2C host, and interrupt handling is configured, and the UI (User Interface) application of the display screen 30 is loaded.

[0059] The button control chip 10 triggers the button signal generation function to generate simulated button signals, which in turn construct the corresponding data packets. Then, it triggers the communication function to send an interrupt signal to the main control chip 20.

[0060] The main control chip 20 performs interrupt processing. When an interrupt signal is detected, it sends an I2C read request to the button control chip 10.

[0061] The button control chip 10 responds to data and sends data packets to the main control chip 20.

[0062] The main control chip 20 processes the data packets, parses the operation corresponding to the simulated button signal, converts it into a UI event, performs a UI response operation, and sends updated display content to the display screen 30 so that the display screen 30 can update the display.

[0063] The button control chip 10 waits for a preset time before constructing the next simulated button signal data packet to test the firmware of the main control chip 20.

[0064] The above process is the normal procedure for the firmware under test to respond to the button signal by the main control chip 20. If an abnormality occurs during this process, it indicates that the firmware under test has a corresponding vulnerability. In this case, the corresponding log needs to be recorded as abnormal record data so that the firmware under test can be repaired.

[0065] In some embodiments, the firmware of the button control chip 10 is reconstructed. Specifically, during testing, its original capacitance detection function is first disabled, and then a programmable analog data generation logic is implanted. This logic will execute cyclically, actively sending a preset test data sequence (analog button signal sequence) to the main control chip 20. The construction of the analog data is based on the communication protocol: the state of multiple buttons is represented by a single byte of data bits, 0x00 when there is no operation and 0x1F when all buttons are pressed. Each test instruction consists of a data value and a duration (ms). Common operation use cases include, but are not limited to: single button short press (0x01, 100), double button short press (0x03, 100), single button long press (0x01, 1500). Abnormal test sequences are designed to break through the boundaries of conventional logic, such as simulating multiple button presses simultaneously (0x1F), simulating rapid key value switching caused by sliding (0x01→0x03→0x07), extremely high frequency clicks (0x01, 5), triggering non-existent buttons (0x20) or data boundary values ​​(0xFF), etc. All these regular and exceptional use cases are integrated into a randomly sampled set of test vectors for the program to call repeatedly. In the case of extremely high frequency clicks (0x01, 5), the 5 represents the duration of a single click, and the duration of the entire signal is greater than 5, such as 100, 200, or 500.

[0066] Finally, the firmware integrating the above logic is burned into the button control chip 10. After the wired controller 100 is powered on, the button control chip 10 automatically enters the autonomous test mode and continuously sends test sequences to the main control chip 20. The main control chip 20 runs the firmware under test and responds interactively on the display screen 30 accordingly. During the test, by monitoring whether the interface of the display screen 30 exhibits unexpected crashes, freezes, or lags, defects and vulnerabilities in the firmware under test of the main control chip 20 can be effectively located and repaired.

[0067] In this embodiment, a simulated button signal is generated by the button control chip 10 and sent to the main control chip 20. The simulated button signal is used to test the firmware under test in the main control chip 20, thereby eliminating the dependence on physical mechanical structure. The firmware under test in the main control chip 20 is tested through the interaction between the button control chip 10 and the main control chip 20 inside the controller 100. This verifies the robustness, fault tolerance and stability of the firmware under test in the main control chip 20, which can reduce testing costs and test cycle. In addition, the button control chip 10 can simulate more types of simulated button signals, such as a series of button signals from normal operation to abnormal button signals, which can improve the test coverage, execution efficiency and reliability in the test process.

[0068] See Figure 3 , Figure 3This is a schematic diagram of an embodiment of the wired controller testing system provided in this application. The wired controller testing system 1000 includes: a wired controller 100 and an image recognition device 200.

[0069] The wired controller 100 is as described in any embodiment of this application.

[0070] The image recognition device 200 is used to capture the images displayed on the screen 30 of the wired controller 100 during the testing process, and to determine whether the wired controller 100 is malfunctioning by recognizing the images displayed on the screen 30. During the testing of the wired controller 100, the image recognition device is simultaneously notified, informing it that the wired controller 100 has entered the testing phase. The image recognition device then activates its image recognition function to monitor the images displayed on the screen 30 of the wired controller 100 during the testing process, and determines whether the wired controller 100 is malfunctioning by recognizing the images displayed on the screen 30. For example, if unexpected crashes, freezes, or stutters are detected on the screen 30, the corresponding timestamp can be recorded for comparison with the timestamps in the logs of the wired controller 100, effectively locating and repairing defects and vulnerabilities in the firmware of the main control chip 20 under test.

[0071] See Figure 4 , Figure 4 This is a flowchart illustrating an embodiment of the wired controller testing method provided in this application. The wired controller is the wired controller 100 as described in any embodiment of this application. The testing method for the wired controller includes:

[0072] Step 41: During the test, the button control chip acquires simulated button signals, which are used to simulate the signals generated when a physical button is pressed.

[0073] Step 42: Send simulated button signals to the main control chip to test the firmware under test in the main control chip.

[0074] For details on the specific implementation of steps 41 to 42, please refer to the other embodiments, which will not be repeated here.

[0075] In this embodiment, a button control chip generates simulated button signals and sends them to the main control chip. The simulated button signals are then used to test the firmware under test in the main control chip, thus eliminating the reliance on physical mechanical structures. The in-line controller unit interacts with the button control chip and the main control chip to test the firmware under test in the main control chip, verifying the robustness, fault tolerance, and stability of the firmware under test in the main control chip. This reduces testing costs and testing cycles. Furthermore, the button control chip can simulate more types of simulated button signals, such as a range of button signals from normal operation to abnormal button signals, which improves test coverage, execution efficiency, and reliability during the testing process.

[0076] In summary, the wired controller testing method, wired controller, and wired controller testing system provided in this application utilize a button control chip to generate simulated button signals and send these signals to the main control chip. The simulated button signals are then used to test the firmware under test (DUT) within the main control chip. This eliminates reliance on physical mechanical structures. The testing of the DUT within the main control chip is achieved through interaction between the button control chip and the main control chip within the wired controller. This verifies the robustness, fault tolerance, and stability of the DUT within the main control chip, reducing testing costs and time. Furthermore, the button control chip can simulate a wider range of simulated button signals, from those for normal operation to those for abnormal operation, thus improving test coverage, execution efficiency, and reliability during the testing process.

[0077] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0078] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processing circuit component (processor) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wire controller characterized by, The wired controller includes: A button control chip is configured to: during testing, acquire simulated button signals from a set of simulated button signals, which are used to simulate signals generated when a physical button is pressed; the set of simulated button signals includes a first type of simulated button signals and a second type of simulated button signals; wherein the first type of simulated button signals is used to simulate signals generated by conventionally pressing the physical button, and the second type of simulated button signals is used to simulate signals generated by unconventional pressing of the physical button; the simulated button signals are constructed by the button control chip; the second type of simulated button signals includes: a fourth simulated button signal, a fifth simulated button signal, a sixth simulated button signal, a seventh simulated button signal, and an eighth simulated button signal; wherein the fourth simulated button signal is used to simulate signals generated by pressing at least three buttons, the fifth simulated button signal is used to simulate signals generated by continuously switching between pressing multiple buttons, the sixth simulated button signal is used to simulate signals generated by pressing a single button multiple times within a fourth duration, the seventh simulated button signal is used to simulate signals generated by pressing a test button, and the eighth simulated button signal is used to simulate data boundary signals, wherein the test button does not exist in the wired controller; The main control chip, connected to the button control chip, is configured to: receive the simulated button signal and use the simulated button signal to perform a stress test on the firmware under test in the main control chip; The button control chip is further configured to disable its capacitance detection function during testing; wherein the capacitance detection function is used to detect whether a physical button is pressed.

2. The drive-by-wire controller of claim 1, wherein, The button control chip is also configured to randomly acquire the simulated button signal from the set of simulated button signals during the test.

3. The drive-by-wire controller of claim 2, wherein, The testing process includes a first testing phase and a second testing phase. The button control chip is further configured to: in the first testing phase, randomly acquire the simulated button signal from the set of simulated button signals without repetition, until all the simulated button signals in the set of simulated button signals have been acquired. In the second test phase, the simulated key signals are again randomly selected from the set of simulated key signals without restriction.

4. The drive-by-wire controller of claim 1, wherein, The first type of simulated button signal includes: a first simulated button signal, a second simulated button signal, and a third simulated button signal; wherein, the first simulated button signal is used to simulate the signal generated when a single button is pressed for a first duration, the second simulated button signal is used to simulate the signal generated when a single button is pressed for a second duration, and the third simulated button signal is used to simulate the signal generated when two buttons are pressed simultaneously for a third duration, wherein the first duration is less than the second duration.

5. The drive-by-wire controller of claim 1, wherein, The main control chip is also configured to: when it detects an anomaly in the firmware under test in the main control chip due to the current simulated key signal, mark the current simulated key signal and terminate the current process; The firmware under test in the main control chip is tested again using the current simulated button signal until the preset number of tests is reached.

6. A wired controller testing system, characterized in that, The wired controller testing system includes: A wired controller, the wired controller being the wired controller as described in any one of claims 1-5; An image recognition device is used to capture the display screen image of the wired controller during the testing process, and to determine whether the wired controller is malfunctioning by recognizing the display screen image.

7. A test method for a wired controller, characterized in that, The wired controller includes: a button control chip and a main control chip, and the testing method for the wired controller includes: During testing, the button control chip acquires simulated button signals from a set of simulated button signals. These simulated button signals are used to simulate the signals generated when a physical button is pressed. The set of simulated button signals includes a first type of simulated button signal and a second type of simulated button signal. The first type of simulated button signal is used to simulate the signal generated by pressing the physical button normally, and the second type of simulated button signal is used to simulate the signal generated by pressing the physical button unconventionally. During testing, the capacitance detection function of the button control chip is disabled. The capacitance detection function is used to detect whether a physical button is pressed. The second type of simulated button signals includes: a fourth simulated button signal, a fifth simulated button signal, a sixth simulated button signal, a seventh simulated button signal, and an eighth simulated button signal. The fourth simulated button signal is used to simulate the signal generated by pressing at least three buttons. The fifth simulated button signal is used to simulate the signal generated by continuously switching between pressing multiple buttons. The sixth simulated button signal is used to simulate the signal generated by pressing a single button multiple times within a fourth time period. The seventh simulated button signal is used to simulate the signal generated by pressing a test button. The eighth simulated button signal is used to simulate a data boundary signal. The test button does not exist in the wired controller. The simulated button signal is sent to the main control chip, and the simulated button signal is used to perform a stress test on the firmware under test in the main control chip.

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