Flash memory grain testing method, electronic device, and computer-readable storage medium

Abstract

The application discloses a flash memory particle test method, an electronic device and a computer readable storage medium. The method comprises the following steps: obtaining a correlation relationship between an instantaneous degradation rate and a test temperature under a plurality of erasing and writing times; wherein, the error rate is obtained when the flash memory particle as a sample is subjected to erasing and writing test at different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the error rate when the erasing and writing times increase; obtaining a reference instantaneous degradation rate corresponding to a reference temperature and a reference erasing and writing time; determining an equivalent erasing and writing time under a target temperature based on the reference instantaneous degradation rate and the correlation relationship; wherein, the reference temperature is lower than the target temperature; and performing erasing and writing test on the flash memory particle to be tested at the target temperature according to the equivalent erasing and writing time. In the foregoing manner, the application can improve the efficiency of the flash memory particle test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of reliability testing, in particular to a flash memory particle testing method, an electronic device and a computer readable storage medium. BACKGROUND

[0002] As an important component of storage devices, flash memories have been widely used in the market, and therefore, the reliability of flash memory particles has been increasingly valued. Conventional testing methods usually perform erase-write testing on flash memory particles at ambient temperature. However, testing a large number of flash memory particles requires a large amount of time, which is difficult to meet the rapid research and production requirements. Therefore, how to improve the efficiency of flash memory particle testing has become a problem to be solved. SUMMARY

[0003] The technical problem solved by the present application is to provide a flash memory particle testing method, an electronic device and a computer readable storage medium, which can improve the efficiency of flash memory particle testing.

[0004] To solve the above technical problem, the first aspect of the present application provides a flash memory particle testing method, comprising: obtaining a correlation between instantaneous degradation rate and test temperature at a plurality of erase-write times; wherein the error rate is obtained when performing erase-write testing on flash memory particles as samples at different test temperatures, and the instantaneous degradation rate corresponds to the change rate of error rate when the erase-write times increase; obtaining a reference instantaneous degradation rate corresponding to a reference temperature and a reference erase-write time; determining an equivalent erase-write time at a target temperature based on the reference instantaneous degradation rate and the correlation; wherein the reference temperature is lower than the target temperature; performing erase-write testing on flash memory particles to be tested at the target temperature according to the equivalent erase-write time.

[0005] To solve the above technical problem, the second aspect of the present application provides an electronic device, comprising: a memory and a processor coupled to each other, wherein the memory stores program data, and the processor calls the program data to execute the method of the first aspect.

[0006] To solve the above technical problem, the third aspect of the present application provides a computer readable storage medium having program data stored thereon, wherein the program data is executed by a processor to implement the method of the first aspect.

[0007] The beneficial effects of this application are as follows: Unlike the prior art, this application obtains the correlation between the instantaneous degradation rate and the test temperature under different erase / write cycles. Specifically, when the flash memory chip used as a sample is erased and written at different test temperatures, the bit error rate that changes with the number of erase / write cycles can be obtained. The instantaneous degradation rate corresponds to the rate of change of the bit error rate with the number of erase / write cycles. The correlation can reflect the relationship between the instantaneous degradation rate and the temperature change under the same number of erase / write cycles when testing the sample. By obtaining the reference instantaneous degradation rate corresponding to the reference temperature and reference erase / write cycles, and calculating the erase / write cycles required at the target temperature to achieve the same test results based on the reference instantaneous degradation rate and its correlation, the equivalent erase / write cycles at a higher target temperature are obtained. Thus, by using the instantaneous degradation rate as an equivalent condition for erase / write cycles under low and high temperature conditions, the equivalent conditions can be determined more accurately by using the rate of change as a reference. The test method of erase / write testing at the target temperature according to the equivalent erase / write cycles is compared with the test method of erase / write testing at the reference temperature according to the reference erase / write cycles. At higher target temperatures, the number of erase / write cycles required for testing can be significantly reduced. Erase / write tests are then performed on a large batch of flash memory chips at the target temperature according to the equivalent erase / write cycles to obtain test results, effectively improving the efficiency of flash memory chip testing. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0009] Figure 1 This is a flowchart illustrating one embodiment of the flash memory chip testing method of this application;

[0010] Figure 2 This is a flowchart illustrating another embodiment of the flash memory chip testing method of this application;

[0011] Figure 3 This is a schematic diagram of the structure of one embodiment of the electronic device of this application;

[0012] Figure 4 This is a schematic diagram of one embodiment of the computer-readable storage medium of this application. Detailed Implementation

[0013] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application, and the embodiments can be combined adaptively. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0014] The terms "system" and "network" are often used interchangeably herein. The term "and / or" herein is only used to describe associated objects, which means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects. In addition, "multiple" herein means two or more than two.

[0015] The flash memory particle test method provided by the present application is used to test the reliability of the flash memory particle, and the corresponding execution subject is a processing unit capable of data processing.

[0016] It can be understood that the bit error rate (BER) obtained in the flash memory particle test process is an important indicator for measuring the reliability of the flash memory particle. The bit error rate represents the proportion of the number of error bits to the total number of bits when reading data. One complete operation of writing and erasing the storage unit corresponds to one PE (Program / Erase), and the number of erasing and writing is increased by one for each PE cycle. The instantaneous degradation rate corresponds to the BER change rate caused by each PE cycle.

[0017] Please refer to Figure 1 , Figure 1 is a flowchart of an embodiment of the flash memory particle test method of the present application. The method comprises:

[0018] S101: Obtain the correlation between the instantaneous degradation rate and the test temperature at different erasing and writing times; wherein, the bit error rate is obtained when the flash memory particle as a sample is tested at different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the bit error rate with the increase of the erasing and writing times.

[0019] Specifically, the correlation between the instantaneous degradation rate and the test temperature at different erasing and writing times is obtained, wherein, the bit error rate changing with the increase of the erasing and writing times can be obtained when the flash memory particle as a sample is tested at different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the bit error rate with the increase of the erasing and writing times.

[0020] It can be understood that the correlation relationship can reflect the correlation between the instantaneous degradation rate and the temperature change at the same number of erasing and writing when the sample is tested, and the instantaneous degradation rate corresponding to the number of erasing and writing changes with the test temperature.

[0021] In an embodiment, a flash memory particle corresponding to the sample to be tested is obtained, and sample test results when the flash memory particle as the sample is tested at different test temperatures are extracted, wherein the sample test results include the error rate corresponding to each number of erasing and writing as the number of erasing and writing increases. Based on the sample test results at multiple test temperatures, the correlation relationship between the instantaneous degradation rate and the test temperature at the same number of erasing and writing is determined.

[0022] In an embodiment, a proportion of flash memory particles from the flash memory particles to be tested is obtained as samples, and erasing and writing tests are performed on the flash memory particles as the samples at different test temperatures to obtain sample test results, wherein each test temperature corresponds to at least one flash memory particle as the sample. The error rate change rate corresponding to the error rate in the sample test results as the number of erasing and writing increases is determined to obtain the instantaneous degradation rate. The correlation relationship between the instantaneous degradation rate and the test temperature at the same number of erasing and writing is determined by using the instantaneous degradation rates corresponding to the same number of erasing and writing at multiple test temperatures.

[0023] It can be understood that it is generally believed that flash memory particles produced by the same production object have close reliability, and therefore, sample test results of a certain batch can be extracted for multiple batches of flash memory particles of the same production object, without the need to select samples for testing for each batch. Therefore, different production objects correspond to a plurality of correlation relationships between the instantaneous degradation rate and the test temperature at the same number of erasing and writing, and each production object can reselect flash memory particles as samples for retesting at a preset time interval, so as to update the correlation relationship between the instantaneous degradation rate and the test temperature at the same number of erasing and writing.

[0024] In some implementation scenarios, based on the sample test results at multiple test temperatures, a regression equation of the instantaneous degradation rate and the test temperature at the same number of erasing and writing is constructed, so as to determine the correlation relationship between the instantaneous degradation rate and the test temperature at different numbers of erasing and writing.

[0025] In some implementation scenarios, a mathematical conversion relationship corresponding to the error rate change with the number of erasing and writing is determined based on the sample test results, and the instantaneous degradation rate is determined after derivation of the corresponding mathematical conversion relationship, so as to fit the correlation relationship between the instantaneous degradation rate and the test temperature based on the instantaneous degradation rates corresponding to the same number of erasing and writing at multiple test temperatures.

[0026] S102: Obtain a reference instantaneous degradation rate corresponding to a reference temperature and a reference erase-write number, and determine an equivalent erase-write number at a target temperature based on the reference instantaneous degradation rate and the correlation relationship; wherein the reference temperature is lower than the target temperature.

[0027] Specifically, the reference instantaneous degradation rate corresponding to the reference temperature and the reference erase-write number is obtained, and the erase-write number at the target temperature when reaching the same test effect is solved based on the reference instantaneous degradation rate and the correlation relationship, so as to obtain the equivalent erase-write number at the target temperature of higher temperature.

[0028] It should be noted that by taking the instantaneous degradation rate as the equivalent condition of the erase-write number under low-temperature and high-temperature conditions, the equivalent condition can be more accurately determined by taking the change rate as the reference, the test mode of performing erase-write test according to the equivalent erase-write number at the target temperature is equivalent to the test mode of performing erase-write test according to the reference erase-write number at the reference temperature, and the erase-write number required during test can be significantly reduced at the higher target temperature.

[0029] In an embodiment, the reference temperature and the reference erase-write number are obtained, the instantaneous degradation rate corresponding to the reference temperature and the reference erase-write number is determined as the reference instantaneous degradation rate, the target temperature is obtained, the correlation relationship between the instantaneous degradation rate and the test temperature under different erase-write numbers is utilized to determine the instantaneous degradation rate corresponding to multiple erase-write numbers at the target temperature, and the erase-write number corresponding to the instantaneous degradation rate screened out is taken as the equivalent erase-write number.

[0030] In some implementation scenarios, the target temperature is pre-confirmed, so as to draw a change curve corresponding to the correlation relationship by utilizing the correlation relationship between the instantaneous degradation rate and the test temperature under different erase-write numbers, extract the instantaneous degradation rate from the change curve according to the target temperature, and compare the instantaneous degradation rate with the reference instantaneous degradation rate, so as to screen out the equivalent erase-write number.

[0031] In an embodiment, the reference temperature and the reference erase-write number are obtained, the instantaneous degradation rate corresponding to the reference temperature and the reference erase-write number is determined as the reference instantaneous degradation rate, the correlation relationship between the instantaneous degradation rate and the test temperature under different erase-write numbers is utilized to determine a candidate temperature satisfying the reference instantaneous degradation rate and a candidate erase-write number corresponding to the candidate temperature, wherein the candidate temperature is higher than the reference temperature, the error code rate of erase-write test at the candidate temperature according to the candidate erase-write number is obtained, and the error code rate of erase-write test at the reference temperature according to the reference erase-write number is obtained, so as to screen out the target temperature and the equivalent erase-write number from the candidate temperature and the candidate erase-write number corresponding to the candidate temperature based on the error code rate.

[0032] In some implementation scenarios, the reference instantaneous degradation rate and the correlation between the instantaneous degradation rate and the test temperature at different erase-write times are used for indexing to determine a candidate temperature that meets the reference instantaneous degradation rate and has a temperature higher than the reference temperature, and obtain the erase-write time corresponding to the candidate temperature as a candidate erase-write time, and then obtain the error rate of the erase-write test at the candidate temperature according to the candidate erase-write time, and the error rate of the erase-write test at the reference temperature according to the reference erase-write time, take the candidate temperature with the minimum error rate deviation as the target temperature, and obtain the corresponding candidate erase-write time as the equivalent erase-write time.

[0033] S103: Perform erase-write test on the flash memory particles to be tested at the target temperature according to the equivalent erase-write time.

[0034] Specifically, the erase-write test is performed on a large batch of flash memory particles to be tested at the target temperature according to the equivalent erase-write time, so as to obtain the test result.

[0035] It can be understood that when the equivalent erase-write time required under the condition of relatively high temperature is obtained, the target temperature can be set and the erase-write test is performed on a large batch of flash memory particles to be tested at the target temperature according to the equivalent erase-write time, which is equivalent to the result of the erase-write test at the reference temperature according to the reference erase-write time, thereby greatly reducing the test time and improving the test efficiency.

[0036] Further, the reference temperature is usually the ambient temperature of the flash memory particles in actual use, which is usually room temperature, and the reference erase-write time is usually a value close to the maximum erase-write time concerned in the actual use of the flash memory particles, and the target temperature is usually a high-temperature environment, which accelerates charge loss and tunnel oxide layer damage through high-temperature stress, and significantly shortens the test period.

[0037] In some implementation scenarios, assuming that the reference temperature is 25℃, the reference erase-write time is 5000 times, the target temperature is 85℃, and the equivalent erase-write time is finally obtained as 2000 times, thereby reducing the original test period to 40% of the original, thereby effectively improving the test efficiency.

[0038] In some implementation scenarios, assuming that the reference temperature is 20℃, the reference erase-write time is 6000 times, the target temperature is 90℃, and the equivalent erase-write time is finally obtained as 1500 times, thereby reducing the original test period to 25% of the original, thereby significantly improving the test efficiency.

[0039] It should be noted that the flash memory particles are particles including multiple layers of storage units, and the multiple test temperatures are sorted according to temperature, and at least one temperature difference corresponds between each two adjacent test temperatures.

[0040] Specifically, the multi-layer storage unit particles include, but are not limited to, multi-level cell (MLC) particles, triple-level cell (TLC) particles, and quad-level cell (QLC) particles, wherein the error rate of the multi-layer storage unit particles increases exponentially with the increase of the erase test, thereby better adapting to the scenario with reference to the instantaneous degradation rate, improving the accuracy of the test, and the test temperature at least includes a normal temperature interval and a high temperature interval, and a temperature difference is set between the temperatures in order of temperature.

[0041] In some implementation scenarios, the same temperature difference is set between all adjacent test temperatures, so that the test temperatures are uniformly distributed, thereby comprehensively testing the flash memory particles as samples at multiple test temperatures.

[0042] In some implementation scenarios, a first temperature difference is set when the temperature is lower than a first temperature, a second temperature difference is set when the temperature is between the first temperature and a second temperature, and a third temperature difference is set when the temperature is higher than the second temperature, wherein the first temperature difference and the third temperature difference are less than the second temperature difference, wherein the test temperature lower than the first temperature is the normal temperature, and the test temperature higher than the second temperature is the high temperature, a smaller temperature difference is set for the temperature interval of interest, thereby obtaining more test results that can be analyzed, and a larger temperature difference is set for the temperature interval of the transition stage, thereby reducing the time and cost of testing the samples.

[0043] The above scheme obtains the correlation between the instantaneous degradation rate and the test temperature at different erase times, wherein when the flash memory particles as samples are subjected to erase test at different test temperatures, the error rate that changes with the increase of the erase times can be obtained, the instantaneous degradation rate corresponds to the change rate of the error rate when the erase times increase, and the correlation can reflect the correlation between the instantaneous degradation rate and the temperature change at the same erase times when the samples are tested. The reference instantaneous degradation rate corresponding to the reference temperature and the reference erase times is obtained, the erase times at the target temperature to achieve the same test effect are solved based on the reference instantaneous degradation rate and the correlation, the equivalent erase times at the target temperature of a higher temperature are obtained, thereby taking the instantaneous degradation rate as the equivalent condition of the erase times under low temperature and high temperature conditions, the change rate is taken as a reference to more accurately determine the equivalent condition, the test mode of performing erase test at the equivalent erase times at the target temperature is equivalent to the test mode of performing erase test at the reference erase times at the reference temperature, and the erase times required for testing at a higher target temperature can be significantly reduced. A large number of flash memory particles to be tested are subjected to erase test at the equivalent erase times at the target temperature, thereby obtaining test results, and the efficiency of flash memory particle testing is effectively improved.

[0044] Referring to Figure 2 , Figure 2 is a flowchart of another embodiment of the flash memory grain test method of the present application, which comprises:

[0045] S201: Obtain the correlation between the instantaneous degradation rate and the test temperature under multiple erase-write times; wherein, the error rate is obtained when the flash memory grain as a sample is tested under different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the error rate when the erase-write times increase.

[0046] Specifically, the correlation between the instantaneous degradation rate and the test temperature under different erase-write times is obtained, wherein, the error rate that changes with the increase of the erase-write times can be obtained when the flash memory grain as a sample is tested under different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the error rate when the erase-write times increase.

[0047] It should be noted that the correlation is obtained based on the following steps: the flash memory grain as a sample is tested under different test temperatures according to different erase-write times, and the sample test results under each test temperature are obtained; based on the sample test results under different test temperatures, the instantaneous degradation rate under any erase-write time is determined, and the correlation between the instantaneous degradation rate and the test temperature is obtained.

[0048] Specifically, the flash memory grain as a sample is tested under different test temperatures in an increasing manner from zero to the maximum erase-write times, and the sample test results under each test temperature are obtained. Each test temperature corresponds to at least one flash memory grain as a sample, and the sample test results include the corresponding error rate at each erase-write time when the erase-write times increase.

[0049] Further, based on the sample test results under different test temperatures, the instantaneous degradation rate under any erase-write time is determined, so that for multiple different erase-write times, the correlation between the instantaneous degradation rate and the test temperature is determined based on the instantaneous degradation rate under the same erase-write time, and finally the correlation between the instantaneous degradation rate and the test temperature under multiple erase-write times is obtained, improving the comprehensiveness and accuracy of the correlation.

[0050] Optionally, the flash memory grain as a sample is pre-screened to ensure that the number deviation of the number of bad blocks is less than a number deviation threshold, thereby controlling the test error caused by the number of bad blocks.

[0051] It should be noted that, based on the sample test results at different test temperatures, the instantaneous degradation rate at any number of erasing and writing times is determined, and the correlation relationship of the instantaneous degradation rate with the test temperature is obtained, including: based on the sample test results at each test temperature, the nonlinear change rule of the error rate with the increase of the number of erasing and writing times at each test temperature is determined, and the nonlinear change rule is used to determine the instantaneous degradation rate at any number of erasing and writing times; a nonlinear degradation model is obtained, based on the instantaneous degradation rates at different test temperatures corresponding to the same number of erasing and writing times, the target parameters of the nonlinear degradation model are determined, and the nonlinear degradation model and the corresponding target parameters are used to determine the correlation relationship of the instantaneous degradation rate with the test temperature.

[0052] Specifically, based on the sample test results at each test temperature, the change rule of the error rate with the increase of the number of erasing and writing times is regressed, and the nonlinear change rule of the error rate with the increase of the number of erasing and writing times at each test temperature is determined. Wherein, the nonlinear change rule can represent the mathematical conversion relationship between the error rate and the number of erasing and writing times, so as to determine the instantaneous degradation rate at any number of erasing and writing times by deriving the corresponding mathematical conversion relationship. After the same processing is performed on the sample test results at all test temperatures, the instantaneous degradation rates at any number of erasing and writing times corresponding to different test temperatures can be obtained.

[0053] Further, a nonlinear degradation model is obtained, the nonlinear degradation model is used to represent the relationship between the instantaneous degradation rate and the temperature, based on the instantaneous degradation rates at different test temperatures corresponding to the same number of erasing and writing times, the parameters in the nonlinear degradation model are solved, the target parameters of the nonlinear degradation model are determined, and the nonlinear degradation model and the corresponding target parameters are used to determine the correlation relationship of the instantaneous degradation rate with the test temperature, so as to improve the accuracy of the correlation relationship by constructing the nonlinear degradation model.

[0054] For the convenience of description, the present application uses a specific test example for description, selects a plurality of flash memory particles as samples, and fixes the same storage block number in each sample as a test object, so as to control the variables in the flash memory particles. n (n>3) test temperatures are set , ... ), and PE cycle test is performed at each test temperature, the PE test range covers (0, PEmax), and the sampling interval is 500 times of PE, wherein PEmax represents the maximum number of erasing and writing times. Wherein, in different implementation scenarios, the specific parameters involved in the present test example can be selected by the user, and the present application does not make specific limitation.

[0055] It can be understood that, for any selected test temperature (1 < m < n), the sample test data of BER changing with PE times can be obtained by experimental measurement. Based on the data, a nonlinear regression model between BER and PE times at the temperature can be established to obtain the nonlinear change rule and quantitatively characterize the reliability degradation rule of the storage unit at the temperature condition. The nonlinear regression model is expressed by the following formula:

[0056] (1)

[0057] wherein, BER is the bit error rate, N is the PE times (0 < N ≤ PEmax), and are the parameters to be fitted.

[0058] Further, the linear fitting of the logarithmic transformation of formula (1) can calculate the parameters of and . Wherein, the process of logarithmic transformation is expressed by the following formula:

[0059] (2)

[0060] It can be understood that the instantaneous degradation rate of PE for M times (0 < M ≤ PEmax, M ≠ N) at the temperature is calculated by the derivative. Wherein, the instantaneous degradation rate is expressed by the following formula:

[0061] (3)

[0062] Therefore, the instantaneous degradation rate of PE for M times at different temperatures , ... can be calculated.

[0063] According to the Arrhenius equation, a nonlinear degradation model of TLC particles based on temperature dependence is established, and the relationship between the instantaneous degradation rate and the test temperature T is expressed by the following formula:

[0064] (4)

[0065] wherein, is the activation energy, is the Boltzmann constant, is the pre-exponential factor. Based on the same batch of flash memory particles, the PE accelerated aging experiment with multiple temperature gradients is carried out, and the model parameters and are fitted, wherein, the solving process of the above formula (4) is the construction process of the nonlinear degradation model.​​

[0066] Linearize the Arrhenius equation, take the natural logarithm:

[0067] (5)

[0068] Take as the vertical axis, as the horizontal axis, the data should be linear, and the slope m and intercept b can be obtained by linear regression fitting:

[0069] (6)

[0070] (7)

[0071] According to formula (6) and formula (7), the activation energy and the pre-exponential factor can be calculated, so as to determine the target parameters of the nonlinear degradation model. Therefore, the correlation between the instantaneous degradation rate of PE as Mth power and the test temperature T can be obtained.

[0072] S202: Obtain the reference instantaneous degradation rate corresponding to the reference temperature and the reference erase-write times, and determine the equivalent erase-write times at the target temperature based on the reference instantaneous degradation rate and the correlation. Wherein, the reference temperature is lower than the target temperature.

[0073] Specifically, the reference instantaneous degradation rate corresponding to the reference temperature and the reference erase-write times is obtained, and the erase-write times at the target temperature when reaching the same test effect are solved based on the reference instantaneous degradation rate and the correlation, to obtain the equivalent erase-write times at the target temperature. Wherein, the reference temperature is lower than the target temperature, the high-temperature stress accelerates the loss of electric charge and the damage of the tunnel oxide layer, significantly shortens the test period, and obtains the equivalent erase-write times which are less than the reference erase-write times.

[0074] In an embodiment, obtaining the reference instantaneous degradation rate corresponding to the reference temperature and the reference erase-write times, and determining the equivalent erase-write times at the target temperature based on the reference instantaneous degradation rate and the correlation, comprises: obtaining a nonlinear degradation model matched with the reference erase-write times, determining the reference instantaneous degradation rate by using the corresponding nonlinear degradation model; and determining the equivalent erase-write times at the target temperature corresponding to the reference instantaneous degradation rate when being equivalent by using the target temperature and the correlation.

[0075] ​Specifically, a nonlinear degradation model matched with the reference erase-write times is acquired, and the corresponding reference instantaneous degradation rate at the reference temperature is determined by using the corresponding nonlinear degradation model, so as to acquire the reference instantaneous degradation rate that can be used as a reference at the equivalent time through the nonlinear degradation model. The reference temperature is usually normal temperature, and the reference erase-write times are usually selected from the erase-write times having the correlation between the instantaneous degradation rate and the test temperature.

[0076] Further, the degradation degree corresponding to the reference instantaneous degradation rate is equivalent based on the target temperature and the correlation between the instantaneous degradation rate and the test temperature at different erase-write times, the equivalent erase-write times corresponding to the reference instantaneous degradation rate at the target temperature are determined when the reference instantaneous degradation rate is equivalent, so as to take the reference instantaneous degradation rate as a reference, and determine the equivalent erase-write times closest to the degradation degree at the target temperature based on the correlation at different erase-write times, improve the precision of the equivalent erase-write times, and make the test effect of the erase-write test at the target temperature according to the equivalent erase-write times as close as possible to the test effect of the erase-write test at the reference temperature according to the reference erase-write times.

[0077] Optionally, the equivalent PE model is established, so that the reference erase-write times at the reference temperature are converted into the equivalent erase-write times at the target temperature. According to formula (4), that is, the instantaneous degradation rate of PE times is calculated by using the nonlinear degradation model when the reference temperature is , 1 :

[0078] (8)

[0079] It can be understood that the target temperature to be equivalent is , 1 , and the equivalent erase-write times are , then the relationship between the instantaneous degradation rate and is:

[0080] (9)

[0081] According to formula (1) to formula (3), the nonlinear relationship model of the BER at the target temperature and the PE times is established, and the instantaneous degradation rate of PE times at the target temperature is calculated by derivation. is:

[0082] (10)

[0083] According to formula (9), the equivalent erase-write times at the target temperature are calculated as: ​​​​

[0084] (11)

[0085] wherein, is the equivalent program-erase number, is the reference temperature, and is the target parameter of the non-linear relationship model of BER and PE number at the target temperature.

[0086] S203: performing erase test on the flash memory particles as samples at the reference temperature according to the reference program-erase number to obtain the reference test result, and performing erase test on the flash memory particles as samples at the target temperature according to the equivalent program-erase number to obtain the equivalent test result.

[0087] Specifically, performing erase test on the flash memory particles as samples at the reference temperature according to the reference program-erase number can obtain the bit error rate changing with the increase of the program-erase number as the reference test result, and performing erase test on the flash memory particles as samples at the target temperature according to the equivalent program-erase number can obtain the bit error rate changing with the increase of the program-erase number as the equivalent test result.

[0088] Optionally, a plurality of test samples are selected, and each of the test samples is executed times of PE cycles at the reference temperature and executed times of PE cycles at the target temperature . Subsequently, a preset proportion of the storage blocks are randomly extracted, and the BER of all the pages in each block is calculated to evaluate whether the equivalent program-erase number is accurate.

[0089] S204: verifying the equivalent program-erase number based on the reference test result and the equivalent test result.

[0090] Specifically, based on the reference test result and the equivalent test result, whether the equivalent program-erase number selected at the target temperature is accurate is evaluated, so that the result error between the reference test result and the equivalent test result is utilized to verify whether the equivalent program-erase number is accurate, so as to guarantee the accuracy of the equivalent program-erase number before performing erase test on a large number of flash memory particles formally.

[0091] It can be understood that the verification of the equivalent program-erase number can utilize the distribution deviation between the reference test result and the equivalent test result, or utilize the numerical deviation between the reference test result and the equivalent test result, or utilize the distribution deviation and the numerical deviation together.

[0092] Preferably, verifying the equivalent erase-write times based on the reference test result and the equivalent test result comprises: obtaining the error rate distribution of the reference test result and the equivalent test result, determining the distribution deviation based on the error rate distribution, obtaining the final test error rate of the reference test result and the equivalent test result, and determining the numerical deviation based on the test error rate; and verifying the equivalent erase-write times based on the distribution deviation and the corresponding distribution deviation threshold and the numerical deviation and the corresponding numerical deviation threshold.

[0093] Specifically, the error rate distribution of the reference test result and the error rate distribution of the equivalent test result are obtained, and whether the two groups of test data come from similar distributions is determined based on the error rate distribution of the reference test result and the error rate distribution of the equivalent test result, and the distribution error is determined.

[0094] Further, the final test error rate of the reference test result and the final test error rate of the equivalent test result are obtained, and the test error rate deviation between the two groups of test data is calculated based on the test error rate of the reference test result and the test error rate of the equivalent test result, and the numerical deviation is obtained.

[0095] It can be understood that the relationship between the distribution deviation and the corresponding distribution deviation threshold is determined, and the relationship between the numerical deviation and the corresponding numerical deviation threshold is determined, and if the distribution deviation and the numerical deviation are within the allowable error range, it is determined that the equivalent erase-write times are verified.

[0096] In some implementation scenarios, Kolmogorov-Smirnov (K-S) test is used to determine whether the two groups of BER data come from the same distribution, and the formula corresponding to the K-S test is as follows:

[0097] (12)

[0098] wherein, and are the cumulative distribution functions of the two groups of data, is a statistic quantity, which is the distribution deviation, and whether the distribution deviation is less than the distribution deviation threshold is determined. In other implementation scenarios, the distribution deviation can also be determined by an empirical distribution function or other ways, which are not limited in the present application.

[0099] In some implementation scenarios, the mean square error (MSE) corresponding to the final test error rate of the two groups of test data is calculated respectively, and the formula corresponding to the MSE is as follows:

[0100] (13)

[0101] wherein, and are the final test error rates of the two groups of test data, respectively. and The bit error rate under the secondary PE cycle, n is the number of samples. Take MSE as the numerical deviation, if MSE is within the allowable error range, it is considered consistent. In other implementation scenarios, the numerical deviation can also be determined by calculating the mean absolute error (MAE) and other methods, which are not limited in the present application.

[0102] It can be understood that, based on the reference test result and the equivalent test result, verifying the equivalent erase-write times further includes: in response to the equivalent erase-write times verification failing, adjusting the target temperature, determining the equivalent erase-write times at the updated target temperature based on the reference instantaneous degradation rate and the correlation; returning to the step of erasing and writing the flash memory particles as samples at the target temperature according to the equivalent erase-write times to obtain the equivalent test result.

[0103] Specifically, when the equivalent erase-write times verification fails, the target temperature is adjusted, so as to re-solve the erase-write times at the target temperature to achieve the same test effect based on the reference instantaneous degradation rate and the correlation, determine the equivalent erase-write times at the updated target temperature, and re-erase and write the flash memory particles as samples at the target temperature according to the equivalent erase-write times to obtain the equivalent test result, so as to verify the equivalent erase-write times again until the equivalent erase-write times that can pass the verification are obtained, thereby guaranteeing the sustainability and reliability of the test.

[0104] Optionally, when the target temperature before adjustment is greater than the first temperature threshold, the target temperature is adjusted lower according to the first preset temperature difference, and when the target temperature before adjustment is less than or equal to the second temperature threshold, the target temperature is adjusted higher according to the second preset temperature difference, so as to control the change trend of the target temperature, find the target temperature with better equivalent effect and the corresponding equivalent erase-write times, and improve the accuracy of the equivalent.

[0105] S205: Erasing and writing the flash memory particles to be tested at the target temperature according to the equivalent erase-write times.

[0106] Specifically, erasing and writing a large number of flash memory particles to be tested at the target temperature according to the equivalent erase-write times, so as to obtain the test result.

[0107] It should be noted that the flash memory particle is a particle including a plurality of layers of storage units, the plurality of test temperatures are arranged according to temperature, and at least one temperature difference is arranged between each two adjacent test temperatures. The particle including a plurality of layers of storage units includes but is not limited to a Multi-Level Cell (MLC) particle, a Triple-Level Cell (TLC) particle, and a Quad-Level Cell (QLC) particle, and at least one temperature difference is arranged between the test temperatures arranged according to temperature in turn.

[0108] Please refer to Figure 3 , Figure 3 is a structural schematic diagram of an embodiment of an electronic device of the present application. The electronic device 30 includes a memory 301 and a processor 302 coupled with each other. The memory 301 stores program data (not shown in the figure), and the processor 302 invokes the program data to implement the method in any of the above embodiments. For related content, please refer to the detailed description of the above method embodiments, which will not be repeated here.

[0109] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of an embodiment of a computer readable storage medium of the present application. The computer readable storage medium 40 stores program data 400. When the program data 400 is executed by a processor, the method in any of the above embodiments is implemented. For related content, please refer to the detailed description of the above method embodiments, which will not be repeated here.

[0110] It should be noted that the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the present embodiment scheme.

[0111] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0112] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods of the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0113] The above only describes the embodiments of the present application, and does not limit the protection scope of the present application. Any equivalent structure or equivalent flow transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the protection scope of the present application.

Claims

1. A flash memory die test method, comprising: The method comprises: obtaining a correlation between the instantaneous degradation rate and the test temperature at multiple erase-write times; wherein the error rate is obtained when the flash memory particles as samples are subjected to erase-write test at different test temperatures, and the instantaneous degradation rate corresponds to the change rate of the error rate when the erase-write times increase; the correlation is obtained based on the following steps: the flash memory particles as samples are subjected to erase-write test at different erase-write times at different test temperatures to obtain sample test results at each test temperature; based on the sample test results at each test temperature, a nonlinear change rule of the error rate when the erase-write times increase is determined, and the instantaneous degradation rate at any erase-write time is determined by using the nonlinear change rule; a nonlinear degradation model is obtained, the target parameters of the nonlinear degradation model are determined based on the instantaneous degradation rates at different test temperatures corresponding to the same erase-write time, and the correlation between the instantaneous degradation rate and the test temperature is determined by using the nonlinear degradation model and the corresponding target parameters; obtaining a reference instantaneous degradation rate corresponding to a reference temperature and a reference erase-write time, and determining an equivalent erase-write time at a target temperature based on the reference instantaneous degradation rate and the correlation; wherein the reference temperature is lower than the target temperature; performing erase-write test on the flash memory particles to be tested at the target temperature according to the equivalent erase-write time.

2. The flash memory device testing method of claim 1, wherein, The method comprises: obtaining a reference instantaneous degradation rate corresponding to a reference temperature and a reference erase-write time, and determining an equivalent erase-write time at a target temperature based on the reference instantaneous degradation rate and the correlation; wherein the reference temperature is lower than the target temperature; performing erase-write test on the flash memory particles to be tested at the target temperature according to the equivalent erase-write time.

3. The flash memory device testing method of claim 1, wherein, The method further comprises, before performing erase-write test on the flash memory particles to be tested at the target temperature according to the equivalent erase-write time: performing erase-write test on the flash memory particles as samples at the reference temperature according to the reference erase-write time to obtain a reference test result, and performing erase-write test on the flash memory particles as samples at the target temperature according to the equivalent erase-write time to obtain an equivalent test result; verifying the equivalent erase-write time based on the reference test result and the equivalent test result.

4. The flash memory device testing method of claim 3, wherein, The method comprises: obtaining the error rate distribution of the reference test result and the equivalent test result, determining the distribution deviation based on the error rate distribution, obtaining the final test error rate of the reference test result and the equivalent test result, and determining the numerical deviation based on the test error rate; verifying the equivalent erase-write time based on the distribution deviation and the corresponding distribution deviation threshold, and the numerical deviation and the corresponding numerical deviation threshold.

5. The flash memory device testing method of claim 3, wherein, The verifying the equivalent program / erase cycles based on the reference test result and the equivalent test result further comprises: in response to the equivalent program / erase cycles verification failing, adjusting the target temperature, determining equivalent program / erase cycles at an updated target temperature based on the reference instantaneous degradation rate and the correlation; returning to the step of erasing the flash memory particles as samples at the target temperature according to the equivalent program / erase cycles to obtain the equivalent test result.

6. The flash memory die test method of any of claims 1-5, wherein, The flash memory particles are particles including multiple layers of storage units, and the multiple test temperatures are arranged according to temperature, and at least one temperature difference corresponds between each two adjacent test temperatures.

7. An electronic device, comprising: comprise: a memory and a processor coupled to each other, wherein the memory stores program data, and the processor invokes the program data to execute the method according to any one of claims 1-6.

8. A computer readable storage medium having stored thereon program data, wherein, The program data is executed by the processor to implement the method according to any one of claims 1-6.

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