Super capacitor charging and discharging circuit and method with low power consumption and hysteresis control

Abstract

The invention relates to the field of power management, discloses a low-power-consumption super-capacitor charging and discharging circuit with hysteresis control and a method, and aims to solve the problems of repeated on-off of power supply output and oscillation caused by small voltage fluctuation of a super-capacitor near a discharging critical voltage point. The circuit comprises a main discharge loop formed by a P-type MOS tube, and a hysteresis discharge unit. The hysteresis discharge unit comprises a voltage detection circuit composed of at least two voltage stabilizing diodes and a voltage divider which are connected in series, wherein the output of the voltage detection circuit controls a first control tube; the first control tube is used for controlling the on-off of the P-type MOS tube; the input end of the bypass control unit is connected with the grid electrode of the P-type MOS tube, and the output path of the bypass control unit is connected with the voltage stabilizing diode in the voltage detection circuit in parallel. By dynamically changing the detection threshold value, a determined voltage hysteresis interval is formed, circuit oscillation is effectively avoided, and the stability and reliability of the system are improved.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a low-power supercapacitor charging and discharging circuit and method with hysteresis control. Background Technology

[0002] With the widespread adoption of wireless communication technologies such as GPRS, NB-IoT, and 4G / 5G, IoT technology is being extensively applied to the data-driven upgrades of various traditional devices, such as enabling remote automatic meter reading in the field of natural gas metering. In these application scenarios, IoT modules generate peak current demands far exceeding their standby power consumption during data transmission. Supercapacitors, due to their superior characteristics such as fast charging speed, long cycle life, strong high-current discharge capability, high power density, and wide operating temperature range, have become ideal energy storage components for addressing such instantaneous high power consumption demands.

[0003] However, in the current technology for the application of supercapacitors, the design focus is generally on the management and protection of the charging stage, such as achieving constant current and constant voltage charging and preventing overvoltage charging. In the more critical discharge stage, there is a general lack of sophisticated and effective response and protection mechanisms.

[0004] This "heavy charging, light discharging" design approach has revealed many problems in practical applications: First, the power supply stability is poor. The discharge curve of a supercapacitor is not linear. When its voltage drops to a certain percentage of its initial voltage (e.g., 50%-70%), the effect of its equivalent series resistance becomes significant, and the output power and current capacity decrease dramatically. When IoT modules perform critical tasks such as data acquisition, processing, and uploading, if the supercapacitor voltage happens to be in this range, it may be unable to provide a stable operating voltage, leading to data transmission interruptions, device restarts, or data errors.

[0005] Second, there are serious safety hazards and risks of lifespan degradation. Due to the lack of an active discharge cutoff mechanism, supercapacitors are extremely prone to over-discharge. Over-discharge not only leads to irreversible capacity decay and significantly shortens its lifespan, but more seriously, it may damage its internal electrode structure, triggering internal short circuits or uncontrolled chemical reactions, resulting in serious safety accidents such as smoke, fire, or even explosion.

[0006] Third, insufficient discharge control precision. In some applications of intelligent sensors or precision instruments with stringent requirements on the supply voltage range, simple discharge control circuits struggle to achieve precise start-up and shutdown voltage control. For example, if only a single voltage threshold is set to control on / off switching, minute fluctuations in the supercapacitor voltage around that threshold can cause the discharge circuit to frequently switch on and off, resulting in a "circuit oscillation" phenomenon. This oscillation not only impacts the load equipment but also damages the supercapacitor itself and reduces the efficient utilization of energy.

[0007] Therefore, existing technologies have significant shortcomings in ensuring that supercapacitors can operate efficiently and safely throughout the entire discharge cycle and provide high-precision voltage control. There is an urgent need for a technical solution that can simultaneously address the issues of power supply stability, over-discharge protection, and precise hysteresis control. Summary of the Invention

[0008] The technical problem to be solved by this invention is that existing supercapacitor applications generally lack accurate and flexible discharge response protection mechanisms. When faced with over-discharge, the supercapacitor capacity is prone to irreversible decay, shortened service life, and may cause power supply instability or safety hazards.

[0009] To address the aforementioned technical problems, this invention provides a low-power supercapacitor charging and discharging circuit and method with hysteresis control. By constructing a discharge control unit with voltage hysteresis characteristics, precise control of the supercapacitor discharge process is achieved, preventing over-discharge, thereby extending its service life and ensuring the stability of the power supply system.

[0010] The first aspect of the present invention provides a low-power supercapacitor charging and discharging circuit with hysteresis control, the circuit comprising a supercapacitor and a hysteresis discharge unit.

[0011] The hysteresis discharge unit is connected to the supercapacitor and is used to start discharging when the voltage of the supercapacitor is higher than an upper threshold, to stop discharging when the voltage of the supercapacitor is lower than a lower threshold, and to maintain the original discharge state when the voltage of the supercapacitor is between the upper threshold and the lower threshold.

[0012] In one specific implementation, the hysteresis discharge unit includes: A P-type MOSFET (Q1) serves as the main switch, with its source connected to the positive terminal of the supercapacitor and its drain connected to the load output terminal (SPC OUT). An NPN transistor (Q2) serves as the first control transistor, with its collector connected to the gate of the P-type MOS transistor (Q1) and its emitter connected to ground. A voltage detection circuit has its input terminal connected to the positive terminal of the supercapacitor and its output terminal connected to the base of the NPN transistor (Q2). The voltage detection circuit forms a path from the positive terminal of the supercapacitor to ground. A first Zener diode (*D1), a second Zener diode (*D2), a first resistor (R3), and a second resistor (R4) are sequentially arranged along this path. Both the first Zener diode (*D1) and the second Zener diode (*D2) are connected to this path with their cathodes facing the positive terminal of the supercapacitor. A bypass control unit, the bypass control unit including a first PNP transistor (Q3) and a second PNP transistor (Q4), which together form a Darlington pair structure.

[0013] The base of the second PNP transistor (Q4) is connected to the gate of the P-type MOS transistor (Q1) via a second resistor (R2); The emitter of the second PNP transistor (Q4) is connected to the base of the first PNP transistor (Q3); The emitter of the first PNP transistor (Q3) is connected to the node between the first Zener diode (*D1) and the second Zener diode (*D2); The collector of the first PNP transistor (Q3) and the collector of the second PNP transistor (Q4) are connected together to the node between the second Zener diode (*D2) and the first resistor (R3), thereby bridging the emitter-collector path of the Darlington pair structure across the two ends of the second Zener diode (*D2).

[0014] The circuit works as follows: The upper limit threshold (V) THH The reverse breakdown voltage (V) of the first Zener diode (*D1) Z,D1 The reverse breakdown voltage (V) of the second Zener diode (*D2) Z,D2 ) and the base-emitter turn-on voltage (V) of the NPN transistor (Q2). BE,Q2 They jointly decide, and their relationship is as follows: V THH ≈V Z,D1 +V Z,D2 +V BE,Q2 ; When the voltage of the supercapacitor is higher than the upper limit threshold, the NPN transistor (Q2) turns on, which in turn turns on the P-type MOS transistor (Q1).

[0015] When the P-type MOS transistor (Q1) is turned on, its gate is at a low level, which turns on the Darlington pair structure in the bypass control unit, thereby forming an electrical bypass to the second Zener diode (*D2).

[0016] The lower limit threshold (V) THL After the second Zener diode (*D2) is bypassed, the reverse breakdown voltage (V) of the first Zener diode (*D1) is... Z,D1 ) and the base-emitter turn-on voltage (V) of the NPN transistor (Q2). BE,Q2 The relationship is determined as follows: V THL ≈V Z,D1 +V BE,Q2 ; When the voltage of the supercapacitor drops below the lower threshold due to discharge, the NPN transistor (Q2) is turned off, which in turn causes the P-type MOS transistor (Q1) to turn off.

[0017] In another specific embodiment, the circuit further includes an external power supply charging unit, an internal battery power supply unit, and a power switching circuit. The power switching circuit, upon detecting the presence of the external power supply charging unit, preferentially selects that unit to charge the supercapacitor and disconnects the charging path of the internal battery power supply unit.

[0018] A second aspect of the present invention provides a low-power supercapacitor charging and discharging method with hysteresis control, the method comprising the following steps: a. Continuously monitor the voltage of a supercapacitor; b. When the voltage of the supercapacitor is higher than an upper limit threshold, a main switch is turned on to establish a discharge circuit between the supercapacitor and the load; c. When the voltage of the supercapacitor is lower than a lower threshold, the main switch is controlled to turn off to disconnect the discharge circuit between the supercapacitor and the load, wherein the lower threshold is lower than the upper threshold; d. When the voltage of the supercapacitor is between the upper threshold and the lower threshold, the original on or off state of the main switch is maintained.

[0019] In one specific implementation, steps b and c are implemented in the following ways: In step b, the voltage of the supercapacitor is compared with a first reference voltage consisting of a first Zener diode and a second Zener diode connected in series. After step b is executed, the comparison reference is switched to a second reference voltage consisting only of the first Zener diode by electrically bypassing the second Zener diode; In step c, the voltage of the supercapacitor is compared with the second reference voltage.

[0020] In another specific embodiment, the method further includes the step of charging the supercapacitor via an external power supply charging unit or an internal battery power supply unit, and when the presence of the external power supply charging unit is detected, the external power supply charging unit is preferentially used for charging.

[0021] In summary, the present invention has at least one of the following beneficial technical effects: 1. This invention, by incorporating a hysteresis discharge unit, can precisely control the main switch to turn off when the voltage of the supercapacitor drops to a preset lower threshold due to discharge, thereby forcibly disconnecting the discharge circuit between the supercapacitor and the load. This mechanism ensures that the supercapacitor is not continuously discharged to a voltage level that could cause irreversible degradation of its capacity, thus significantly extending the effective operating life of the supercapacitor and improving the long-term reliability of the power supply system.

[0022] 2. The upper and lower discharge thresholds of the circuit of this invention are mainly determined by the reverse breakdown voltages of the first and second Zener diodes. Designers only need to select high-precision Zener diodes with different specifications to conveniently and accurately set the operating voltage range and hysteresis width of the supercapacitor without changing the overall circuit topology, so as to adapt to the characteristics of different types of supercapacitors or the stringent requirements for power supply stability in specific application scenarios.

[0023] 3. This invention ingeniously utilizes a combination of basic discrete components such as P-type MOSFETs, NPN transistors, and PNP Darlington pairs to realize complex voltage hysteresis control logic. This design avoids the use of expensive and fixed-function dedicated control integrated circuits, which not only significantly simplifies the circuit structure and reduces bill of materials costs, but also reduces the area occupied on the printed circuit board, which is very beneficial for product integration and miniaturization design. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a low-power supercapacitor charging and discharging circuit with hysteresis control according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a hysteresis discharge unit according to an embodiment of the present invention; Figure 3 This is a flowchart of the low-power supercapacitor charging and discharging method with hysteresis control according to the present invention.

[0025] Among them, 100 is the hysteresis discharge unit; 200 is the external power supply charging unit; and 300 is the internal battery power supply unit. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0027] See attached document Figure 1 , Figure 1 This is a schematic diagram of a low-power supercapacitor charging and discharging circuit with hysteresis control according to an embodiment of the present invention. The low-power supercapacitor charging and discharging circuit with hysteresis control provided by the present invention may include: a hysteresis discharge unit 100, an external power supply charging unit 200, and an internal battery power supply unit 300.

[0028] Hysteresis discharge unit 100, which is connected to a supercapacitor SPC, is used to monitor the voltage of the supercapacitor SPC and control the discharge process to the load based on two different voltage thresholds, namely an upper threshold and a lower threshold.

[0029] The external power supply charging unit 200 is connected to an external power supply Power-Ext and is used to provide charging current to the supercapacitor SPC when the external power supply is connected.

[0030] An internal battery power supply unit 300, connected to an internal power battery, provides charging current to the supercapacitor SPC when no external power source is available. The circuit also includes a power switching circuit to prioritize the use of the external power supply charging unit 200.

[0031] The core of this embodiment lies in the hysteresis discharge unit 100, which achieves hysteresis control of the discharge process through a specific combination of discrete components. The conduction and cutoff of the hysteresis discharge unit 100 are respectively determined by an upper threshold V. THH and lower limit threshold V THL Decide.

[0032] Upper limit threshold V THH The calculation formula is: V THH ≈V Z,D1 +V Z,D2 +V BE,Q2 ; in: V THH The upper limit voltage threshold for enabling discharge of the hysteresis discharge unit 100; V Z,D1This is the reverse breakdown voltage of the first Zener diode *D1 in the voltage detection circuit; V Z,D2 This is the reverse breakdown voltage of the second Zener diode *D2 in the voltage detection circuit; V BE,Q2 This is the base-emitter turn-on voltage of the NPN transistor Q2, which acts as the first control transistor.

[0033] Lower limit threshold V THL The calculation formula is: V THL ≈V Z,D1 +V BE,Q2 ; in: V THL The lower limit voltage threshold for shutting off the discharge of the hysteresis discharge unit 100.

[0034] From the above formula, we can see that V THH Greater than V THL The difference between the two is V THH -V THL This constitutes the hysteresis voltage width of the circuit, which is approximately equal to the reverse breakdown voltage V of the second Zener diode *D2. Z,D2 .

[0035] See attached document Figure 2 , Figure 2 This is a schematic diagram of a hysteresis discharge unit 100 according to an embodiment of the present invention. The specific circuit structure and component connection relationships of the hysteresis discharge unit 100 will be described in detail below.

[0036] The main discharge circuit of the hysteresis discharge unit 100 is composed of a P-type MOSFET Q1. The source of the P-type MOSFET Q1 is connected to the positive terminal of the supercapacitor SPC, and its drain serves as the load output terminal SPC OUT of the circuit. An RC network consisting of a resistor R1 and a capacitor C1 connected in parallel is connected between the source and drain of the P-type MOSFET Q1.

[0037] The gate of the P-type MOSFET Q1 is connected to the collector of an NPN transistor Q2 via a control line. The NPN transistor Q2, acting as the first control transistor, has its emitter directly connected to the circuit's ground terminal GP-. Therefore, the on / off state of the NPN transistor Q2 directly determines the gate potential of the P-type MOSFET Q1, thereby controlling the opening and closing of the main discharge circuit.

[0038] The base of the NPN transistor Q2 is connected to the output node of a voltage detection circuit via a fifth resistor R5. The voltage detection circuit forms a series voltage divider path from the positive terminal of the supercapacitor SPC to the ground terminal GP-. A first Zener diode *D1, a second Zener diode *D2, a first resistor R3, and a second resistor R4 are sequentially arranged in this path. Both the first Zener diode *D1 and the second Zener diode *D2 are connected in reverse series in this path with their cathodes facing the positive terminal of the supercapacitor SPC. The output node of the voltage detection circuit is located between the first resistor R3 and the second resistor R4. A second capacitor C2 is connected in parallel between the node between the first resistor R3 and the second resistor R4 and the ground terminal GP-.

[0039] The core of this embodiment, the bypass control unit used to form the hysteresis characteristic, consists of a Darlington pair structure formed by a first PNP transistor Q3 and a second PNP transistor Q4. The control input terminal of this bypass control unit is taken from the gate of the P-type MOSFET Q1. Specifically, the base of the second PNP transistor Q4 is connected to the gate of the P-type MOSFET Q1 via a second resistor R2.

[0040] Inside this Darlington pair structure, the emitter of the second PNP transistor Q4 is connected to the base of the first PNP transistor Q3. The emitter of the first PNP transistor Q3 is connected to the node between the first Zener diode *D1 and the second Zener diode *D2 in the voltage detection circuit. The collectors of the first PNP transistor Q3 and the second PNP transistor Q4 are both connected to the node between the second Zener diode *D2 and the first resistor R3 in the voltage detection circuit.

[0041] With the above connection method, the emitter-collector main path of the Darlington pair composed of Q3 and Q4 is completely connected across the two ends of the second Zener diode *D2. When the Darlington pair is triggered to conduct, it will form a low-impedance electrical bypass to the second Zener diode *D2, thereby changing the overall voltage division characteristics of the voltage detection circuit.

[0042] See attached document Figure 1 - Appendix Figure 3 The present invention also provides a low-power supercapacitor charging and discharging method with hysteresis control, which may include the following steps: S1 continuously monitors the voltage of the supercapacitor SPC.

[0043] S2, when the voltage of the supercapacitor SPC is higher than a preset upper limit threshold, a discharge circuit is established between the supercapacitor SPC and the load to start the discharge.

[0044] S3: When the voltage of the supercapacitor SPC is lower than a preset lower threshold, disconnect the discharge circuit between the supercapacitor SPC and the load to stop the discharge.

[0045] S4, when the voltage of the supercapacitor SPC is between the upper and lower thresholds, maintain the original on or off state of the discharge circuit.

[0046] In step S1, the voltage of the supercapacitor SPC is continuously detected by the voltage detection circuit in the hysteresis discharge unit 100.

[0047] Specifically, the real-time voltage of the supercapacitor SPC is continuously applied to a series path consisting of a first Zener diode *D1, a second Zener diode *D2, a first resistor R3, and a second resistor R4. This path continuously compares the voltage of the supercapacitor SPC with an internal reference voltage. This internal reference voltage is initially determined by the sum of the reverse breakdown voltages of the first Zener diode *D1 and the second Zener diode *D2.

[0048] When the voltage of the supercapacitor SPC exceeds the internal reference voltage, current flows through this path, generating a voltage drop across the voltage divider formed by the first resistor R3 and the second resistor R4. At the node between the first resistor R3 and the second resistor R4, a detection voltage positively correlated with the supercapacitor voltage is generated. This detection voltage is applied to the base of the NPN transistor Q2 through the fifth resistor R5 to control its on / off state, thereby converting the detection result of the supercapacitor voltage into a control signal for the subsequent switching circuit.

[0049] In step S2, when the voltage of the supercapacitor SPC rises during the charging process and exceeds a preset upper limit threshold V... THH At this time, the circuit performs the following series of actions to establish a discharge circuit.

[0050] The upper limit threshold V THH The voltage threshold is determined by the reverse breakdown voltage of the first Zener diode *D1 and the second Zener diode *D2, as well as the base-emitter turn-on voltage of the NPN transistor Q2. When the voltage of the supercapacitor SPC reaches this threshold, the first Zener diode *D1 and the second Zener diode *D2 in the voltage detection circuit successively undergo reverse breakdown and conduct, allowing current to flow through the first resistor R3 and the second resistor R4.

[0051] Current flows through the voltage divider formed by resistors R3 and R4, causing the node potential between them to rise. This increased potential is applied to the base of NPN transistor Q2 through resistor R5. When this base potential is sufficient to overcome the potential barrier between its base and emitter, NPN transistor Q2 changes from the cutoff state to the conduction state.

[0052] After the NPN transistor Q2 is turned on, its collector potential is rapidly pulled down to near the ground terminal GP-. Since the gate of the P-type MOSFET Q1 is connected to the collector of the NPN transistor Q2, the gate potential of Q1 is also pulled down. At this time, a sufficiently large negative gate-source voltage (Vgs) is formed between the source (connected to the positive terminal of the supercapacitor SPC) and the gate of the P-type MOSFET Q1.

[0053] The negative gate-source voltage drives the P-type MOSFET Q1 from the off state to the fully on state, forming a low-impedance path between its source and drain. At this point, the discharge circuit from the positive terminal of the supercapacitor SPC, through the source-drain path of the P-type MOSFET Q1, to the load output terminal SPC OUT is successfully established, and the supercapacitor SPC begins to discharge to the load.

[0054] In step S3, a prerequisite needs to be clarified first: after step S2 is executed, the main switching transistor, the P-type MOSFET Q1, is turned on, causing its gate to present a low level. This low level triggers the Darlington pair composed of Q3 and Q4 to conduct through the second resistor R2 and the second PNP transistor Q4. The conduction of this Darlington pair effectively bypasses the second Zener diode *D2 in the voltage detection circuit.

[0055] Under this premise, when the voltage of the supercapacitor SPC drops due to continuous discharge and falls below the lower threshold V determined by the reverse breakdown voltage of the first Zener diode *D1 and the base-emitter turn-on voltage of the NPN transistor Q2... THL When this occurs, the circuit performs a shutdown operation.

[0056] Specifically, since the voltage of the supercapacitor SPC is insufficient to generate enough drive current for the bypassed voltage detection circuit (at this time, the reference is mainly determined by the first Zener diode *D1), the current flowing through the first resistor R3 and the second resistor R4 decreases, causing the node potential between them to decrease accordingly. When this node potential drops to a level that can no longer maintain the base-emitter forward bias of the NPN transistor Q2, the NPN transistor Q2 changes from the on state to the off state.

[0057] The cutoff of NPN transistor Q2 interrupts the low-resistance path from the gate of P-type MOSFET Q1 to ground GP-. The gate potential of P-type MOSFET Q1 is no longer pulled low, and its gate-source voltage (Vgs) approaches zero, thus causing P-type MOSFET Q1 to switch from the on state to the off state. The cutoff of P-type MOSFET Q1 cuts off the main discharge circuit from supercapacitor SPC to the load output terminal SPC OUT, stopping the discharge process.

[0058] With the P-type MOSFET Q1 turning off, its gate potential returns to a high level. This high level acts on the base of the second PNP transistor Q4 through the second resistor R2, causing the Darlington pair formed by Q3 and Q4 to return to the off state, thereby releasing the bypass on the second Zener diode *D2. At this point, the voltage detection circuit returns to its initial state, and its detection threshold also returns to the higher upper limit threshold V. THH This prepares the device for the next charge-discharge cycle.

[0059] In step S4, when the voltage of the supercapacitor SPC is at the upper limit threshold V THH With lower threshold V THL The mechanism by which the discharge circuit maintains its original on or off state during this period is a direct manifestation of the circuit's hysteresis characteristic. This mechanism relies on the voltage detection circuit's threshold point dynamically switching according to the on / off state of the main discharge circuit.

[0060] If the discharge circuit is in the conducting state, that is, the supercapacitor SPC voltage has previously exceeded the upper limit threshold V. THH At this time, the P-type MOSFET Q1 is turned on, and its gate is at a low level. This low level has electrically bypassed the second Zener diode *D2 through the bypass control unit. Therefore, the reference voltage used by the voltage detection circuit to turn off the discharge has been switched to the lower lower threshold voltage V. THL When the SPC voltage of the supercapacitor drops into this hysteresis range, its voltage is still above the lower threshold V. THL The NPN transistor Q2 remains on, and the gate of the P-type MOSFET Q1 is continuously pulled low, thus maintaining the conduction state of the discharge circuit.

[0061] If the discharge circuit is in the off state, that is, the supercapacitor SPC voltage has previously been below the lower threshold V THL At this time, the P-type MOSFET Q1 is turned off, and its gate is at a high level. This high level keeps the bypass control unit off, and the second Zener diode *D2 is not bypassed. Therefore, the reference voltage used by the voltage detection circuit to enable discharge is at a higher upper threshold voltage V. THH When the SPC voltage of the supercapacitor rises back into this hysteresis range during charging, its voltage still has not reached the upper limit threshold V. THH The NPN transistor Q2 remains off, and the gate potential of the P-type MOSFET Q1 is unaffected, thus maintaining the off state of the discharge circuit.

[0062] In this way, the circuit's turn-on threshold is higher than its turn-off threshold, forming a defined voltage hysteresis window. As long as the supercapacitor's voltage fluctuates within this window, the circuit's output state will not change, thus avoiding circuit oscillations that may occur near the critical voltage point.

[0063] The technical solution of the present invention will be described below using a specific application scenario as an example.

[0064] In a power supply system for an IoT module used in a natural gas flow meter, a supercapacitor (SPC) with a nominal voltage of 3.6V is employed. In actual operation, the maximum charging voltage of this supercapacitor is limited to 3.95V. When the supercapacitor's voltage drops to near 2.5V due to discharge, a significant amount of its stored energy has been released. Continued discharge risks failing to provide a stable operating voltage for subsequent IoT modules and may damage the supercapacitor's cycle life.

[0065] To address this issue, this embodiment employs the aforementioned hysteresis discharge circuit, setting a discharge voltage hysteresis range of 2.7V to 3.0V for the supercapacitor. Specifically, when the supercapacitor voltage drops to 2.7V due to discharge, the circuit stops outputting power; thereafter, the circuit only resumes outputting power when the supercapacitor is recharged to above 3.0V. When the supercapacitor voltage is within the 2.7V to 3.0V range, the circuit maintains its original output state (on or off). This hysteresis control mechanism ensures that the circuit does not experience state oscillations near the threshold voltage point.

[0066] See attached document Figure 1 The specific working principle of the hysteresis discharge unit 100 in this embodiment is described below. The main components used in this unit include: a P-type MOSFET Q1, an NPN transistor Q2, a first PNP transistor Q3 and a second PNP transistor Q4 forming a Darlington pair, and a first Zener diode *D1 and a second Zener diode *D2.

[0067] In this embodiment, to achieve an upper threshold of 3.0V and a lower threshold of 2.7V, the typical parameters of the selected components are: the reverse breakdown voltage V of the first Zener diode *D1. Z,D1 The reverse breakdown voltage of the second Zener diode *D2 is 2.0V. Z,D2 The base-emitter voltage V of NPN transistor Q2 is 0.3V. BE,Q2 It is approximately 0.7V.

[0068] Upper limit threshold V THH It is calculated using the following formula: V THH =V Z,D1 +V Z,D2 +V BE,Q2 =2.0V + 0.3V + 0.7V = 3.0V; Lower limit threshold V THL It is calculated using the following formula: V THL =VZ,D1 +V BE,Q2 =2.0V + 0.7V = 2.7V; When the voltage of the supercapacitor SPC is in the hysteresis range of 2.7V to 3.0V, the circuit's operating state is analyzed as follows: In the first scenario, the circuit is initially in a normal discharge state, meaning the supercapacitor voltage drops from above 3.0V to this range. At this time, the P-type MOSFET Q1, NPN transistor Q2, and the Darlington pair formed by Q3 and Q4 are all conducting. Due to the conduction of the Darlington pair, the second Zener diode *D2 is bypassed by its emitter-collector path. As long as the supercapacitor voltage remains above the lower threshold of 2.7V, NPN transistor Q2 will remain conducting, thus keeping the P-type MOSFET Q1 conducting, and the circuit will continue to supply power.

[0069] In the second scenario, the circuit is initially in an undervoltage cutoff state, meaning the supercapacitor voltage has recovered from below 2.7V to this range. At this time, the P-type MOSFET Q1, NPN transistor Q2, and Darlington pair are all in the off state, and the second Zener diode *D2 is not bypassed. The voltage detection circuit needs to overcome the reverse breakdown voltage formed by *D1 and *D2. As long as the supercapacitor voltage is below the upper threshold of 3.0V, the NPN transistor Q2 cannot conduct, and the P-type MOSFET Q1 also remains off, meaning the circuit does not supply power externally.

[0070] In a specific implementation of this invention, the first Zener diode*D1 and the second Zener diode*D2 can be high-precision Zener diodes. Zener diodes have characteristics such as high breakdown voltage accuracy and small temperature drift coefficient, which can ensure the stability and accuracy of the upper and lower threshold values. For applications requiring a small hysteresis range, the second Zener diode*D2 can also be replaced by other components that can provide a stable voltage drop, such as one or more standard silicon diodes, germanium diodes, or the collector-emitter path of a transistor in a saturated conduction state.

[0071] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-power supercapacitor charging and discharging circuit with hysteresis control, characterized in that, include: Supercapacitors; Hysteresis discharge unit, which is connected to the supercapacitor, is used to start discharging when the voltage of the supercapacitor is higher than the upper threshold, to stop discharging when the voltage of the supercapacitor is lower than the lower threshold, and to maintain the original discharge state when the voltage of the supercapacitor is between the upper threshold and the lower threshold. The hysteresis discharge unit includes: The P-type MOSFET, which serves as the main switch, has its source connected to the supercapacitor and its drain connected to the load output terminal. The NPN transistor, which serves as the first control transistor, has its output state used to control the conduction and cutoff of the P-type MOS transistor. A voltage detection circuit, the input of which is connected to the supercapacitor, and the output of which is connected to the base of the first control transistor, the voltage detection circuit including a first Zener diode and a second Zener diode connected in series.

2. The low-power supercapacitor charging and discharging circuit with hysteresis control according to claim 1, characterized in that, The hysteresis discharge unit further includes a bypass control unit, which is controlled by the state of the first control transistor and forms an electrical bypass for the second Zener diode when the first control transistor is turned on, so that the reference voltage for determining the lower threshold is lower than the reference voltage for determining the upper threshold.

3. The low-power supercapacitor charging and discharging circuit with hysteresis control according to claim 2, characterized in that, The bypass control unit includes one or more PNP transistors, the collector-emitter path of which is connected across the two ends of the second Zener diode.

4. The low-power supercapacitor charging and discharging circuit with hysteresis control according to claim 2, characterized in that, The upper limit threshold is determined by the sum of the reverse breakdown voltage of the first Zener diode, the reverse breakdown voltage of the second Zener diode, and the base turn-on voltage of the first control transistor. The lower threshold is determined by the sum of the reverse breakdown voltage of the first Zener diode and the base conduction voltage of the first control transistor.

5. The low-power supercapacitor charging and discharging circuit with hysteresis control according to claim 1, characterized in that, Also includes: External power supply charging unit and internal battery power supply unit; Both the external power supply charging unit and the internal battery power supply unit are connected to the supercapacitor and are used to charge the supercapacitor.

6. The low-power supercapacitor charging and discharging circuit with hysteresis control according to claim 5, characterized in that, It also includes a power switching circuit, which, when the presence of the external power supply charging unit is detected, selects the external power supply charging unit to charge the supercapacitor and disconnects the charging path of the internal battery power supply unit.

7. A low-power supercapacitor charging and discharging method with hysteresis control, based on the circuit described in any one of claims 1-7, characterized in that, Includes the following steps: a) Continuously monitor the voltage of the supercapacitor; b) When the voltage of the supercapacitor is higher than the upper limit threshold, the main switch is turned on to establish a discharge circuit between the supercapacitor and the load; c) When the voltage of the supercapacitor is lower than the lower threshold, the main switch is controlled to turn off to disconnect the discharge circuit between the supercapacitor and the load; wherein the lower threshold is lower than the upper threshold. d) When the voltage of the supercapacitor is between the upper and lower thresholds, the original on or off state of the main switch is maintained.

8. The low-power supercapacitor charging and discharging method with hysteresis control according to claim 7, characterized in that, The implementation methods of steps b and c include: In step b, the voltage of the supercapacitor is compared with a first reference voltage consisting of a first Zener diode and a second Zener diode connected in series. After step b is executed, the comparison reference is switched to a second reference voltage consisting only of the first Zener diode by electrically bypassing the second Zener diode; In step c, the voltage of the supercapacitor is compared with the second reference voltage.

9. The low-power supercapacitor charging and discharging method with hysteresis control according to claim 7, characterized in that, It also includes the following steps: The supercapacitor is charged by an external power supply unit or an internal battery power supply unit.

10. The low-power supercapacitor charging and discharging method with hysteresis control according to claim 9, characterized in that, The charging step also includes: The presence of the external power supply charging unit is detected; if it exists, the external power supply charging unit is used for charging.

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