Frequency reduction circuit, switching power supply chip and electronic device

Abstract

The application belongs to the technical field of switching power supply, and provides a frequency reduction circuit, a switching power supply chip and an electronic device. The frequency reduction circuit comprises a detection module, an amplification module and a frequency generation module, the amplification module is connected with the detection module and the frequency generation module respectively; the detection module is used for receiving a first signal and outputting a second signal according to the first signal, the first signal is a signal directly or indirectly reflecting the duty cycle of the switching power supply; the amplification module is used for amplifying and operating the second signal to obtain a frequency increment signal; the frequency generation module outputs a frequency-reduced clock signal according to the frequency increment signal, and the frequency-reduced clock signal is used for determining the switching frequency of the switching power supply. The frequency reduction circuit provided in the application takes the signal directly or indirectly reflecting the duty cycle of the switching power supply as the input, converts the signal into the frequency increment signal after amplification and operation, thereby realizing variable-amplitude frequency reduction directly controlled by the duty cycle, and solving the problem of insufficient flexibility of the fixed-amplitude frequency reduction scheme.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of switching power supply, and particularly relates to a frequency reduction circuit, a switching power supply chip and electronic equipment. BACKGROUND

[0002] The switching power supply control chip promotes the integration evolution of the switching power supply system. In particular in the design of small power switching power supply, the general switching power supply control chip has realized the high integration of the switching power supply system. In particular, the on-chip integration of the power switching transistor greatly reduces the devices required by the peripheral circuit.

[0003] One of the advantages of the high integration of the switching power supply system is the support of higher working frequency. The increase of the working frequency not only allows the circuit to use inductance with smaller inductance and capacitance with smaller capacitance, but also further reduces the output voltage ripple and improves the dynamic response performance of the system. However, the increase of the working frequency brings difficulties in chip design. On the one hand, the higher working frequency requires strict transmission delay, and on the other hand, when working at a large current, the comparator needs to be reserved enough jitter elimination time due to more signal glitches. These two factors will limit the duty cycle of the system. This not only greatly increases the design difficulty of extreme configurations such as high input-low output and low input-high output, but also may lead to the loss of control of the control loop.

[0004] In view of these difficulties, there are two common solutions: one is to optimize the circuit delay and layout to achieve a wider duty cycle range, but this method is limited by the semiconductor process and the precision of the simulation model of the wafer factory; the second is to reduce the frequency at the extreme duty cycle, and by sacrificing some performance indicators such as dynamic response, efficiency, and ripple, to ensure that the core indicators such as output voltage and current meet the requirements. In actual design, the first method is usually given priority, and if the target cannot be achieved, the second method will be added on this basis. The second method usually adopts a fixed amplitude frequency reduction scheme. Although this scheme is simple to implement, it lacks flexibility, which may cause the frequency reduction amplitude to be too large in some duty cycle ranges, and thus cause unnecessary degradation of performance indicators such as dynamic response, efficiency, and ripple in this range. SUMMARY

[0005] The embodiments of the application provide a frequency reduction circuit, a switching power supply chip and electronic equipment, which can solve the problem of insufficient flexibility of the fixed amplitude frequency reduction scheme.

[0006] In a first aspect, the embodiments of the application provide a frequency reduction circuit, which comprises a detection module, an amplification module and a frequency generation module, the amplification module is connected with the detection module and the frequency generation module respectively.

[0007] The detection module is configured to receive a first signal and output a second signal according to the first signal, the first signal being a signal directly or indirectly reflecting a duty cycle of the switching power supply; the amplification module is configured to amplify and process the second signal to obtain a frequency increment signal; and the frequency generation module is configured to output a frequency-reduced clock signal according to the frequency increment signal, the frequency-reduced clock signal being used to determine a switching frequency of the switching power supply.

[0008] In a possible implementation manner of the first aspect, the detection module comprises a first sampling unit and a second sampling unit, and the first sampling unit and the second sampling unit are connected to the amplification module respectively.

[0009] The first sampling unit is configured to receive an input voltage of the switching power supply and sample the input voltage to obtain a first voltage; and the second sampling unit is configured to receive an output voltage of the switching power supply and sample the output voltage to obtain a second voltage; wherein the first signal comprises the output voltage and the input voltage; and the second signal comprises the first voltage and the second voltage.

[0010] In a possible implementation manner of the first aspect, the amplification module comprises a transconductance amplifier, a first input end of the transconductance amplifier is connected to the first sampling unit, a second input end of the transconductance amplifier is connected to the second sampling unit, and an output end of the transconductance amplifier is connected to the frequency generation module.

[0011] In a possible implementation manner of the first aspect, the detection module comprises an error amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor and a third capacitor, a first input end of the error amplifier is configured to receive a feedback voltage of the switching power supply, a second input end of the error amplifier receives a reference voltage, an output end of the error amplifier is connected to a first end of the first resistor and a first end of the second capacitor respectively, a second end of the first resistor is connected to a first end of the first capacitor and a first end of the second resistor respectively, a second end of the second resistor is connected to a first end of the third capacitor and the amplification module respectively, and second ends of the first capacitor, the second capacitor and the third capacitor are grounded; wherein the first signal is the feedback voltage; and the second signal is a voltage on the second resistor.

[0012] In a possible implementation manner of the first aspect, the amplification module comprises a transconductance amplifier, a first input end of the transconductance amplifier is connected to a first end of the second resistor, a second input end of the transconductance amplifier receives a frequency-reduction adjustment starting threshold voltage, and an output end of the transconductance amplifier is connected to the frequency generation module.

[0013] In a possible implementation manner of the first aspect, the trans-impedance amplifier is a trans-impedance amplifier with a unidirectional output current capability.

[0014] In a possible implementation manner of the first aspect, the frequency generation module comprises a subtractor and a clock signal generator, a first input terminal of the subtractor receives a reference current, a second input terminal of the subtractor is connected with the amplification module, and an output terminal of the subtractor is connected with the clock signal generator.

[0015] In a possible implementation manner of the first aspect, the clock signal generator comprises an oscillator, and the oscillator is connected with the output terminal of the subtractor.

[0016] In the second aspect, the embodiments of the present application provide a switching power supply chip, comprising the frequency reduction circuit in any of the first aspect.

[0017] In the third aspect, the embodiments of the present application provide an electronic device, comprising the switching power supply chip in any of the second aspect.

[0018] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0019] The embodiments of the present application provide a frequency reduction circuit, comprising a detection module, an amplification module and a frequency generation module, and the amplification module is connected with the detection module and the frequency generation module.

[0020] The detection module is configured to receive a first signal and output a second signal according to the first signal, the first signal being a signal directly or indirectly reflecting a duty cycle of a switching power supply. The amplification module is configured to amplify and process the second signal to obtain a frequency increment signal. The frequency generation module is configured to output a frequency-reduced clock signal according to the frequency increment signal, and the frequency-reduced clock signal is used to determine a switching frequency of the switching power supply.

[0021] The frequency reduction circuit provided by the present application takes a signal directly or indirectly reflecting a duty cycle of a switching power supply as input, converts the signal into a frequency increment signal after amplification and processing, and thus realizes variable-amplitude frequency reduction directly controlled by the duty cycle, thereby solving the problem of insufficient flexibility of the fixed-amplitude frequency reduction scheme.

[0022] It can be understood that the beneficial effects of the second aspect to the third aspect can be referred to the related description in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0024] Figure 1 is the schematic diagram of the frequency reduction circuit provided by an embodiment of the present application;

[0025] Figure 2 is the circuit schematic diagram of the first embodiment of the present application;

[0026] Figure 3 is the circuit schematic diagram of the second embodiment of the present application.

[0027] In the figure: 10, detection module; 11, first sampling unit; 12, second sampling unit; 13, error amplifier; 20, amplification module; 21, transconductance amplifier; 30, frequency generation module; 31, subtractor; 32, clock signal generator. DETAILED DESCRIPTION

[0028] In the following description, for the purpose of explanation and not for the purpose of limitation, specific details are set forth, such as specific system structures, techniques, etc., in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted in order not to obscure the description of the present application with unnecessary details.

[0029] It should be understood that when used in the specification and the appended claims of the present application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] It should also be understood that the term "and / or" used in the specification and the appended claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0031] As used in the specification and the appended claims, the term "if' can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to a determination" or "once [a described condition or event] is detected" or "in response to detecting [a described condition or event]" depending on the context.

[0032] In addition, the terms "first", "second", "third", etc. as used in the description of the specification and the appended claims are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0033] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments" and so on, in various places in the specification are not necessarily all referring to the same embodiment, unless otherwise specifically stated. The terms "comprising", "including", "having" and their variants mean "including but not limited to", unless otherwise specifically stated.

[0034] Switching power supply control chips have promoted the integration evolution of switching power supply systems. In particular in the design of small power switching power supplies, general switching power supply control chips have achieved high integration of switching power supply systems. In particular, the integration of power switching transistors on chip greatly reduces the devices required by the peripheral circuit.

[0035] One of the advantages of the high integration of switching power supply systems is the ability to support higher operating frequencies. Taking a DC-DC (direct current-direct current) switching power supply control chip as an example, the operating frequency of the current mainstream products in the industry generally reaches 1.2MHz or above, and some manufacturers have already launched products with operating frequencies of 2.4MHz or above. The increase in operating frequency not only allows the circuit to use inductors with smaller inductance and capacitors with smaller capacitance, but also further reduces the output voltage ripple and improves the dynamic response performance of the system.

[0036] However, the increase of the operating frequency brings difficulties to the chip design: higher operating frequency requires lower transmission delay in the chip; meanwhile, when the chip works under large current, the power line and ground line in the chip will have large jitter with the same frequency as the switching frequency, which will be coupled to the signal lines and introduce a large amount of spurs, thus requiring the comparators in the switching control loop to have sufficient jitter elimination time. The above two factors will limit the on-time and off-time of the system, and thus limit the duty cycle of the system. Specifically, when the controller in the switching power supply control chip works in the limit configuration (for example, high input-low output, the duty cycle can be less than 10%; low input-high output, the duty cycle can be higher than 90%), the design difficulty of the chip will be greatly increased.

[0037] Under the condition of low duty cycle, if the required short on-time cannot be achieved and the system is in a light load state, the actual operating frequency can be reduced by the skip cycle operation mode, and thus the required output voltage is obtained; but if the system uses the forced continuous mode, that is, regardless of the load, it always works in the continuous mode of inductor current, and cannot enter the skip cycle operation mode, at this time the problem of output voltage always higher than the preset value will occur. Under the condition of high duty cycle, if the required off-time is too short and cannot be achieved, the output voltage will always be less than the preset value. In the above two cases, the switching control loop is actually out of control.

[0038] For the above difficulties, there are two common solutions. The first method is to optimize the circuit delay, layout, etc., to try to reduce the signal delay in the chip, and thus achieve a wider duty cycle range; but this method is limited by the precision of the simulation model provided by the semiconductor process and wafer factory, and may not achieve the design goal. The second method is to ensure a higher switching frequency for more commonly used medium duty cycle applications, and to reduce the frequency for more extreme applications such as very high and very low duty cycles, by sacrificing certain dynamic response, efficiency, ripple, and other performance indicators to ensure that the output voltage, current, and other core indicators meet the requirements. In actual design, the first method is usually given priority, and if it cannot achieve the goal, the second method will be added on this basis.

[0039] Some products currently launched by the industry have the function of reducing the frequency in high or low duty cycle applications, and usually use a simple fixed amplitude frequency reduction scheme. For example, in a buck DC-DC circuit, when the duty cycle is higher than the preset threshold, the switching frequency is reduced to 50% of the normal working state.

[0040] The advantage of the fixed-amplitude frequency reduction scheme lies in simple structure, less required circuit components and easy implementation, but the scheme lacks flexibility. The reason is that the frequency reduction amplitude in the scheme has only one or at most several fixed values, which inevitably leads to excessive frequency reduction amplitude in some duty cycle ranges, and further causes unnecessary deterioration of dynamic response, efficiency, ripple and other performance indicators in these ranges.

[0041] To solve the problem of lack of flexibility of the fixed-amplitude frequency reduction scheme, the embodiment of the present application provides a frequency reduction circuit, as shown in Figure 1 The frequency reduction circuit includes a detection module 10, an amplification module 20 and a frequency generation module 30, and the amplification module 20 is connected with the detection module 10 and the frequency generation module 30 respectively.

[0042] Specifically, the detection module 10 is used to receive a first signal and output a second signal according to the first signal, and the first signal is a signal directly or indirectly reflecting the duty cycle of the switching power supply. The amplification module 20 is used to amplify and process the second signal to obtain a frequency increment signal. The frequency generation module 30 is used to output a frequency-reduced clock signal according to the frequency increment signal, and the frequency-reduced clock signal is used to determine the switching frequency of the switching power supply.

[0043] The frequency reduction circuit provided by the present application takes the signal directly or indirectly reflecting the duty cycle of the switching power supply as input, and converts it into a frequency increment signal after amplification and operation processing, thereby realizing variable-amplitude frequency reduction directly controlled by the duty cycle and solving the problem of lack of flexibility of the fixed-amplitude frequency reduction scheme.

[0044] The technical key point of the present application lies in the framework structure of the frequency reduction circuit, and the core is the process of detecting the signal directly or indirectly reflecting the duty cycle of the switching power supply and converting the signal into a frequency increment signal.

[0045] According to the difference of the input signal of the detection module, the framework structure of the frequency reduction circuit can adopt open-loop control or closed-loop control. Among them, compared with the fixed-amplitude frequency reduction scheme, the frequency reduction amplitude of the open-loop control is directly determined by the duty cycle, which can realize continuous variable-amplitude frequency reduction adjustment, and the increased circuit size and complexity are roughly the same as those of the fixed-amplitude frequency reduction scheme.

[0046] The closed-loop control further optimizes the control logic of the frequency reduction amplitude on the basis of the open-loop control: the frequency reduction amplitude is no longer dependent on the preset, but is adjusted through feedback control, so that the actual duty cycle reaches the required target value. This control method has higher accuracy, and also does not greatly increase the size and complexity of the circuit.

[0047] Figure 2The circuit schematic diagram of the first embodiment of the application is shown, and the embodiment is applicable to a Buck DC-DC switching power supply control chip, and the frequency reduction adjustment is for the case of high duty cycle. It should be noted that the diagram only includes the circuit modules related to the embodiment, and is not a complete Buck DC-DC switching power supply control chip circuit.

[0048] Figure 2 The dashed box in the figure represents the boundary between the inside and the outside of the chip, wherein the input voltage pin VIN and the output voltage pin VOUT are the chip pins related to the embodiment. It should be noted that in the embodiment, the Buck DC-DC switching power supply control chip transmits the output voltage V OUT to the inside of the chip through the output voltage pin VOUT, and is built-in with an output voltage sampling circuit, and most of such chips have the function of continuously adjusting the output voltage V OUT in real time. In contrast, most general-purpose DC-DC switching power supply control chips adopt an external output voltage sampling design, only have a voltage sampling feedback pin FB, and do not have an output voltage pin VOUT to transmit the output voltage V OUT back to the inside of the chip, so such chips are not applicable to the embodiment.

[0049] As shown in Figure 2 , the detection module 10 includes a first sampling unit 11 and a second sampling unit 12, and the first sampling unit 11 and the second sampling unit 12 are respectively connected with the amplification module 20. The first sampling unit 11 is further used to be connected with the input voltage pin VIN, and the second sampling unit 12 is further used to be connected with the output voltage pin VOUT.

[0050] The first sampling unit 11 is used to receive the input voltage V IN of the switching power supply, and sample the input voltage V IN to obtain a first voltage β 1 V IN , wherein β 1 is the sampling ratio of the first sampling unit 11. The second sampling unit 12 is used to receive the output voltage V OUT of the switching power supply, and sample the output voltage V OUT to obtain a second voltage β 2 V OUT , wherein β 2 is the sampling ratio of the second sampling unit 12. The first signal includes the output voltage VOUT and input voltage V IN . The second signal comprises a first voltage β 1 V IN and a second voltage β 2 V OUT .

[0051] As shown in Figure 2 , the amplification module 20 comprises a transconductance amplifier 21, a first input end of the transconductance amplifier 21 is connected with the first sampling unit 11, a second input end of the transconductance amplifier 21 is connected with the second sampling unit 12, and an output end of the transconductance amplifier 21 is connected with the frequency generation module 30. In the embodiment, the first input end of the transconductance amplifier 21 is an inverting input end, and the second input end is a non-inverting input end.

[0052] As shown in Figure 2 , the frequency generation module 30 comprises a subtractor 31 and a clock signal generator 32, a first input end of the subtractor 31 receives a reference current I REF , a second input end of the subtractor 31 is connected with the amplification module 20, and an output end of the subtractor 31 is connected with the clock signal generator 32. In the embodiment, the clock signal generator 32 comprises an oscillator, and the output end of the subtractor 31 is connected with the oscillator. The oscillator adopts a “capacitor charging and discharging” structure, and a frequency CLK of a clock signal f CLK generated by the oscillator has a linear relationship with a bias current I OSC , which is a common oscillator structure of a switching power supply control chip.

[0053] The input signals required by the embodiment are three: an input voltage V IN and an output voltage V OUT , which are from outside the chip and are input by corresponding pins of the chip; a reference current I REF which is generated inside the chip and is a reference current of the frequency generation module 30.

[0054] The output signal of the embodiment is a clock signal CLK output by the oscillator, which will be transmitted to a PWM modulation circuit (not shown in Figure 2 ), and a rising edge of the clock signal CLK starts a switching operation.

[0055] The working principle of the embodiment is described as follows.

[0056] The detection module 10 respectively measures the input voltage V IN and output voltage V OUT Sampling was performed to obtain the first voltage. β 1 V IN Second voltage β 2 V OUT First voltage β 1 V IN The second voltage is transmitted to the inverting input of the transconductance amplifier 21. β 2 V OUT It is transmitted to the non-inverting input of the transconductance amplifier 21.

[0057] The output of the transconductance amplifier 21 is designed to have only unidirectional output current capability, meaning it can only send current outward and cannot draw current inward.

[0058] This satisfies the following relationship:

[0059] (1);

[0060] in, V OUT_TH This is the starting voltage for frequency reduction regulation.

[0061] Because in the Buck DC-DC switching power supply architecture, the duty cycle D = V OUT / V IN Therefore, the detection module 10 detects the input voltage. V IN and output voltage V OUT The sampling essentially reflects the duty cycle directly, which is consistent with the... Figure 1 Description of the detection module 10.

[0062] at the same time, β 1 and β 2 is a circuit design parameter, which is a fixed value; in practice, it refers to the initial duty cycle of the frequency reduction adjustment. D TH It is also a constant value, that is D TH = V OUT_TH / V IN .

[0063] For a given input voltage V IN ,whenV OUT < V OUT_TH , i.e. D < D TH When I FR =0;

[0064] When V OUT > V OUT_TH , i.e. D > D TH When I FR , we have:

[0065] I FR = G M (1) V OUT - V OUT_TH (2);

[0066] where G M is the transconductance of the transconductance amplifier 21; the current I FR output by the transconductance amplifier 21 has a negative value corresponding to a negative incremental signal of the frequency.

[0067] The output current I FR of the transconductance amplifier 21 is subtracted from the reference current I REF by the subtracter 31 to obtain the bias current I OSC , i.e.

[0068] I OSC = I REF - I FR (3)

[0069] Thus, when V OUT < V OUT_TH , we have I FR =0, then I OSC = I REF andV OUT > V OUT_TH hour, I FR >0, then I OSC < I REF .

[0070] As mentioned earlier, the clock signal output by the oscillator CLK frequency f CLK With bias current I OSC Linear relationship:

[0071] f CLK = KI OSC (4);

[0072] in, K It is a constant, determined by the design parameters of the oscillator.

[0073] Therefore, when V OUT > V OUT_TH At that time, clock signal CLK frequency f CLK It will decrease, the frequency reduction magnitude △ f CLK As shown in the following formula:

[0074] △ f CLK =﹣ KG M ( V OUT - V OUT_TH )=﹣ KG M ( D - D TH ) V IN (5);

[0075] As can be seen from equation (5), in conjunction with the preceding description, this embodiment addresses the high duty cycle scenario; the higher the duty cycle, the stronger the clock signal. CLK The greater the frequency reduction, the better it compensates for the problem that the switch turn-off time is too short to meet design requirements under high duty cycles. Furthermore, this embodiment achieves continuous frequency adjustment, and the additional circuit module size required is roughly equivalent to that of a fixed-amplitude frequency reduction scheme.

[0076] It should be noted that, in this embodiment, the output voltage... V OUT It can be adjusted in real time without power interruption, for each given... V OUT The set value is the input voltage. V IN At a certain time, clock signal CLK Frequency reduction △ f CLK All these parameters are deterministic, therefore this is an open-loop control. For open-loop control, the frequency adjustment range needs to be estimated during the circuit design phase to set the maximum frequency adjustment amplitude and avoid excessive frequency descent. Furthermore, due to the frequency descent amplitude Δ... f CLK Duty cycle D The correspondence is based on simple linear interpolation, so it is impossible to completely avoid the problem of excessive or insufficient frequency reduction in some intermediate values.

[0077] Figure 3 The diagram shown is a circuit schematic of the second embodiment of this application. This embodiment is applicable to DC-DC switching power supply control chips with forced continuous inductor current and peak current mode. The frequency reduction adjustment is for low duty cycle and light load situations. It should be noted that this diagram only includes the circuit modules related to this embodiment and is not a complete switching power supply control chip circuit.

[0078] Figure 3 The dashed box in the figure represents the boundary between the inside and outside of the chip. The voltage sampling feedback pin FB is a chip pin related to this embodiment. This embodiment is applicable to most general-purpose DC-DC switching power supply control chips that use external output voltage sampling.

[0079] like Figure 3 As shown, the detection module 10 includes an error amplifier 13, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first input terminal of the error amplifier 13 is used to receive the feedback voltage from the switching power supply. V FB The second input terminal of the error amplifier 13 receives the reference voltage. V REF The output terminal of error amplifier 13 is connected to the first terminal of the first resistor R1 and the first terminal of the second capacitor C2, respectively. The second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1 and the first terminal of the second resistor R2, respectively. The second terminal of the second resistor R2 is connected to the first terminal of the third capacitor C3 and the amplification module 20, respectively. The second terminals of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are all grounded. The first signal is the feedback voltage. V FBThe second signal is the voltage across the second resistor R2. In this embodiment, the first input terminal of the error amplifier 13 is the inverting input terminal, and the second input terminal is the non-inverting input terminal. It should be noted that the first resistor R1, the first capacitor C1, and the second capacitor C2 form a Type II compensation network, and the second resistor R2 and the third capacitor C3 form an RC low-pass filter. The error amplifier 13 and the Type II compensation network are also part of the switching power supply PWM control loop (the rest of the control loop is not shown).

[0080] like Figure 3 As shown, the amplification module 20 includes a transconductance amplifier 21. The first input terminal of the transconductance amplifier 21 is connected to the first terminal of the second resistor R2, and the second input terminal of the transconductance amplifier 21 receives the down-frequency adjustment starting threshold voltage. V TH_FR The output terminal of the transconductance amplifier 21 is connected to the frequency generation module 30. In this embodiment, the first input terminal of the transconductance amplifier 21 is an inverting input terminal, and the second input terminal is a non-inverting input terminal.

[0081] like Figure 3 As shown, the frequency generation module 30 includes a subtractor 31 and a clock signal generator 32. The first input terminal of the subtractor 31 receives a reference current. I REF The second input terminal of subtractor 31 is connected to amplification module 20, and the output terminal of subtractor 31 is connected to clock signal generator 32. In this embodiment, clock signal generator 32 includes an oscillator, and the output terminal of subtractor 31 is connected to the oscillator. The oscillator adopts a "capacitor charging and discharging" structure, and the clock signal it generates... CLK frequency f CLK With bias current I OSC The relationship is linear, which is a common oscillator structure in switching power supply control chips.

[0082] This embodiment requires a total of four input signals: feedback voltage. V FB The input signals originate externally to the chip and are transmitted to the first input terminal of the error amplifier 13 via the voltage sampling feedback pin FB; the other three input signals are generated internally by the chip, with the reference voltage... V REF The signal is transmitted to the second input of error amplifier 13, and the starting threshold voltage is adjusted by frequency reduction. V TH_FR The reference current is transmitted to the second input terminal of the transconductance amplifier 21. I REF The data is transmitted to the first input terminal of the subtractor 31.

[0083] This embodiment has two output signals: the clock signal output by the oscillator.CLK , which will be transmitted to the PWM modulation circuit (not shown in the figure) Figure 3 , the rising edge of the clock signal CLK starts a switching operation, which is the same as in the first embodiment. The error signal output by the error amplifier 13 V EA is also transmitted to the PWM modulation circuit to generate a PWM modulation signal. The specific process is not involved in this embodiment, and will not be described here. The level of the error signal V EA determines the on-time of the switch, thereby indirectly reflecting the high and low of the duty cycle.

[0084] The working principle of this embodiment is described as follows.

[0085] When the controller of the DC-DC switching power supply control chip is in a stable working state, the following relationships are established:

[0086] (6);

[0087] wherein, β is the output voltage sampling ratio.

[0088] Of course, this is only the result under ideal conditions, and there will be some differences in the actual circuit.

[0089] First, the output voltage V OUT has a ripple, which will be amplified by the error amplifier 13 and reflected in the error signal V EA . Therefore, instead of directly using the error signal V EA , this embodiment uses a second signal obtained by passing a signal from the first capacitor C1 plate through a first RC filter, i.e. the voltage V EA_C , wherein ; the voltage V EA_C serves as the inverting input of the transconductance amplifier 21, which can avoid the ripple being further amplified, thereby preventing the clock signal CLK from having a large amplitude jitter. It should be noted that the values of the second resistor R2 and the third capacitor C3 need to be carefully calculated and simulated during design to avoid introducing non-negligible zero-pole points in the type II compensation network, which may cause additional stability risks in the control loop.

[0090] Secondly, since the gain A of the error amplifier 13 is a finite value, and in order to save the area overhead of compensation resistors and capacitors, the gain A of the error amplifier 13 is further reduced in the fully integrated switching power supply control chip, soV REF - V FB ≠0; in other words, the actual output voltage V OUT is slightly different from the set target value V OUT_TARG . V REF - V FB Generally referred to as the gain error, as the input to the error amplifier 13, the error signal V EA is at a certain level; it should be noted that the error signal V EA is the sum of a DC signal and an AC signal. In the control loop of the peak current mode, the error signal V EA represents the peak value of the inductor current in a switching cycle, and therefore, under heavy load conditions, the error signal V EA is at a high level, and at this time V FB - V REF <0, i.e. V OUT < V OUT_TARG ; on the contrary, under light load conditions, especially under no-load or near no-load conditions, the error signal V EA is at a low level, and at this time V FB - V REF >0, i.e. V OUT > V OUT_TARG .

[0091] When the system is operating in the normal operating mode, a lower limit level is set for the error signal V EA . When the load decreases, and the error signal V EA drops to the set lower limit level, the system enters the skip cycle operating mode; at this time, the actual switching frequency decreases to meet the required duty cycle.

[0092] However, in the present embodiment, the system operates in the inductor current forced continuous mode and cannot enter the skip cycle operating mode, and therefore, no lower limit is set for the error signal V EA , and the error signal V EAThe voltage will continue to decrease until the switch is turned on t ON to the extent that the required duty cycle is met. If the target duty cycle V OUT_TARG is too low, the error signal D TARG will continue to decrease until it approaches 0V, which in turn results in the required switch on time V EA being too small t ON than the minimum switch on time t ON_min (where the minimum switch on time t ON_min is determined by the de-bounce time of the modules and the signal transmission delay time). The required switch on time t ON will not meet the above requirement, i.e. the actual duty cycle D > D TARG , the output voltage V OUT will continue to decrease V OUT_TARG until it is out of control. V OUT

[0093] Therefore, the present embodiment adds a frequency reduction control: a frequency reduction adjustment starting threshold voltage V TH_FR is set, which can be referenced from the error signal V EA in the normal working mode to be the lower limit level at which the skip cycle working mode is triggered, and then reduced by 10-20%. When the target duty cycle D TARG is too low and cannot be achieved, V OUT > V OUT_TARG , i.e. V FB - V REF > 0, the error signal V EA will continue to decrease, which in turn results in the voltage V EA_C continuing to decrease until V EA_C < V TH_FR , the frequency reduction circuit starts to reduce the frequency CLK of the clock signal f CLK . ​

[0094] Let the output of error amplifier 13 equal V TH_FR The corresponding output voltage value is V OUT0 That is:

[0095] A V REF βV OUT0 V TH_FR (7);

[0096] It can be roughly considered that V OUT0 ≈ V OUT_TARG Or, in the no-load or near no-load state, V OUT0 That is, the target output voltage is in line with the allowable range of gain error.

[0097] Thus, the amplitude reduction △ f CLK can be calculated:

[0098] △ f CLK =﹣ KAG M β V OUT V OUT0 (8);

[0099] That is, the output voltage V OUT floats up, the switching frequency begins to drop, and the actual duty cycle D will decrease accordingly, making V OUT gradually close to V OUT0 until reaching equilibrium. At this time, the error ( V OUT - V OUT0 ) is proportional to the minimum switching-on time t ON_min and inversely proportional to the transconductance of transconductance amplifier 21. G M

[0100] ​​​​​​Different from the first embodiment, the present embodiment is a closed-loop control process, which can effectively avoid the problem of excessive or insufficient frequency reduction that may occur in the first embodiment; and the application scenario of the present embodiment is not limited to the buck DC-DC switching power supply control chip, but can also be applied to the boost DC-DC switching power supply control chip. At the same time, the present embodiment does not significantly increase the circuit complexity, and the additional area overhead is only generated by the RC low-pass filter composed of the second resistor R2 and the third capacitor C3.

[0101] It should be noted that the present embodiment introduces an additional feedback loop in the system, so when designing, the transconductance of the transconductance amplifier 21 needs to be calculated and simulated to ensure the stability of the overall loop. G M

[0102] The above describes the present application through two embodiments, but the present application is not limited to the above two specific implementation manners, as long as the switching power supply control chip with the built-in "capacitor charging and discharging" timing structure can adopt the scheme of the present application to reduce the switching frequency. It should be noted that the "timing structure" here is not limited to an oscillator; for example, in the constant off-time architecture, the "timing structure" used to calculate the off-time is also applicable to the scheme of the present application.

[0103] The present application embodiment also provides a switching power supply chip comprising the above-mentioned frequency reduction circuit. Since the switching power supply chip provided by the present application embodiment adopts all the technical solutions of the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0104] The present application embodiment also provides an electronic device comprising the above-mentioned switching power supply chip. Since the electronic device provided by the present application embodiment adopts all the technical solutions of the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here. The electronic device provided by the present application embodiment can be any electronic device containing the above-mentioned switching power supply chip.

[0105] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0106] ​The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A frequency reduction circuit, characterized in that, It includes a detection module, an amplification module, and a frequency generation module, wherein the amplification module is connected to the detection module and the frequency generation module respectively; The detection module is used to receive a first signal and output a second signal based on the first signal. The first signal is a signal that directly or indirectly reflects the duty cycle of the switching power supply. The amplification module is used to amplify and process the second signal to obtain a frequency increment signal. The frequency generation module is used to output a down-frequency clock signal based on the frequency increment signal. The down-frequency clock signal is used to determine the switching frequency of the switching power supply. The detection module includes a first sampling unit and a second sampling unit, which are respectively connected to the amplification module. The first sampling unit is used to receive the input voltage of the switching power supply and sample the input voltage to obtain a first voltage; the second sampling unit is used to receive the output voltage of the switching power supply and sample the output voltage to obtain a second voltage; wherein, the first signal includes the output voltage and the input voltage; the second signal includes the first voltage and the second voltage.

2. The frequency reduction circuit according to claim 1, characterized in that, The amplification module includes a transconductance amplifier, the first input terminal of which is connected to the first sampling unit, the second input terminal of which is connected to the second sampling unit, and the output terminal of which is connected to the frequency generation module.

3. A frequency reduction circuit, characterized in that, It includes a detection module, an amplification module, and a frequency generation module, wherein the amplification module is connected to the detection module and the frequency generation module respectively; The detection module is used to receive a first signal and output a second signal based on the first signal. The first signal is a signal that directly or indirectly reflects the duty cycle of the switching power supply. The amplification module is used to amplify and process the second signal to obtain a frequency increment signal. The frequency generation module is used to output a down-frequency clock signal based on the frequency increment signal. The down-frequency clock signal is used to determine the switching frequency of the switching power supply. The detection module includes an error amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, and a third capacitor. The first input terminal of the error amplifier is used to receive the feedback voltage from the switching power supply, and the second input terminal of the error amplifier receives a reference voltage. The output terminal of the error amplifier is connected to the first terminal of the first resistor and the first terminal of the second capacitor, respectively. The second terminal of the first resistor is connected to the first terminal of the first capacitor and the first terminal of the second resistor, respectively. The second terminal of the second resistor is connected to the first terminal of the third capacitor and the amplification module, respectively. The second terminals of the first capacitor, the second capacitor, and the third capacitor are all grounded. The first signal is the feedback voltage, and the second signal is the voltage across the second resistor.

4. The frequency reduction circuit according to claim 3, characterized in that, The amplification module includes a transconductance amplifier, the first input terminal of which is connected to the first terminal of the second resistor, the second input terminal of which receives a frequency reduction adjustment starting threshold voltage, and the output terminal of which is connected to the frequency generation module.

5. The frequency reduction circuit according to claim 2 or 4, characterized in that, The transconductance amplifier is a transconductance amplifier with unidirectional output current capability.

6. The frequency reduction circuit according to claim 1 or 3, characterized in that, The frequency generation module includes a subtractor and a clock signal generator. The first input terminal of the subtractor receives a reference current, the second input terminal of the subtractor is connected to the amplification module, and the output terminal of the subtractor is connected to the clock signal generator.

7. The frequency reduction circuit according to claim 6, characterized in that, The clock signal generator includes an oscillator, which is connected to the output of the subtractor.

8. A switching power supply chip, characterized in that, Includes the frequency reduction circuit as described in any one of claims 1-7.

9. An electronic device, characterized in that, Includes the switching power supply chip as described in claim 8.

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