Phase-locked frequency-stable multi-core control radio frequency system

Abstract

The application relates to the technical field of radio frequency generator circuits, and provides a phase-locked frequency-stabilized multi-core control radio frequency system, a digital baseband processing module, I / Q signal processing and multi-core task distribution and cooperation mechanism construction, pre-distortion processing and system scheduling, a double closed-loop control module, stable base frequency and temperature drift correction, compensation and adjustment of frequency swing amplitude, a hybrid power amplifier module, multi-stage hybrid power amplification signal processing through a combination topology of a driving stage and an output stage, and temperature monitoring, and a feedback sampling network module, real-time acquisition of output signals through a directional coupler, and feedback adjustment of the precision control frequency stability according to the output signals.

Description

Technical Field

[0001] This invention relates to the field of precision control and intelligent adjustment technology for radio frequency signal processing, and in particular to a phase-locked loop frequency stabilization multi-core control radio frequency system. Background Technology

[0002] Currently, in modern high-performance radio frequency systems, such as precision radar, high-speed communication (5G / 6G and above), and high-resolution spectrum analysis, ultra-high stability and extremely low phase noise of the frequency source are core performance indicators. As application demands for system performance continue to increase, phase-locked loop (PLL) frequency stabilization systems face many new challenges, including: A surge in performance requirements: increasingly higher demands are placed on phase noise, frequency switching speed, frequency resolution, spurious suppression, and loop bandwidth flexibility; Increased complexity: modern applications often require support for multiple frequency points, wide bandwidths, complex modulation formats, and multi-channel collaborative operation; Stringent real-time requirements: high-speed frequency transitions, adaptive loop bandwidth adjustment, real-time calibration and compensation, and high-order digital loop filtering, nonlinear correction, digital predistortion, noise shaping, and other operations need to be completed in a very short time with complex processing and coordinated control. Multi-band coordination has the following drawbacks: First, there is a switching delay problem: the mechanical relay switching takes a long time, causing communication test interruptions; second, there is an impedance mismatch problem: the impedance changes of the output ports of different frequency bands cause the VSWR to deteriorate; third, there is a local oscillator interference problem: phase noise coupling between independent local oscillator sources; and there is insufficient long-term stability, such as thermal drift accumulation: changes in the junction temperature of the power amplifier tube cause large fluctuations in output power; vibration sensitivity problem: mechanical shock causes VCO frequency jumps; there are also electromagnetic compatibility problems, such as digital noise pollution: FPGA switching noise is coupled to the RF link through the power supply ground; and harmonic radiation problem: high-order harmonic interference to peripheral equipment is not filtered out; multi-mode adaptation limitations, such as pulse waveform distortion: the charging and discharging of the energy storage capacitor causes the flat top to fall; and frequency modulation phase breakage: phase discontinuity during DDS frequency switching.

[0003] Single-core processors or simple microcontrollers face numerous challenges when dealing with the ever-increasing demands of real-time digital signal processing and complex control. These challenges include processing capacity bottlenecks: a single core struggles to efficiently handle computationally intensive tasks such as high-order filtering, fast Fourier transforms, and complex state machine control while meeting stringent timing requirements; real-time response limitations: interrupt responses and task scheduling overhead can increase loop control latency, impacting dynamic performance such as frequency switching time and stability; and difficulties in functional integration: integrating multiple functions such as spectrum monitoring, automatic gain control, fault diagnosis, communication interface management, and intelligent processing presents challenges related to resource conflicts and performance degradation. Therefore, it is necessary to provide a phase-locked loop (PLL) frequency-stabilized multi-core control RF system to partially address these technical problems. Summary of the Invention

[0004] This invention provides a phase-locked loop (PLL) frequency-stabilized multi-core control RF system. By proposing a PLL frequency-stabilized multi-core control RF system, the stability of the RF generator circuit and the high efficiency of control can be guaranteed.

[0005] This invention provides a phase-locked loop frequency-stabilized multi-core control radio frequency system, comprising:

[0006] The digital baseband processing module processes I / Q signals and constructs a multi-core task allocation and coordination mechanism, performing predistortion processing and system scheduling.

[0007] The dual closed-loop control module stabilizes the base frequency and corrects for temperature drift, while compensating for and adjusting the frequency oscillation amplitude.

[0008] The hybrid power amplifier module performs multi-stage hybrid power amplification signal processing and temperature monitoring through a combination topology of driver stage and output stage.

[0009] The feedback sampling network module acquires the output signal in real time through a directional coupler and adjusts the frequency stability of the precision control based on the feedback of the output signal.

[0010] Preferably, the digital baseband processing module includes: a heterogeneous multi-core processor and a coprocessor, which construct a multi-core task allocation and coordination mechanism; the heterogeneous multi-core processor, which generates I / Q signals in real time, processes I / Q signals, and performs system scheduling and I / Q balance adjustment control; inputs predistortion compensation information; the coprocessor, which performs predistortion processing; a frequency synthesis layer, which performs multi-channel digital frequency synthesis and dynamically configures local oscillator resources; and a signal shaping processing layer, which performs I / Q balance adjustment through vector modulation and programmable filter banks.

[0011] Preferably, the dual closed-loop control module includes: a main phase-locked loop (PLL1) and an auxiliary phase-locked loop (PLL2);

[0012] The main phase-locked loop (PLL1) generates discrete frequency signals with the same stability within a set range based on the reference oscillation signal generated by the crystal oscillator to lock the base frequency and stabilize the base frequency.

[0013] The auxiliary phase-locked loop (PLL2) performs temperature drift compensation and correction, adjusting the frequency swing amplitude. Abnormal hot spots are detected by a temperature sensor, and the auxiliary PLL2 compensates for the frequency error caused by the abnormal hot spots, performing temperature drift compensation and correction. The frequency swing amplitude is adjusted by adjusting the VCO tuning voltage compensation slope of the main phase-locked loop (PLL1).

[0014] Preferably, the hybrid power amplifier module includes: a driver-stage RF power amplifier, a multi-stage matching network, and a final-stage RF power amplifier, forming a multi-stage hybrid power amplifier engine architecture through multi-stage cascaded hybrid power amplification.

[0015] Preferably, the feedback sampling network module includes: a directional coupler and a high-speed ADC; the directional coupler acquires the output signal in real time and transmits the output signal to the high-speed ADC for feedback to the heterogeneous multi-core processor and coprocessor; by adjusting the sampling frequency and quantization order, high-order intermodulation distortion is offset; feedback adjustment precisely controls frequency stability.

[0016] Preferably, the heterogeneous multi-core processor includes: a high-frequency response real-time core, an efficiency-first application core, and a programmable logic core, which integrate the heterogeneous multi-cores and build a multi-core task allocation and coordination mechanism; the multi-core task allocation and coordination mechanism sends control commands, frequency point information, and spectrum data through shared memory Mailbox communication to allocate and coordinate multi-core tasks; and inputs predistortion compensation information to perform predistortion compensation.

[0017] Preferably, the frequency synthesis layer includes: a multi-channel digital frequency synthesizer and an N-type phase-locked loop;

[0018] A multi-channel digital frequency synthesizer that directly generates a set frequency signal using digital frequency control codes;

[0019] The N-type phase-locked loop precisely subdivides the frequency steps at the reference frequency.

[0020] Preferably, the programmable logic core further includes: using distributed SRAM, embedded multipliers, and lookup tables to construct frequency dividers, phase detectors, filters, and digitally controlled oscillators respectively; performing high-resolution digital phase detection and digital filtering to control high-speed data transmission and reception synchronization.

[0021] Preferably, a multi-core task allocation and coordination mechanism is constructed, including:

[0022] Through a high-frequency response real-time core, deterministic real-time tasks are executed: periodically triggering phase-locked loop closed-loop control; handling the coefficient loading and mode switching of loop filtering; monitoring VCO linear region calibration to prevent voltage control voltage saturation; exclusive memory area for isolation and protection to avoid access conflicts from other cores; and highest priority interrupts to reduce jitter.

[0023] The system monitors the application core with an efficiency-first approach, performing phase noise analysis and frequency stability analysis; it also handles external communication, including Ethernet and receiving configuration command frequency hopping sequences; and performs non-real-time diagnostics, including updating the temperature drift compensation table and analyzing fault logs.

[0024] Through a programmable logic core, it performs signal processing and digital phase detection, including TDC time-to-digital conversion; runs fixed-order digital filtering and preprocesses ADC data; and manages serial data transmission and reception via a high-speed serial interface.

[0025] Preferably, the multi-core task allocation and coordination mechanism also includes: sending control commands, frequency point information and spectrum data through shared memory Mailbox communication to perform multi-core task allocation and coordination, and inputting predistortion compensation information for predistortion compensation; flexible and high-performance frequency switching; higher frequency resolution; low cost and low power consumption, with multi-channel digital frequencies using digital circuits, significantly reducing power consumption; introducing communication middleware for efficient data distribution and distributed task allocation and coordination; reducing external interference and increasing RF stability.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] This invention features multi-band switching, employing a hardware pre-loading mechanism. Target frequency band parameters are pre-configured before switching, and the switching matrix is ​​triggered in parallel. It adapts to high-frequency bands through a multi-level matching network, adjustable capacitor array, and distributed matching topology. A multi-dimensional stability assurance system is established, including three-dimensional thermal field control for thermal management and linear frequency modulation optimization. A phase memory unit is constructed, with external SRAM storing phase states and loading historical phase values. Frequency response correction is performed: VCO tuning linearization and intelligent temperature compensation. Based on output power, heat generation is predicted, temperature is intelligently adjusted, and frequency feedback closed-loop control is implemented for precise control. The core control tasks, auxiliary function tasks, and intelligent control strategy tasks of the phase-locked loop are rationally allocated to different processing cores for parallel execution. Key loop control tasks receive the highest priority and maintain execution time, significantly reducing loop latency. Multi-core collaboration provides powerful processing capabilities, supporting complex digital signal processing and the implementation of advanced control strategies. High-precision phase-locked loop frequency stabilization technology is deeply integrated with multi-core parallel processing control capabilities to construct a phase-locked loop frequency stabilization multi-core control RF system.

[0028] The advantages of this invention's architecture include: a real-time core with hard real-time task isolation, solving closed-loop latency and jitter control; hardware parallel processing and direct connection interfaces, addressing high-speed signal processing bottlenecks; an application core that offloads non-real-time tasks and integrates complex functions, enhancing real-time performance; an interconnect architecture with hierarchical buses and hardware integration, increasing the determinism of inter-core communication; a synchronization network with a global clock tree and hardware triggering, improving multi-core collaborative timing consistency; this architecture achieves ultra-precise RF control with phase-locked loop frequency stabilization through hardware acceleration, task isolation, and deterministic communication; and parallel processing that rationally distributes the core control tasks, auxiliary function tasks, and intelligent control strategy tasks of the phase-locked loop to different processing cores. Parallel execution; critical loop control tasks receive the highest priority and maintain execution time, significantly reducing loop latency; multi-core collaboration provides powerful processing capabilities, supporting complex digital signal processing and the implementation of advanced control strategies; improved system flexibility and scalability: modular design facilitates function additions and removals and performance upgrades, and different cores can run different operating systems or real-time kernels to adapt to diverse needs; therefore, by deeply integrating high-precision phase-locked loop (PLL) frequency stabilization technology with powerful multi-core parallel processing control capabilities, a PLL frequency stabilization multi-core control RF system can be constructed, adapting to modern cutting-edge RF fields and possessing advantages such as ultra-high frequency stability, ultra-low noise, rapid agility, and intelligent control.

[0029] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0030] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0032] Figure 1 This is a diagram of an embodiment of a phase-locked loop frequency-stabilized multi-core controlled radio frequency system architecture.

[0033] Figure 2 This is a diagram of an embodiment of a phase-locked loop frequency stabilization multi-core control radio frequency system with multi-core collaboration.

[0034] Figure 3 This is a diagram of an embodiment of a phase-locked loop frequency stabilization (PLL) multi-core control RF system with dual closed-loop frequency stabilization. Detailed Implementation

[0035] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0036] This invention provides a phase-locked loop frequency-stabilized multi-core control radio frequency system, such as... Figures 1-3 As shown, it includes:

[0037] The digital baseband processing module processes I / Q signals and constructs a multi-core task allocation and coordination mechanism, performing predistortion processing and system scheduling.

[0038] The dual closed-loop control module stabilizes the base frequency and corrects for temperature drift, while compensating for and adjusting the frequency oscillation amplitude.

[0039] The hybrid power amplifier module performs multi-stage hybrid power amplification signal processing and temperature monitoring through a combination topology of driver stage and output stage.

[0040] The feedback sampling network module acquires the output signal in real time through a directional coupler and adjusts the frequency stability of the precision control based on the feedback of the output signal.

[0041] The working principle and beneficial effects of this invention are as follows: Multi-band switching employs a hardware pre-loading mechanism: target frequency band parameters are pre-configured before switching, and the switching matrix is ​​triggered in parallel; high-frequency bands are adapted through multi-level matching networks, adjustable capacitor arrays, and distributed matching topologies; a multi-dimensional stability assurance system is established, including three-dimensional thermal field control for thermal management and linear frequency modulation optimization; a phase memory unit is constructed: external SRAM stores phase states and loads historical phase values; frequency response correction is performed: VCO tuning linearization and intelligent temperature compensation; heat generation is predicted based on output power, temperature is intelligently adjusted, and frequency feedback closed-loop precise control is implemented; the core control tasks, auxiliary function tasks, and intelligent control strategy tasks of the phase-locked loop are combined... The processing is distributed to different processing cores for parallel execution; critical loop control tasks receive the highest priority and maintain execution time, significantly reducing loop latency; multi-core collaboration provides powerful processing capabilities to support complex digital signal processing and the implementation of advanced control strategies; high-precision phase-locked loop (PLL) frequency stabilization technology is deeply integrated with multi-core parallel processing control capabilities to construct a PLL frequency stabilization multi-core control RF system; the PLL performs frequency tracking, phase synchronization, and noise suppression, performs RF signal frequency stabilization and synthesis, compares the phase difference between the reference signal and the voltage-controlled oscillator (VCO) output signal through a phase detector to generate an error voltage, which is smoothed by a loop filter and then controls the frequency and phase of the VCO to form a precise lock of the output signal to the reference signal source;

[0042] The advantages of this invention's architecture include: a real-time core with hard real-time task isolation, solving closed-loop latency and jitter control; hardware parallel processing and direct connection interfaces, addressing high-speed signal processing bottlenecks; an application core that offloads non-real-time tasks and integrates complex functions, enhancing real-time performance; an interconnect architecture with hierarchical buses and hardware integration, increasing the determinism of inter-core communication; a synchronization network with a global clock tree and hardware triggering, improving multi-core collaborative timing consistency; this architecture achieves ultra-precise RF control with phase-locked loop frequency stabilization through hardware acceleration, task isolation, and deterministic communication; and parallel processing that rationally distributes the core control tasks, auxiliary function tasks, and intelligent control strategy tasks of the phase-locked loop to different processing cores. Parallel execution; critical loop control tasks receive the highest priority and maintain execution time, significantly reducing loop latency; multi-core collaboration provides powerful processing capabilities, supporting complex digital signal processing and the implementation of advanced control strategies; improved system flexibility and scalability: modular design facilitates function additions and removals and performance upgrades, and different cores can run different operating systems or real-time kernels to adapt to diverse needs; therefore, the deep integration of high-precision phase-locked loop (PLL) frequency stabilization technology with powerful multi-core parallel processing control capabilities creates a PLL frequency stabilization multi-core control RF system that can adapt to modern cutting-edge RF fields, possessing advantages such as ultra-high frequency stability, ultra-low noise, rapid agility, and intelligent control;

[0043] A hardware watchdog monitors the high-frequency response real-time core jumps; a software watchdog monitors the state of efficiency-priority application cores in real time; fault switching automatically switches the programmable logic core to safe mode when the high-frequency response real-time core malfunctions by backing up the VCO driver parameter table; thermal management performance is optimized by partitioning the high-frequency response real-time core and the programmable logic core, combined with heat sinks and temperature sensors to dynamically adjust the workload; multi-core collaboration includes Cortex-R, Cortex-A, and FPGA, with physical isolation between the RF system and digital circuits to suppress radiated interference; system fault tolerance and reliability are significantly improved.

[0044] In one embodiment, the digital baseband processing module includes: a heterogeneous multi-core processor and a coprocessor, which construct a multi-core task allocation and coordination mechanism; the heterogeneous multi-core processor, which generates I / Q signals in real time, processes I / Q signals, and performs system scheduling and I / Q balance adjustment control; inputs predistortion compensation information; the coprocessor, which performs predistortion processing; a frequency synthesis layer, which performs multi-channel digital frequency synthesis and dynamically configures local oscillator resources; and a signal shaping processing layer, which performs I / Q balance adjustment through vector modulation and programmable filter banks.

[0045] The working principle and beneficial effects are as follows: An 8-channel digital frequency synthesizer and 4 phase-locked loops are used to form a reconfigurable local oscillator network; the digital baseband processing module includes a heterogeneous multi-core processor and a coprocessor to build a multi-core task allocation and coordination mechanism; the heterogeneous multi-core processor generates I / Q signals in real time, processes I / Q signals, and performs system scheduling and I / Q balance adjustment control; it inputs predistortion compensation information; the coprocessor performs predistortion processing; the frequency synthesis layer performs multi-channel digital frequency synthesis and dynamically configures local oscillator resources; the signal shaping processing layer performs I / Q balance adjustment through vector modulation and programmable filter banks; the signal shaping processing layer architecture includes a vector modulator, a programmable filter bank, and a dynamic attenuator.

[0046] In one embodiment, the dual closed-loop control module includes: a main phase-locked loop (PLL1) and an auxiliary phase-locked loop (PLL2);

[0047] The main phase-locked loop (PLL1) generates discrete frequency signals with the same stability within a set range based on the reference oscillation signal generated by the crystal oscillator to lock the base frequency and stabilize the base frequency.

[0048] The auxiliary phase-locked loop (PLL2) is used to perform temperature drift compensation and correction, and to adjust the frequency swing amplitude.

[0049] The working principle and beneficial effects are as follows: The dual closed-loop control module includes a main phase-locked loop (PLL1) and an auxiliary phase-locked loop (PLL2). The main PLL1 generates a discrete frequency signal with the same stability within a set range based on the reference oscillation signal generated by the crystal oscillator to lock the fundamental frequency and stabilize it. The auxiliary PLL2 performs temperature drift compensation correction and adjusts the frequency swing amplitude. Abnormal hot spots are detected by a temperature sensor, and the auxiliary PLL2 compensates for the frequency error caused by the abnormal hot spots and performs temperature drift compensation correction. The frequency swing amplitude is adjusted by adjusting the VCO tuning voltage compensation slope of the main PLL1.

[0050] In one embodiment, the hybrid power amplifier module includes: a driver-stage RF power amplifier, a multi-stage matching network, and a final-stage RF power amplifier, forming a multi-stage hybrid power amplifier engine architecture through multi-stage cascaded hybrid power amplification.

[0051] The working principle and beneficial effects are as follows: The hybrid power amplifier module includes: a driver-stage RF power amplifier, a multi-stage matching network and a final-stage RF power amplifier. A multi-stage hybrid power amplifier engine architecture is formed by constructing a multi-stage hybrid power amplifier through multi-stage hybrid power amplification. The multi-stage hybrid power amplifier engine architecture includes: a GaN driver-stage amplifier, a multi-stage impedance matching network and a Si LDMOS final-stage RF power amplifier, forming a multi-stage hybrid power amplifier engine for the PA power amplifier.

[0052] In one embodiment, the feedback sampling network module includes: a directional coupler and a high-speed ADC; the directional coupler acquires the output signal in real time and transmits the output signal to the high-speed ADC for feedback to the heterogeneous multi-core processor and coprocessor; by adjusting the sampling frequency and quantization order, high-order intermodulation distortion is offset; feedback adjustment precisely controls frequency stability.

[0053] The working principle and beneficial effects are as follows: The feedback sampling network module includes a directional coupler and a high-speed ADC; the directional coupler acquires the output signal in real time and transmits the output signal to the high-speed ADC for feedback to the heterogeneous multi-core processor and coprocessor; by adjusting the sampling frequency and quantization order, high-order intermodulation distortion is offset; the input of the lookup table is adjusted to reduce the difference between the input signal and the power amplifier output signal; the envelope of the input signal is also an input to the lookup table, the feedback path samples the power amplifier distortion output, and then feeds it back to the heterogeneous multi-core processor and coprocessor after analog-to-digital conversion by the high-speed ADC to update the lookup table; the feedback adjustment precisely controls the frequency stability.

[0054] In one embodiment, the heterogeneous multi-core processor includes: a high-frequency response real-time core, an efficiency-first application core, and a programmable logic core, which integrate the heterogeneous multi-cores and construct a multi-core task allocation and coordination mechanism; the multi-core task allocation and coordination mechanism sends control commands, frequency point information, and spectrum data through shared memory Mailbox communication to allocate and coordinate multi-core tasks; and inputs predistortion compensation information to perform predistortion compensation.

[0055] The working principle and beneficial effects are as follows: The heterogeneous multi-core processor includes: high-frequency response real-time core, efficiency-first application core and programmable logic core, which integrates heterogeneous multi-core and builds a multi-core task allocation and coordination mechanism;

[0056] The multi-core task allocation and coordination mechanism uses shared memory Mailbox communication to send control commands, frequency point information and spectrum data to allocate and coordinate multi-core tasks; and inputs predistortion compensation information to perform predistortion compensation.

[0057] Through a high-frequency response real-time core, key closed-loop control with nanosecond-level response is performed, core control is carried out, and phase detection error processing and VCO drive are performed.

[0058] The efficiency-first application kernel runs the operating system kernel system and handles high-level management tasks, including: user interface, network communication, and data logging.

[0059] The programmable logic core preprocesses the ADC data, generates and processes I / Q signals; using the double data rate IP unit, data is received at both the rising and falling edges of the reference clock, and data is sampled at both the rising and falling edges to obtain double data rate, and double clock rate data latching is performed. The high-speed ADC input data is collected and divided into I / Q signals to generate double clock rate I / Q signals.

[0060] In one embodiment, the frequency synthesis layer includes: a multi-channel digital frequency synthesizer and an N-type phase-locked loop;

[0061] A multi-channel digital frequency synthesizer that directly generates a set frequency signal using digital frequency control codes;

[0062] The N-type phase-locked loop precisely subdivides the frequency steps at the reference frequency.

[0063] The working principle and beneficial effects are as follows: The frequency synthesis layer includes: a multi-channel digital frequency synthesizer and an N-type phase-locked loop; the multi-channel digital frequency synthesizer directly generates the set frequency signal using digital frequency control codes; the N-type phase-locked loop precisely subdivides the frequency steps at the reference frequency; it keeps the frequency signal stable; the digital implementation is constructed using adders and D flip-flops.

[0064] In one embodiment, the programmable logic core further includes: constructing a frequency divider, a phase detector, a filter, and a digitally controlled oscillator using distributed SRAM, an embedded multiplier, and a lookup table, respectively; performing high-resolution digital phase detection and digital filtering to control high-speed data transmission and reception synchronization.

[0065] The working principle and beneficial effects are as follows: The programmable logic core also includes: using distributed SRAM, embedded multipliers and lookup tables to construct frequency dividers, phase detectors, filters and digitally controlled oscillators respectively; performing high-resolution digital phase detection and digital filtering, and controlling high-speed data transmission and reception synchronization;

[0066] The frequency divider divides the reference signal and compares it with the local oscillator signal; the phase detector detects the phase difference between the two signals and outputs the phase difference signal; the filter filters the phase difference signal from the phase detector, removes high-frequency noise, and converts the phase difference signal into a control digital signal; the digitally controlled oscillator adjusts the output frequency of the control digital signal, tunes the local oscillator signal, and synchronizes the phase of the tuned local oscillator signal with the phase of the input signal.

[0067] In one embodiment, a multi-core task allocation and coordination mechanism is constructed, including:

[0068] Through a high-frequency response real-time core, deterministic real-time tasks are executed: periodically triggering phase-locked loop closed-loop control; handling the coefficient loading and mode switching of loop filtering; monitoring VCO linear region calibration to prevent voltage control voltage saturation; exclusive memory area for isolation and protection to avoid access conflicts from other cores; and highest priority interrupts to reduce jitter.

[0069] The system monitors the application core with an efficiency-first approach, performing phase noise analysis and frequency stability analysis; it also handles external communication, including Ethernet and receiving configuration command frequency hopping sequences; and performs non-real-time diagnostics, including updating the temperature drift compensation table and analyzing fault logs.

[0070] Through a programmable logic core, it performs signal processing and digital phase detection, including TDC time-to-digital conversion; runs fixed-order digital filtering and preprocesses ADC data; and manages serial data transmission and reception via a high-speed serial interface.

[0071] The working principle and beneficial effects are as follows: A multi-core task allocation and coordination mechanism is constructed, including: executing deterministic real-time tasks through a high-frequency response real-time core: periodically triggering phase-locked loop closed-loop control; handling coefficient loading and mode switching of loop filtering, such as bandwidth switching instructions; monitoring VCO linear region calibration to prevent voltage-controlled voltage saturation; exclusively occupying memory areas for isolation and protection to avoid access conflicts from other cores; using the highest priority interrupt to reduce jitter; running system monitoring through an efficiency-first application core, performing phase noise analysis and frequency stability analysis; handling external communication, including Ethernet and receiving configuration command frequency hopping sequences; performing non-real-time diagnostics, including temperature drift compensation table updates and fault log analysis; performing signal processing and digital phase detection through a programmable logic core, including TDC time-to-digital conversion; running fixed-order digital filtering to preprocess ADC data; and managing serial data transmission and reception of the high-speed serial interface.

[0072] In one embodiment, the multi-core task allocation and coordination mechanism further includes: sending control commands, frequency point information, and spectrum data through shared memory Mailbox communication to perform multi-core task allocation and coordination, and inputting predistortion compensation information for predistortion compensation; flexible and high-performance frequency switching; higher frequency resolution; low cost and low power consumption, with multi-channel digital frequencies using digital circuits, resulting in significantly reduced power consumption; introduction of communication middleware for efficient data distribution and distributed task allocation and coordination; reduction of external interference and increase of radio frequency stability.

[0073] The working principle and beneficial effects are as follows: The multi-core task allocation and coordination mechanism also includes: sending control commands, frequency point information and spectrum data through shared memory Mailbox communication to perform multi-core task allocation and coordination, and inputting predistortion compensation information for predistortion compensation; flexible and high-performance frequency switching; higher frequency resolution; low cost and low power consumption, multi-channel digital frequency uses digital circuits, significantly reducing power consumption; introducing communication middleware for efficient data distribution and distributed task allocation and coordination; reducing external interference and increasing RF stability; constructing a phase memory unit: external SRAM stores phase state and loads historical phase values; performing frequency response correction: VCO tuning linearization and intelligent temperature compensation; predicting heat generation based on output power, intelligent temperature adjustment, and precise frequency feedback closed-loop control; rationally allocating the core control tasks, auxiliary function tasks and intelligent control strategy tasks of the phase-locked loop to different processing cores for parallel execution; key loop control tasks obtain the highest priority and maintain execution time, significantly reducing loop latency.

[0074] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A phase-locked loop frequency-stabilized multi-core control radio frequency system, characterized in that, include: The digital baseband processing module processes I / Q signals and constructs a multi-core task allocation and coordination mechanism, performing predistortion processing and system scheduling. The dual closed-loop control module stabilizes the base frequency and corrects for temperature drift, while compensating for and adjusting the frequency oscillation amplitude. The hybrid power amplifier module performs multi-stage hybrid power amplification signal processing and temperature monitoring through a combination topology of driver stage and output stage. The feedback sampling network module acquires the output signal in real time through a directional coupler and adjusts the precision control frequency stability based on the feedback of the output signal. The digital baseband processing module includes: a heterogeneous multi-core processor and coprocessor, which constructs a multi-core task allocation and coordination mechanism; the heterogeneous multi-core processor, which generates and processes I / Q signals in real time, performs system scheduling and I / Q balance adjustment control; inputs predistortion compensation information; the coprocessor, which performs predistortion processing; a frequency synthesis layer, which performs multi-channel digital frequency synthesis and dynamically configures local oscillator resources; and a signal shaping processing layer, which performs I / Q balance adjustment through vector modulation and programmable filter banks. The heterogeneous multi-core processor includes: a high-frequency response real-time core, an efficiency-first application core, and a programmable logic core. It integrates heterogeneous multi-cores and builds a multi-core task allocation and coordination mechanism. The multi-core task allocation and coordination mechanism sends control commands, frequency point information, and spectrum data through shared memory Mailbox communication to allocate and coordinate multi-core tasks. It also inputs predistortion compensation information to perform predistortion compensation.

2. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 1, characterized in that, The dual closed-loop control module includes: a main phase-locked loop (PLL1) and an auxiliary phase-locked loop (PLL2); The main phase-locked loop (PLL1) generates discrete frequency signals with the same stability within a set range based on the reference oscillation signal generated by the crystal oscillator to lock the base frequency and stabilize the base frequency. The auxiliary phase-locked loop (PLL2) is used to perform temperature drift compensation and correction, and adjust the frequency swing amplitude.

3. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 1, characterized in that, The hybrid power amplifier module includes a driver-stage RF power amplifier, a multi-stage matching network, and a final-stage RF power amplifier, forming a multi-stage hybrid power amplifier engine architecture through multi-stage cascaded hybrid power amplification.

4. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 1, characterized in that, The feedback sampling network module includes: a directional coupler and a high-speed ADC; the directional coupler acquires the output signal in real time and transmits the output signal to the high-speed ADC for feedback to the heterogeneous multi-core processor and coprocessor; by adjusting the sampling frequency and quantization order, high-order intermodulation distortion is offset; feedback adjustment precisely controls frequency stability.

5. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 1, characterized in that, The frequency synthesis layer includes: a multi-channel digital frequency synthesizer and an N-type phase-locked loop; A multi-channel digital frequency synthesizer that directly generates a set frequency signal using digital frequency control codes; The N-type phase-locked loop precisely subdivides the frequency steps at the reference frequency.

6. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 1, characterized in that, The programmable logic core also includes: using distributed SRAM, embedded multipliers, and lookup tables to construct frequency dividers, phase detectors, filters, and digitally controlled oscillators respectively; performing high-resolution digital phase detection and digital filtering to control high-speed data transmission and reception synchronization.

7. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 4, characterized in that, Construct a multi-core task allocation and coordination mechanism, including: Through a high-frequency response real-time core, deterministic real-time tasks are executed: periodically triggering phase-locked loop closed-loop control; handling the coefficient loading and mode switching of loop filtering; monitoring VCO linear region calibration to prevent voltage control voltage saturation; exclusive memory area for isolation and protection to avoid access conflicts from other cores; and highest priority interrupts to reduce jitter. The system monitors the application core with an efficiency-first approach, performing phase noise analysis and frequency stability analysis; it also handles external communication, including Ethernet and receiving configuration command frequency hopping sequences; and performs non-real-time diagnostics, including updating the temperature drift compensation table and analyzing fault logs. Through a programmable logic core, it performs signal processing and digital phase detection, including TDC time-to-digital conversion; runs fixed-order digital filtering and preprocesses ADC data; and manages serial data transmission and reception via a high-speed serial interface.

8. The phase-locked loop frequency-stabilized multi-core control radio frequency system according to claim 7, characterized in that, The multi-core task allocation and coordination mechanism also includes: sending control commands, frequency point information and spectrum data through shared memory Mailbox communication to perform multi-core task allocation and coordination, and inputting predistortion compensation information for predistortion compensation; flexible and high-performance frequency switching; higher frequency resolution; low cost and low power consumption, with multi-channel digital frequencies using digital circuits, resulting in significantly reduced power consumption; introduction of communication middleware for efficient data distribution and distributed task allocation and coordination; and reduction of external interference and increased RF stability.

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