Ethernet data transceiver circuit, circuit board and data transceiver device

Abstract

The application provides an Ethernet data transceiving circuit, a circuit board and a data transceiving device, relates to the technical field of electronic circuits, and solves the problem that the data collection scheme provided by the related art is difficult to meet the multi-protocol coexistence requirement in an industrial scene. The data transceiving circuit of the scheme can realize the adaptation to different Ethernet modes based on the switching of the transmission channel of the channel switching module, thereby guaranteeing the "zero delay" collection requirement of real-time Ethernet such as EtherCAT, and can also meet the full-duplex communication requirement of data collection in a gigabit Ethernet. Therefore, the Ethernet data transceiving circuit of the scheme can provide a more reliable data collection scheme and meet the multi-protocol coexistence requirement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to an Ethernet data transceiving circuit, a circuit board and a data transceiving device. BACKGROUND

[0002] With the development of industrial automation and intelligent manufacturing, industrial Ethernet occupies a core position in device communication and control, and it needs to transmit control instructions and state data in real time and accurately. The real-time and accuracy requirements of data collection and analysis are strict, and there is a demand for coexistence of multiple protocols (such as EtherCAT and Gigabit Ethernet) in industrial scenarios, and different rates and protocols of Ethernet data processing need to be adapted.

[0003] In related technologies, the data of the traditional data collection scheme needs to be forwarded by a PHY chip, an FPGA or a processor logic, and the delay of digital-to-analog conversion and logic forwarding is obvious. However, in the EtherCAT and other time-sensitive scenarios, the delay will cause the time sequence of the data to be disordered, which will affect the collaborative control accuracy of the devices, and cannot meet the demand of industrial real-time control for low-delay data capture. Moreover, the analyzer provided in the related technologies is only for data analysis of the 100 Mbps Ethernet protocol, and its mode is fixed. In the face of the demand for coexistence of multiple protocols in industrial scenarios, it is difficult to efficiently implement Ethernet data processing. SUMMARY

[0004] The present application provides an Ethernet data transceiving circuit, a circuit board and a data transceiving device, which solves the problem that the data collection scheme provided in the related technologies cannot meet the demand for coexistence of multiple protocols in industrial scenarios. The Ethernet data transceiving circuit provided in the present application can realize Ethernet data processing by switching different channels, thereby meeting the demand for coexistence of multiple protocols.

[0005] In a first aspect, the present application provides an Ethernet data transceiving circuit, which includes a channel switching module, a data transceiving module, a SoC chip and at least one pair of transceiving interfaces.

[0006] The pair of transceiving interfaces are used to connect a first device and a second device for data transmission between the first device and the second device. The channel switching module corresponds to the transceiving interfaces one by one, and the channel switching module includes four input terminals and two output terminals. The two output terminals of the channel switching module are respectively connected to two first terminals on the corresponding transceiving interfaces for transmitting data. A pair of input terminals in the channel switching module corresponds to an output terminal and is used to switch different input terminals and form a first data transmission channel or a second data transmission channel when a control signal is received.

[0007] The data transceiving module and the channel switching module correspond to each other, the data transceiving module includes two data sending ends and two data receiving ends, the two data sending ends of the data transceiving module are connected to two input ends of the corresponding first data sending channel in the channel switching module, the two data receiving ends of the data transceiving module are connected to two second terminals for receiving data on the corresponding transceiving interface of the channel switching module, and the two data receiving ends of the data transceiving module are also connected to two input ends of the corresponding second data sending channel in another channel switching module, and the channel switching module connected to the data sending end of the data transceiving module and another channel switching module connected to the data receiving end of the data transceiving module are both used for connecting the same pair of transceiving interfaces.

[0008] The logic control port of the SoC chip is connected to the control end of the channel switching module, and the data transceiving end of the SoC chip is connected to the data interface end of the data transceiving module for transmitting data to or receiving data from the data transceiving module.

[0009] In a second aspect, the present application further provides a circuit board, which comprises the Ethernet data transceiving circuit provided in the first aspect.

[0010] In a third aspect, the present application further provides a data transceiving device, which comprises the circuit board provided in the second aspect.

[0011] The data transceiving circuit provided in the present application can realize the adaptation to different Ethernet modes based on the switching of the transmission channel of the channel switching module, thereby guaranteeing the "zero delay" collection requirement of real-time Ethernet such as EtherCAT, and meeting the full-duplex communication requirement of data collection in gigabit Ethernet, so that the Ethernet data transceiving circuit provided in the present application can provide a more reliable data collection scheme and meet the multi-protocol coexistence requirement. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A logic block diagram of the Ethernet data transceiving circuit provided in an embodiment of the present application.

[0013] Figure 2 A circuit structure diagram of a differential subunit provided in an embodiment of the present application.

[0014] Figure 3 A circuit structure diagram of a channel switching module provided in an embodiment of the present application.

[0015] Figure 4 A structure schematic diagram of the Ethernet data transceiving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The application will be described in further detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the application and not to limit the application. In addition, it should be noted that, for the sake of description, only parts related to the embodiments of the application are shown in the drawings, and those skilled in the art should understand that, as long as the technical features are not mutually contradictory, any combination of technical features can constitute an optional embodiment.

[0017] The terms "first", "second", and the like in the specification and claims of the application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually a class and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the front and rear associated objects. In the description of the application, "a plurality of" means two or more, and "several" means one or more.

[0018] With the development of industrial automation and intelligent manufacturing, industrial Ethernet occupies a core position in device communication and control, which requires real-time and accurate transmission of control instructions and state data, and strict real-time and accuracy requirements for data acquisition and analysis. At the same time, there is a demand for multiple protocols coexisting in industrial scenarios, which requires adaptation to different rates and protocol data processing. For example, EtherCAT, Gigabit Ethernet and other protocols use different data processing methods, and EtherCAT is a fieldbus system based on Ethernet.

[0019] In related technologies, the data of the traditional data acquisition scheme needs to be forwarded by the PHY chip, FPGA or processor logic, and the delay of digital-to-analog conversion and logic forwarding is obvious. However, in the scene of EtherCAT and other time-sensitive scenes, the delay will cause the time sequence of the data to be disordered, affecting the collaborative control accuracy of the device, and unable to meet the demand of low-delay data capture of industrial real-time control. Moreover, the analyzer provided in the related technologies is only for data analysis of the 100 Mbps Ethernet protocol, and its mode is fixed. In the face of the demand for multiple protocols coexisting in industrial scenarios, it is difficult to efficiently implement Ethernet data processing.

[0020] To this end, the application provides an Ethernet data transceiver circuit, which can be used to connect two devices that need to transmit data, and also connected with devices such as host computers, so that the host computer can complete data acquisition while transmitting data between devices, thereby realizing a more optimal data processing scheme. Figure 1A logic block diagram of an Ethernet data transceiver circuit provided by an embodiment of the present application is shown in Figure 1 In an embodiment, the Ethernet data transceiver circuit includes a channel switching module 120, a data transceiver module 130, a SoC (System on Chip) chip and at least one pair of transceiver interfaces 110.

[0021] The same pair of transceiver interfaces 110 is used to connect a first device and a second device for data transmission between the first device and the second device, i.e., one interface of the same pair of transceiver interfaces 110 is used to connect the first device and the other interface is used to connect the second device. The channel switching module 120 corresponds to the transceiver interfaces 110 one by one, i.e., the channel switching module 120 also has at least two to connect different transceiver interfaces 110 in the same pair. Specifically, two first terminals for transmitting data and two second terminals for receiving data are provided on the transceiver interfaces 110, the channel switching module 120 includes four input terminals and two output terminals, and the two output terminals of the channel switching module 120 are respectively connected to the two first terminals for transmitting data on the corresponding transceiver interfaces 110. The four input terminals of the channel switching module 120 can be divided into two pairs, and each pair of input terminals corresponds to an output terminal. In this regard, the channel switching module 120 can be controlled by a control signal to switch different input terminals to form a first data transmission channel or a second data transmission channel.

[0022] It can be understood that, in the case of receiving the control signal, both pairs of input terminals of the channel switching module 120 are switched, so that before and after each switching, there is one input terminal in each pair of input terminals of the channel switching module 120 connected to the corresponding output terminal. In this regard, different data transmission channels are formed before and after switching, and each type of data transmission channel is provided with two. For example, the channel switching module 120 includes four input terminals of port I1, port I2, port I3 and port I4 and two output terminals of port O1 and port O2, wherein port I1 and port I2 are a pair and correspond to port O1, port I3 and port I4 are a pair and correspond to port I2. When the channel switching module 120 is switched to port I1 connected to port O1 and port I3 connected to port O2, a first data transmission channel is formed in the channel switching module 120. When the channel switching module 120 is switched to port I2 connected to port O1 and port I4 connected to port O2, port O1 and port O2 are respectively connected to the two first terminals on the first interface I RD1

[0023] ​The data transceiving module 130 corresponds to the channel switching module 120. Similarly, the number of the data transceiving module 130 is the same as the number of the transceiving interface 110. The data transceiving module 130 includes two data sending ends and two data receiving ends. The two data sending ends of the data transceiving module 130 are connected to the two input ends of the corresponding first data sending channel in the channel switching module 120. The two data receiving ends of the data transceiving module 130 are connected to the two second terminals of the corresponding transceiving interface 110 for receiving data. The two data receiving ends of the data transceiving module 130 are also connected to the two input ends of the corresponding second data sending channel in another channel switching module 120. The channel switching module 120 connected to the data sending end of the data transceiving module 130 and the other channel switching module 120 connected to the data receiving end of the data transceiving module 130 are both used to connect the same pair of transceiving interfaces 110. For example, the data transceiving module 130 includes two data sending ends, i.e., port TD1 and port TD2, and two data receiving ends, i.e., port RD1 and port RD2. The port TD1 is connected to the port I1 of the channel switching module 120, and the port TD2 is connected to the port I3 of the channel switching module 120. The port RD1 is connected to one second terminal of the first interface I1, and the port RD2 is connected to another second terminal of the first interface I1. The port RD1 and the port RD2 on another data transceiving module 130 are connected to the two first terminals of the first interface I1, respectively. RD1 RD1 RD1

[0024] The logic control port of the SoC chip 140 is connected to the control end of the channel switching module 120, and the data transceiving end of the SoC chip 140 is connected to the data interface end of the data transceiving module 130 for sending data to the data transceiving module 130 or receiving data from the data transceiving module 130, that is, the SoC chip 140 and the data transceiving module 130 can perform bidirectional data transmission. The SoC chip 140 is also connected to the channel switching module 120 to send a control signal to the channel switching module 120, so as to realize the switching control of the data sending channel.

[0025] ​​​It can be understood that the channel switching module 120 is connected with the data sending end of one data transceiver module 130 and the data receiving end of another data transceiver module 130 through the input end thereof, and the data receiving end of the data transceiver module 130 is also connected with the second terminal of the corresponding transceiver interface 110. Based on this, the switching of the data channel of different transmission directions is realized by controlling the channel switching module 120, such as controlling the channel switching module 120 to enable the data sent by the first device to flow into another transceiver interface 110 through the channel switching module 120 after passing through the transceiver interface 110, thereby being transmitted to the second device, or enabling the data sent by the second device to flow into another transceiver interface 110 through the channel switching module 120 after passing through the transceiver interface 110, thereby being transmitted to the first device. And after the channel switching module 120 is controlled to switch, the transmission requirement of the full-duplex signal of the gigabit Ethernet can also be adapted by the data transceiver module 130 to realize the data transmission of the gigabit Ethernet. That is, by controlling the channel switching module 120, different data transmission modes are realized and the transmission requirements of different protocols are adapted.

[0026] Optionally, in an embodiment, the SoC chip is also connected with a storage unit and stores data in the storage unit, and the storage unit includes at least one of a storage card corresponding to an SD type, a memory corresponding to a DDR3 type, and an embedded flash memory corresponding to an EMMC type. That is, the SoC chip can store data in the storage unit or read data from the storage unit and send it to other devices, for example, the SoC chip is connected with a storage card corresponding to an SD (Secure Digital) type, a memory corresponding to a DDR3 (Double-Data-Rate Three) type, and an embedded flash memory corresponding to an EMMC type, and then stores the received data in the corresponding storage device, wherein the embedded flash memory corresponding to the EMMC type is used to store system firmware, the memory corresponding to the DDR3 type is used for caching Ethernet data, and the storage card corresponding to the SD type is used to save the parsed Ethernet signal for offline analysis by the user.

[0027] As can be known from the above scheme, the data transceiver circuit of the present scheme can adapt to different Ethernet modes based on the switching of the transmission channel on the channel switching module, thereby guaranteeing the "zero delay" acquisition requirement of EtherCAT and other real-time Ethernet, and also meeting the full-duplex communication requirement of data acquisition in gigabit Ethernet, so that the Ethernet data transceiver circuit of the present scheme can provide a more reliable data acquisition scheme and meet the multi-protocol coexistence requirement.

[0028] In an embodiment, the data transceiver module comprises a double differential driving unit, a PHY chip and an isolation transformer. Specifically, the double differential driving unit is configured to provide a full duplex transmission channel. The double differential driving unit comprises two first transceiving ends and two second transceiving ends, the first transceiving ends correspond to the second transceiving ends one by one, the isolation transformer comprises four signal access ends and four output ends, and the output ends of the isolation transformer correspond to the corresponding signal access ends respectively to realize the transmission of signals.

[0029] To this end, the two first transceiving ends of the double differential driving unit are respectively configured as two data receiving ends of the data transceiver module, and the two second transceiving ends of the double differential driving unit are respectively connected to two signal access ends in the isolation transformer. The other two signal access ends in the isolation transformer are respectively configured as two data sending ends of the data transceiver module, the four output ends of the isolation transformer are respectively connected to the first signal transceiving ends of the PHY chip, and the second signal transceiving ends of the PHY chip are connected to the data transceiving ends of the SoC chip. It is conceivable that a plurality of interface terminals are arranged on the first signal transceiving ends and the second signal transceiving ends of the PHY chip, so as to be connected to the isolation transformer and the SoC chip. Alternatively, the PHY chip and the SoC chip are connected based on an RGMII interface, the RGMII interface is a 4-bit data interface, and the transmission efficiency is high, so that fast data transmission between the PHY chip and the SoC chip can be realized. It can be understood that the double differential driving unit provides a full duplex transmission channel, that is, the data transceiver module can receive data from the transceiving interface or send data to the transceiving interface through the double differential driving unit, thereby realizing the data transceiving function. Therefore, by providing a full duplex transmission channel through the double differential driving unit, and by mode switching realized through the channel switching module, the Ethernet data transceiver circuit can adapt to the data acquisition requirement of the gigabit Ethernet, thereby helping to provide a reliable data acquisition channel.

[0030] In some embodiments, the double differential driving unit comprises two differential sub-units, and the input end of each differential sub-unit is connected to the output end of the other differential sub-unit. It can be understood that the input end of each differential sub-unit to its output end is equivalent to a transmission channel. By connecting the input end of one differential sub-unit to the output end of the other differential sub-unit, and connecting the output end of the one differential sub-unit to the input end of the other differential sub-unit, a bidirectional transmission channel is provided to realize the transmission of full duplex signals of the gigabit Ethernet. The double differential driving unit of the present scheme provides a full duplex transmission channel to adapt to the data transmission requirement, so that different channels can be switched to meet the multi-protocol coexistence requirement, and the scheme structure is simple and more efficient.

[0031] Alternatively, Figure 2As shown in the circuit structure diagram of the differential subunit provided in an embodiment of the present application, the differential subunit comprises a differential driver Q1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The positive output terminal of the differential driver Q1 is connected to the first resistor R1, the negative output terminal of the differential driver Q1 is connected to the second resistor R2, the inverting input terminal of the differential driver Q1 is connected to the first capacitor C1, and the non-inverting input terminal of the differential driver Q1 is connected to the second capacitor C2. The positive power supply voltage terminal of the differential driver Q1 is connected to the first terminal of the third capacitor C3, the first terminal of the third capacitor C3 is connected to a positive voltage, the fourth capacitor C4 is connected in parallel with the third capacitor C3, and the second terminal of the third capacitor C3 is grounded. The negative power supply voltage terminal of the differential driver Q1 is connected to the first terminal of the fifth capacitor C5, the first terminal of the fifth capacitor C5 is connected to a negative voltage, the sixth capacitor C6 is connected in parallel with the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is grounded. It can be understood that the positive voltage and the negative voltage connected to the differential driver Q1 can be provided by an isolation power supply, and a better low-distortion performance can be obtained by using a negative power supply. The signal is connected through the first capacitor C1 and the second capacitor C2 on the inverting input terminal and the non-inverting input terminal of the differential driver Q1. The first capacitor C1 and the second capacitor C2 can also isolate the direct current voltage on the Ethernet cable. The first resistor R1 and the second resistor R2 serve as matching resistors, which form impedance matching in the transmission line to improve signal integrity.

[0032] Optionally, the differential driver is a high-speed differential driver, which can provide double signal gain. It can be understood that the resistance connected to the output terminal of the high-speed differential driver on the transmission line will attenuate the output signal by half. In the case where the high-speed differential driver provides double signal gain, even if the output signal is attenuated by half, the net gain of the system end to end can still remain 1, that is, consistent with the original signal amplitude, which helps to ensure complete signal transmission.

[0033] Figure 3 As shown in the circuit structure diagram of the channel switching module provided in an embodiment of the present application, in an embodiment, the channel switching module comprises an NPN transistor Q2, a third resistor R3, a fourth resistor R4, a seventh capacitor C7, an eighth capacitor C8, a diode D1, and a double-switch relay. Specifically, the base terminal of the NPN transistor Q2 is connected to the first terminal of the third resistor R3, the second terminal of the third resistor R3 serves as the control terminal of the channel switching module, the first terminal of the fourth resistor R4 is connected to the second terminal of the third resistor R3, the second terminal of the fourth resistor R4 is connected to the emitter terminal of the NPN transistor Q2, and the emitter terminal of the NPN transistor Q2 is grounded.

[0034] The collector terminal of the NPN transistor Q2 is connected to the negative terminal of the coil K1C of the double switch relay, and the positive terminal of the coil K1C of the double switch relay is connected to the working voltage, and the double switch relay is used to control the switching of the first switch K1A and the second switch K1B through the coil K1C, and the first switch K1A and the second switch K1B are used to provide the first data transmission channel and the second data transmission channel respectively. The negative terminal of the coil K1C of the double switch relay is also connected to the seventh capacitor C7 grounded, and the positive terminal of the coil K1C of the double switch relay is also connected to the eighth capacitor C8 grounded, the anode terminal of the diode D1 is connected to the negative terminal of the coil K1C of the double switch relay, and the cathode terminal of the diode D1 is connected to the positive terminal of the coil K1C of the double switch relay.

[0035] It can be understood that after receiving the control signal provided by the SoC chip at a high level, the base terminal of the NPN transistor Q2 receives the signal through the third resistor R3, and then the NPN transistor Q2 is turned on, so that the coil K1C of the double switch relay connected to the working voltage can form a conduction loop through the NPN transistor Q2, that is, the coil K1C is powered on. Under the action of the powered coil K1C, the first switch K1A and the second switch K1B are switched to switch the first data transmission channel to the second data channel or the second data channel to the first data channel. As shown in the figure, in the case where the coil K1C is not powered on, the first input terminal of the first switch K1A is connected to the transceiver interface, the second input terminal of the first switch K1A is connected to the isolation transformer in the data transceiver module, the first input terminal of the second switch K1B is connected to the transceiver interface, and the second input terminal of the second switch K1B is connected to the isolation transformer in the data transceiver module. At this time, the first input terminal and the output terminal of the first switch K1A are in communication, and the first input terminal and the output terminal of the second switch K1B are in communication. Based on this, when the coil K1C is powered on, the first switch K1A and the second switch K1B are switched, that is, the second input terminal and the output terminal of the first switch K1A are in communication, and the second input terminal and the output terminal of the second switch K1B are in communication. Therefore, the present scheme uses the conduction control of the switch tube to realize the switching of different data channels in the channel switching module, effectively realizes the transmission control of the data, and further improves the reliability of the circuit in the Ethernet data transmission.

[0036] Figure 4As shown in the structural schematic diagram of the Ethernet data transceiving circuit provided by an embodiment of the present application, the transceiving interface of the Ethernet data transceiving circuit includes at least one pair, and the transceiving interface can be an RJ45 interface. The transceiving interface includes an interface NET0 and an interface NET1, and each transceiving interface includes two first terminals (such as terminals TD_0+ and TD_0-) for transmitting data and two second terminals (such as terminals RD_0+ and RD_0-) for receiving data. The channel switching module is also provided with at least two channels corresponding to the transceiving interfaces, wherein the two output terminals of the channel switching module are connected to the two first terminals of the transceiving interfaces (such as the terminals TD_0+ and TD_0- of the interface NET0), the two input terminals of the channel switching module are connected to the second terminals of the other transceiving interface (such as the terminals RD_0+ and RD_0- of the interface NET1), and the other two input terminals of the channel switching module are connected to two signal access terminals of the isolation transformer in the data transceiving module, which correspond to the two first terminals of the transceiving interfaces.

[0037] In addition, the two second terminals of the transceiving interface are also connected to the input terminal of a differential driver of a double differential driving unit in the data transceiving module, and the output terminal of the differential driver is connected to the other two signal access terminals of the isolation transformer. The double differential driving unit is also provided with another differential driver, which is connected in reverse parallel with the other differential driver, that is, the input terminal of the differential driver is connected to the output terminal of the other differential driver, and the output terminal of the differential driver is also connected to the input terminal of the other differential driver. The output terminal of the isolation transformer is connected to the first signal transceiving terminal of the PHY chip, and the second signal transceiving terminal of the PHY chip is connected to the data transceiving terminal of the SoC chip. The SoC chip is also connected to a storage card of the SD type, a memory of the DDR3 type, and an embedded flash memory of the EMMC type.

[0038] It can be understood that the interface NET0 accesses the first device for transmitting data, the interface NET1 accesses the second device for receiving data, and the SoC chip can output corresponding control signals through the logic control port thereon to enable the channel switching module to switch different input terminals to form a first data transmission channel or a second data transmission channel. As shown in the figure, when the input terminals conducting in the control channel switching module are switched to the two input terminals connected to the second terminals on another transceiver interface, the data transmitted from the first device enters from the interface NET0 and flows out from the interface NET1, and after the data enters from the interface NET0, it is divided into two parts, one of which is forwarded to the interface NET1 through the transmission channel formed by the channel switching module. This path is a hardware direct connection and does not introduce time delay to the signal, which can maintain the properties of the original communication link, that is, it realizes direct forwarding through the interface, effectively eliminates the time delay, and thus can effectively meet the real-time requirements of EtherCAT. The other part is connected to the isolation transformer through the gain of the differential driver. Due to the high impedance input of the differential driver, on the one hand, the impedance change caused by the signal to the transformer is avoided, and on the other hand, the differential signal is boosted to enhance the driving capability and reduce the probability of communication error and device failure.

[0039] However, when the input terminals conducting in the control channel switching module are switched to the two input terminals connected to the two signal access terminals in the isolation transformer, full-duplex communication is required in the gigabit Ethernet acquisition mode. For this purpose, another differential driver is connected in reverse parallel on the differential driver, so as to form two transmission channels in different directions to provide a bidirectional transmission channel after the signal is accessed through the second terminal on the interface NET0 or the interface NET1, thereby realizing full-duplex communication to avoid signal superposition during bidirectional transmission.

[0040] The application also provides a circuit board comprising the Ethernet data transceiver circuit provided in the above embodiments, which is connected with other devices to access the data transmitted by other devices, thereby ensuring "zero delay" acquisition of EtherCAT and other real-time Ethernet, avoiding signal interference, and being compatible with different Ethernet scenarios. The scheme can optimize the data path, use high-impedance differential driving, and introduce a mode switching mechanism to accurately solve the pain points of industrial Ethernet data acquisition and support efficient and stable operation of industrial automation. Through mode switching of the relay in the channel switching module, the Ethernet data transceiver circuit of the scheme is also applicable to data acquisition and analysis of gigabit Ethernet.

[0041] The application also provides a data transceiving device, which comprises the circuit board provided by the above-mentioned embodiments, and can be connected with a device in need of data transmission, and can also realize switching of different modes through the circuit structure thereon, so as to guarantee "zero delay" collection of real-time Ethernet such as EtherCAT and compatibility with different Ethernet scenes, and then efficiently realize data transmission and collection.

[0042] It should also be noted that the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device comprising the element.

[0043] It should be noted that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. An Ethernet data transceiver circuit, characterized in that, include: At least one pair of transceiver interfaces, the pair of transceiver interfaces being used to connect a first device and a second device, so that the first device and the second device can transmit data; A channel switching module is provided, which corresponds one-to-one with the transceiver interface. The channel switching module includes four input terminals and two output terminals. The two output terminals of the channel switching module are respectively connected to two first terminals on the corresponding transceiver interface for sending data. In the channel switching module, a pair of input terminals corresponds to one output terminal and is used to switch different input terminals and form a first data transmission channel or a second data transmission channel when a control signal is received. A data transceiver module, which corresponds one-to-one with the channel switching module, includes two data transmitting ends and two data receiving ends. The two data transmitting ends of the data transceiver module are respectively connected to the two input ends of the channel switching module corresponding to the first data transmitting channel. The two data receiving ends of the data transceiver module are connected to the two second terminals on the transceiver interface corresponding to the channel switching module for receiving data. The two data receiving ends of the data transceiver module are also connected to the two input ends of another channel switching module corresponding to the second data transmitting channel. The channel switching module to which the data transmitting ends of the data transceiver module are connected and the other channel switching module to which the data receiving ends of the data transceiver module are connected are both used to connect to the same pair of transceiver interfaces. The SoC chip has its logic control port connected to the control terminal of the channel switching module, and its data transceiver terminal connected to the data interface terminal of the data transceiver module for sending data to or receiving data from the data transceiver module.

2. The Ethernet data transceiver circuit according to claim 1, characterized in that, The data transceiver module includes a dual differential drive unit, a PHY chip, and an isolation transformer; The two first transceiver terminals of the dual differential drive unit serve as the two data receiving terminals of the data transceiver module, and the two second transceiver terminals of the dual differential drive unit are respectively connected to the two signal input terminals in the isolation transformer. The dual differential drive unit is used to provide a full-duplex transmission channel. The other two signal input terminals of the isolation transformer serve as the two data transmission terminals of the data transceiver module, and the four output terminals of the isolation transformer are respectively connected to the first signal transceiver terminal of the PHY chip. The second signal transceiver terminal of the PHY chip is connected to the data transceiver terminal of the SoC chip.

3. The Ethernet data transceiver circuit according to claim 2, characterized in that, The dual differential drive unit includes two differential numerator units, and the input of each differential numerator unit is connected to the output of the other differential numerator unit.

4. The Ethernet data transceiver circuit according to claim 3, characterized in that, The differential numerator unit includes a differential driver, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; The positive output terminal of the differential driver is connected to the first resistor, the negative output terminal of the differential driver is connected to the second resistor, the inverting input terminal of the differential driver is connected to the first capacitor, and the non-inverting input terminal of the differential driver is connected to the second capacitor. The positive power supply voltage terminal of the differential driver is connected to the first terminal of the third capacitor, the first terminal of the third capacitor is connected to a positive voltage, the fourth capacitor is connected in parallel with the third capacitor, and the second terminal of the third capacitor is grounded; the negative power supply voltage terminal of the differential driver is connected to the first terminal of the fifth capacitor, the first terminal of the fifth capacitor is connected to a negative voltage, the sixth capacitor is connected in parallel with the fifth capacitor, and the second terminal of the fifth capacitor is grounded.

5. The Ethernet data transceiver circuit according to claim 4, characterized in that, The differential driver is a high-speed differential driver, and the high-speed differential driver is used to provide twice the signal gain.

6. The Ethernet data transceiver circuit according to any one of claims 2-5, characterized in that, The PHY chip and the SoC chip are connected via the RGMII interface.

7. The Ethernet data transceiver circuit according to claim 1 or 2, characterized in that, The channel switching module includes an NPN transistor, a third resistor, a fourth resistor, a seventh capacitor, an eighth capacitor, a diode, and a dual-switch relay. The base of the NPN transistor is connected to the first end of the third resistor, the second end of the third resistor serves as the control terminal of the channel switching module, the first end of the fourth resistor is connected to the second end of the third resistor, the second end of the fourth resistor is connected to the emitter of the NPN transistor, and the emitter of the NPN transistor is grounded. The collector of the NPN transistor is connected to the negative terminal of the coil of the dual-switch relay, and the positive terminal of the coil of the dual-switch relay is connected to the working voltage. The dual-switch relay is used to control the switching of the first switch and the second switch through the coil. The first switch and the second switch are respectively used to provide the first data transmission channel and the second data transmission channel. The negative terminal of the coil of the dual-switch relay is also connected to the grounded seventh capacitor, and the positive terminal of the coil of the dual-switch relay is also connected to the grounded eighth capacitor. The anode of the diode is connected to the negative terminal of the coil of the dual-switch relay, and the cathode of the diode is connected to the positive terminal of the coil of the dual-switch relay.

8. The Ethernet data transceiver circuit according to claim 1, characterized in that, The SoC chip is also connected to a storage unit and stores data in the storage unit, which includes at least one of a memory card of type SD, internal memory of type DDR3, and embedded flash memory of type EMMC.

9. A circuit board, characterized in that, Includes the Ethernet data transceiver circuit as described in any one of claims 1-8.

10. A data transceiver device, characterized in that, Includes the circuit board as described in claim 9.

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