Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a bit line extending in a first direction on a substrate; a gate isolation insulating layer disposed on the bit line and extending in a second direction crossing the first direction and standing in a third direction; a channel layer extending along a side surface of the gate isolation insulating layer and a top surface of the bit line between the gate isolation insulating layer and an adjacent gate isolation insulating layer; a cover insulating layer configured to cover the channel layer; and a word line disposed on a side surface of the capping insulating layer over the gate isolation insulating layer. A bottom surface of the word line may not contact a top surface of a capping insulating layer disposed between the gate isolation insulating layer and an adjacent gate isolation insulating layer.

Description

Cross Reference to Related Applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0067808, filed May 24, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference for all purposes. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a vertical channel transistor (VCT) and a method of manufacturing the same. BACKGROUND

[0003] The integration density of a two-dimensional (2D) or planar semiconductor memory device can be determined mainly by the area occupied by a unit memory cell, and thus the integration density can be significantly affected by a technology for forming a fine pattern. An apparatus required to improve pattern fineness can impose a limitation on increasing the integration density of a 2D semiconductor memory device. A vertical channel transistor formed vertically on a semiconductor substrate has been proposed as an alternative to a planar channel transistor on a semiconductor substrate. SUMMARY

[0004] One or more embodiments provide a semiconductor device in which word line residues can be effectively prevented from being formed or left between bit lines adjacent to each other, and a method of manufacturing the same.

[0005] The problems to be solved by the disclosure are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0006] According to an aspect, a semiconductor device including a vertical channel transistor includes a substrate, a bit line disposed on the substrate and extending in a first direction, a gate isolation insulating layer disposed on the bit line and extending in a second direction crossing the first direction and standing in a third direction perpendicular to the substrate, a channel layer extending along side surfaces of the gate isolation insulating layer and top surfaces of the bit line between the gate isolation insulating layers and adjacent gate isolation insulating layers, a cover insulating layer configured to cover the channel layer, and a word line disposed on side surfaces of the cover insulating layer above the gate isolation insulating layer. A bottom surface of the word line can be spaced apart from a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0007] A top surface of a first portion of the bit line under the gate isolation insulating layer can be formed at a position higher than a bottom surface of the word line.

[0008] A top surface of a first portion of the bit line under the gate isolation insulating layer can be formed at a position same as a bottom surface of the word line.

[0009] A top surface of a first portion of the bit line under the gate isolation insulating layer can be formed at a position lower than a bottom surface of the word line and higher than a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0010] An offset region can be formed between a bottom surface of the word line and a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0011] An upper surface of the offset region can be formed as a horizontal surface, an inclined surface, a stepped surface, or a surface recessed toward the cover insulating layer.

[0012] The semiconductor device can further include a fill insulating layer disposed in a space between the gate isolation insulating layer and the adjacent gate isolation insulating layer. The fill insulating layer can be disposed in the offset region.

[0013] The gate isolation insulating layer can include a first insulating layer disposed on the bit line, and a second insulating layer disposed on the first insulating layer.

[0014] The semiconductor device can further include a data storage pattern electrically connected to the channel layer, and a landing pad disposed between the channel layer and the data storage pattern.

[0015] The semiconductor device can further include an insulating film disposed between the bit line and the substrate.

[0016] According to another aspect, a semiconductor device including a vertical channel transistor can include a substrate; a bit line disposed on the substrate and extending in a first direction; a gate isolation insulating layer disposed on the bit line and extending in a second direction crossing the first direction and standing in a third direction; a channel layer extending along side surfaces of the gate isolation insulating layer and a top surface of the bit line between the gate isolation insulating layer and an adjacent gate isolation insulating layer; a cover insulating layer configured to cover the channel layer; a fill insulating layer disposed on the cover insulating layer; and a word line disposed on the fill insulating layer and on side surfaces of the cover insulating layer above the gate isolation insulating layer.

[0017] An offset region can be formed between a bottom surface of the word line and a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer, and the bottom surface of the word line can be spaced apart from the top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0018] An upper surface of the offset region can be formed as a horizontal surface, an inclined surface, a stepped surface, or a surface recessed toward the cover insulating layer.

[0019] According to another aspect, a method of manufacturing a semiconductor device includes forming a bit line extending in a first direction on a substrate; forming a gate isolation insulating layer extending in a second direction crossing the first direction on the bit line and standing in a third direction perpendicular to the substrate, the gate isolation insulating layer being disposed adjacent to an adjacent gate isolation insulating layer; forming a channel layer extending along side surfaces of the gate isolation insulating layer and a top surface of the bit line between the gate isolation insulating layer and the adjacent gate isolation insulating layer; forming a cover insulating layer configured to cover the channel layer; forming a sacrificial pattern layer on the cover insulating layer; forming a word line on the sacrificial pattern layer and the cover insulating layer; and removing the sacrificial pattern layer.

[0020] Forming the sacrificial pattern layer can include forming the sacrificial pattern layer up to a same height as a top surface of the cover insulating layer covering a second portion of the bit line outside the gate isolation insulating layer.

[0021] Forming the bit line can include forming the bit line having a uniform thickness.

[0022] Forming the sacrificial pattern layer can include forming the sacrificial pattern layer up to a position higher than the top surface of the cover insulating layer covering the second portion of the bit line outside the gate isolation insulating layer.

[0023] Forming the bit line can include forming a first portion of the bit line under the gate isolation insulating layer to be thicker than a second portion of the bit line outside the gate isolation insulating layer.

[0024] A top surface of the bit line under the gate isolation insulating layer can be formed at a position higher than a bottom surface of the word line.

[0025] A top surface of the first portion of the bit line under the gate isolation insulating layer can be formed at a same position as the bottom surface of the word line.

[0026] A top surface of the first portion of the bit line under the gate isolation insulating layer can be formed at a position lower than the bottom surface of the word line and higher than a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0027] Removing the sacrificial pattern layer can include forming an offset region between a bottom surface of the word line and a top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

[0028] Forming the word line can include depositing a material; and partially etching the material to form the word line on a side surface of the cover insulating layer above the gate isolation insulating layer.

[0029] The method can further include forming a fill insulating layer filling a space between the plurality of gate isolation insulating layers.

[0030] The method can further include forming an anchor pad connected to the trench layer, and forming a data storage pattern connected to the anchor pad.

[0031] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description, or can be learned by practice of the disclosure.

[0032] According to an embodiment, a semiconductor device and a method of manufacturing the same can effectively suppress or prevent a word line residue from being formed or left between bit lines adjacent to each other.

[0033] According to an embodiment, a semiconductor device and a method of manufacturing the same can effectively suppress or prevent a word line bridge from being formed due to a word line residue formed or left between bit lines adjacent to each other.

[0034] Accordingly, according to an embodiment, a semiconductor device and a method of manufacturing the same can prevent a problem from occurring in the operation of a transistor due to an uneven flow of current between a source and a drain when a word line bridge is formed.

[0035] Effects according to the present disclosure are not limited to what has been described above, and other effects not mentioned above will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0036] The embodiments will become more fully understood from the detailed description given herein below and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present disclosure, and wherein:

[0037] FIG. 1A 、 FIG. 1B 、 FIG. 1C and FIG. 1D shows a semiconductor device according to the related art;

[0038] FIG. 2 is a block diagram showing a semiconductor memory device having a semiconductor device according to an embodiment;

[0039] FIG. 3 is a circuit diagram schematically showing a semiconductor memory device having a semiconductor device according to an embodiment;

[0040] FIG. 4 is a layout diagram showing a semiconductor device according to an embodiment;

[0041] FIG. 5 is a perspective view showing a semiconductor device according to an embodiment;

[0042] FIG. 6 is a cross-sectional view taken along line K-K' of FIG. 5

[0043] ​FIG. 7 It is along FIG. 5 A cross-sectional view taken from line M-M';

[0044] FIG. 8 It is along FIG. 5 The cross-sectional view of an example semiconductor device according to an embodiment is shown by line K-K'.

[0045] FIG. 9 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0046] FIG. 10 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0047] FIG. 11 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0048] FIG. 12 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0049] FIG. 13 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0050] FIG. 14 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0051] FIG. 15 It is along FIG. 5 The cross-sectional view of another example of a semiconductor device according to an embodiment is shown by line K-K'.

[0052] FIG. 16 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment;

[0053] FIGS. 17A-17B , FIGS. 18A-18B , FIGS. 19A-19B , FIGS. 20A-20B , FIGS. 21A-21B , FIGS. 22A-22B , FIGS. 23A-23B ,as well as FIGS. 24A-24B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device; and

[0054] FIGS. 25A-25B ,FIGS. 26A-26B , FIGS. 27A-27B , FIGS. 28A-28B , FIGS. 29A-29B , FIGS. 30A-30B , FIGS. 31A-31B ,as well as FIGS. 32A-32B This is a cross-sectional view of another example used to describe a method for manufacturing a semiconductor device. Detailed Implementation

[0055] In the following, embodiments will be described in detail with reference to the accompanying drawings. This disclosure allows for various changes and multiple embodiments, which will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the embodiments to specific implementations, and it should be understood that this disclosure covers all changes, equivalents, and substitutions without departing from the spirit and scope of the inventive concept. In this disclosure, certain detailed descriptions may be omitted where they would obscure the essence of the inventive concept.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. It will also be understood that the terms “comprising / including” and / or “including / including” as used herein mean the presence of the said feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Terms such as those defined in common dictionaries shall be interpreted as having the same meaning as in the context of the relevant technology and this disclosure, and shall not be interpreted as having an ideal or overly formal meaning unless expressly defined herein.

[0058] The same reference numerals refer to the same components, and repetitive descriptions related to them may be omitted or simplified. Detailed descriptions of well-known related structures or functions may be omitted in the description to support a clear and concise presentation.

[0059] Additionally, terms such as first, second, A, B, (a), (b) may be used in this document to describe components. Each of these terms is not intended to define the nature, order, or sequence of the corresponding component, but only to distinguish the corresponding component from other components. It should be noted that if a component is described in the specification as being "connected," "coupled," or "joined" to another component, the former may be directly "connected," "coupled," or "joined" to the latter, or may be "connected," "coupled," or "joined" to the latter via other components.

[0060] Repetitive description of components can be omitted or simplified. Unless otherwise disclosed, a description of any aspect, component or method can apply to various embodiments and repetitive description thereof can be omitted or simplified.

[0061] FIG. 1A 、 FIG. 1B 、 FIG. 1C and FIG. 1D shows a conventional semiconductor device. FIG. 1A is a perspective view of the conventional semiconductor device. FIG. 1B is a top view of the semiconductor device of FIG. 1A . FIG. 1C is a cross-sectional view taken along line I-I' of FIG. 1A . FIG. 1D is a cross-sectional view taken along line J-J' of FIG. 1A .

[0062] Referring to FIG. 1A , in the conventional semiconductor device 100, the bit lines BL can extend in a first direction D1, and the word lines WL can extend in a second direction D2 crossing the first direction D1.

[0063] Referring to FIGS. 1B-1D , a space can be formed between the word lines WL adjacent to each other by etching a material for forming the word lines WL.

[0064] Due to the process of forming the space between the word lines WL adjacent to each other, the material for forming the word lines WL can not exist in an upper surface portion A of the cover insulating layer 130 covering the bit lines BL, where the upper surface portion A is outside the gate isolation insulating layer 110.

[0065] However, the word line residues WL_R and the word line bridges WL_B can be formed in portions between the bit lines BL adjacent to each other (i.e., at portions where the bit lines BL are not disposed).

[0066] Specifically, the bit line isolation insulating layers 150 can be disposed between the bit lines BL adjacent to each other. The cover insulating layer 130 can be disposed on the bit line isolation insulating layers 150. The word line residues WL_R can remain in the regions B adjacent to the bit lines BL in the upper surface portion of the cover insulating layer 130 covering the bit line isolation insulating layers 150. The word line residues WL_R between the bit lines BL can be connected to each other by the word line bridges WL_B. The word line bridges WL_B can be in the center regions C in the upper surface portion of the cover insulating layer 130 covering the bit line isolation insulating layers 150.

[0067] When the word line bridge WL_B is formed, the smooth flow of current between the source and the drain can be suppressed, which can cause problems to occur in the operation of the transistor. In a process of manufacturing a conventional semiconductor device, a step can be generated between the bit line BL and the bit line isolation insulating layer 150, which can cause the word line residue WL_R and the word line bridge WL_B to be formed. For example, in a process of performing etching to form the plurality of gate isolation insulating layers 110, and a process of performing etching to form the channel layer 120 on the bit line BL, a step can be generated.

[0068] FIG. 2 is a block diagram illustrating a semiconductor memory device having a semiconductor device according to an embodiment.

[0069] The semiconductor memory device can include a memory cell array 1, a row decoder 2, a sense amplifier 3 (sense amplifier), a column decoder 4, and control logic 5. For example, the semiconductor memory device can be implemented as a dynamic random access memory (DRAM) device.

[0070] The memory cell array 1 can include a plurality of memory cells MC. The plurality of memory cells MC can be arranged two-dimensionally or three-dimensionally. For example, the memory cell array 1 can be disposed on a surface of a substrate, and a plane of the memory cell array 1 can be parallel to a plane of the substrate. Each memory cell MC can be connected to a word line WL and a bit line BL that cross each other.

[0071] Each memory cell MC can include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS can be electrically connected to each other. The selection element TR can be connected to both the word line WL and the bit line BL. For example, the selection element TR can be disposed at a position at which the word line WL and the bit line BL cross each other. The selection element TR can include, for example, a field effect transistor (FET). The data storage element DS can include, for example, a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the selection element TR can be a transistor, and the transistor can include a gate electrode connected to the word line WL, a source terminal connected to one of the bit line BL or the data storage element DS, and a drain terminal connected to the other of the bit line BL or the data storage element DS that is not connected to the source terminal.

[0072] The selection element TR of each memory cell MC can include a vertical channel transistor (VCT). A length direction of a channel of the vertical channel transistor (VCT) can be perpendicular to a surface (e.g., a top surface) of a substrate. The data storage element DS of each memory cell MC can include a data storage pattern DSP.

[0073] The row decoder 2 can decode an address input from the outside of the semiconductor storage device. The row decoder 2 can select a word line WL of the memory cell array 1 based on a result obtained by decoding the address. A result obtained by decoding the address in the row decoder 2 (e.g., a decoded address) can be supplied to a row driver (not shown). The row driver can supply a predetermined voltage to the selected word line WL and the unselected word line, respectively, in response to a control signal of the control circuit.

[0074] The sense amplifier 3 can sense, amplify, and output a voltage difference between a reference bit line and a bit line BL selected based on an address decoded by the column decoder 4.

[0075] The column decoder 4 can provide a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can decode an externally input address to select a bit line BL.

[0076] The control logic 5 can generate a control signal that can be used to control an operation of writing data to or reading data from a corresponding memory cell in the memory cell array 1.

[0077] For reference, the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 are shown as being around the memory cell array 1, however, embodiments are not limited thereto. For example, a peripheral circuit including the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 can be disposed on a plane different from a plane on which the memory cell array 1 is disposed. The peripheral circuit can be disposed above or below the memory cell array 1, for example, using a circuit over periphery (COP) structure. In an example, the peripheral circuit can be disposed on a substrate, and the memory cell array 1 can be disposed on the peripheral circuit. In another example, the peripheral circuit can be disposed on a first substrate, and the memory cell array 1 can be disposed on a second substrate. In this example, the first substrate and the second substrate can face each other.

[0078] FIG. 3 is a circuit diagram schematically illustrating a semiconductor storage device having a semiconductor device according to an embodiment.

[0079] Reference FIG. 3 A semiconductor storage device having a semiconductor device can include a peripheral circuit structure PS, a substrate CC, and a cell array structure CS. The peripheral circuit structure PS can be disposed on the substrate CC. The cell array structure CS can be disposed on the peripheral circuit structure PS.

[0080] The peripheral circuit structure PS can include a core and a peripheral circuit (SWD / PERI) that can be formed on the substrate CC. The core and the peripheral circuit can include a referenceFIG. 2 A row decoder 2, a column decoder 4, a sense amplifier (S / A) 3, and control logic 5 are described. A peripheral circuit structure PS can be provided between the substrate CC and the cell array structure CS in a third direction D3 perpendicular to the top surface of the substrate CC.

[0081] For reference, the first direction D1 and the second direction D2 can be directions parallel to the top surface of the substrate CC and perpendicular to each other. The third direction D3 can be a direction perpendicular to the first direction D1 and the second direction D2.

[0082] The cell array structure CS can include bit lines BL, word lines WL, and memory cells (e.g., memory cells MC) at intersections of the bit lines BL and the word lines WL. FIG. 2 The memory cells (e.g., memory cells MC) can be arranged two-dimensionally or three-dimensionally on a plane parallel to the top surface of the substrate CC and can extend in the first direction D1 and the second direction D2 crossing each other. Each memory cell (e.g., memory cell MC) can include a selection element SE and a data storage element DS, as described herein. FIG. 2 FIG. 2

[0083] Each memory cell (e.g., memory cell MC) can include a vertical channel transistor (VCT) as the selection element SE. The vertical channel transistor can be a structure in which a channel extends in a third direction D3 perpendicular to the top surface of the substrate CC. In addition, each memory cell (e.g., memory cell MC) can include a capacitor as the data storage element DS. FIG. 2 FIG. 2

[0084] FIG. 4 is a layout view illustrating a semiconductor device according to an embodiment. FIG. 5 is a perspective view illustrating a semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view taken along line K-K' of FIG. 5 FIG. 7 is a cross-sectional view taken along line M-M' of FIG. 5 A semiconductor device according to an embodiment can include a memory cell having a vertical channel transistor (VCT).

[0085] Referring to FIGS. 4-7 , a semiconductor device 200 can include a substrate CC, a bit line BL, a gate isolation insulating layer 210, a channel layer 220, a cover insulating layer 230, a word line WL, an offset region OF_1, a fill insulating layer 240, a landing pad LP, a data storage pattern DSP, a bit line isolation insulating layer 250, and an insulating film 260. The gate isolation insulating layer 210 can include a first insulating layer 211 and a second insulating layer 212. ​​​​​

[0086] The substrate CC can extend in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can cross each other and can be parallel to a top surface of the substrate CC. The substrate CC can be a semiconductor substrate. The substrate CC can be a silicon substrate. In an embodiment, the substrate CC can include other materials (e.g., silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide), but is not limited thereto.

[0087] The bit line BL can be disposed on the substrate CC. The insulating film 260 can be disposed between the substrate CC and the bit line BL. The insulating film 260 can have a peripheral gate structure. The peripheral gate structure can include a peripheral gate insulating film, a peripheral lower conductive pattern, and a peripheral upper conductive pattern. The insulating film 260 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, but is not necessarily limited thereto.

[0088] The bit line BL can extend longitudinally in the first direction D1. For example, a plurality of bit lines BL can be disposed on the substrate CC and spaced apart from each other in the second direction D2.

[0089] The bit line BL can include, for example, at least one of doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), or LSCo), but is not limited thereto. The bit line BL can include a single layer or multiple layers that can include the materials described herein or combinations thereof. The bit line BL can include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material can include graphene or carbon nanotubes, or combinations thereof.

[0090] At least a portion of spaces between the bit lines BL can be filled with a bit line isolation insulating layer 250. The bit line isolation insulating layer 250 can include at least one of silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material can include, for example, a metal oxide or a metal oxynitride. The high-k dielectric material can include, for example, at least one of SiN, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but is not limited thereto. A height of the bit line isolation insulating layer 250 in the third direction D3 can be less than a height of the bit line BL.

[0091] The data storage pattern DSP can be electrically connected to the channel layer 220. The landing pad LP can be disposed between the channel layer 220 and the data storage pattern DSP.

[0092] The landing pad LP can have various shapes (e.g., a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape). The landing pad LP can include a conductive material. The landing pad LP can include, for example, at least one of doped polysilicon, a conductive metal nitride, a conductive metal nitride silicon, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, a metal, or a metal alloy.

[0093] The data storage pattern DSP can be disposed on the landing pad LP, respectively. The data storage pattern DSP can be arranged in a matrix form in the second direction D2 and the first direction D1. The data storage pattern DSP can completely or partially overlap the landing pad LP in the third direction D3. For example, an area of the data storage pattern DSP in a plan view can be less than or equal to an area of the landing pad LP on which the data storage pattern DSP is disposed. The data storage pattern DSP can be in contact with the entire top surface of the landing pad LP or a partial top surface of the landing pad LP.

[0094] The data storage pattern DSP can be a capacitor. The data storage pattern DSP can include a capacitor dielectric film interposed between a storage electrode and a plate electrode. The storage electrode can be in contact with the landing pad LP. In a plan view, the storage electrode can have various shapes (e.g., a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape).

[0095] In an embodiment, the data storage pattern DSP can be a variable resistance pattern. For example, the data storage pattern DSP can be switched between two resistance states by an electrical pulse applied to a storage element. For example, the data storage pattern DSP can include a phase change material having a crystalline state that can be changed according to an amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0096] The landing pad LP and the data storage pattern DSP are illustrated as being disposed above the bit line BL and the word line WL in the third direction D3, however, embodiments are not necessarily limited thereto. For example, the landing pad LP and the data storage pattern DSP can be disposed below the bit line BL and the word line WL in the third direction D3.

[0097] The gate isolation insulating layer 210 can extend in a second direction D2 crossing the first direction D1. The gate isolation insulating layer 210 can be disposed on the bit line BL. The gate isolation insulating layer 210 can have a height in a third direction D3 perpendicular to the substrate CC. The third direction D3 can be a direction perpendicular to both the first direction D1 and the second direction D2. For example, a plurality of gate isolation insulating layers 210 can be disposed on the bit line BL and spaced apart from each other by a predetermined distance.

[0098] The gate isolation insulating layer 210 can include a first insulating layer 211 and a second insulating layer 212. The gate isolation insulating layer 210 can include the first insulating layer 211 disposed on the bit line BL and the bit line isolation insulating layer 250, and the second insulating layer 212 disposed on the first insulating layer 211. For example, the first insulating layer 211 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, but is not necessarily limited thereto. The second insulating layer 212 can include at least one of silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material can include, for example, a metal oxide or a metal oxynitride. The high-k dielectric material can include, for example, at least one of SiN, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but is not limited thereto.

[0099] The channel layer 220 can extend along side surfaces of each of the gate isolation insulating layers 210 and a top surface of the bit line BL between the gate isolation insulating layers 210 adjacent to each other. The channel layer 220 can also extend along a top surface of each of the gate isolation insulating layers 210. For example, the channel layer 220 can also extend along a top surface of each of the second insulating layers 212. The channel layer 220 can not be formed on the bit line isolation insulating layer 250 disposed between the bit lines BL adjacent to each other, or on a portion of the gate isolation insulating layer 210 disposed above the bit line isolation insulating layer 250.

[0100] The channel layer 220 can include one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) doped with impurities, indium oxide (InO), zinc oxide (ZnO), gallium oxide (GaO), tin oxide (SnO), aluminum zinc oxide (AZO), or indium tin oxide (ITO). In the indium zinc oxide (IZO) doped with impurities, the impurities can include, for example, at least one of magnesium (Mg), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), tin (Sn), or tantalum (Ta). The same or different amounts of indium (In), gallium (Ga), and zinc (Zn) can be included in the IGZO. The channel layer 220 can be a single layer or a plurality of layers, but is not limited thereto.

[0101] The cover insulating layer 230 can cover the channel layer 220. The cover insulating layer 230 can also cover a portion exposed by the channel layer 220, for example, the gate isolation insulating layer 210 or the bit line isolation insulating layer 250 between the bit lines BL adjacent to each other. For example, the cover insulating layer 230 can be disposed directly on the bit line isolation insulating layer 250 disposed between the bit lines BL adjacent to each other, or on a portion of the gate isolation insulating layer 210 disposed above the bit line isolation insulating layer 250.

[0102] The cover insulating layer 230 can be disposed between the channel layer 220 and the word line WL. The cover insulating layer 230 can include a silicon oxide film, a silicon oxynitride film, a high-k dielectric insulating film having a dielectric constant greater than that of a silicon oxide film, or a combination thereof. The cover insulating layer 230 can also be formed of aluminum oxide (ALO). However, embodiments are not necessarily limited thereto.

[0103] The word line WL can be disposed on a sidewall of the cover insulating layer 230 disposed on a side of each gate isolation insulating layer 210. The word line WL can be disposed between the cover insulating layer 230 and the fill insulating layer 240. The word line WL can extend longitudinally in the second direction D2. Adjacent word lines WL can be spaced apart from each other in the first direction D1. A top surface of the word line WL can be formed at a height lower than that of a top surface of the fill insulating layer 240 or the cover insulating layer 230.

[0104] The word line WL can include at least one of, for example, doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), or LSCo), but is not limited thereto. The word line WL can include a single layer or multiple layers including the materials described herein. The word line WL can include a 2D semiconductor material. For example, the 2D semiconductor material can include graphene or a carbon nanotube, or a combination thereof.

[0105] The fill insulating layer 240 can be disposed on the plurality of gate isolation insulating layers 210 and the word line WL. The fill insulating layer 240 can fill a space between the plurality of gate isolation insulating layers 210. The fill insulating layer 240 can fill a space between the word lines WL adjacent to each other. The fill insulating layer 240 can also fill the offset region OF_1. The fill insulating layer 240 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, but is not necessarily limited thereto.

[0106] A bottom surface of the word line WL can be spaced apart from a top surface of the cover insulating layer 230 between the gate isolation insulating layers 210 adjacent to each other. An offset region OF_1 can be formed between the bottom surface of the word line WL and the top surface of the cover insulating layer 230 between the gate isolation insulating layers 210 adjacent to each other. Through the offset region OF_1, the bottom surface of the word line WL can be spaced apart from the top surface of the cover insulating layer 230. The fill insulating layer 240 can be disposed in the offset region OF_1. For example, the offset region OF_1 can be filled with the fill insulating layer 240. A top surface of the offset region OF_1 can be formed as a horizontal surface. The offset region OF_1 can be formed through the method of manufacturing a semiconductor device described herein.

[0107] Referring to FIG. 5 , a plurality of bit lines BL can be disposed on the substrate CC and extend in a first direction, and a plurality of gate isolation insulating layers 210 can be disposed on the bit lines BL and extend in a second direction crossing the first direction and stand in a third direction. Also, a channel layer 220 can extend along side surfaces of the gate isolation insulating layers 210 and a top surface of the bit line BL between the gate isolation insulating layers 210 adjacent to each other. The channel layer 220 can include a plurality of portions extending along each side surface of the gate isolation insulating layers 210 and the top surface of the bit line BL between the gate isolation insulating layers 210 adjacent to each other. For example, a portion of the channel layer 220 can extend along a side surface of the gate isolation insulating layer 210 and a top surface of the bit line BL between the gate isolation insulating layer 210 and an adjacent gate isolation insulating layer. A plurality of word lines WL can be disposed on side walls of the cover insulating layer 230 disposed on the sides of the gate isolation insulating layers 210. The plurality of word lines WL can have a flat top surface and a flat bottom surface disposed in parallel with the top surface. For example, a height of the word line WL above the cover insulating layer 230 can vary along a length of the word line WL. For example, a first height of the word line WL above the cover insulating layer 230 disposed on the bit line BL can be less than a second height of the word line WL above the cover insulating layer 230 disposed on the bit line isolation insulating layer.

[0108] Referring to FIG. 7 , in the semiconductor device 200 having the structure described herein, a material for forming the word line WL can not be present at an upper surface portion A' of the cover insulating layer 230 covering a portion of the bit line BL outside the gate isolation insulating layer 210. The word lines WL adjacent to each other can be completely separated from each other. A space can be formed between the word lines WL adjacent to each other and at least partially filled with the fill insulating layer 240. In addition, word line residue and word line bridging can not be present in a portion between the bit lines BL adjacent to each other, i.e., a portion in which the bit line BL is not formed.

[0109] In an embodiment, a bit line isolation insulating layer 250 can be disposed between the bit lines BL adjacent to each other. The cover insulating layer 230 can be disposed on the bit line isolation insulating layer 250. A word line residue can not exist in a region B' adjacent to the bit line BL on an upper surface portion of the cover insulating layer 230 covering the bit line isolation insulating layer 250. A word line bridge can not exist in a center region C' on the upper surface portion of the cover insulating layer 230 covering the bit line isolation insulating layer 250.

[0110] In other words, the material forming the word line WL can exist on the side surface of the cover insulating layer 230 above each gate isolation insulating layer 210. The material forming the word line WL can not exist in one or more other portions of the semiconductor device 200. In other words, the material forming the word line WL can exist only on the side surface of the cover insulating layer 230 above each gate isolation insulating layer 210.

[0111] In an embodiment, the semiconductor device 200 can effectively suppress or prevent leaving a word line residue and a word line bridge between the bit lines BL adjacent to each other. In addition, the electrical characteristics and reliability of the semiconductor device 200 can be improved.

[0112] Reference FIG. 6 The height LV1 of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height LV2 of the bottom surface of the word line WL in the third direction D3. The thickness of the first portion of the bit line BL under the gate isolation insulating layer 210 can be greater than the thickness of the second portion of the bit line BL outside the gate isolation insulating layer 210. Based on the structure of the bit line BL described above, the gate-underlap phenomenon of the word line WL can be prevented from occurring in response to the formation of the offset region OF_1.

[0113] Hereinafter, repetitive descriptions to which the technical idea described herein can be equally applicable can be omitted or simplified, and mainly the differences between various other embodiments are described.

[0114] FIG. 8 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment taken along a line K-K' of FIG. 5 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment taken along a line K-K' of

[0115] Reference FIG. 8 The height LV1 of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 of the semiconductor device 200-1 can be equal to the height LV2 of the bottom surface of the word line WL. The thickness of the first portion of the bit line BL under the gate isolation insulating layer 210 can be greater than the thickness of the second portion of the bit line BL outside the gate isolation insulating layer 210.

[0116] FIG. 9 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment taken along a line K-K' of FIG. 5FIG. 6 is a cross-sectional view of another example of a semiconductor device according to an embodiment, taken along line K-K' of FIG. 5.

[0117] Referring to FIG. 9 The height LV1 of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 of the semiconductor device 200-2 can be lower than the height LV2 of the bottom surface of the word line WL. Here, the height LV1 of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height LV3 of the top surface of the cover insulating layer 230 between the gate isolation insulating layers 210 adjacent to each other. The height LV1 of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be between the height LV2 of the bottom surface of the word line WL and the height LV3 of the top surface of the cover insulating layer 230 between the gate isolation insulating layers 210 adjacent to each other. The thickness of the first portion of the bit line BL under the gate isolation insulating layer 210 can be greater than the thickness of the second portion of the bit line BL outside the gate isolation insulating layer 210.

[0118] FIG. 10 FIG. 6 is a cross-sectional view of another example of a semiconductor device according to an embodiment, taken along line K-K' of FIG. 5. FIG. 5 FIG. 6 is a cross-sectional view of another example of a semiconductor device according to an embodiment, taken along line K-K' of FIG. 5.

[0119] Referring to FIG. 10 The upper surface of the offset region OF_2 of the semiconductor device 200-3 can be formed to be inclined. For example, the upper surface of the offset region OF_2 of the semiconductor device 200-3 can be formed to be inclined upward from the cover insulating layer 230 to the fill insulating layer 240. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0120] FIG. 11 FIG. 6 is a cross-sectional view of another example of a semiconductor device according to an embodiment, taken along line K-K' of FIG. 5. FIG. 5 FIG. 6 is a cross-sectional view of another example of a semiconductor device according to an embodiment, taken along line K-K' of FIG. 5.

[0121] Referring to FIG. 11The upper surface of the offset region OF_3 of the semiconductor device 200-4 can be formed to be inclined. For example, the upper surface of the offset region OF_3 of the semiconductor device 200-4 can be formed to be inclined downward from the overcoat insulating layer 230 to the fill insulating layer 240. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0122] FIG. 12 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment taken along line K-K' of FIG. 5

[0123] Referring to FIG. 12 The upper surface of the offset region OF_4 of the semiconductor device 200-5 can be formed such that a central portion of the upper surface of the offset region OF_4 can be concave toward the overcoat insulating layer 230 in a circular shape. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0124] FIG. 13 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment taken along line K-K' of FIG. 5

[0125] Referring to FIG. 13 The upper surface of the offset region OF_5 of the semiconductor device 200-6 can be formed such that a central portion of the upper surface of the offset region OF_5 can be concave in a wedge shape. For example, the upper surface of the offset region OF_5 of the semiconductor device 200-6 can be formed such that a central portion of the upper surface of the offset region OF_5 can be concave toward the overcoat insulating layer 230 in a sharp wedge shape. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0126] FIG. 14 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment taken along line K-K' of FIG. 5

[0127] Referring to FIG. 14 ​​​The upper surface of the offset region OF_6 of the semiconductor device 200-7 can be formed in a stepped shape. For example, the upper surface of the offset region OF_6 of the semiconductor device 200-7 can be formed in a stepped shape that rises from the capping insulating layer 230 toward the filling insulating layer 240. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0128] FIG. 15 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment taken along line K-K' of FIG. 5

[0129] Referring to FIG. 15 The upper surface of the offset region OF_7 of the semiconductor device 200-8 can be formed in a stepped shape that descends from the capping insulating layer 230 toward the filling insulating layer 240. The height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be higher than the height of the lowermost surface of the word line WL. However, embodiments are not necessarily limited thereto, and the height of the top surface of the first portion of the bit line BL under the gate isolation insulating layer 210 can be equal to or lower than the height of the lowermost surface of the word line WL.

[0130] FIG. 16 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0131] Referring to FIG. 16 The method of manufacturing a semiconductor device according to an embodiment can include an operation S110 of forming a bit line extending in a first direction on a substrate, the bit line being formed in a plurality of pieces; an operation S120 of forming a gate isolation insulating layer extending on the bit line in a second direction crossing the first direction and standing in a third direction perpendicular to the substrate, the gate isolation insulating layer being formed in a plurality of pieces; an operation S130 of forming a channel layer extending along side surfaces of the gate isolation insulating layer and a top surface of the bit line between the gate isolation insulating layers adjacent to each other; an operation S140 of forming a capping insulating layer configured to cover the channel layer; an operation S150 of forming a sacrificial pattern layer reaching a preset height on the capping insulating layer; an operation S160 of forming a word line on the sacrificial pattern layer; an operation S170 of removing the sacrificial pattern layer; an operation S180 of forming a filling insulating layer configured to fill at least a portion of a space between the plurality of gate isolation insulating layers; an operation S191 of forming a landing pad connected to the channel layer; and an operation S192 of forming a data storage pattern connected to the landing pad.

[0132] ​Operation S120 can include forming a first insulating layer on the bit line, and forming a second insulating layer on the first insulating layer.

[0133] In operation S150, a sacrificial pattern layer can be formed up to a position higher than a top surface of the cover insulating layer covering the bit line located outside the gate isolation insulating layer. The sacrificial pattern layer can be a spin-on hard mask (SOH). However, embodiments are not necessarily limited thereto. The sacrificial pattern layer can function to fill a step formed between the bit line BL and the bit line isolation insulating layer.

[0134] In operation S110, a first portion of the bit line under the gate isolation insulating layer can be formed thicker than a second portion of the bit line outside the gate isolation insulating layer. In an example, a top surface of the first portion of the bit line under the gate isolation insulating layer can be formed at a position higher than a bottom surface of the word line. In another example, the top surface of the first portion of the bit line under the gate isolation insulating layer can be formed at a position same as the bottom surface of the word line. In another example, the top surface of the first portion of the bit line under the gate isolation insulating layer can be formed at a position lower than the bottom surface of the word line and higher than a top surface of the cover insulating layer disposed between the gate isolation insulating layers adjacent to each other.

[0135] Operation S160 can include operation S161 of depositing a word line, and operation S162 of partially etching the word line such that a portion of the word line remains on a side surface of the cover insulating layer above the gate isolation insulating layer.

[0136] In operation S170, an offset region can be formed between a bottom surface of the word line and a top surface of the cover insulating layer disposed between the gate isolation insulating layers adjacent to each other. The offset region can be formed in a region where the sacrificial pattern layer is removed. Operation S170 can be performed by various processes. For example, operation S170 can be performed by an SOH ashing process.

[0137] An upper surface of the offset region can be formed as a horizontal surface, an inclined surface, a stepped surface, or a surface recessed toward the cover insulating layer.

[0138] In operation S180, the offset region can have a space at least partially filled with a fill insulating layer.

[0139] In operation S150, the sacrificial pattern layer can be formed up to a same height as a top surface of the cover insulating layer covering the bit line located outside the gate isolation insulating layer. For example, the sacrificial pattern layer can be formed up to a same height as a top surface of the cover insulating layer covering the bit line located outside the gate isolation insulating layer only.

[0140] In operation S110, the bit line can be formed to have a uniform thickness. For example, a first portion of the bit line under the gate isolation insulating layer can be formed to have the same thickness as a second portion of the bit line outside the gate isolation insulating layer.

[0141] In operation S170, an offset region can not be separately formed between a bottom surface of the word line and a top surface of the cover insulating layer disposed between the gate isolation insulating layers adjacent to each other. For example, the bottom surface of the word line can be in contact with the top surface of the cover insulating layer disposed between the gate isolation insulating layers adjacent to each other.

[0142] The technical idea described herein can be equally applicable to operations S120, S130, S140, S160, S180, S191, and S192. FIGS. 5-15

[0143] FIGS. 17A-24B is a cross-sectional view for describing an example of a method of manufacturing a semiconductor device. FIG. 17A , FIG. 18A , FIG. 19A , FIG. 20A , FIG. 21A , FIG. 22A , FIG. 23A and FIG. 24A is a cross-sectional view observed in the same or similar direction as the direction along the line K-K' of FIG. 5 . FIG. 17B , FIG. 18B , FIG. 19B , FIG. 20B , FIG. 21B , FIG. 22B , FIG. 23B and FIG. 24B is a cross-sectional view observed in the same or similar direction as the direction along the line M-M' of FIG. 5 .

[0144] Referring to FIG. 17A and FIG. 17B , a bit line BL extending in the first direction D1 can be formed on the insulating film 260 on the substrate CC. The bit line BL can be formed to have a preset thickness. A plurality of bit lines BL can be provided, and the plurality of bit lines BL can be spaced apart from each other in the second direction D2. The space between the bit lines BL can be at least partially filled with a bit line isolation insulating layer 250. For example, the bit line isolation insulating layer 250 and another material can fill the space between the bit lines BL. In another example, a multi-layer bit line isolation insulating layer 250 can fill the space between the bit lines BL.

[0145] Referring to FIG. 18A and FIG. 18B ​A plurality of gate isolation insulating layers 210 extending in a second direction D2 crossing the first direction D1 can be formed on the bit line BL. The gate isolation insulating layers 210 can stand in a third direction D3 perpendicular to the substrate CC. The gate isolation insulating layers 210 can include first insulating layers 211 disposed on the bit line BL, and second insulating layers 212 disposed on the first insulating layers 211. A thickness of a first portion of the bit line BL under the gate isolation insulating layers 210 can be maintained to be greater than a thickness of a second portion of the bit line BL outside the gate isolation insulating layers 210.

[0146] Referring to FIG. 19A and FIG. 19B A channel layer 220 can be formed along a top surface and a side surface of each of the gate isolation insulating layers 210, and a top surface of a portion of the bit line BL between the gate isolation insulating layers 210 adjacent to each other. For example, a portion of the side surface of the bit line BL can be exposed above the bit line isolation insulating layer 250.

[0147] A staircase can be formed between the bit line BL and the bit line isolation insulating layer 250 by an etching process performed in a process of forming the plurality of gate isolation insulating layers 210 and the channel layer 220 described herein.

[0148] Referring to FIG. 20A and FIG. 20B A cover insulating layer 230 can be formed to cover the channel layer 220, and a portion in which the channel layer 220 is not formed.

[0149] Referring to FIG. 21A and FIG. 21B A sacrificial pattern layer SS can be formed up to a position higher than a top surface of the cover insulating layer 230 covering a second portion of the bit line BL outside the gate isolation insulating layers 210. The sacrificial pattern layer SS can function to fill the staircase formed between the bit line BL and the bit line isolation insulating layer 250.

[0150] Referring to FIG. 22A and FIG. 22B A word line WL can be formed on the sacrificial pattern layer SS.

[0151] Referring to FIG. 23A and FIG. 23B The word line WL can be partially etched and removed such that a portion of the word line WL remains only on a side surface of the cover insulating layer 230 above each of the gate isolation insulating layers 210. The word lines WL adjacent to each other can be separated from each other, and a space can be formed between the word lines WL adjacent to each other. For example, the word lines WL adjacent to each other can be completely separated from each other, and a space can be formed between the word lines WL adjacent to each other.

[0152] The sacrificial pattern layer can be removed after etching of the word lines WL. In the region left after removing the sacrificial pattern layer, an offset region OF_1 can be formed. Through the offset region OF_1, a bottom surface of the word lines WL can be spaced apart from a top surface of the covering insulating layer 230.

[0153] The material for forming the word lines WL can not exist in an upper surface portion A' of the covering insulating layer 230 covering the second portion of the bit lines BL outside the gate isolation insulating layers 210. In addition, a word line residue can not exist in a region B' of an upper surface portion of the covering insulating layer 230 covering the bit line isolation insulating layers 250 adjacent to the bit lines BL. A word line bridge can not exist in a central region C' of the upper surface portion of the covering insulating layer 230 covering the bit line isolation insulating layers 250.

[0154] Reference FIG. 24A and FIG. 24B The space between the plurality of gate isolation insulating layers 210 can be filled with the filling insulating layer 240. The space between the word lines WL adjacent to each other can be filled with the filling insulating layer 240. The offset region OF_1 can also be filled with the filling insulating layer 240.

[0155] In addition, a portion of the channel layer 220 can be exposed by an etching process. In an embodiment, the channel layer 220 and a data storage pattern (not shown) can be electrically connected to each other by a bonding pad (not shown).

[0156] FIGS. 25A-32B is a cross-sectional view for describing another example of a method of manufacturing a semiconductor device. FIG. 25A , FIG. 26A , FIG. 27A , FIG. 28A , FIG. 29A , FIG. 30A , FIG. 31A and FIG. 32A is a cross-sectional view observed in the same or similar direction as the direction along the line K-K' of FIG. 5 . FIG. 25B , FIG. 26B , FIG. 27B , FIG. 28B , FIG. 29B , FIG. 30B , FIG. 31B and FIG. 32B is a cross-sectional view observed in the same or similar direction as the direction along the line M-M' of FIG. 5 .

[0157] Reference FIG. 25A and FIG. 25BA bit line BL extending in the first direction D1 can be formed on the insulating film 360 provided on the substrate CC. The bit line BL can be formed with a preset thickness. A plurality of bit lines BL can be provided and can be spaced apart from each other in the second direction D2. The space between the bit lines BL can be at least partially filled with the bit line isolation insulating layer 350.

[0158] Referring to FIG. 26A and FIG. 26B A plurality of gate isolation insulating layers 310 extending in a second direction D2 crossing the first direction D1 can be formed on the bit line BL. The gate isolation insulating layers 310 can stand in a third direction D3 perpendicular to the substrate CC. The gate isolation insulating layers 310 can include a first insulating layer 311 provided on the bit line BL, and a second insulating layer 312 provided on the first insulating layer 311. The thickness of a first portion of the bit line BL under the gate isolation insulating layer 310 can be maintained to be the same as the thickness of a second portion of the bit line BL outside the gate isolation insulating layer 310.

[0159] Referring to FIG. 27A and FIG. 27B A channel layer 320 can be formed along the top surface and the side surface of each of the gate isolation insulating layers 310, and the top surface of the bit line BL between the gate isolation insulating layers 310 adjacent to each other. The portion of the side surface of the bit line BL having a height greater than that of the bit line isolation insulating layer 350 can be exposed through the channel layer 320.

[0160] A step can be formed between the bit line BL and the bit line isolation insulating layer 350 by an etching process performed in a process of forming the plurality of gate isolation insulating layers 310 and the channel layer 320 described herein.

[0161] Referring to FIG. 28A and FIG. 28B A cover insulating layer 330 can be formed to cover the channel layer 320, and a portion in which the channel layer 320 is not formed.

[0162] Referring to FIG. 29A and FIG. 29B A sacrificial pattern layer SS can be formed up to the same height as the top surface of the cover insulating layer 330 covering the bit line BL outside the gate isolation insulating layer 310. The sacrificial pattern layer SS can function to fill the step formed between the bit line BL and the bit line isolation insulating layer 350.

[0163] Referring to FIG. 30A and FIG. 30B A word line WL can be formed on the sacrificial pattern layer SS.

[0164] Referring to FIG. 31A and FIG. 31BThe word lines WL can be partially etched and removed, such that a portion of the word lines WL remains only on side surfaces of the cover insulating layers 330 above each of the gate isolation insulating layers 310. The word lines WL adjacent to each other can be completely separated from each other. For example, the word lines WL adjacent to each other can be completely separated from each other, and a space can be formed between the word lines WL adjacent to each other.

[0165] The sacrificial pattern layer can be removed after the partial etching of the word lines WL. The offset region can not be separately formed between the bottom surface of the word lines WL and the top surface of the cover insulating layers 330 disposed between the gate isolation insulating layers 310 adjacent to each other. The bottom surface of the word lines WL can be in contact with the top surface of the cover insulating layers 330 disposed between the gate isolation insulating layers 310 adjacent to each other.

[0166] The material for forming the word lines WL can not exist in an upper surface portion A' of the cover insulating layers 330 covering the bit lines BL located outside the gate isolation insulating layers 310. For example, the upper surface portion A' of the cover insulating layers 330 covering the bit lines BL located outside the gate isolation insulating layers 310 can be exposed by the space between the word lines WL adjacent to each other. In addition, the word line residue can not exist in a region B' of the upper surface portion of the cover insulating layers 330 covering the bit line isolation insulating layers 350 adjacent to the bit lines BL. The word line bridge can not exist in a central region C' of the upper surface portion of the cover insulating layers 330 covering the bit line isolation insulating layers 350.

[0167] Reference FIG. 32A and FIG. 32B The space between the plurality of gate isolation insulating layers 310 can be at least partially filled with the fill insulating layer 340. The space formed between the word lines WL adjacent to each other can be at least partially filled with the fill insulating layer 340. For example, a spacer can be formed by the fill insulating layer 340 in a portion between the word lines WL adjacent to each other.

[0168] In addition, a portion of the channel layer 320 can be exposed by an etching process. In an embodiment, the channel layer 320 and a data storage pattern (not shown) can be electrically connected to each other by a bonding pad (not shown).

[0169] The semiconductor device according to the embodiment and the method of manufacturing the same can effectively suppress or prevent the formation or leaving of the word line residue and the word line bridge between the bit lines adjacent to each other.

[0170] In addition, the semiconductor device according to the embodiment and the method of manufacturing the same can effectively prevent a problem from occurring in the operation of the transistor due to the smooth flow of the current between the source and the drain being not possible when the word line bridge is formed. Furthermore, the electrical characteristics and the reliability of the semiconductor device can be improved.

[0171] While embodiments are described with reference to the figures, it will be clear to those of ordinary skill in the art having the benefit of this disclosure that changes and modifications can be made to the embodiments without departing from the spirit and scope of the claims and their equivalents. For example, the described technology can be implemented in different sequences of steps and / or implemented with different components in different arrangements and / or with other components not expressly described herein, without departing from the spirit and scope of the described technology.

Claims

1. A semiconductor device including a vertical channel transistor, comprising: a substrate; a bit line provided on the substrate and extending in a first direction; a gate isolation insulating layer provided on the bit line and extending in a second direction intersecting the first direction and standing in a third direction perpendicular to the substrate; a channel layer extending along side surfaces of the gate isolation insulating layer and top surfaces of the bit line between the gate isolation insulating layers and adjacent gate isolation insulating layers; a cover insulating layer configured to cover the channel layer; and a word line provided on side surfaces of the cover insulating layer above the gate isolation insulating layers, wherein a bottom surface of the word line is spaced apart from a top surface of the cover insulating layer provided between the gate isolation insulating layer and the adjacent gate isolation insulating layer. A top surface of a first portion of the bit line under the gate isolation insulating layer is formed at a position higher than a bottom surface of the word line, or at a position the same as the bottom surface of the word line, or at a position lower than the bottom surface of the word line and higher than the top surface of the cover insulating layer provided between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

2. The semiconductor device of claim 1, wherein, An offset region is formed between the bottom surface of the word line and the top surface of the cover insulating layer provided between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

3. The semiconductor device of claim 1, wherein, An upper surface of the offset region is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface recessed toward the cover insulating layer.

4. The semiconductor device of claim 3, wherein, 5. The semiconductor device according to claim 3, further comprising: a filling insulating layer provided in a space between the gate isolation insulating layer and the adjacent gate isolation insulating layer, wherein the filling insulating layer is provided in the offset region. The gate isolation insulating layer includes:

6. The semiconductor device of claim 1, wherein, a first insulating layer provided on the bit line; and a second insulating layer provided on the first insulating layer.

7. The semiconductor device according to claim 1, further comprising: a data storage pattern electrically connected to the channel layer; and a landing pad provided between the channel layer and the data storage pattern.

8. The semiconductor device according to claim 1, further comprising: an insulating film provided between the bit line and the substrate.

9. A semiconductor device including a vertical channel transistor, comprising: a substrate; a bit line provided on the substrate and extending in a first direction; a gate isolation insulating layer provided on the bit line and extending in a second direction intersecting the first direction and standing in a third direction perpendicular to the substrate; a channel layer extending along side surfaces of the gate isolation insulating layer and top surfaces of the bit line between the gate isolation insulating layers and adjacent gate isolation insulating layers; a cover insulating layer configured to cover the channel layer; a filling insulating layer provided on the cover insulating layer; and a word line provided on the filling insulating layer and on side surfaces of the cover insulating layer above the gate isolation insulating layers. ​ ​ ​ The bottom surface of the word line is spaced apart from the top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

10. The semiconductor device of claim 9, wherein, An offset region is formed between the bottom surface of the word line and the top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

11. The semiconductor device of claim 10, wherein, An upper surface of the offset region is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface recessed toward the cover insulating layer.

12. A method of manufacturing a semiconductor device, the method comprising: forming a bit line extending in a first direction on a substrate; forming a gate isolation insulating layer extending on the bit line in a second direction crossing the first direction and standing in a third direction perpendicular to the substrate, the gate isolation insulating layer being disposed adjacent to an adjacent gate isolation insulating layer; forming a channel layer extending along side surfaces of the gate isolation insulating layer and a top surface of the bit line between the gate isolation insulating layer and the adjacent gate isolation insulating layer; forming a cover insulating layer configured to cover the channel layer; forming a sacrificial pattern layer on the cover insulating layer; forming a word line on the sacrificial pattern layer and the cover insulating layer; and removing the sacrificial pattern layer. The forming of the sacrificial pattern layer includes forming the sacrificial pattern layer up to a same height as a top surface of the cover insulating layer covering a second portion of the bit line outside the gate isolation insulating layer.

13. The method of claim 12, wherein, The forming of the bit line includes forming the bit line with a uniform thickness.

14. The method of claim 13, wherein, The forming of the sacrificial pattern layer includes forming the sacrificial pattern layer up to a position higher than a top surface of the cover insulating layer covering a second portion of the bit line outside the gate isolation insulating layer.

15. The method of claim 12, wherein, The forming of the bit line includes forming a first portion of the bit line under the gate isolation insulating layer thicker than the second portion of the bit line outside the gate isolation insulating layer.

16. The method of claim 14, wherein, A top surface of the first portion of the bit line under the gate isolation insulating layer is formed at a position higher than a bottom surface of the word line, or at a same position as the bottom surface of the word line, or at a position lower than the bottom surface of the word line and higher than the top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

17. The method of claim 16, wherein, The removing of the sacrificial pattern layer includes forming an offset region between a bottom surface of the word line and the top surface of the cover insulating layer disposed between the gate isolation insulating layer and the adjacent gate isolation insulating layer.

18. The method of claim 15, wherein, The forming of the word line includes:

19. The method of claim 12, wherein, depositing a material; and partially etching the material to form the word line on a side surface of the cover insulating layer above the gate isolation insulating layer.

20. The method of claim 12, further comprising: forming a fill insulating layer filling a space between a plurality of gate isolation insulating layers including the gate isolation insulating layer; ​ forming a contact pad connected to the channel layer; and forming a data storage pattern connected to the contact pad.

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